JP2013215005A - Circuit for preventing simultaneous on action of relays in relay drive device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for preventing a simultaneous on action of relays in a relay drive device which can inexpensively prevent a simultaneous on action with reliability.SOLUTION: In the relay drive device having two one-way conduction drive relays 1, 2 and drive control means 3 for outputting two pulse control signals to be input into the two one-way conduction drive relays 1, 2, respectively, the two pulse control signals from the drive control means are individually output high level or low level signals, and are controlled such that when one is at the high level, the other is at the low level, the two one-way conduction relays 1, 2 each have one signal line 5a, 5b that must be prevented from switching on simultaneously, and output terminals of first and second logic elements 6a and 6b, into which the two pulse control signals from the drive control means are input, respectively, are connected to two junctions where the two one-way conduction drive relays 1, 2 are connected in opposite directions, respectively.

Description

  The present invention relates to a relay drive device that drives and controls a plurality of relays, and more particularly, to a technique for preventing simultaneous ON of a plurality of relays.

  As a simultaneous ON prevention circuit in a conventional relay drive device, there is a general inhibit circuit composed of a logic IC.

  FIG. 5 is a circuit diagram showing a simultaneous ON prevention circuit in a conventional relay driving apparatus. In FIG. 3, the relay drive circuit includes two semiconductor relays 1 and 2 and control signal output terminals P1 and P2 of a control unit 3 composed of a microcomputer or the like that controls on / off of the semiconductor relays 1 and 2. An inhibit circuit 4 is connected as a simultaneous ON prevention circuit. The control signal output terminals P1 and P2 each output a control signal in which when one is at the H (high) level, the other is at the L (low) level.

  The semiconductor relay 1 includes a photocoupler including an LED (light emitting diode) 1a connected to a + Vcc power source via a resistor R11, and a semiconductor switch element 1b including a MOSFET that is on / off controlled by the output voltage of the photocoupler. Has been. The semiconductor switch elements 1b are connected to one signal line 5a of the two signal lines 5a and 5b, which should be alternately turned on and dangerous when turned on at the same time.

  Similarly, the semiconductor relay 2 includes a photocoupler including an LED 2a connected to a + Vcc power source via a resistor R2, and a semiconductor switch element 2b composed of a MOSFET controlled to be turned on / off by the output voltage of the photocoupler. Yes. The semiconductor switch elements 2b are connected to the other signal line 5b of the two signal lines 5a and 5b, which should be alternately turned on and dangerous when turned on at the same time.

  The inhibit circuit 4 is composed of four 2-input NAND gate elements 4a to 4d made of CMOS-IC or the like. The two input terminals of the NAND gate element 4a are connected to the control signal output terminal P2, and the output terminal is connected to one input terminal of the NAND gate element 4b. The other input terminal of the NAND gate element 4b is connected to the control signal output terminal P1, and the output terminal is connected to the LED 1a of the semiconductor relay 1. The two input terminals of the NAND gate element 4d are connected to the control signal output terminal P1, and the output terminal is connected to one input terminal of the NAND gate element 4c. The other input terminal of the NAND gate element 4c is connected to the control signal output terminal P2, and the output terminal is connected to the LED 2a of the semiconductor relay 2.

  In the above-described configuration, when the control signal output terminal P1 of the control unit 3 becomes H level and the control signal output terminal P2 becomes L level during normal operation, the output of the NAND gate element 4b of the inhibit circuit 4 accordingly. The terminal becomes L level, and the output terminal of the NAND gate element 4c becomes H level. Therefore, the LED 1a of the semiconductor relay 1 is turned on and the semiconductor switch element 1b is turned on, but the LED 2a of the semiconductor relay 2 is turned off and the semiconductor switch element 2b is turned off.

  On the other hand, when the control signal output terminal P2 of the control unit 3 becomes H level and the control signal output terminal P1 becomes L level, the output terminal of the NAND gate element 4c of the inhibit circuit 4 becomes L level accordingly. The output terminal of the NAND gate element 4b is at the H level. Therefore, the LED 2a of the semiconductor relay 2 is turned on and the semiconductor switch element 2b is turned on, but the LED 1a of the semiconductor relay 1 is turned off and the semiconductor switch element 1b is turned off.

  On the other hand, at the time of abnormal operation in which both the control signal output terminals P1 and P2 of the control unit 3 are at the H level due to a malfunction or runaway of the microcomputer, the output terminals of the NAND gate elements 4b and 4c are both at the H level. Accordingly, the LEDs 1a and 2a of the semiconductor relays 1 and 2 are both turned off, and the semiconductor switch elements 1b and 2b are both turned off. As described above, the semiconductor switch elements 1b and 2b are prevented from being simultaneously turned on during an abnormal operation such as a malfunction or runaway of the microcomputer.

Japanese Patent Laying-Open No. 2006-197276 (FIG. 5)

  However, in the above-described conventional circuit, it is possible to reliably prevent two outputs from being simultaneously turned on in the event of a microcomputer failure or runaway. However, when the inhibit circuit 4 itself fails (for example, when latched up), There is a possibility that the output terminals of the two NAND gate elements 4b and 4c both become L level, the LEDs 1a and 2a are both turned on, and both the semiconductor switch elements 1b and 2b are simultaneously turned on. In addition, four NAND gate elements 4a to 4d and two resistors R1 and R2 are required, and there is a problem that the cost of parts becomes high.

  Accordingly, an object of the present invention is to provide a simultaneous ON prevention circuit for relays of a relay drive device that can reliably prevent simultaneous ON at low cost in view of the above-described conventional problems.

  In order to solve the above-mentioned problem, the simultaneous ON-prevention circuit for the relay of the relay driving device according to claim 1 is composed of two unidirectional energization driving relays 1 and 2 and the two unidirectional energization driving relays. Drive control means 3 for outputting two pulse control signals input to 1 and 2, respectively, in the relay drive device, the two pulse control signals from the drive control means are respectively output at a high level or It is a low level signal, and when one is high level, the other is controlled to be low level, and it is necessary to prevent the two one-way energizing relays 1 and 2 from being turned on simultaneously. The drive control unit is connected to both connection points having a certain signal line 5a, 5b and the two one-way energization drive relays 1, 2 connected in opposite directions. The two pulse control signal from the first and second logic elements 6a are input, an output terminal of 6b, characterized in that it is connected.

  In order to solve the above-mentioned problem, the invention according to claim 2 is the simultaneous on-prevention circuit for the relay of the relay drive device according to claim 1, wherein the one-way energization drive type relays 1, 2 are the drive It is a semiconductor relay including LEDs 1a and 2a to which output signals are supplied and semiconductor switch elements 1b and 2b inserted into the signal lines 5a and 5b and controlled to be turned on and off based on optical signals from the LEDs 1a and 2a. Features.

  The reference numerals in the description of the means for solving the above-described problems correspond to the reference numerals in the following description of the best mode for carrying out the invention, but these are the interpretations of the claims. It is not intended to limit.

  According to the first aspect of the present invention, there are provided two unidirectional energization drive relays and drive control means for outputting two pulse control signals input to the two unidirectional energization drive relays, respectively. In the relay drive device, the two pulse control signals from the drive control means are high level or low level signals respectively output, and when one is high level, the other is controlled to be low level, Each of the two one-way energization type relays has one signal line that needs to be prevented from being turned on at the same time, and the two one-way energization drive type relays are connected so that they are opposite to each other. Since the output terminals of the first and second logic elements, to which two pulse control signals from the drive control means are respectively input, are connected to the point, the control side has an abnormality such as a failure. Simultaneous ON prevention circuit of the relay of the relay driving unit to reliably perform simultaneous ON prevention during work can be realized at a low cost.

  According to the second aspect of the present invention, the unidirectional energization drive type relay includes an LED to which a drive output signal is supplied, a semiconductor switch element that is inserted into a signal line and controlled to be turned on / off based on an optical signal from the LED. Therefore, it is possible to reliably prevent simultaneous ON when a semiconductor relay is used.

It is a circuit diagram which shows the structure of the simultaneous ON prevention circuit of the relay of the relay drive device which concerns on embodiment of this invention. It is a circuit diagram which shows the detailed structure of a semiconductor relay. It is a circuit diagram which shows the case where the simultaneous ON prevention circuit of the relay of the relay drive device of this invention is applied to a flying capacitor system insulation detection apparatus. It is a circuit diagram which shows the other Example of the simultaneous ON prevention circuit of the relay of the relay drive device of this invention. It is a circuit diagram which shows the simultaneous on prevention circuit in the conventional relay drive device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of a relay simultaneous on prevention circuit of a relay drive device according to an embodiment of the present invention. In FIG. 1, a relay driving device includes two semiconductor relays 1 and 2, a control unit 3 including a microcomputer for controlling on / off of these semiconductor relays 1 and 2, and a CMOS logic element of NAND logic. It is composed of two NAND gate elements 6a and 6b made of IC and one current limiting resistor R1. The semiconductor relays 1 and 2 correspond to the one-way energization drive type relay in the claims, the NAND gate element 6a corresponds to the first logic element in the claims, and the NAND gate element 6b corresponds to the second logic element in the claims. The control unit 3 corresponds to a logic element, and corresponds to drive control means in the claims.

  The semiconductor relay 1 includes a photocoupler including an LED 1a and a semiconductor switching element 1b including a MOSFET that is controlled to be turned on / off by an output voltage of the photocoupler, and is configured as a one-way energization drive type relay. The semiconductor switch element 1b is inserted into one of the two signal lines 5a and 5b, which should be alternately turned on and dangerous when turned on at the same time.

  As shown in FIG. 2, the detailed configuration of the semiconductor relay 1 includes an LED 1a connected to input terminals 1B and 1C and an array of photodiodes 1c that receive a light emission signal output from the LED 1a and generate photovoltaic power. A photocoupler 1A and a semiconductor switch element 1b made of a MOSFET that is ON / OFF controlled by the output voltage of the photocoupler 1A.

  Similarly, the semiconductor relay 2 includes a photocoupler including an LED 2a and a semiconductor switch element 2b including a MOSFET that is on / off controlled by an output voltage of the photocoupler, and is configured as a one-way energization drive type relay. The semiconductor switch elements 2b are inserted into the other signal line 5b of the two signal lines 5a and 5b, which should be alternately turned on and dangerous when turned on at the same time. For example, it is assumed that the signal line 5a is a positive power supply line, the signal line 5b is a negative power supply line, and the power supply is short-circuited when the semiconductor switch elements 1b and 2b are simultaneously turned on. The detailed configuration of the semiconductor relay 2 is the same as the configuration of the semiconductor relay 1 shown in FIG.

  The anode of the LED 1a of the semiconductor relay 1 is connected to the output terminal of the NAND gate element 6b via the current limiting resistor R1, and the cathode is connected to the output terminal of the NAND gate element 6a. The anode of the LED 2a of the semiconductor relay 2 is connected to the output terminal of the NAND gate element 6a, and the cathode is connected to the output terminal of the NAND gate element 6b via the current limiting resistor R1. That is, the LEDs 1a and 1b are reversely connected to each other between the output terminals of the NAND gate elements 6a and 6b.

  The two input terminals of the NAND gate element 6a are connected to the control signal output terminal P1 of the control unit 3 so that the NAND gate element functions as an inverter element. Similarly, the two input terminals of the NAND gate element 6b Are connected to a control signal output terminal P2 of the control unit 3 so as to function as an inverter element. The control signal output terminals P1 and P2 of the control unit 3 each output a pulse control signal in which when one is at the H (high) level, the other is at the L (low) level.

  In the above configuration, during normal operation, when the control signal output terminal P1 of the control unit 3 becomes H level due to the output of the pulse control signal and the control signal output terminal P2 becomes L level, the output of the NAND gate element 6a The terminal outputs an L level drive output signal, and the output terminal of the NAND gate element 6b outputs an H level drive output signal. Accordingly, since the potential difference between the H level drive output signal and the L level drive output signal is applied to the LED 1a of the semiconductor relay 1 as a forward voltage, the current limiting resistor R1 and the LED 1a are connected from the output terminal of the NAND gate element 6b. As a result, a current flows to the output terminal of the NAND gate element 6a, the LED 1a is turned on, and the semiconductor switch element 1b is turned on. At this time, since a reverse voltage is applied to the LED 2a of the semiconductor relay 2, no current flows, the LED 2a is turned off, and the semiconductor switch 2b is turned off.

  On the other hand, when the control signal output terminal P1 of the control unit 3 is at L level and the control signal output terminal P2 is at H level, the output terminal of the NAND gate element 6b outputs an L level drive output signal, and NAND The output terminal of the gate element 6a outputs an H level drive output signal. Accordingly, since a forward voltage is applied to the LED 2a of the semiconductor relay 2, a current flows from the output terminal of the NAND gate element 6a to the output terminal of the NAND gate element 6b via the LED 2a and the current limiting resistor R1, and the LED 2a Lights up and the semiconductor switch element 2b is turned on. At this time, since the reverse voltage is applied to the LED 1a of the semiconductor relay 1, no current flows, the LED 1a is turned off, and the semiconductor switch 1b is turned off.

  On the other hand, at the time of abnormal operation in which both the control signal output terminals P1 and P2 of the control unit 3 become H level or L level due to a malfunction or runaway of the microcomputer, the output terminals of the NAND gate elements 6a and 6b are both L level or Becomes H level. Therefore, since forward voltage is not applied to the LEDs 1a and 2a of the semiconductor relays 1 and 2, the LEDs 1a and 2a are both turned off, and the semiconductor switch elements 1b and 2b are both turned off. As described above, the semiconductor switch elements 1b and 2b are prevented from being simultaneously turned on at the time of abnormal operation of the control unit 3 due to failure of the microcomputer or runaway.

  Further, when the output terminals of the NAND gate elements 6a and 6b both become L level or H level due to failure of one or both of the NAND gate elements 6a and 6b, the semiconductor relays 1 and 2 are connected in the same manner as described above. Since no forward voltage is applied to the LEDs 1a and 2a, the LEDs 1a and 2a are both turned off, and the semiconductor switch elements 1b and 2b are both turned off. As described above, the semiconductor switch elements 1b and 2b are prevented from being simultaneously turned on even during an abnormal operation such as failure of one or both of the NAND gate elements 6a and 6b, that is, in any state of the logic element. .

  In addition, the absolute rating of the reverse breakdown voltage VR of the LEDs 1a and 2a of the semiconductor relays 1 and 2 is 5V, the maximum value of the forward voltage VF is 1.5V, the H level drive output signal voltage of the NAND gate elements 6a and 6b is 5V, If the L level drive output signal voltage is set to the ground potential, the reverse voltage applied to the LEDs 1a and 2a in this circuit configuration does not exceed the reverse breakdown voltage VR, and the reverse breakdown voltage VR is equal to the forward voltage VF. Since it is twice or more, a sufficient margin can be secured.

  As described above, according to the present invention, the relay drive operation is reliable, and the switches inserted in the signal lines 5a and 5b are not simultaneously turned on even during an abnormal operation such as a failure of the control unit 3 or the NAND gate element. An on-prevention function can be reliably performed. Further, compared with the above-described conventional configuration, two logic elements 2 and one resistor can be reduced, which can be realized at low cost.

  Next, FIG. 3 is a circuit diagram showing a case in which the relay simultaneous ON prevention circuit of the relay drive circuit of the present invention is applied to a flying capacitor type insulation detection device.

  In the figure, a power source 3 is configured as a high-voltage DC power source in which a plurality of batteries V1 to Vn are connected in series, and the power source 3 is insulated from a ground potential G of a measurement system such as the microcomputer 20.

  As shown in the figure, the insulation detection device is a first switch for connecting a bipolar capacitor (ie, a flying capacitor) 9 and the positive electrode of the power source 3 insulated from the ground potential G to one end of the capacitor 9. And a semiconductor relay 11 as a second switch for connecting the negative electrode of the power source 3 to the other end of the capacitor 9.

  Further, the insulation detection device includes the semiconductor relay 2 as a third switch for connecting one end of the capacitor 9 to the input port P6 of the microcomputer 20 as the control unit via the low-pass filter 14 for noise removal, and the capacitor 9. And a semiconductor relay 12 as a fourth switch for connecting the other end to the ground potential G.

  Between the connection point of the semiconductor switch element 1b of the semiconductor relay 1 and the semiconductor switch element 2b of the semiconductor relay 2, and the connection point of the semiconductor switch element 11b of the semiconductor relay 11 and the semiconductor switch 12b of the semiconductor relay 12, a diode D1 and a resistor R2 and capacitor 9 are sequentially connected in series. A diode D2 and a resistor R3 are sequentially connected in series between a connection point between the resistor R2 and the capacitor 9 and a connection point between the semiconductor switch element 1b of the semiconductor relay 1 and the semiconductor switch element 2b of the semiconductor relay 2. . That is, the diode D1 and the resistor R1, and the diode D2 and the resistor R2 are connected in parallel so that the polarities of the diodes are opposite to each other.

  A resistor R4 is connected between the input port P6 side of the semiconductor switch element 2b and the ground potential G, and a resistor R5 is connected between the ground potential G side of the semiconductor switch element 12b and the ground potential G.

  The LED 1a of the semiconductor relay 1 and the LED 2a of the semiconductor relay 2 are reversely connected to each other between the output terminals of the NAND gate elements 6a and 6b similarly to the relay driving device shown in FIG. 1, and the input terminals of the NAND gate elements 6a and 6b are These are connected to the output ports P1 and P2 of the microcomputer 20, respectively.

  Similarly to the relay driving device shown in FIG. 1, the LED 11a of the semiconductor relay 11 and the LED 12a of the semiconductor relay 12 are reversely connected to each other between the output terminals of the NAND gate elements 16a and 16b, and input to the NAND gate elements 16a and 16b. The terminals are connected to the output ports P3 and P4 of the microcomputer 20, respectively.

  The microcomputer 20 has a voltage detection function of detecting a voltage input to the input port P6 by A / D (analog / digital) conversion. Further, the microcomputer 20 outputs a pulse control signal from one of the output ports P1 and P3 and the output ports P2 and P4 so that when one is at the H (high) level and the other is at the L (low) level, the semiconductor relay 1 The semiconductor switch elements 1b and 11b of 11 and 11 and the semiconductor switch elements 2b and 12b of the semiconductor relays 2 and 12 can be controlled on and off in conjunction with each other.

  The insulation detection device further includes a semiconductor relay 13 as a fifth switch for connecting the connection point of the diode D2 and the resistor R2 to the ground potential G via the resistor R6 having a resistance value lower than that of the resistor R3. Yes. The anode of the LED 13a of the semiconductor relay 13 is connected to the power supply + Vcc, and the cathode is connected to the output port P5 of the microcomputer 20 via the resistor R7. The semiconductor relay 13 and the resistor 6 constitute a reset circuit. When the semiconductor switch element 13b is controlled to be closed, the charge accumulated in the capacitor 9 can be discharged quickly by the resistor R6.

Next, the operation of the insulation detection device having the above-described configuration will be described. First, the microcomputer 20 measures the voltage V _{0 of the} power supply 3. Specifically, this measurement is performed as follows. The microcomputer 20 outputs an H level control signal to the output ports P1 and P3 and outputs an L level control signal to the output ports P2 and P4 from the initial state in which all the switches are open, and the semiconductor switch element 1b. And 11b are closed. Thereby, the voltage of the power supply V is charged in the capacitor 9.

Next, the microcomputer 20 outputs an L level control signal to the output ports P1 and P3 and outputs an H level control signal to the output ports P2 and P4 to control the semiconductor switch elements 1b and 11b to open. Semiconductor switch elements 2b and 12b are controlled to open. As a result, the voltage across the capacitor 9, that is, the voltage V ₀ across the power supply 3 is supplied to the input port P 6 of the microcomputer 20, and the voltage V ₀ across the A / D is A / D converted and read by the microcomputer 20 as the voltage of the power supply 3.

Next, the microcomputer 20 measures the voltage V _RL− according to the value of the negative side ground fault resistance RL−. Specifically, this measurement is performed as follows. That is, the microcomputer 20 outputs an L level control signal to the output port P5 to reset the semiconductor switch element 13b, then resets the output port P1 to the H level control signal and the output port P2 to control the L level. In addition to outputting a signal, an L level control signal is output to the output port P3, and an H level control signal is output to the output port P4, thereby closing the semiconductor switch elements 1b and 12b. As a result, the capacitor 9 is charged with a voltage corresponding to the value of the negative side ground fault resistance RL−.

Next, the microcomputer 20 outputs an L level control signal to the output port P1, and outputs an H level control signal to the output port P2, thereby controlling the semiconductor switch element 1b to open and closing the semiconductor switch element 2b. The closed control of the element 12b is maintained. Thereby, the voltage V _RL− corresponding to the voltage across the capacitor 9, that is, the value of the negative side ground fault resistance _RL− is read by the microcomputer 20.

Next, the microcomputer 10 measures the voltage V _{RL +} according to the value of the positive side ground fault resistance RL + (step S13). Specifically, this measurement is performed as follows. That is, the microcomputer 20 outputs an L level control signal to the output port P5 to reset the semiconductor switch element 13b, and then resets the output signal to the output port P3. Then, the microcomputer 20 controls the output port P4 to have the L level. In addition to outputting a signal, an L level control signal is output to the output port P1, and an H level control signal is output to the output port P2, thereby closing the semiconductor switch elements 11b and 2b. As a result, a voltage corresponding to the value of the positive side ground fault resistance RL + is charged in the capacitor 9.

Next, the microcomputer 20 outputs an L level control signal to the output port P3 and an H level control signal to the output port P4 to control the semiconductor switch element 11b to open and to close the semiconductor switch element 12b. The closed control of the element 2b is maintained. Thereby, the voltage V _{RL +} corresponding to the voltage across the capacitor 9, that is, the value of the positive side ground fault resistance _{RL +} is read by the microcomputer 20.

Then, microcomputer 20 measures a voltage corresponding measurement voltage V _{RL +} the sum of the corresponding to the measurement voltage V _RL- and the positive electrode side grounding resistor RL + corresponding to the negative electrode side grounding resistor RL- the voltage across the high-voltage power source V operation is divided by V ₀ and _{(V RL- + V RL + /} V 0) performed. Next, the microcomputer 20 calculates the ground fault resistance of the power source 3 with reference to the calculation value versus ground fault resistance conversion table stored in advance in the internal memory based on the calculated value.

Thus, the microcomputer 20 controls the semiconductor switch elements 1b, 2b, 11b, and 12b as the first to fourth switches, respectively, and the voltage V _{0 corresponding to} the both-ends voltage V ₀ of the power source 3 and the positive-side ground fault resistance RL +. Every time the capacitor 9 is charged with the voltage V _RL− according to _{RL +} and the negative side ground fault resistance RL−, the voltage _across the capacitor 9 at that time is read by the microcomputer 20 to detect the insulation state of the power supply 3. Can do.

  In addition, when the microcomputer 20 or the NAND gate elements 6a, 6b, 16a, 16b malfunctions, the semiconductor switch elements 1b and 2b and 11b and 12b do not turn on at the same time, so there is no possibility of erroneous detection.

  As described above, the best mode of the present invention has been described, but the present invention is not limited to this, and various modifications and applications are possible.

  For example, in the above-described embodiment, the NAND gate element is used. However, the present invention is not limited to this, and other logic elements may be used.

  Moreover, in the above-mentioned embodiment, although the semiconductor relay is used, this invention is not limited to this, A mechanical relay can also be used.

  FIG. 4 is a circuit diagram showing another embodiment of the simultaneous ON prevention circuit for the relay of the relay driving apparatus when a mechanical relay is used. 4 uses two mechanical relays 21 and 22 in place of the semiconductor relays 1 and 2 in FIG.

  The mechanical relay 21 has an exciting coil 21a and a contact 21b. The mechanical relay 21 further includes a diode 21c connected in series to the exciting coil 21a. Similarly, the mechanical relay 22 has an exciting coil 22a and a contact 22b. The mechanical relay 22 further includes a diode 22c connected in series to the exciting coil 22a. The mechanical relays 21 and 22 function as one-way energization drive type relays with the above-described configuration.

  The cathode of the diode 21c and the anode of the diode 22c are connected to the output terminal of the NAND gate element 6a. The exciting coils 21a and 22a are connected to the output terminal of the NAND gate element 6b via the current limiting resistor R1. That is, the diodes 21c and 22c are reversely connected to each other between the output terminals of the NAND gate elements 6a and 6b.

  In the above configuration, during normal operation, when the control signal output terminal P1 of the control unit 3 becomes H level due to the output of the pulse control signal and the control signal output terminal P2 becomes L level, the output of the NAND gate element 6a The terminal becomes L level, and the output terminal of the NAND gate element 6b becomes H level. Accordingly, a current flows through the exciting coil 21a of the mechanical relay 21, so that the contact 21b is turned on. However, no current flows through the exciting coil 22a of the mechanical relay 22, and the contact 22b is turned off.

  On the other hand, when the control signal output terminal P1 of the control unit 3 is at L level and the control signal output terminal P2 is at H level, the output terminal of the NAND gate element 6b is at L level, and the output terminal of the NAND gate element 6a. Becomes H level. Accordingly, since a current flows through the excitation coil 22a of the mechanical relay 22, the contact 22b is turned on, but no current flows through the excitation coil 21a of the mechanical relay 21, and the contact 21b is turned off.

  On the other hand, at the time of abnormal operation in which both the control signal output terminals P1 and P2 of the control unit 3 become H level or L level due to a malfunction or runaway of the microcomputer, the output terminals of the NAND gate elements 6a and 6b are both L level or Becomes H level. Accordingly, since no current flows through the exciting coils 21a and 22a, both the contacts 21b and 22b are turned off. In this manner, the mechanical relays 21 and 22 are prevented from being simultaneously turned on during abnormal operation of the control unit 3 due to a malfunction of the microcomputer or runaway.

  Further, when the output terminals of the NAND gate elements 6a and 6b both become L level or H level due to a failure of one or both of the NAND gate elements 6a and 6b, the excitation coils 21a and 22a are connected to the exciting coils 21a and 22a as described above. Since no current flows, both the contacts 21b and 22b are turned off. Accordingly, the mechanical relays 21 and 22 are prevented from being simultaneously turned on even during an abnormal operation such as a failure of one or both of the NAND gate elements 6a and 6b.

  In the above description, the diodes 22 c and 22 c are incorporated in the mechanical relays 21 and 22, but may be external diodes that are not incorporated in the mechanical relays 21 and 22.

1 Semiconductor relay (one-way energization drive type relay)
1a LED
1b Semiconductor switch element 2 Semiconductor relay (one-way energization drive type relay)
2a LED
2b Semiconductor switch element 3 Control part (drive control means)
6a NAND gate element (first logic element)
6b NAND gate element (second logic element)
21 Mechanical relay (one-way energization drive type relay)
22 Mechanical relay (one-way energization drive type relay)

Claims (2)

In a relay drive device comprising two unidirectional energization drive type relays and drive control means for outputting two pulse control signals inputted to the two unidirectional energization drive type relays, respectively.
The two pulse control signals from the drive control means are high level or low level signals respectively output, and when one is high level, the other is controlled to be low level,
Each of the two one-way energization drive type relays has one signal line that needs to be prevented from being turned on simultaneously,
The first and second pulse control signals from the drive control means are respectively input to both connection points where the two one-way energization drive relays are connected in opposite directions. An output terminal of the logic element is connected to the relay on-relay circuit for the relay of the relay drive device. In the relay simultaneous ON prevention circuit of the relay drive device according to claim 1,
The one-way energization drive type relay is a semiconductor relay including an LED to which the drive output signal is supplied and a semiconductor switch element inserted into the signal line and controlled to be turned on / off based on an optical signal from the LED. The simultaneous ON prevention circuit of the relay of the relay drive device characterized by this.

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