JP2013200906A - Semiconductor memory device and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of speeding up a data read operation or a data write operation.SOLUTION: A semiconductor memory device is provided with memory banks including nonvolatile memory cells. The buffers are provided corresponding to the memory banks, respectively and can temporarily store data of the memory banks when writing or reading data. A sense amplifier detects the data of the memory cells via a selected bit line. A multiplexer selectively connects one of bit lines to the sense amplifier. A flag register stores a window flag that inhibits changing of a column address that specifies a bit line. A controller activates the window flag during a read latency period for reading data from the memory cells to the buffers. The controller inactivates the window flag after the read latency period.

Description

  Embodiments described herein relate generally to a semiconductor memory device and a driving method thereof.

  A nonvolatile memory such as an MRAM (Magnetic Random Access Memory) uses a current detection type sense amplifier. Since the current detection type sense amplifier has a large area, the multiplexer selectively connects the column address CSL (bit line or bit line pair) in the memory block to the sense amplifier. Therefore, when changing the column address CSL in the same memory block in data reading or data writing, it is necessary to switch the column address CSL by an active command after the precharge period has elapsed. Therefore, it takes a long time for the data reading operation and the data writing operation.

Japanese Patent Laid-Open No. 08-339686

  Provided is a semiconductor memory device capable of speeding up a data read operation or a data write operation.

  The semiconductor memory device according to the present embodiment includes a plurality of memory banks including a plurality of nonvolatile memory cells. The plurality of buffers are provided corresponding to each of the plurality of memory banks, and temporarily store data in the memory banks at the time of data writing or data reading. The plurality of bit lines and the plurality of word lines are connected to a plurality of memory cells. The sense amplifier detects data in the memory cell via a bit line selected from a plurality of bit lines. The multiplexer selectively connects one of the plurality of bit lines to the sense amplifier. The flag register stores a window flag that prohibits the change of the column address designating the bit line. The controller activates the window flag during a read latency period in which data is read from the memory cell to the buffer. The controller deactivates the window flag after the read latency period.

1 is a block diagram showing a configuration of an MRAM according to a first embodiment. 3 is an explanatory diagram showing a configuration of a single memory cell MC. FIG. The conceptual diagram which shows an example of a structure of several memory bank BK. FIG. 4 is a block diagram showing the configuration and read operation of an address sequencer ADDSEQ, a flag latch unit FL, a memory bank BK, and a page buffer WRB. FIG. 5 is a timing chart showing a data read operation of the MRAM according to the present embodiment. FIG. 5 is a timing chart showing a data read operation of the MRAM according to the present embodiment. The figure which shows the flag state in the data read-out operation | movement of MRAM according to this embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the MRAM according to the first embodiment. The MRAM according to the present embodiment includes a memory bank BK, a command / address receiver CAR, a command controller COMCNT, a data buffer DQB, and an input / output unit I / O.

  The memory bank BK includes, for example, a memory cell array MCA including a plurality of memory cells MC that are two-dimensionally arranged in a matrix. Each memory cell MC is connected to a bit line pair (for example, bit line BL1 and bit line BL2 as shown in FIG. 1) and a word line WL. That is, one end of the memory cell MC is connected to one bit line BL1 of the bit line pair, and the other end is connected to the other bit line BL2 of the bit line pair. The bit line pair BL1, BL2 extends in the column direction. The word line WL extends in the row direction orthogonal to the column direction.

  The memory bank BK further includes a sense amplifier SA, a write driver WD, a column decoder CD, a row decoder RD, a main controller MCNT, and a write read page buffer WRB (hereinafter also simply referred to as a page buffer WRB). I have.

  For example, the sense amplifier SA is connected to the memory cell MC via the bit line BL1 and has a function of detecting data in the memory cell MC. The bit line BL2 is connected to a reference voltage (ground). The write driver WD is connected to the memory cell MC via, for example, the bit line BL1, and has a function of writing data to the memory cell MC.

  The multiplexer MUX connects the bit line selected by the column address CSL among the plurality of bit lines BL (a plurality of bit line pairs) to the sense amplifier SA.

  The command / address receiver CAR receives a command, an address, and a clock that determine the operation of the memory bank BK. The command / address receiver RCA receives, for example, a bank address, a column address, a row address, and the like as an address. The command / address receiver RCA receives, for example, an active command, a write command, a read command, and a reset command as commands. With these commands, the memory bank BK can execute various operations.

  The command controller CMDC receives commands indicating various operations such as a read operation and a write operation, and controls the main controller MCNT in accordance with those commands.

  The main controller MCNT transfers the data received from the input / output unit I / O and the DQ buffer DQB to the write driver WD so as to write to the memory bank according to the address, or reads the data read from the memory bank according to the address to the input / output unit The entire memory bank BK is controlled to be transferred to the I / O and DQ buffer DQB.

  The column decoder CD is configured to select a bit line pair of a certain column according to the column address. The row decoder RD selects the word line WL according to the row address.

  The page buffer WRB temporarily stores write data input via the input / output unit I / O and the data buffer DQB, or temporarily stores read data from the memory cell MC.

  The data buffer DQB outputs read data to the outside via the input / output unit I / O or transfers the write data taken from the outside via the input / output unit I / O to the inside. Hold temporarily.

  In FIG. 1, one memory bank BK is shown. However, normally, a plurality of memory banks BK are two-dimensionally arranged in a matrix.

  FIG. 2 is an explanatory diagram showing a configuration of a single memory cell MC. Each memory cell MC includes a magnetic tunnel junction element (MTJ (Magnetic Tunnel Junction) element) and a cell transistor CT. The MTJ element and the cell transistor CT are connected in series between the bit line BL1 and the bit line BL2. In the memory cell MC, the cell transistor CT is disposed on the bit line BL2 side, and the MTJ element is disposed on the bit line BL1 side. The gate of the cell transistor CT is connected to the word line WL.

  An MTJ element using the TMR (tunneling magnetoresistive) effect has a laminated structure composed of two ferromagnetic layers and a nonmagnetic layer (insulating thin film) sandwiched between them, and exhibits magnetoresistance due to the spin-polarized tunnel effect. Stores digital data with changes. The MTJ element can take a low resistance state and a high resistance state depending on the magnetization arrangement of the two ferromagnetic layers. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element. Of course, the low resistance state may be defined as data “1”, and the high resistance state may be defined as data “0”. For example, the MTJ element is configured by sequentially laminating a fixed layer P, a tunnel barrier layer B, and a recording layer Fr as shown in FIG. The fixed layer P and the recording layer Fr are made of a ferromagnetic material, and the tunnel barrier layer B is made of an insulating film. The fixed layer P is a layer whose magnetization direction is fixed, and the recording layer Fr has a variable magnetization direction, and stores data according to the magnetization direction.

  When a current equal to or greater than the reversal threshold current is passed in the direction of the arrow A1 during writing, the recording layer Fr is in an anti-parallel state with respect to the magnetization direction of the fixed layer P, and is in a high resistance state (data “1”). When a current equal to or greater than the inversion threshold current is passed in the direction of the arrow A2 at the time of writing, the magnetization directions of the fixed layer P and the recording layer Fr are in a parallel state and a low resistance state (data “0”). Thus, the TMJ element can write different data depending on the direction of current.

  FIG. 3 is a conceptual diagram showing an example of the configuration of the plurality of memory banks BK. The memory banks BK having the same address are included on the left side and the right side in FIG. 3, and two memory banks BK having the same address can be accessed simultaneously. For example, in the memory bank BK0L on the left side and the memory bank BK0L on the right side, the bank address BK0, the bank address BK1, and the column address AC5 are all “0”.

  Similarly, when the bank address BK0, the bank address BK1, and the column address AC5 are “0”, “1”, and “0”, respectively, the memory bank BK2L on the left side and the memory bank BK2L on the right side are selected. The

  Thus, by designating the bank address BK0, the bank address BK1, and the column address AC5, one from each of the plurality of memory banks BK0L to BK3U on the left side and the plurality of memory banks BK0L to BK3U on the right side. The memory bank BK can be selected simultaneously. That is, the left memory bank BK0L and the right memory bank BK0L having the same address can be accessed simultaneously. The selected memory bank BK is subjected to a data read operation or a data write operation.

  Each of the memory banks BK0L to BK3U includes a page buffer WRB, and can temporarily store read data and / or write data. For example, each of the memory banks BK0L to BK3U has 16 pages (32 bits / page) in each column. That is, the page buffer WRB of each of the memory banks BK0L to BK3U can store 512-bit data. Therefore, the page buffer WRB of each of the memory banks BK0L to BK3U has a capacity capable of temporarily storing data of all pages of a certain column of the corresponding memory bank.

  As shown in FIG. 3, each of the memory banks BK0L to BK3U is divided into an UPPER array and a LOWER array, and each of the UPPER array and the LOWER array stores 8 pages of data.

  Each of the memory banks BK0L to BK3U includes a sense amplifier SA and a write driver WD corresponding to the UPPER array and the LOWER array, respectively. The sense amplifier SA can read data from the UPPER array or the LOWER array via the multiplexer MUX, or the write driver WD can write data to the UPPER array or the LOWER array via the multiplexer.

  FIG. 4 is a block diagram showing the configuration and read operation of address sequencer ADDSEQ, flag latch unit FL, memory bank BK, and page buffer WRB. The address sequencer ADDSEQ receives clock signals CK_t and CK_c and a command / address signal CA <9: 0> from the outside, decodes these signals, and sends them to the flag latch unit FL, the memory bank BK or the page buffer WRB. <9: 0> represents an integer of 0 to 9.

  ACR_BK0 to ACR_BK3 are a bank address and a column address. DELAYED_ACCR_BK0 to DELAYED_ACCR_BK3 are page addresses. The signals DELAYED_LATEST_BK0 to DELAYED_LATEST_BK3 are signals for setting or resetting the state of the flag of the flag latch unit FL based on commands and addresses such as an active command, a read command, a write command, a bank address, a column address, and a page address. The signals DELAYED_LATETEST_BK0 to DELAYED_LATEST_BK3 may be added as additional bits to an active command, a read command, or a write command that is input when data is read or written. Thus, the main controller MCNT can set the flag state of the flag latch unit FL when receiving an active command, a read command, or a write command.

  Each memory cell array MCA of the memory banks BK0 to BK3 receives the bank address and column addresses ACR_BK0 to ACR_BK3 from the address sequencer ADDSEQ, respectively, and sends the data of the selected column to the corresponding page buffer WRB.

  Each page buffer WRB of the memory banks BK0 to BK3 receives the page address DELAYED_ACCR_BK0 to DELAYED_ACCR_BK3 from the address sequencer ADDSEQ, and outputs data DQ from the selected page.

  The flag latch unit FL includes flag latch circuits FLAG_BK0 to FLAG_BK3 corresponding to the memory banks BK0 to BK3. The flag latch circuits FLAG_BK0 to FLAG_BK3 include latch circuits corresponding to the read flag READ_FLAG, the write flag WRITE_FLAG, the CSL window flag CSL_WINDOW, and the unlock flag UNLOCK_FLAG, respectively. In FIG. 4, these latch circuits are shown in a simplified manner.

  The read flag READ_FLAG is a flag activated (rises) in the data read operation, and is activated when a read command READ_COM instructing the data read operation is received.

  The write flag WRITE_FLAG is a flag activated (rises) in the data write operation, and is activated when a write command WRITE_COM instructing the data write operation is received.

  Normally, in the MRAM, a data mask unit for prohibiting data writing is different from a data writing unit (ECC (Error Correction Code) unit). For example, the MRAM includes an ECC every 64 bits and performs data masking in units of 32 bits. In this case, the sense amplifier SA needs to once read data of a certain page to which data is written into the page buffer WRB. At the time of reading to the page buffer WRB, the data is corrected using the ECC, and then the page buffer WRB stores the data. For this reason, the data write operation and the data read operation cannot be distinguished only by the read command READ_CMD. Therefore, in order to distinguish between the data write operation and the data read operation, a write flag WRITE_FLAG indicating that the write command WRITE_COM is received is provided. For example, when the MRAM receives both the read command READ_CMD and the write command WRITE_CMD, it is understood that the data write operation is performed. When the MRAM receives only the read command READ_CMD and does not receive the write command WRITE_CMD, it is understood that the data read operation is performed.

  The CSL window flag CSL_WINDOW is a flag indicating a CSL window that prohibits the change of the column address CSL. A period during which the CSL window flag CSL_WINDOW is activated is a CSL window period, and is a period during which the change of the column address CSL is prohibited. The main controller MCNT activates the CSL window flag CSL during the period of the read latency RLT, and deactivates the CSL window flag CSL after the end of the read latency RLT.

  The unlock flag UNLOCK_FLAG is a flag indicating whether or not the column address CSL can be changed. The main controller MCNT deactivates the unlock flag UNLOCK_FLAG during the read latency RLT, and activates the unlock flag UNLOCK_FLAG after the read latency RLT ends. Changing the column address CSL is permitted when the unlock flag UNLOCK_FLAG is activated.

  Whether the column address CSL can be changed can be determined from either or both of the CSL window flag CSL_WINDOW and the unlock flag UNLOCK_FLAG. Therefore, either the CSL window flag CSL_WINDOW or the unlock flag UNLOCK_FLAG may be omitted.

  In the data read operation and data write operation, when the unlock flag UNLOCK_FLAG is in an inactive state, the main controller MCNT prohibits the change of the column address CSL in the corresponding memory bank among the memory banks BK0 to BL3, To do. In the data read operation and data write operation, when the unlock flag UNLOCK_FLAG is in the active state, the corresponding memory bank among the memory banks BK0 to BL3 is allowed to change the column address CSL and is set to the unlock state.

  Hereinafter, a period in which the unlock flag UNLOCK_FLAG is in an inactive state and the CSL window flag CSL_WINDOW is in an active state is referred to as a “CSL window”. During the period of the CSL window, change of the column address CSL is prohibited. The MRAM according to the present embodiment enables a safe column address CSL change by monitoring the CSL window.

  Generally, in the MRAM, a precharge period is required when changing a column address. The precharge period is a period for changing the row address, and the column address CSL can be changed after the row address is changed (after the precharge period has elapsed). In order to change the row address, it is necessary to charge the word line specified by the row address. For this reason, a precharge period (tRAS-CAS) is required. Therefore, conventionally, the column address CSL can only be changed after the precharge period.

The MRAM according to the present embodiment clearly defines the period of the read latency RLT in which the change of the column address (CSL) is prohibited by providing a CSL window. Thereby, the change of the column address is permitted after the read latency RLT has elapsed. The column address changeable period T _CSL is a period from the end of the CSL window to the start of the next CSL window. In the column address changeable period _TCSL , the main controller MCNT changes the column address without executing precharge, that is, without changing the row address.

  5 and 6 are timing charts showing the data read operation of the MRAM according to the present embodiment. FIG. 7 is a diagram showing a flag state in the data read operation of the MRAM according to the present embodiment. FIG. 5 shows a sequence SEQ1 in which another command is issued after the CSL window. FIG. 6 shows a sequence SEQ2 in which another command is issued in the CSL window. FIG. 7 shows the flag states of sequences SEQ1 and SEQ2. In FIG. 7, a filled square indicates that the command or flag is in an inactive state, and an unfilled square indicates that the command or flag is in an active state.

  In the following description, it is assumed that the column address CSL <1> is selected after the column address CSL <0> in the memory bank BK0L is selected. The MRAM according to the present embodiment operates according to the clock signals CK_t and CK_c.

  First, the sequence SEQ1 shown in FIG. 5 will be described. At T0, the MRAM receives an active command (not shown) and a read command READ_CMD. When an active command is received, a bank address and a row address are received, and when a read command READ_CMD is received, a bank address and a column address CA <9: 0> are received.

  Here, the data read target bank is the memory bank BK0L, and the data read target column is the column CLS <0> of the memory bank BK0L. In the following, only the operation of the left memory bank BK0L in FIG. 3 has been described, but as described above, the same operation is performed for the right memory bank BK0L in FIG. Further, by changing the addresses BK0 and AC5, other memory banks can operate in the same manner.

  After the read command READ_CMD, the MRAM has not received the write command WRITE_CMD. That is, as shown in FIG. 7, the write flag WRITE_FLAG is inactive when the read command READ_CMD is issued. Therefore, the sequence SEQ1 is a data read operation.

  During the period of read latency RLT from T0 to T8, data in the memory cell array MCA in the memory bank BK0L is read to the page buffer WRB. Page buffer read signals PBR_LTC <0> to PBR_LTC <7> are signals that are activated when data is read from the memory cell array MCA to the page buffer WRB. When page buffer read signal PBR_LTC <i> is activated, data of page <i> is read from memory cell array MCA to page buffer WRB out of 8 pages on the UPPER side and LOWER side of memory bank BK0L. . In the period of the read latency RLT, the data of the selected page in the memory bank BK0L is read from the memory cell array MCA to the page buffer WRB.

  Since data is read from the memory cell array MCA of the memory bank BK0L to the page buffer WRB during the read latency RLT, the column address CSL of the memory bank BK0L cannot be changed. Accordingly, at T0 to T8, the CSL window flag CSL_WINDOW is set to the active state, and the unlock flag UNLOCK_FLAG is set to the inactive state. The inactive state of the unlock flag UNLOCK_FLAG is also shown in FIG.

  Here, in sequence SEQ1, no other read command or write command is issued in the CSL window flag CSL_WINDOW. Therefore, as shown in FIG. 7, READ_CMD / WRITE_CMD in the CSL window flag CSL_WINDOW is in an inactive state.

  It should be noted that the READ_CMD / WRITE_CMD flag in the CSL window flag CSL_WINDOW may be added to the flag latch unit FL in FIG. Alternatively, when READ_CMD / WRITE_CMD is issued in the CSL window flag CSL_WINDOW, the CSL window is reset as in sequence SEQ2 described later, so the CSL window flag CSL_WINDOW is deactivated and the unlock flag UNLOCK_FLG is activated. You can just do it.

When the read latency RLT ends at T8 shown in FIG. 5, the CSL window flag CSL_WINDOW is deactivated and the unlock flag UNLOCK_FLAG is activated. As a result, the CSL window ends, and the memory bank BK0L enters the CSL changeable period T _CSL .

In the CSL changeable period _TCSL , the MRAM changes the column address CSL (bit line BL) without changing the row address (word line WL). Since the row address is not changed, an active command and a precharge period become unnecessary. As described above, in the MRAM according to the present embodiment, the column address CSL can be changed without changing the row address in the _CSL changeable period _TCSL , and the precharge period is omitted. In order to omit the precharge period, a CSL window is provided, and the change of the column address CSL is prohibited during the period of the CSL window. Thus, in the present embodiment, since the change of the column address CSL is prohibited during the CSL window period, it is not necessary to issue a precharge command for changing the column address CSL as in the prior art.

  Next, the sequence SEQ2 shown in FIG. 6 will be described. The operation of the MRAM from T0 to T5 in the sequence SEQ2 is the same as the operation of the MRAM from T0 to T5 in the sequence SEQ1.

  Thereafter, in sequence SEQ2, another read command READ_CMD for the memory bank BK0L is issued at T6 during the period of the CSL window.

  In this case, the main controller MCNT resets the CSL window. That is, by resetting the CSL window, the column address CSL can be changed and the CSL window is started again. For example, the read command READ_CMD issued at T6 includes the column address CSL <1>. Thereby, when the CSL window is reset, the column address CSL is changed from CSL <0> to CSL <1>. Then, a new CSL window is set from T6. This new CSL window ends at the end of the read latency RLT at T14. During the period of the CSL window (T12 to T13), the data of the selected page of the memory bank BK0L is read from the memory cell array MCA to the page buffer WRB.

In T14~T17, MRAM enters the CSL change period _{T CSL.} Further, after the read latency RLT ends (after data is read from the memory cell array MCA to the page buffer WRB in the memory bank BK0L), the read data is output to the outside. The data output at this time is the data of the column address CSL <1>.

In the CSL changeable period _TCSL , the MRAM can change the column address CSL without changing the row address in the _CSL changeable period _TCSL , and omits the precharge period.

  As described above, when the MRAM according to the present embodiment receives the read command READ_CMD of the same memory bank BK0L during the period of the CSL window, the MRAM resets the CSL window and starts a new CSL window. That is, as shown in FIG. 7, the main controller MCNT once activates the unlock flag UNLOCK_FLAG, and after changing the column address, sets the unlock flag UNLOCK_FLAG corresponding to the new CSL window again. In other words, the main controller MCNT once resets the CSL window flag to the inactive state, changes the column address, and then sets the CSL window flag to the active state again. As a result, the MRAM can safely read data corresponding to the new read command READ_CMD.

  Even when a write command for the same memory bank BK0L is received during the CSL window, the main controller MCNT resets the CSL window. As a result, the MRAM can safely write data corresponding to the new write command.

  By providing the CSL window, the MRAM according to the present embodiment can read data without destroying data while changing the column address CSL without performing precharge. As a result, since it is not necessary to provide a precharge period when changing the column address CSL, data can be read at a high speed while changing the column address CSL.

  When changing the row address, an active command and a precharge period are required.

  The above embodiment is an embodiment related to a data read operation. However, the above embodiment can be applied to a data write operation. In the data write operation, the main controller MCNT may set the CSL window during the write latency period in which data is written from the page buffer WRB to the memory cell array MCA. This speeds up the data write operation.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

BL ... bit line, WL ... word line, BK ... memory bank, CAR ... command / address receiver, MCNT ... main controller, DQB ... data buffer, I / O ... Input / output unit, MCA ... memory cell array, SA ... sense amplifier, WD ... write driver, CD ... column decoder, RD ... row decoder, WRB ... page buffer, MUX ... Multiplexer, ADDSEQ ... Address sequencer, FL ... Flag latch

Claims (6)

A plurality of memory banks including a plurality of nonvolatile memory cells;
A plurality of buffers provided corresponding to each of the plurality of memory banks, and temporarily storing data of the memory banks at the time of data writing or data reading;
A plurality of bit lines and a plurality of word lines connected to the plurality of memory cells;
A sense amplifier that detects data of the memory cell via a bit line selected from the plurality of bit lines;
A multiplexer that selectively connects any of the plurality of bit lines to the sense amplifier;
A flag register for storing a window flag for prohibiting a change in a column address specifying the bit line;
A controller for controlling the state of the window flag,
The controller activates the window flag during a read latency period for reading data from the memory cell to the buffer, and deactivates the window flag after the read latency period. Storage device.   The flag register further stores a read flag indicating whether or not a read command for instructing data reading is received and a write flag indicating whether or not a write command for instructing data writing is received. Item 14. The semiconductor memory device according to Item 1.   The semiconductor memory device according to claim 1, wherein the flag register further stores an unlock flag indicating whether the column address can be changed.   4. The window flag according to claim 1, wherein the window flag is set by an additional bit added to a read command for instructing data reading or a write command for instructing data writing. Semiconductor memory device.   When the controller receives another read command or another write command for the first memory bank during a period in which the window flag corresponding to the first memory bank is active, the window flag 2. The window flag is reset to an active state after the column address is changed in accordance with the other read command or the other write command, and the window flag is reset to an active state. 5. The semiconductor memory device according to any one of 4. A plurality of memory banks including a plurality of nonvolatile memory cells, a plurality of buffers provided corresponding to each of the plurality of memory banks, and temporarily storing data of the memory banks at the time of data writing or data reading; A plurality of bit lines and a plurality of word lines connected to the plurality of memory cells; a sense amplifier for detecting data in the memory cells via a bit line selected from the plurality of bit lines; A multiplexer that selectively connects one of the bit lines to the sense amplifier, a flag register that stores a window flag that prohibits a change in a column address that specifies the bit line, and a controller that controls the state of the window flag; In a method for driving a semiconductor memory device comprising:
During the read latency period of reading data from the memory cell to the buffer, the window flag is activated,
A method for driving a semiconductor memory device, comprising: bringing the window flag into an inactive state after the read latency period.

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