JP2013254858A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent or suppress energization degradation phenomenon without reducing the surge withstand capability of a JBS diode, in a semiconductor device using a silicon carbide substrate.SOLUTION: In a semiconductor device provided with a vertical JBS diode in a substrate in which an ndrift layer 2 composed of silicon carbide is formed in an upper layer of an nsubstrate 1 composed of silicon carbide, a first nregion 2a in Schottky-contact with an anode electrode 11, second p regions 4 in Schottky-contact with the anode electrode 11, and first p regions 3 in Ohmic-contact with the anode electrode 11 in a surface of the ndrift layer 2. Additionally, the second p region 4 and second nregion 2b are disposed in order from the first nregion 2a between the first nregion 2a and the first p region 3. An insulating layer 9a is formed on surfaces of the second nregions 2b, and the anode electrode 11 and the second nregions 2b are insulated and isolated.

Description

  The present invention relates to a semiconductor device using a silicon carbide substrate and a method for manufacturing the same, and in particular, a junction barrier Schottky diode (Junction Barrier Schottky diode: hereinafter referred to as JBS) that combines a Schottky Barrier diode and a pn diode. The present invention relates to a technology effective when applied to a semiconductor device provided with a diode) on a silicon carbide substrate and a manufacturing method thereof.

  Since the breakdown field of silicon carbide (SiC) is about 10 times larger than the breakdown field of silicon (Si), the SiC diode has a thinner drift layer that maintains the breakdown voltage than the Si diode. In addition, the concentration can be increased. Therefore, the recovery loss at the time of switching is smaller than that of the pn diode, and a Schottky barrier diode having the same conduction loss as that of the pn diode can be manufactured.

The pn diode has a larger recovery loss than the Schottky barrier diode because holes, which are minority carriers, are injected into the n drift layer when conducting. For example, Non-Patent Document 1 discloses that a lifetime of holes in a 4H-SiC diode with a withstand voltage of 5.5 kV is 0.6 to 3.8 μs (300 to 550 K), and a diffusion length of holes is 16 to 22 μm (impurity concentration 6). X10 ¹⁴ cm ⁻³ ).

By the way, although the Schottky barrier diode has a small recovery loss, there is a problem that the reverse leakage current in the blocking state is large. Therefore, a semiconductor device called a JBS diode has been proposed for the purpose of reducing reverse leakage current. In a JBS diode, for example, a plurality of p-type silicon carbide regions (hereinafter referred to as p-regions) are formed on the surface of a drift layer made of n-type silicon carbide provided on a substrate made of n-type silicon carbide. It is provided in a separated state. An anode electrode that is in ohmic contact with a plurality of p regions and in Schottky contact with the drift layer is provided on the surface of the drift layer, and a cathode electrode is provided on the back surface of the substrate. Since the concentration of the n-type impurity added to the drift layer is lower than the concentration of the n-type impurity added to the substrate, the substrate is referred to as an n ⁺ substrate and the drift layer is referred to as an n ⁻ drift layer.

In this JBS diode, in a forward conduction state in which a positive voltage is applied to the anode electrode, current flows from the anode electrode to the n ⁻ drift layer in Schottky contact, and operates as a Schottky barrier diode. On the other hand, in the blocking state in which a positive voltage is applied to the cathode electrode, the depletion layer extending from the p region relaxes the electric field applied to the Schottky contact surface between the n ⁻ drift layer and the anode electrode and reverse leakage The current is reduced.

By the way, in the forward conduction state, a forward voltage is also applied between the junction of the p region and the n ⁻ drift layer, so that holes are injected from the p region into the n ⁻ drift layer. Usually, when a forward voltage of, for example, about 2.6 V or more is applied between the junction of the p region and the n ⁻ drift layer, a large amount of holes are injected. However, since the structure is usually designed so that a large amount of holes are not injected, the holes injected from the p region into the n ⁻ drift layer do not affect the recovery current at the time of switching.

However, n ^- holes are injected into the drift layer, n ^- stacking fault in the basal plane dislocation that exists in the drift layer and the electrons and holes the recombination, which by the released energy, and the basal plane dislocations and the core Will grow. The stacking fault forms an energy level below 0.2 eV of the conduction band edge of 4H—SiC (see, for example, Non-Patent Document 2), and the on-state voltage increases with time due to the growth of the stacking fault. There arises a problem that the direction leakage current also increases with time. This phenomenon is a phenomenon observed in a compound semiconductor such as silicon carbide, and is referred to as an energization deterioration phenomenon. The energization deterioration phenomenon in the JBS diode is particularly noticeable in a high breakdown voltage diode having a high on-voltage. This is because, when the ON voltage is high, the p region and the n ^- large voltage across the junction between the drift layer is applied, the p region n ^- is because holes are injected into the drift layer easily.

Thus, for example, Patent Document 1 discloses a method of suppressing the above-described deterioration phenomenon of energization in a JBS diode by making the anode electrode and the p region into Schottky contact. In a forward conduction state in which a positive voltage is applied to the anode electrode, a reverse voltage is applied between the junction between the anode electrode and the p region, and sufficient between the junction between the p region and the n ⁻ drift layer. Since no voltage is applied, holes are not injected from the p region into the n ⁻ drift layer.

  Further, for example, in Non-Patent Document 3, when a direct current (DC) stress is applied to a 1.2 kV withstand voltage JBS diode and a 3.5 kV withstand voltage JBS diode in the forward direction, it is turned on in the 3.5 kV withstand voltage JBS diode. It has been disclosed that an increase in voltage and an increase in reverse leakage current occurred, but these deteriorations did not occur in a 1.2 kV JBS diode.

Special table 2008-541459 gazette

PA Ivanov, ME Levinshtein, KG Irvine, O. Kordina, JW Palmour, SL Rumyantsev, and R. Singh, “High hole lifetime (3.8μs) in 4H-SiC diodes with 5.5kV blocking voltage,” Electronics Letters, 1999. Vol. 35, No. 16, p. 1382 to 1383 A. Galeckas, J. Linnros, and P. Pirouz, “Recombination-enhanced extension of stacking faults in 4H-SiC p-i-ndiodes under forward bias,” Applied Physics Letters, 2002, Vol. 81, No. 5, p. 883-885 P. Brosselard, N. Camara, V. Banu, X. Jorda, M. Vellvehi, P. Godignon, and J. Millan, “Bipolar Conduction Impact on Electrical Characteristics and Reliability of 1.2- and 3.5-kV 4H-SiC JBS Diodes IEEE Transactions on Electron Devices, 2008, Vol. 55, No. 8, p. 1847-1856

  However, in order to avoid the current deterioration phenomenon, in the method described in Patent Document 1 in which the anode electrode and the p region are in Schottky contact, holes are not injected from the p region into the drift layer. Does not occur, and there is a problem that the surge resistance is low. When the potential difference between the anode electrode and the cathode electrode becomes large without conductivity modulation when a surge current larger than that during normal operation flows instantaneously, the JBS diode itself or the JBS diode is electrically connected. Insulated Gate Bipolar Transistor (IGBT), which is a power system element, may be destroyed.

  An object of the present invention is to provide a technique capable of suppressing or preventing a current deterioration phenomenon in a semiconductor device using a silicon carbide substrate without reducing the surge resistance of a JBS diode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a typical embodiment is a semiconductor device in which a vertical diode is provided on a silicon carbide substrate, and the second conductive material is in ohmic contact with the anode electrode on the surface side of the first conductive silicon carbide substrate. A first region of the mold, a second region of the second conductivity type that makes a Schottky contact with the anode electrode, a third region of the first conductivity type that makes a Schottky contact with the anode electrode, and adjacent to the first region and the second region A fourth region of the first conductivity type disposed between them is provided, and a second region and a fourth region are disposed between the first region and the third region.

  Also, a method of manufacturing a semiconductor device according to a typical embodiment includes a semiconductor made of silicon carbide of a first conductivity type having a lower impurity concentration than that of the substrate formed on the substrate made of silicon carbide of the first conductivity type. Forming a plurality of first regions of a second conductivity type different from the first conductivity type on the surface side of the layer in a state of being separated from each other; and a plurality of second regions of a second conductivity type on the surface side of the semiconductor layer. Forming two regions in a state of being separated from each other, forming a third region of the first conductivity type adjacent to the second region, making ohmic contact with the first region, and the second region And forming an anode electrode in Schottky contact with the third region, forming a fourth region of the first conductivity type between the first region and the second region, and Between the region and the third region, the second region and the fourth region. It is characterized in further comprising the step of forming and.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  In a semiconductor device using a silicon carbide substrate, the energization deterioration phenomenon can be suppressed or prevented without reducing the surge resistance of the JBS diode.

1 is an overall plan view of a JBS diode chip according to a first embodiment of the present invention. It is sectional drawing of the II line | wire of FIG. It is sectional drawing of the II-II line of FIG. It is a circuit diagram of the JBS diode chip of FIG. FIG. 2 is a fragmentary cross-sectional view of the JBS diode chip of FIG. 1 during the manufacturing process. FIG. 6 is a fragmentary cross-sectional view of the JBS diode chip during the manufacturing process following that of FIG. 5; FIG. 7 is a fragmentary cross-sectional view of the JBS diode chip during a manufacturing step following that of FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the JBS diode chip during the manufacturing process following that of FIG. 7; It is principal part sectional drawing of the same location as FIG. 2 of the JBS diode chip | tip of Embodiment 2 of this invention. It is a whole top view of the JBS diode chip of Embodiment 3 of the present invention. It is sectional drawing of the III-III line of FIG. It is a principal part top view of the active area | region of the JBS diode chip of Embodiment 4 of this invention. It is sectional drawing of the IV-IV line of FIG. FIG. 13 is a fragmentary cross-sectional view of the JBS diode chip of FIG. 12 during a manufacturing step. FIG. 15 is a fragmentary cross-sectional view of the JBS diode chip during a manufacturing step following that of FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the JBS diode chip during the manufacturing step following that of FIG. 15; FIG. 17 is an essential part cross-sectional view of the JBS diode chip during a manufacturing step following that of FIG. 16; It is the whole JBS diode chip top view which showed the modification of the plane shape of the 1st p field which is in ohmic contact with an anode electrode. It is principal part sectional drawing of the active area | region of the JBS diode before this invention examined by this inventor is applied. It is a graph which shows the current-voltage characteristic of the forward direction of the JBS diode before and behind energization stress application. It is a graph which shows the electric current-voltage characteristic of the reverse direction of the JBS diode before and behind energization stress application. It is a graph which shows the electric current-voltage characteristic of the forward direction of the pn diode before and behind energization stress application. It is a graph which shows the electric current-voltage characteristic of the reverse direction of the pn diode before and behind energization stress application. It is an energy band figure of n Schottky interface when a reverse voltage is applied to the JBS diode containing a stacking fault. It is an energy band figure when a reverse voltage is applied to the pn diode containing a stacking fault. Relationship between stacking fault area exposed to Schottky interface (normalized by active area) and reverse leakage current when reverse voltage is applied to JBS diode and electric field strength at Schottky interface is 1.5MV / cm It is a graph figure of the result of having calculated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless explicitly stated or in principle limited to a specific number, It is not limited to the specific number, and it may be more or less than the specific number.

  Furthermore, in the embodiment, it is needless to say that the constituent elements (including element steps and the like) are not necessarily essential unless otherwise specified or apparently essential in principle. . Similarly, in the embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc., is substantially changed to the shape, etc., unless explicitly stated or otherwise considered in principle. Approximate or similar. The same applies to the above numerical values and ranges.

Also in the embodiment, since the concentration of the n-type impurity added to the drift layer of the JBS diode is lower than the concentration of the n-type impurity added to the substrate, the substrate is the n ⁺ substrate and the drift layer is the n ⁻ This is referred to as a drift layer. A region made of p-type silicon carbide is called a p region, a region made of n-type silicon carbide is called an n region, and a region made of n ⁻ -type silicon carbide is called an n ⁻ region.

(Embodiment 1)
When a diode is formed on a silicon carbide substrate as described above, a Schottky barrier diode can be manufactured that has a recovery loss during switching smaller than that of a pn diode and can provide a conduction loss comparable to that of a pn diode. The key barrier diode has a problem that the reverse leakage current in the blocking state is large. Thus, a JBS diode has been proposed to reduce the reverse leakage current.

An example of the structure of this JBS diode is shown in FIG. Reference numeral 81 is an n ⁺ substrate made of silicon carbide, reference numeral 82 is an n ⁻ drift layer made of silicon carbide, reference numeral 83 is a p region made of silicon carbide, reference numeral 84 is an anode electrode, and reference numeral 85 is a cathode electrode. The anode electrode 84 and the n ⁻ drift layer 82 are in Schottky contact, and the anode electrode 84 and the p region 83 are in ohmic contact.

As described above, in the JBS diode, when a positive voltage is applied to the anode electrode 84, a current flows from the anode electrode 84 to the n ⁻ drift layer 82 and operates as a Schottky barrier diode. On the other hand, in the blocking state in which a positive voltage is applied to the cathode electrode 85, the depletion layer extending from the p region 83 relaxes the electric field applied to the Schottky contact surface between the n ⁻ drift layer 82 and the anode electrode 84. Thus, the reverse leakage current is reduced.

Further, as described above, in this JBS diode, in the forward conduction state, a forward voltage is also applied between the junction of p region 83 and n ⁻ drift layer 82, and therefore, n ⁻ drift from p region 83. Holes are injected into layer 82. Usually, when a forward voltage of, for example, about 2.6 V or more is applied between the junction of p region 83 and n ⁻ drift layer 82, a large amount of holes are injected. However, since the structure is usually designed so that a large amount of holes are not injected, the holes injected from the p region 83 into the n ⁻ drift layer 82 do not affect the recovery current at the time of switching.

However, n ^- holes are injected into the drift layer 82, n ^- when in the basal plane dislocation that exists in the drift layer 82 and the electrons and holes are recombined, laminated was a basal plane dislocation core by the released energy Defect F grows. This stacking fault F forms an energy level 0.2 eV below the conduction band edge of 4H—SiC (see Non-Patent Document 2). The on-voltage rises with time due to the growth of the stacking fault F, and the reverse leakage current also increases with time (energization deterioration phenomenon). This phenomenon is a phenomenon observed in a compound semiconductor such as silicon carbide. The energization deterioration phenomenon in the JBS diode is particularly noticeable in a high breakdown voltage diode having a high on-voltage. This is because, when the ON voltage is high, the p region 83 and the n ^- large voltage across the junction between the drift layer 82 is applied, the p region 83 n ^- because holes are injected into the drift layer 82 easily.

  Next, the cause of the energization deterioration phenomenon of the JBS diode found by the present inventor and the means for avoiding it, and the effect of the p region in the JBS diode will be described in detail with reference to FIGS.

  First, the influence on the electrical characteristics of the energization deterioration phenomenon in the JBS diode and pn diode found by the present inventor will be described. 20 and 21 are current-voltage characteristics in the forward and reverse directions of the JBS diode before and after application of the energization stress, respectively. FIGS. 22 and 23 are currents in the forward and reverse directions of the pn diode before and after application of the energization stress, respectively. -Voltage characteristics, FIG. 24 is an energy band diagram of an n Schottky interface when a reverse voltage is applied to a JBS diode including a stacking fault, and FIG. 25 is a voltage applied to a pn diode including a stacking fault. Fig. 26 shows the stacking fault area exposed at the Schottky interface when the reverse voltage is applied to the JBS diode and the electric field strength at the Schottky interface is 1.5 MV / cm (normalized by the active area). ) And the reverse leakage current are calculated.

  When a stacking fault is grown by energization stress, the stacking fault traps conduction carriers, so that the ON voltage increases as shown in the forward characteristics of FIGS. On the other hand, as shown in FIGS. 21 and 23, the reverse characteristics after growing stacking faults due to energization stress increase the leakage current in the JBS diode, but the leakage current hardly changes in the pn diode. It was. This is due to the following reason.

  The reverse leakage current in the JBS diode is mainly composed of the tunnel current at the n Schottky interface. As shown in FIG. 24, the stacking fault forms an energy level below 0.2 eV of the conduction band edge of 4H—SiC (see Non-Patent Document 2). Therefore, when the stacking fault extends to the vicinity of the n Schottky interface, Leakage current increases due to lowering of the Schottky barrier and tunneling through stacking faults. The tunneling probability at the Schottky interface is as follows, assuming that the Schottky barrier height is φ, the electric field strength is F, the electron mass is m, the Planck constant is h, and the electron energy is E.

  When the leakage current is calculated in consideration of the reduction of the Schottky barrier due to stacking faults near the Schottky interface, the leakage current is as shown in FIG. 26 when the electric field strength is 1.5 MV / cm. It can be seen that the current becomes very large. The presence of a location where the leak current is locally large in this way causes electric field concentration and reduces the reliability of the diode.

  The increase in the on-voltage can be explained as an increase in the resistance of the stacking fault portion, and can be ignored if the stacking fault area is small. On the other hand, as shown in FIG. Even if the area of the stacking fault is small, the influence is large.

  When the stacking fault grows in the JBS diode, the reverse leakage current increases, whereas in the pn diode, the pn junction has the maximum electric field when the reverse voltage is applied, but the band gap of 4H-SiC is 3.26 eV. Since it is large, as shown in FIG. 25, the energy difference between the stacking fault energy level and the valence band edge is also large, the tunnel current passing through the stacking fault hardly flows, and the leakage current hardly changes.

  From the above, in order to avoid a decrease in reliability due to deterioration of energization, a structure in which stacking faults do not extend to the vicinity of the n Schottky interface may be used. In the forward conduction state, holes injected from the p region are recombined with electrons, so that they decrease as they move away from the injection site and expand to the diffusion length. Therefore, if the distance between the p region where hole injection occurs and the n Schottky interface is wider than the hole diffusion length, the probability that the stacking fault extends to the vicinity of the n Schottky interface can be reduced.

  The diffusion length is as follows, where D is the diffusion coefficient and τ is the lifetime.

  Therefore, although depending on the impurity concentration and temperature, the diffusion length of holes is about 10 μm in the case of 4H—SiC epitaxial layer (see Non-Patent Document 1), and 7 μm in the case of a 3 kV class diode. In addition, since recombination centers are introduced into the region where impurity ions have been implanted, the lifetime is reduced by ion implantation.

  Next, the effect of the p region in the JBS diode found by the present inventor (method for making the JBS diode high surge resistance) will be described.

  In the JBS diode, when the voltage (forward voltage) between the anode electrode and the cathode electrode is increased, current starts to flow in the n Schottky region at about 1V. In the case of a JBS diode having no p region in ohmic contact with the anode electrode, when the current increases, the temperature rises due to self-heating and the resistance increases. For this reason, there is an upper limit to the current that can be flowed, and if a current larger than that is flowed, the voltage (forward voltage) between the anode electrode and the cathode electrode increases and eventually breaks down. On the other hand, in the case of a JBS diode having a p region that is in ohmic contact with the anode electrode, when a high voltage is applied between the junction of the p region and the drift layer, holes are injected from the p region into the drift layer and conducted. Degree modulation occurs. This reduces the resistance and allows a larger current to flow. That is, the surge resistance can be increased.

  Next, an example of a specific structure of a semiconductor device in which a JBS diode is provided on a silicon carbide substrate will be described with reference to FIGS.

  1 is an overall plan view of a JBS diode chip according to the first embodiment, FIG. 2 is a cross-sectional view taken along line II in FIG. 1, and FIG. 3 is a cross-sectional view taken along line II-II in FIG. In FIG. 1, the surface of the JBS diode chip below the anode electrode is shown through to make the drawing easier to see. Further, FIG. 1 is a plan view, but is hatched for easy understanding of the drawing.

An n ⁺ substrate 1 constituting a JBS diode chip (semiconductor device) is made of, for example, n ⁺ type silicon carbide, and an n ⁻ drift layer (semiconductor layer) 2 made of, for example, n ⁻ type silicon carbide is formed on the surface thereof. Is formed by an epitaxial method or the like. The impurity concentration of the n ⁻ drift layer 2 is lower than the impurity concentration of the n ⁺ substrate 1, for example, about 2 × 10 ¹⁵ cm ⁻³ , and the thickness of the n ⁻ drift layer 2 is, for example, about 30 μm.

The active region (active region) on the surface of the n ⁻ drift layer 2 (the surface opposite to the surface in contact with the n ⁺ substrate 1) has a plurality of first p regions (first regions) made of, for example, p-type silicon carbide. 1 region) 3 and a plurality of second p regions (second regions) 4 are formed in a state of being separated from each other.

  As shown in FIG. 1, the first p region 3 and the second p region 4 are arranged in a stripe shape, for example. That is, the first p region 3 and the second p region 4 are formed, for example, in a planar line extending in one direction (up and down direction in FIG. 1), and in the width direction (left and right in FIG. 1) intersecting the extending direction. Direction). The first p region 3 and the second p region 4 are arranged by repeating a predetermined unit structure along the width direction, but the structure of the repeating unit is limited to that shown in FIG. Various modifications are possible.

The impurity concentration of the portion exposed to the surface of the n ⁻ drift layer 2 in each first p region 3 is, for example, about 1 × 10 ²⁰ cm ⁻³ , and the depth of the first p region 3 (the depth from the surface of the n ⁻ drift layer 2). Is), for example, 0.3 to 1.0 μm. Further, the impurity concentration of the portion of the second p region 4 exposed on the surface of the n ⁻ drift layer 2 is lower than the impurity concentration of the first p region 3, for example, 1 × 10 ¹⁹ cm ⁻³ or less, and the depth of the second p region 4 The depth (depth from the surface of the n ⁻ drift layer 2) is substantially the same as that of the first p region 3, and is, for example, 0.3 to 1.0 μm.

In addition, a first n ⁻ region (third region) 2 a configured by a part of the n ⁻ drift layer 2 is disposed between adjacent second p regions 4 and 4. Further, on both sides in the width direction of each first p region 3, a second n ⁻ region (fourth region) constituted by a part of the n ⁻ drift layer 2 is provided between the first p region 3 and the second p region 4 adjacent to each other. 2b is arranged.

As shown in FIG. 1 and FIG. 3, a guard ring (fifth region) 5a and an outer periphery of the terminal region on the outer periphery of the active region on the surface side of the n ⁻ drift layer 2 are doubled, for example. Arranged floating guard rings 6 and 6 are formed.

The inner guard ring 5a is made of, for example, p-type silicon carbide, and is formed in a planar endless frame shape so as to surround the active region. The impurity concentration of the portion exposed to the surface of the n ⁻ drift layer 2 in the guard ring 5 a is, for example, 1 × 10 ¹⁹ cm ⁻³ or less, and the depth of the guard ring 5 a (depth from the surface of the n ⁻ drift layer 2). ) Is, for example, about 0.5 to 2.0 μm. The plane width of the guard ring 5a is wider than the plane width of each of the first p region 3 and the second p region 4 described above in consideration of misalignment in the manufacturing process, for example, a width of 20 μm or more. . The guard ring 5 a is separated (insulated) from the first p region 3, but is directly connected to the second p region 4 through both longitudinal end portions of the second p region 4. For this reason, the guard ring 5 a may be formed simultaneously with the second p region 4.

Each of the outer floating guard rings 6 and 6 is made of, for example, p-type silicon carbide, and is formed in a planar endless frame shape so as to surround the guard ring 5a. The floating guard rings 6 and 6 are separated (insulated) from each other and also separated (insulated) from the guard ring 5a. The impurity concentration of the portion exposed to the surface of the n ⁻ drift layer 2 in the floating guard ring 6 is, for example, 1 × 10 ¹⁹ cm ⁻³ or less, and the depth of the floating guard ring 6 (from the surface of the n ⁻ drift layer 2) The depth) is, for example, about 0.5 to 2.0 μm. The floating guard ring 6 may be formed simultaneously with the second p region 4 and the guard ring 5a.

As shown in FIGS. 2 and 3, an insulating film 9 a is formed in the active region on the surface of the n ⁻ drift layer 2. The insulating film 9a is made of, for example, a thermal oxide film or a deposited oxide film, and has a thickness of about 0.5 to 1.0 μm, for example.

In addition, in the termination region on the surface of the n ⁻ drift layer 2, an insulating film 9 b and a passivation film 10 are formed in order from the lower layer. The insulating film 9b is made of, for example, a thermal oxide film or a deposited oxide film, and may be formed simultaneously with the above-described insulating film 9a. The total thickness of the insulating film 9b and the passivation film 10 is, for example, about 5 μm.

An anode electrode 11 is formed on the insulating films 9a and 9b. The anode 11 is made of, for example, nickel (Ni), is in ohmic contact with the first p region 3 through the holes 12 formed in the insulating films 9a and 9b, and is in contact with the first n ⁻ region 2a, the second p region 4, and the guard ring. 5a is electrically connected to each region in a Schottky contact state.

On the other hand, a cathode electrode 13 is formed on the back surface of the n ⁺ substrate 1 of the JBS diode chip (the surface opposite to the surface in contact with the n ⁻ drift layer 2). The cathode electrode 13 is made of, for example, Ni or titanium (Ti).

In such a JBS diode chip according to the first embodiment, the surface of the second n ^- region 2b is covered with the insulating film 9a, and the anode 11 and the second n ^- region 2b are separated by the insulating film 9a. (Insulated). Therefore, the anode electrode 11 does not contact the second n ⁻ region 2b, and no Schottky contact portion is formed on the surface portion of the second n ⁻ region 2b.

As described above, the second p region 4 in which the anode electrode 11 is in Schottky contact is between the first p region 3 in which the anode electrode 11 is in ohmic contact and the first n ^- region 2a in which the anode electrode 11 is in Schottky contact. And the second n ⁻ region 2b. Thereby, a sufficient distance LA (see FIG. 2) between the first p region 3 in which the anode electrode 11 is in ohmic contact and the first n ^- region 2a in which the anode electrode 11 is in Schottky contact is secured. The interval LA is formed wider than the hole diffusion length (that is, (Dτ) ^1/2 shown in the above formula 2). Specifically, the interval LA is set to 7 μm or more, for example. With such a configuration, since holes injected from the first p region 3 do not reach the n Schottky interface, an increase in leakage current due to stacking fault expansion can be suppressed or prevented.

  Next, FIG. 4 shows a circuit diagram of the JBS diode chip of the first embodiment.

The left Schottky barrier diode SDn in FIG. 4 is connected in the forward direction between the anode electrode 11 and the cathode electrode 13. The Schottky barrier diode SDn is formed at a contact portion between the anode electrode 11 and the first n ⁻ region 2a.

The pn diode D1 in the center of FIG. 4 is connected in the forward direction between the anode electrode 11 and the cathode electrode 13 in parallel with the Schottky barrier diode SDn. The pn diode D1 is formed at the junction between the first p region 3 and the n ⁻ drift layer 2 described above.

The pn diode D2 on the right side of FIG. 4 is connected in the forward direction between the anode electrode 11 and the cathode electrode 13 in parallel with the Schottky barrier diode SDn. The pn diode D2 is formed at the junction between the second p region 4 and the n ⁻ drift layer 2 described above.

  The Schottky barrier diode SDp on the right side of FIG. 4 is connected in the opposite direction between the anode electrode 11 and the cathode electrode 13 in parallel with the Schottky barrier diode SDn. The Schottky barrier diode SDp is formed at the contact portion between the anode electrode 11 and the second p region 4 described above.

  Next, the operation of the JBS diode chip of the first embodiment will be described with reference to FIG. 2 and FIG.

In a forward conduction state in which a positive voltage is applied to the anode electrode 11, a current flows from the anode electrode 11 to the n ⁻ drift layer 2 through the first n ⁻ region 2a in Schottky contact and operates as a Schottky barrier diode. To do. Even when a large surge current instantaneously flows during normal operation, the potential of the anode electrode 11 becomes high, and even if a large voltage is applied between the junction of the first p region 3 and the n ⁻ drift layer 2, the first p region Since holes are injected from 3 into the n ⁻ drift layer 2 and conductivity modulation occurs, a large surge current can be absorbed. For this reason, a surge withstand voltage can be secured. At this time, even if the potential of the anode electrode 11 becomes high, a large voltage is not applied between the junction of the second p region 4 and the n ⁻ drift layer 2, and the second p region 4 leads to the n ⁻ drift layer 2. Does not inject holes. Further, since the first p region 3 and the second p region 4 are separated (insulated), holes are not injected from the second p region 4 into the n ⁻ drift layer 2 via the first p region 3. For this reason, the conduction deterioration phenomenon peculiar to silicon carbide can be suppressed or prevented.

On the other hand, in a blocking state in which a positive voltage is applied to the cathode electrode 13, a depletion layer extending from the first p region 3 and the second p region 4 forms a Schottky contact interface between the anode electrode 11 and the first n ⁻ region 2a. The reverse leakage current can be reduced by relaxing the electric field.

  Next, the operation of the guard ring 5a of the JBS diode chip according to the first embodiment will be described.

Since the guard ring 5a is formed wide as described above, when the guard ring 5a and the anode electrode 11 are in ohmic contact, when a positive voltage is applied to the anode electrode 11, the guard ring 5a n ^- is the junction between the drift layer 2, a 1p region 3 and n ^- a large voltage is applied than the junction between the drift layer 2. In this case, holes can be injected into the n ⁻ drift layer 2 from the guard ring 5 a earlier than holes are injected from the first p region 3. Further, when the guard ring 5a and the anode electrode 11 are in Schottky contact, if the guard ring 5a and the first p region 3 are connected, the guard ring 5a is connected to the n ⁻ via the first p region 3. Holes can be injected into the drift layer 2. For this reason, in the case of these structures, there is a case where a current deterioration phenomenon occurs in the termination region of the JBS diode chip.

On the other hand, in the JBS diode chip according to the first embodiment, the guard ring 5a is in Schottky contact with the anode 11 and is not connected to the first p region 3. Holes are not injected into the n ⁻ drift layer 2, and the current deterioration phenomenon in the termination region can be suppressed or prevented.

  Next, an example of a method for manufacturing the JBS diode according to the first embodiment of the present invention will be described with reference to FIGS. 5-8 is sectional drawing in the manufacturing process of the part applicable to FIG.

First, as shown in FIG. 5, a base body in which an n ⁻ drift layer 2 is laminated on the surface of an n ⁺ substrate 1 made of silicon carbide is prepared. The n ⁻ drift layer 2 is formed by, for example, an epitaxial growth method, and has an impurity concentration of, for example, about 2 × 10 ¹⁵ cm ⁻³ and a thickness of, for example, about 30 μm.

Subsequently, after a mask material 15A for ion implantation is applied on the surface of the n ⁻ drift layer 2, the mask material 15A is patterned. Thereafter, as indicated by an arrow, a p-type impurity such as aluminum (Al) is ion-implanted into the n ⁻ drift layer 2 to form a plurality of second p regions 4 (see FIGS. 1 and 2). The impurity concentration of the portion exposed on the surface of the n ⁻ drift layer 2 in the second p region 4 is, for example, about 1 × 10 ¹⁹ cm ⁻³ , and the depth of the second p region 4 is, for example, about 0.3 to 1.0 μm. is there.

At this time, using the same mask material 15A, p-type impurities are ion-implanted into the n ⁻ drift layer 2 in the termination region to form the guard ring 5a and the floating guard rings 6 and 6 (see FIGS. 1 and 3). . Guard ring 5a and floating guard rings 6 and 6 may be formed using a mask material for ion implantation different from mask material 15A.

Next, after removing the mask material 15A, as shown in FIG. 6, a mask material 15B for ion implantation is applied on the surface of the n ⁻ drift layer 2 and patterned. At this time, the mask material 15B is patterned so that the opening of the mask material 15B does not cover the second p region 4.

Subsequently, a p-type impurity such as Al is ion-implanted into the n ⁻ drift layer 2 to form a first p region 3 (see FIGS. 1 and 2). The impurity concentration of the exposed portion of the first p region 3 on the surface of the n ⁻ drift layer 2 is, for example, 1 × 10 ²⁰ cm ⁻³ or less, and the depth of the first p region 3 is, for example, about 0.3 to 1.0 μm. It is.

Further, the width of the first p region 3 is set such that the impurity concentration of the n ⁻ drift layer 2 and the depth of the first p region 3 are set so that a large amount of holes are not injected from the first p region 3 to the n ⁻ drift layer 2 during normal operation. , And the area ratio of the third n region 2a in Schottky contact with the anode electrode 11, for example, 10 μm or less is desirable.

Next, after removing the mask material 15B, for example, heat treatment is performed on the n ⁺ substrate 1 and the n ⁻ drift layer 2 at a temperature of 1700 ° C. to activate the ion-implanted Al, as shown in FIG. a, n ^- the surface side of the drift layer 2, a 1p region 3, the 2p region 4, the 1n ^- forming a region 2b ^- region 2a and the 2n.

Subsequently, as shown in FIG. 8, an insulating film 9a is formed so as to cover the surface of the n ⁻ drift layer 2 (the first p region 3, the second p region 4, the first n ⁻ region 2a, and the second n ⁻ region 2b). . The insulating film 9a is, for example, a thermal oxide film or a deposited oxide film. At this time, the passivation film 10 (see FIG. 3) may be formed at the same time. Thereafter, as shown in FIG. 2, a cathode electrode 13 made of, for example, Ni or Ti is formed on the back surface of the n ⁺ substrate 1.

Next, as shown in FIG. 2, a hole 12 is formed in the insulating film 9a so that a part of the surface side of the first p region 3, the second p region 4, and the first n ^- region 2a is exposed. At this time, the insulating film 9a is processed so that the second n ⁻ region 2b on the surface of the n ⁻ drift layer 2 adjacent to the first p region 3 is covered with the insulating film 9a.

Subsequently, after depositing a metal film made of, for example, Ni on the n ⁻ drift layer 2, the metal film is processed to contact the first p region 3, the second p region 4, and the first n ⁻ region 2 a through the hole 12. Thus, the anode electrode 11 is formed. Since the impurity concentration of the first p region 3 is set to a high concentration (for example, about 1 × 10 ²⁰ cm ⁻³ ), the first p region 3 is in ohmic contact with the anode electrode 11. On the other hand, since the impurity concentration of the second p region 4 is low (for example, 1 × 10 ¹⁹ cm ⁻³ or less), the second p region 4 is in Schottky contact with the anode electrode 11. Further, since the impurity concentration of the first n ⁻ region 2a is also low (for example, about 2 × 10 ¹⁵ cm ⁻³ ), the first n ⁻ region 2a is in Schottky contact with the anode 11.

  Thereafter, as shown in FIG. 3, the passivation film 10 is formed, whereby the JBS diode chip according to the first embodiment is substantially completed.

  According to the first embodiment, the following effects can be obtained.

  In the JBS diode chip of the first embodiment, even if the stacking fault is expanded due to energization stress, the stacking fault can be prevented from reaching the vicinity of the n Schottky interface, and the reverse leakage current increases in the blocking state. Can be prevented.

  Further, in the JBS diode chip of the first embodiment, the first p region 3 that is in ohmic contact with the anode electrode 11 absorbs a large surge current, so that a high surge resistance can be obtained.

  For these reasons, in the JBS diode chip of the first embodiment, it is possible to suppress or prevent the energization deterioration phenomenon without reducing the surge withstand capability.

(Embodiment 2)
The JBS diode chip according to the second embodiment will be specifically described with reference to FIG.

  FIG. 9 is a cross-sectional view of a main part of the active region of the JBS diode chip according to the second embodiment at the same location as in FIG.

In the second embodiment, an n-type semiconductor layer (eighth region) 20 having an impurity concentration higher than that of the n ⁻ drift layer 2 is formed on the surface side of the n ⁻ drift layer 2. The semiconductor layer 20 has a function as a current diffusion layer. The impurity contained in the semiconductor layer 20 is, for example, nitrogen (N), and the impurity concentration is, for example, about 1 × 10 ¹⁶ cm ⁻³ .

  In this case, a first n region (third region) 20 a configured by a part of the n-type semiconductor layer 20 is disposed between adjacent second p regions 4 and 4. Further, on both sides in the width direction of each first p region 3, a second n region (fourth region) constituted by a part of the n-type semiconductor layer 20 is provided between the first p region 3 and the second p region 4. 20b is arranged. The first p region 3, the second p region 4, the first n region 20 a and the second n region 20 b are formed so as to be included in the semiconductor layer 20.

  In this case, the anode electrode 11 is electrically connected in a Schottky contact with the first n region 20a. The surface of the second n region 20b is covered with an insulating film 9a, and the anode electrode 11 and the second n region 20b are separated (insulated) by the insulating film 9a. Also in this case, the second p region 4 and the second n region 20b are arranged between the first p region 3 in which the anode electrode 11 is in ohmic contact and the first n region 20a in which the anode electrode 11 is in Schottky contact. Thereby, a sufficient distance LA (see FIG. 9) between the first p region 3 and the first n region 20a is secured. The interval LA is formed wider than the hole diffusion length (see the above formula 2). Specifically, the interval LA is set to 7 μm or more, for example. Therefore, also in the second embodiment, since holes injected from the first p region 3 do not reach the n Schottky interface, it is possible to suppress or prevent an increase in leakage current due to the stacking fault expansion.

Further, in the first embodiment, since the surface area of the first n ^- region 2a (see FIG. 2) in Schottky contact with the anode electrode 11 is small, there is a concern about an increase in on-resistance. On the other hand, in the second embodiment, since the first n region 20a is formed of the n-type semiconductor layer 20 having a higher impurity concentration than the n ⁻ drift layer 2, the on-resistance can be reduced. Furthermore, since the first p region 3 and the second p region 4 are also provided in the semiconductor layer 20, current can flow so as to spread efficiently to the lower part of the first p region 3 and the second p region 4 during forward energization. The on-resistance can be further reduced.

However, the lower portion of the first p region 3 may reach the n ⁻ drift layer 2 below the semiconductor layer 20. In this case, the efficiency of hole injection from the first p region 3 to the n ⁻ drift layer 2 is increased. Further, the current can be efficiently spread to the lower portion of the second p region 4 during forward energization, and the on-resistance can be reduced.

(Embodiment 3)
The JBS diode chip according to the third embodiment will be specifically described with reference to FIG. 10 and FIG.

  10 is an overall plan view of the JBS diode chip according to the third embodiment, and FIG. 11 is a cross-sectional view taken along line III-III in FIG. In FIG. 10, the surface of the JBS diode chip below the anode electrode is shown through as in FIG. FIG. 10 is a plan view, but is hatched in the same manner as FIG.

The basic structure of the active region of the JBS diode chip of the third embodiment is the same as that of the first embodiment. Further, the n-type semiconductor layer 20 may be provided in the n ⁻ drift layer 2 as in the second embodiment.

  In the JBS diode chip of the third embodiment, a planar endless frame-shaped second p region (second region) 4a is formed on the outer periphery of the active region, and a plurality of planar linear shapes arranged in the active region are formed. The second p region 4 is electrically connected to the planar frame-shaped second p region 4a through both longitudinal ends thereof.

  The planar width, impurity type and concentration of the second p region 4a are the same as those of the second p region 4 in the active region. The anode electrode 11 is electrically connected in a Schottky contact with the second p region 4a.

  A guard ring (sixth region) 5b is disposed on the outer periphery of the planar frame-shaped second p region 4a. The guard ring 5b is made of, for example, p-type silicon carbide, and is formed in a planar endless frame shape so as to surround the second p region 4a.

The impurity concentration of the portion exposed to the surface of the n ⁻ drift layer 2 of the guard ring 5b is higher than the impurity concentration of the guard ring 5a described in the first embodiment, and is, for example, about 1 × 10 ²⁰ cm ^−3. . For this reason, the anode electrode 11 is electrically connected in ohmic contact with the guard ring 5b.

The depth of the guard ring 5b (depth from the surface of the n ⁻ drift layer 2) is, for example, 0.5 to 2.0 μm. In this case, the guard ring 5b may be formed simultaneously with the first p region 3. Further, the plane width of the guard ring 5b is wider than the plane width of each of the first p region 3 and the second p region 4 in consideration of manufacturing misalignment, for example, 20 μm or more.

Between the second p region 4a and the guard ring 5b, a third n ⁻ region (seventh region) 2c constituted by a part of the n ⁻ drift layer 2 is disposed, and the guard ring 5b and the second p The regions 4 and 4a are separated (insulated). The surface of the third n ^- region 2c is covered with an insulating film 9a, and the third n ^- region 2c and the anode electrode 11 are separated (insulated).

In such a JBS diode of the third embodiment, the second p region 4a is provided between the guard ring 5b in which the anode electrode 11 is in ohmic contact and the first n ^- region 2a in which the anode electrode 11 is in Schottky contact. A third n region 2c is arranged. Accordingly, the guard ring 5b and the 1n ^- distance between the region 2a LB (see FIG. 10) is sufficiently ensured. The interval LB is formed wider than the hole diffusion length (see the above formula 2). Specifically, the interval LB is set to 7 μm or more, for example. Therefore, in Embodiment 3, since holes injected from the first p region 3 and the guard ring 5b do not reach the n Schottky interface, an increase in leakage current due to stacking fault expansion can be suppressed or prevented. .

  According to the third embodiment, in addition to the effects of the first and second embodiments, the following effects can be obtained.

That is, since the guard ring 5b is normally formed wide as described above, when the guard ring 5b and the anode electrode 11 are in ohmic contact, when a positive voltage is applied to the anode electrode 11, the guard ring 5b A voltage larger than that between the junction of the first p region 3 and the n ⁻ drift layer 2 is applied between the junction of 5 b and the n ⁻ drift layer 2. For this reason, holes are injected into the n ⁻ drift layer 2 from the guard ring 5 b earlier than holes are injected from the first p region 3. Thereby, in this Embodiment 3, a JBS diode chip with high surge tolerance can be obtained.

(Embodiment 4)
The JBS diode chip according to the fourth embodiment will be specifically described with reference to FIGS.

  FIG. 12 is a main part plan view of the active region of the JBS diode chip according to the fourth embodiment, and FIG. 13 is a cross-sectional view taken along the line IV-IV in FIG.

  The overall plan view of the JBS diode chip is the same as that described with reference to FIG. 1 and FIG. 10, and FIG. 13 shows a cross section of the portion corresponding to the line II in FIG. Further, in FIG. 12, the surface portion of the JBS diode chip below the anode electrode is shown in the same manner as in FIG. FIG. 12 is a plan view, but is hatched in the same manner as FIG.

In the JBS diode chip of the fourth embodiment, a third n region (fourth region) 21 having, for example, a plurality of hole coupling centers is formed on the surface of the n ⁻ drift layer 2 adjacent to the first p region 3. ing. The third n region 21 is provided so as to surround the planar outer periphery of the first p region 3.

The third n region 21 is formed by an ion implantation method or the like, and its impurity is, for example, nitrogen (N), and its impurity concentration is, for example, about 5 × 10 ¹⁶ cm ⁻³ . The depth of the third n region 21 (depth from the surface of the n ⁻ drift layer 2) is, for example, 0.5 to 1.0 μm. The width of the third n region 21 sandwiched between the first p region 3 and the second p region 4 is shorter than the sum of the depletion layer widths extending from the first p region 3 and the second p region 4 to the third n region 21.

Since the third n region 21 is formed by the ion implantation method, the lifetime of holes in the third n region 21 is short, and the holes injected from the first p region 3 into the n ⁻ drift layer 2 are in the third n region. It disappears due to recombination with electrons in 21 and does not reach the Schottky interface of the third n region 21. Therefore, an increase in leakage current due to expansion of stacking faults can be prevented.

The anode electrode 11 is in Schottky contact with the first n ⁻ region 2 a, the second p region 4 and the third n region 21 of the n ⁻ drift layer 2, and is in ohmic contact with the first p region 3. In the first p region 3 and the second p region 4, a predetermined unit structure is repeatedly arranged along the width direction, and the structure of the repeating unit is that shown in FIG. 12 and FIG. It is not limited to.

The impurity concentration of the n ⁻ drift layer 2 is, for example, about 2 × 10 ¹⁵ cm ⁻³ , and the impurity concentration of the portion exposed to the surface of the n ⁻ drift layer 2 in the first p region 3 is, for example, about 1 × 10 ²⁰ cm ^−3. The impurity concentration of the portion exposed on the surface of the n ⁻ drift layer 2 in the second region 4 is, for example, 1 × 10 ¹⁹ cm ⁻³ or less. The thickness of the n ⁻ drift layer 2 is, for example, about 30 μm, and the depth of the first p region 3 and the second p region 4 (depth from the surface of the n ⁻ drift layer 2) is, for example, 0.5 to 1. 0 μm.

Also in the JBS diode chip of the fourth embodiment, between the first p region 3 in which the anode electrode 11 is in ohmic contact and the first n ⁻ region (third region) 2a in which the anode electrode 11 is in Schottky contact. The second p region 4 and the third n region 21 where the anode electrode 11 is in Schottky contact are arranged. Thereby, a sufficient gap LA (see FIG. 13) between the first p region 3 and the first n ^- region 2a is secured. The distance LA between the first p region 3 and the first n ⁻ region 2a is formed wider than the hole diffusion length (see (Dτ) ^1/2 shown in the above equation ² ). Specifically, the interval LA is set to 7 μm or more, for example. Thereby, since holes injected from the first p region 3 do not reach the n Schottky interface, it is possible to suppress or prevent an increase in leakage current due to the stacking fault expansion.

In the fourth embodiment, the n-type semiconductor layer 20 may be provided in the n ⁻ drift layer 2 as in the second embodiment. Further, the structures related to the guard rings 5a and 5b and the floating guard ring 6 on the outer periphery of the JBS diode chip are the same as those described in the first and third embodiments.

  Next, an example of a method for manufacturing the JBS diode chip according to the fourth embodiment of the present invention will be described with reference to FIGS. 14-17 is sectional drawing in the manufacturing process of the part applicable to FIG.

First, as shown in FIG. 14, similarly to the first embodiment, a base body in which an n ⁻ drift layer 2 is laminated on the surface of an n ⁺ substrate 1 made of silicon carbide is prepared.

Subsequently, a mask material 15C for ion implantation is applied on the surface of the n ⁻ drift layer 2, and then the mask material 15C is patterned. Thereafter, as indicated by an arrow, an n-type impurity such as nitrogen (N) is ion-implanted into the n ⁻ drift layer 2 to form a third n region 21 (see FIGS. 12 and 13). The impurity concentration of the third n region 21 is, for example, about 5 × 10 ¹⁶ cm ⁻³ , and the depth of the third n region 21 is, for example, about 0.5 to ^1.0 μm.

Subsequently, after removing the mask material 15C, as shown in FIG. 15, a mask material 15A for ion implantation is applied on the surface of the n ⁻ drift layer 2, and then the mask material 15A is patterned. Thereafter, as indicated by an arrow, a p-type impurity such as Al is ion-implanted into the n ⁻ drift layer 2 to form the second p region 4 (see FIGS. 12 and 13). The impurity concentration of the portion exposed to the surface of the n ⁻ drift layer 2 in the second p region 4 is, for example, about 1 × 10 ¹⁹ cm ⁻³ or less, and the depth of the second p region 4 is, for example, about 0.5 to ^1.0 μm. It is.

Next, after removing the mask material 15A, as shown in FIG. 16, a mask material 15B for ion implantation is applied on the surface of the n ⁻ drift layer 2 and patterned. At this time, the mask material 15B is patterned so that the opening of the mask material 15B does not cover the second p region 4.

Subsequently, a p-type impurity such as Al is ion-implanted into the n ⁻ drift layer 2 to form a first p region 3 (see FIGS. 12 and 13). The impurity concentration of the exposed portion of the first p region 3 on the surface of the n ⁻ drift layer 2 is, for example, about 1 × 10 ²⁰ cm ⁻³ , and the depth of the first p region 3 is, for example, about 0.5 to ^1.0 μm. It is.

Further, the width of the first p region 3 is set such that the impurity concentration of the n ⁻ drift layer 2 and the depth of the first p region 3 are set so that a large amount of holes are not injected from the first p region 3 to the n ⁻ drift layer 2 during normal operation. , And the area ratio of the first n ^- region 2a in Schottky contact with the anode electrode 11, for example, 10 μm or less is desirable.

  Further, in order to reduce the leakage current at the Schottky interface on the surface of the third n region 21 during the blocking operation, the width of the third n region 21 sandwiched between the first p region 3 and the second p region 4 is the first p region 3 and It is shorter than the sum of the depletion layer widths extending from each of the second p regions 4 to the third n region 21, for example, 1.0 μm or less.

Next, after removing the mask material 15B, heat treatment is performed on the n ⁺ substrate 1 and the n ⁻ drift layer 2 at a temperature of 1700 ° C., for example, to activate the ion-implanted N and Al. As shown, the first p region 3, the second p region 4, the first n ⁻ region 2 a and the third n region 21 are formed on the surface side of the n ⁻ drift layer 2.

Subsequently, as shown in FIG. 13, a cathode electrode 13 made of, for example, Ni or Ti is formed on the back surface of the n ⁺ substrate 1.

Next, after depositing a metal film made of, for example, Ni on the n ⁻ drift layer 2, the first p region 3, the second p region 4, the first n ⁻ region 2 a, and the third n region 21 are contacted by processing the metal film. Thus, the anode electrode 11 is formed. Since the impurity concentration of the first p region 3 is set to a high concentration (for example, about 1 × 10 ²⁰ cm ⁻³ ), the first p region 3 is in ohmic contact with the anode electrode 11. On the other hand, since the impurity concentration of the second p region 4 is low (for example, 1 × 10 ¹⁹ cm ⁻³ or less), the second p region 4 is in Schottky contact with the anode electrode 11. Further, since the impurity concentration of the third n region 21 is also low (for example, about 5 × 10 ¹⁶ cm ⁻³ ), the third n region 21 is in Schottky contact with the anode electrode 11.

  Through the above manufacturing process, the JBS diode chip of the fourth embodiment is substantially completed.

  According to the fourth embodiment, the following effects can be obtained.

  In the JBS diode chip according to the fourth embodiment, even when the stacking fault is expanded due to energization stress, the stacking fault can be prevented from reaching the vicinity of the n Schottky interface, and the reverse leakage current increases in the blocking state. Can be prevented.

  Moreover, in the JBS diode chip of the fourth embodiment, the first p region 3 that is in ohmic contact with the anode electrode 11 absorbs a large surge current, so that a high surge resistance can be obtained.

  For these reasons, in the JBS diode chip of the fourth embodiment, it is possible to suppress or prevent the energization deterioration phenomenon without reducing the surge withstand capability.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the first to fourth embodiments, the first p region 3 has a planar line shape, but is not limited to this and can be variously changed. FIG. 18 is an overall plan view of a JBS diode chip showing a modification of the planar shape of the first p region 3. Here, a plurality of planar island-shaped (rectangular) first p regions 3 are arranged side by side along one direction.

  The present invention can be applied to a semiconductor device including a diode on a substrate made of silicon carbide and a method for manufacturing the semiconductor device.

1 n ⁺ substrate 2 n ⁻ drift layer 2a 1n ⁻ region 2b 2n ⁻ region 2c 3n ⁻ region 3 1p region 4 and 4a 2p regions 5a and 5b guard ring 6 floating guard rings 9a and 9b insulating film 10 passivation Film 11 Anode electrode 12 Hole 13 Cathode electrode 20 Semiconductor layer 20a First n region 20b Second n region 21 Third n region

Claims (15)

A substrate made of silicon carbide of the first conductivity type;
A semiconductor layer made of silicon carbide of the first conductivity type formed on the main surface of the substrate and having an impurity concentration lower than that of the substrate;
A plurality of first regions of a second conductivity type different from the first conductivity type formed on the surface side of the semiconductor layer and spaced apart from each other;
A plurality of second regions of the second conductivity type formed on the surface side of the semiconductor layer and spaced apart from each other;
A third region of the first conductivity type disposed between adjacent the second region;
A fourth region of the first conductivity type disposed between adjacent the first region and the second region;
An anode electrode formed on the surface of the semiconductor layer, in ohmic contact with the first region, and in Schottky contact with the second region and the third region;
A semiconductor device comprising: a cathode electrode formed on a back surface opposite to the main surface of the substrate.   2. The semiconductor device according to claim 1, wherein a distance between the first region and the third region is wider than a hole diffusion length.   2. The semiconductor device according to claim 1, wherein the fourth region is covered with an insulating film and insulated from the anode electrode.   2. The semiconductor device according to claim 1, wherein a hole recombination center is formed in the fourth region, and the anode electrode is in Schottky contact with the fourth region. apparatus.   5. The semiconductor device according to claim 4, wherein a width of the fourth region is larger than a sum of widths of depletion layers extending from the first region and the second region adjacent to the fourth region to the fourth region. A semiconductor device characterized by being short.   2. The semiconductor device according to claim 1, wherein the plurality of first regions and the plurality of second regions are separated from the plurality of first regions on the surface side of the semiconductor layer, and the plurality of first regions are separated from each other. A fifth region of a second conductivity type electrically connected to the two regions is formed, and the anode electrode is in Schottky contact with the fifth region.   2. The semiconductor device according to claim 1, wherein the plurality of first regions and the plurality of second regions are separated from the plurality of first regions and the plurality of second regions on the outer surface of the plurality of first regions and the plurality of second regions on the surface side of the semiconductor layer. A second region of the second conductivity type is formed, a seventh region of the first conductivity type is disposed between the second region and the sixth region, and the anode electrode A semiconductor device which is in ohmic contact with the sixth region.   8. The semiconductor device according to claim 7, wherein a distance between the sixth region and the third region is wider than a hole diffusion length.   2. The semiconductor device according to claim 1, wherein an eighth region of a first conductivity type having an impurity concentration higher than that of the semiconductor layer is formed in the third region where the anode electrode is in Schottky contact. Semiconductor device.   10. The semiconductor device according to claim 9, wherein the eighth region is formed so as to include the plurality of first regions and the plurality of second regions.   2. The semiconductor device according to claim 1, wherein the impurity concentration of the first region is higher than the impurity concentration of the second region. Preparing a substrate made of silicon carbide of the first conductivity type;
Forming a semiconductor layer made of silicon carbide of the first conductivity type having a lower impurity concentration than the substrate on the substrate;
Forming a plurality of first regions of a second conductivity type different from the first conductivity type on the surface side of the semiconductor layer in a state of being separated from each other;
Forming a plurality of second conductivity type second regions on the surface side of the semiconductor layer in a state of being spaced apart from each other, and forming a first conductivity type third region adjacent to the second region;
Forming an anode electrode in ohmic contact with the first region and in Schottky contact with the second region and the third region on the semiconductor layer;
Forming a cathode electrode on the back surface of the substrate,
Forming a fourth region of a first conductivity type between the first region and the second region; and between the first region and the third region, the second region and the fourth region, A method for manufacturing a semiconductor device comprising a step of forming a semiconductor device.   13. The method of manufacturing a semiconductor device according to claim 12, wherein an interval between the first region and the third region is formed wider than a hole diffusion length.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the first region is formed on the semiconductor layer after forming the plurality of first regions, the plurality of second regions, the third region, and the fourth region. And a step of forming an insulating film in which the second region and the third region are exposed and the fourth region is covered. 13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of ion-implanting impurities into the fourth region to form a hole recombination center.
After forming the plurality of first regions, the plurality of second regions, the third region, and the fourth region, the first region, the second region, and the third region on the semiconductor layer And forming an insulating film exposing the fourth region,
In the forming step of the anode electrode, the anode electrode is in Schottky contact with the fourth region.

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