JP2013251468A - Semiconductor device and method for controlling the same - Google Patents

Abstract

To provide a semiconductor device and a semiconductor device control method in which a gate-collector capacitance is reduced, a breakdown voltage is high, and an on-voltage is reduced.
A trench gate type MOS structure including a gate trench, a gate insulating film, and a gate electrode, a dummy trench, a dummy gate insulating film, and a dummy gate electrode are formed on the front surface of the semiconductor substrate. And a dummy trench gate structure. A p base region 2 is provided between the gate trench 4 and the dummy trench 14. No p-type region is provided between adjacent dummy trenches 14. The dummy gate electrode 16 is electrically connected to the emitter electrode 7. The trench pitch d is so narrow that the mesa region 12 sandwiched between adjacent dummy trenches 14 is depleted during forward voltage blocking, for example, 1.8 μm or more and 3.6 μm or less. Mesa region 12 sandwiched between adjacent dummy trenches 14 has a low impurity concentration that is depleted when blocking forward voltage.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a semiconductor device control method.

Conventionally, a trench gate type IGBT (insulated gate type bipolar transistor) having a dummy gate electrode with an emitter potential is known as a power semiconductor device used for a power conversion device or the like (for example, see Patent Document 1 below). FIG. 4 is a cross-sectional view showing a configuration of a conventional semiconductor device. FIG. 4 shows the semiconductor device shown in FIG. In the conventional semiconductor device shown in FIG. 4, a p base region 102 is provided in the surface layer on the front surface side of the semiconductor substrate to be the n ⁻ drift region 101. An n ⁺ emitter region 103 is provided inside the p base region 102.

A plurality of trenches 104 (hereinafter referred to as gate trenches) 104 penetrating the p base region 102 and the n ⁺ emitter region 103 and reaching the n ⁻ drift region 101 are provided at a predetermined pitch. Inside the gate trench 104, a gate insulating film 105 is provided along the side wall and the bottom surface of the gate trench 104. A gate electrode 106 is provided inside the gate insulating film 105 inside the gate trench 104. Emitter electrode 107 is in contact with p base region 102 and n ⁺ emitter region 103.

Between adjacent gate trenches 104, a plurality of dummy trenches 114 that penetrates the p base region 102 and reaches the n ⁻ drift region 101 are provided at a predetermined pitch. Ie, p base region 102, the dummy trench 114 is divided into plural regions, and the region 102a which is n ⁺ emitter region 103 is provided, and a region 102b in which the n ⁺ emitter region 103 is not provided is formed . A region (hereinafter, referred to as a p-floating (floating) region) 102b in which the n ⁺ emitter region 103 is not provided in the p base region 102 is in an electrically floating (floating) state.

  A dummy gate insulating film 115 is provided inside the dummy trench 114 along the side wall and the bottom surface of the dummy trench 114. A dummy gate electrode 116 is embedded inside the dummy gate insulating film 115 inside the dummy trench 114. The dummy gate electrode 116 is electrically connected to the emitter electrode 107 and has an emitter potential. An n buffer region 109, a p collector region 110, and a collector electrode 111 are provided on the back surface of the semiconductor substrate.

  By providing the dummy gate electrode with the emitter potential in this way, the parasitic capacitance (Qgc) between the gate and the collector (hereinafter referred to as the gate-collector capacitance) is reduced, and the switching operation is speeded up. In addition, gate driving with a gate driver having low driving capability is also possible. Further, by providing the p floating region, it is possible to prevent a decrease in breakdown voltage even when the pitch of the dummy trenches is wide.

  In order to bring the p floating region into a complete floating state, the p floating region and a p-type region having an emitter potential for extracting holes provided in the outer periphery of the active region (hereinafter referred to as hole extracting p). It is necessary to electrically isolate it from the mold region (see, for example, Patent Document 2 below). FIG. 5 is a cross-sectional view showing another example of the configuration of a conventional semiconductor device. FIG. 5 shows a trench gate type IGBT having an isolation structure shown in Patent Document 2 below. As shown in FIG. 5, a p floating region 122b is provided outside the p base region 122a (active region outer peripheral portion side) with a gate trench 124 interposed therebetween.

A p-type region 122c for extracting a hole is provided outside the p-floating region 122b with the isolation structure 130 interposed therebetween. The isolation structure 130 includes an n ⁻ drift region 121 sandwiched between two isolation trenches 134. By providing the isolation structure 130 between the p floating region 122b and the hole extracting p-type region 122c, the p floating region 122b and the hole extracting p-type region 122c are electrically separated, and the hole extracting p-type The hole current is prevented from flowing from the p floating region 122b to the emitter electrode via the region 122c.

As another example of a conventional trench gate type IGBT having a dummy gate electrode with an emitter potential, a striped p floating region extending to the cell end in a direction orthogonal to the direction in which a plurality of p floating regions are arranged is provided. A device is known in which a cell end of a p floating region is brought into contact with an emitter electrode so that the p floating region is in a substantially complete floating state (hereinafter referred to as incomplete floating). In the steady ON state, the hole current density is as high as several tens A / cm ² to several hundreds A / cm ^2, and the ratio of the hole current flowing into the contact portion with the emitter electrode at the cell end is the same as that of the emitter electrode at the cell end. It is less than the hole current flowing into other than the contact area. For this reason, the portions other than the cell end portion of the p floating region are substantially in a completely floating state.

Furthermore, as another example of a conventional trench gate type IGBT having a dummy gate electrode with an emitter potential, two gate trenches are provided in succession, and n.sup ^. An apparatus that employs a structure in which an emitter region is provided and no p-well is provided at both ends of an emitter trench has been proposed (see, for example, Patent Document 3 (paragraph 0170, FIG. 48) below).

Japanese Patent No. 4205128 US Pat. No. 6,815,769 JP-A-9-331063

  However, in the structure provided with the isolation structure 130 shown in Patent Document 2 (FIG. 5), when the separation distance d130 between the p floating region 122b and the p-type region 122c for hole extraction is short, the p floating region in the steady-on state. The hole current flows from 122b to the hole extraction p-type region 122c, the surface hole concentration decreases, and the on-voltage increases. On the other hand, when the separation distance d130 between the p floating region 122b and the hole extraction p-type region 122c is long, the area occupied by the separation structure 130 occupying one cell increases. Further, there is a problem that the electric field strength at the bottom of the isolation trench 134 is increased, the breakdown voltage is decreased, and the avalanche resistance is also decreased.

  In a trench gate type IGBT having an incompletely floating p-floating region, a hole current is drawn to the emitter electrode via the p-floating region in the vicinity of the cell end. As a result, the electron injection promotion (IE) effect is reduced, so that the surface hole concentration in the p floating region is reduced and the on-voltage is increased. As a whole element, it can be considered that a region in the vicinity of the cell end portion having a high on-voltage and a region other than the cell end portion having a low on-voltage are connected in parallel. For this reason, there is a problem that the on-voltage of the entire device rises due to the adverse effect of the on-voltage rise near the cell edge. Further, in the configuration in which the p floating region shown in Patent Document 3 is not provided, when the pitch of the dummy trenches is wide, there is a problem that avalanche breakdown is likely to occur at the bottom of the trench and the breakdown voltage is reduced.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a semiconductor device control method capable of reducing a gate-collector capacitance in order to solve the above-described problems caused by the prior art. Another object of the present invention is to provide a semiconductor device capable of maintaining a high breakdown voltage and a method for controlling the semiconductor device in order to eliminate the above-described problems caused by the prior art. Furthermore, an object of the present invention is to provide a semiconductor device and a semiconductor device control method capable of reducing the on-voltage in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention includes a plurality of trenches provided at a predetermined pitch on a first main surface of a first conductivity type semiconductor substrate, and a plurality of trenches. A first insulating film provided in the first trench along an inner wall of the first trench, and a first insulating film provided in the first trench through the first insulating film. A control electrode, a second insulating film provided inside the second trench along an inner wall of the remaining second trench excluding the first trench among the plurality of trenches, and via the second insulating film A second control electrode provided in the second trench and electrically insulated from the first control electrode, and sandwiched between the first trench and the second trench of the first conductivity type semiconductor substrate. The first trench only in A second conductive type semiconductor region provided in contact with the first conductive type semiconductor region; a first conductive type semiconductor region formed in contact with the first trench in the second conductive type semiconductor region; and the second conductive type semiconductor. A first main electrode electrically connected to the region and the first conductivity type semiconductor region; a second conductivity type semiconductor layer provided on a second main surface of the first conductivity type semiconductor substrate; and the second A second main electrode in contact with the conductive semiconductor layer, wherein the second control electrode is electrically connected to the first main electrode, and the second conductive electrode adjacent to the first conductive semiconductor substrate. The trenches are provided at the predetermined pitch at which a portion sandwiched between the trenches is depleted when forward voltage is blocked.

Further, in the semiconductor device according to the present invention, in the above-described invention, the depth of the second conductive type semiconductor region is shallower than the depth of the trench, and the adjacent second trenches of the first conductive type semiconductor substrate. The impurity concentration of the portion sandwiched between the layers is 2.0 × 10 ¹⁰ cm ⁻² or less.

  The semiconductor device according to the present invention is characterized in that, in the above-described invention, the pitch of the trenches is 3.6 μm or less.

  In order to solve the above-described problems and achieve the object of the present invention, a method for controlling a semiconductor device according to the present invention includes a plurality of methods provided at a predetermined pitch on a first main surface of a first conductivity type semiconductor substrate. A plurality of trenches, a first insulating film provided inside the first trench along an inner wall of the first trench among the plurality of trenches, and inside the first trench via the first insulating film A first control electrode provided; a second insulating film provided in the second trench along an inner wall of the remaining second trench excluding the first trench among the plurality of trenches; A second control electrode provided inside the second trench through two insulating films and electrically insulated from the first control electrode; and the first trench and the first of the first conductivity type semiconductor substrate. Only in the part sandwiched between two trenches, A second conductive semiconductor region provided in contact with the first trench; a first conductive semiconductor region formed in contact with the first trench in the second conductive semiconductor region; A second conductive type semiconductor region, a first main electrode electrically connected to the first conductive type semiconductor region, and a second conductive type semiconductor layer provided on a second main surface of the first conductive type semiconductor substrate And a second main electrode in contact with the second conductivity type semiconductor layer, wherein the pitch of the portion of the first conductivity type semiconductor substrate sandwiched between the adjacent second trenches is depleted when blocking forward voltage In the method of controlling a semiconductor device provided with the trench, the second control electrode and the second control electrode are arranged such that a potential of the second control electrode is the same as that of the first main electrode during operation of the semiconductor device. Voltage is applied between the first main electrode And wherein the Rukoto.

  According to the above-described invention, by providing the second trench in which the second control electrode of the emitter potential is embedded so as to sandwich the first trench in which the first control electrode is embedded, the gate potential at the turn-on is prevented from rising, The time change rate di / dt of the collector current can be reduced.

  According to the above-described invention, the second conductivity type floating region is not provided between the second trenches in which the second control electrode is embedded, and the first conductivity type semiconductor substrate is sandwiched between adjacent second trenches. Impurities per unit area integrated in a direction parallel to the first main surface of the first conductivity type semiconductor substrate of the mesa region by narrowing the trench pitch to such an extent that the portion (mesa region) is depleted when blocking forward voltage. The concentration can be lowered. For this reason, the electric field at the bottom of the trench where avalanche breakdown is likely to occur can be relaxed.

In addition, according to the above-described invention, the impurity concentration per unit area integrated in the direction parallel to the first main surface of the first conductivity type semiconductor substrate in the mesa region, with the trench pitch narrowed to 3.6 μm or less. Is set to 2.0 × 10 ¹⁰ cm ⁻² or less, so that the breakdown voltage of the active region can be 95% or more of the flat junction breakdown voltage and the breakdown voltage of the edge region can be equal to or higher than the breakdown voltage of the active region. can do. For this reason, the thickness of the n ⁻ drift region can be reduced to a thickness necessary for realizing a desired breakdown voltage, and the on-voltage can be reduced.

  Further, according to the above-described invention, the second conductivity type floating region and the outer periphery of the active region are conventionally provided by not providing the second conductivity type floating region between the second trenches in which the second control electrode is embedded. There is no need to separate the hole extraction second conductivity type region of the portion (for example, the edge structure region) with a trench (separation structure portion). Therefore, when the forward voltage is blocked (in a blocking state where no current flows), the electric field concentration in the separation structure portion does not occur, and a decrease in breakdown voltage can be prevented. Further, in the steady-on state, holes are not extracted from the second conductivity type region for hole extraction via the second conductivity type floating region, so that it is possible to prevent the surface hole concentration from decreasing and the ON voltage from increasing. Can do.

  According to the semiconductor device and the method for controlling the semiconductor device according to the present invention, it is possible to reduce the gate-collector capacitance. In addition, according to the semiconductor device and the semiconductor device control method of the present invention, it is possible to provide a semiconductor device having a high breakdown voltage and a method for controlling the semiconductor device. In addition, according to the semiconductor device and the method for controlling the semiconductor device according to the present invention, it is possible to provide a semiconductor device having a low on-voltage and a method for controlling the semiconductor device.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment. It is a characteristic view shown about the on-voltage characteristic of the semiconductor device concerning an embodiment. It is a characteristic view shown about the pressure resistance characteristic of the semiconductor device concerning an embodiment. It is sectional drawing which shows the structure of the conventional semiconductor device. It is sectional drawing which shows another example of a structure of the conventional semiconductor device.

  Exemplary embodiments of a semiconductor device and a semiconductor device control method according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. A case where the semiconductor device according to the embodiment is applied to a field stop type IGBT (FS-IGBT) will be described as an example. As shown in FIG. 1, the semiconductor device according to the first embodiment is provided on the front surface (first main surface) of an n ⁻ semiconductor substrate (first conductivity type semiconductor substrate) to be the n ⁻ drift region 1. p base region (second conductivity type semiconductor region) 2, n ⁺ emitter region (first conductivity type semiconductor region) 3, first trench (hereinafter referred to as gate trench) 4, gate insulating film (first insulating film) 5 And a trench gate type MOS (insulated gate made of metal-oxide film-semiconductor) structure comprising a gate electrode (first control electrode) 6. The region provided with the trench gate type MOS structure is an active region through which a current flows when the semiconductor device is turned on.

Further, a second trench (hereinafter referred to as a dummy trench) 14, a dummy gate insulating film (second insulating film) 15, and a dummy gate electrode (second control electrode) 16 are formed on the front surface of the n ⁻ semiconductor substrate. A dummy trench gate structure is provided. A p ⁺ collector region (second conductivity type semiconductor layer) 10 is provided on the surface layer of the back surface (second main surface) of the n ⁻ semiconductor substrate. An n buffer region 9 is provided between the n ⁻ drift region 1 and the p ⁺ collector region 10. The collector electrode (second main electrode) 11 is in contact with the p ⁺ collector region 10 and further connected to the collector pad C. The region in which the dummy trench 14 is provided is an edge structure region that relaxes the electric field on the front surface side of the n ⁻ drift region 1 and maintains a withstand voltage.

Gate trench 4 and dummy trench 14 are provided with a depth that does not reach the back surface from the front surface of the n ⁻ semiconductor substrate, and are constituted by a plurality of trenches arranged at a predetermined pitch. The plurality of trenches have a striped planar layout extending in a direction (the depth direction in FIG. 1, hereinafter referred to as the longitudinal direction in FIG. 1) orthogonal to the direction in which the trenches are arranged (hereinafter referred to as the lateral direction). A gate oxide film is provided along the inner wall of each trench. Each trench is provided with a gate electrode made of low-resistance polysilicon (poly-Si) doped with phosphorus (P) at a high impurity concentration through a gate oxide film.

The width (hereinafter simply referred to as width) w1 of the trench in the short direction is preferably larger than 1.0 μm and not larger than 2.0 μm. The reason is as follows. This is because when the trench width w1 is 1.0 μm or less, the gate resistance increases and the gate delay increases. Further, if the width w1 of the trench is larger than 2.0 μm, it is difficult to fill the trench uniformly with polysilicon. The trench pitch d is preferably so narrow that the portion (mesa region) 12 sandwiched between the adjacent dummy trenches 14 in the n ⁻ drift region 1 is depleted when blocking forward voltage. The mesa region 12 sandwiched between the adjacent dummy trenches 14 is preferably depleted to such an extent that a desired breakdown voltage can be realized, for example, and preferably completely depleted. More specifically, the trench pitch d is preferably, for example, not less than 1.8 μm and not more than 3.6 μm. The reason is as follows.

When the trench pitch d is smaller than 1.8 μm, the width (hereinafter simply referred to as width) w2 of the mesa region 12 sandwiched between adjacent trenches is smaller than 0.8 μm, so that the semiconductor device is manufactured. Because it becomes difficult. Further, when the trench pitch d is larger than 3.6 μm, the mesa region 12 sandwiched between the adjacent dummy trenches 14 is not easily depleted when the forward voltage is blocked, and the breakdown voltage is reduced. If the breakdown voltage is too low, the thickness of the n ⁻ drift region 1 needs to be thicker than the minimum thickness of the n ⁻ drift region required to achieve the desired breakdown voltage, and the on-voltage is further increased. Problems also arise. Further, the breakdown voltage of the active region is higher than the breakdown voltage of the edge structure region, and the avalanche breakdown resistance decreases in the edge structure region.

Among these trenches, n ⁺ emitter regions 3 are provided on both side surfaces parallel to the longitudinal direction of some of the trenches. The n ⁺ emitter region 3 is in contact with the gate insulating film 5 provided along the side wall of the gate trench 4. A trench with which the n ⁺ emitter region 3 is in contact is a gate trench 4, and a current flow between the n ⁺ emitter region 3 and the p ⁺ collector region 10 is controlled by the gate electrode 6 embedded in the gate trench 4. A control voltage is applied. The gate electrode 6 is connected to the gate pad G at the end in the longitudinal direction of the gate trench 4.

The n ⁺ emitter region 3 has a higher impurity concentration than the n ⁻ drift region 1 and is formed, for example, by doping with arsenic (As). The n ⁺ emitter region 3 is surrounded by the p base region 2. The p base region 2 is provided only in a portion of the n ⁻ drift region 1 sandwiched between the gate trench 4 and the dummy trench 14. The p base region 2 may be in contact with the side surface of the dummy trench 14 adjacent to the gate trench 4 on the gate trench 4 side. A portion of p base region 2 sandwiched between n ⁺ emitter region 3 and n ⁻ drift region 1 is in contact with gate insulating film 5 provided along the side wall of gate trench 4. The depth of the p base region 2 is shallower than the depth of the gate trench 4. Emitter electrode (first main electrode) 7 is electrically connected to p base region 2 and n ⁺ emitter region 3. The emitter electrode 7 is connected to the emitter pad E.

  Among the plurality of trenches, a trench other than the gate trench 4 is a dummy trench 14. A plurality of dummy trenches 14 are provided between adjacent gate trenches 4 (not shown). That is, both sides of one gate trench 4 are dummy trenches 14. The gate insulating film provided along the inner wall of the dummy trench 14 is the dummy gate insulating film 15, and the gate electrode embedded in the dummy trench 14 is the dummy gate electrode 16. The dummy gate electrode 16 is electrically insulated from the gate electrode 6 by the interlayer insulating film 8. All the dummy gate electrodes 16 are connected to the emitter pad E at the end in the longitudinal direction of the dummy trench 14, for example, and have an emitter potential. The dummy gate electrode 16 may be in direct contact with the emitter electrode 7.

The mesa region 12 sandwiched between adjacent dummy trenches 14 is not provided with a p-floating region as in the prior art. That is, the mesa region 12 sandwiched between the adjacent dummy trenches 14 is the n ⁻ drift region 1. The impurity concentration of the mesa region 12 sandwiched between adjacent dummy trenches 14 is preferably in the range of 1.0 × 10 ⁹ cm ⁻² or more and 2.0 × 10 ¹² cm ⁻² or less. The reason is as follows.

Silicon (Si), which is a constituent material of the n ⁻ semiconductor substrate (n ⁻ drift region 1), exhibits a physical property of reaching a critical electric field at a dose of 1.3 × 10 ¹² cm ⁻² . Therefore, when the depletion layer extends from the side surfaces of the dummy trenches 14 on both sides of the mesa region 12 to the mesa region 12, the impurity concentration of the mesa region 12 sandwiched between the adjacent dummy trenches 14 is 2.6 × 10 ¹² cm. Must be less than ^-2 . Therefore, considering the safety margin, the impurity concentration of the mesa region 12 sandwiched between the adjacent dummy trenches 14 is preferably in the range of 2.0 × 10 ¹² cm ⁻² or less.

Further, when the impurity concentration of the n ⁻ semiconductor substrate is 1.0 × 10 ¹³ cm ⁻² and the width w2 of the mesa region 12 is 0.8 μm, which is the manufacturable limit of the semiconductor device, it is sandwiched between the adjacent dummy trenches 14. The impurity concentration of the mesa region 12 is about 1.0 × 10 ⁹ cm ⁻² . When the impurity concentration of the mesa region 12 sandwiched between the adjacent dummy trenches 14 is smaller than 1.0 × 10 ⁹ cm ^−2, it is difficult to manufacture the semiconductor device, and at the same time, the mesa sandwiched between the adjacent dummy trenches 14. The resistance of the region 12 is increased. Therefore, the impurity concentration of the mesa region 12 sandwiched between the adjacent dummy trenches 14 is preferably in the range of 1.0 × 10 ⁹ cm ⁻² or more.

Next, the operation of the semiconductor device according to the embodiment will be described. In the off state, with the gate electrode 6 at the same potential with respect to the emitter electrode 7, a positive voltage of several volts is applied to the collector electrode 11 to bring the collector electrode 11 to a high potential with respect to the emitter electrode 7. In this state, n ^- the reverse-biased junction between the drift region 1 and the p base region 2, below the Gyaku耐voltage the n ^- depletion layer extends from the pn junction between the drift region 1 and the p base region 2, IGBT Becomes blocked. In this state, a positive voltage of about 15 V, for example, is applied to the gate electrode 6 to bring the gate electrode 6 to a high potential with respect to the emitter electrode 7.

Since the collector electrode 11 is at a higher potential than the emitter electrode 7, charges start to be accumulated in the gate electrode 6. At the same time, an n-channel region (not shown) inverted to the n-type is formed in a region of the p base region 2 that is in contact with the gate insulating film 5. When an n channel region is formed between the n ⁺ emitter region 3 and the n ⁻ drift region 1, the reverse bias junction disappears in the path passing through the n channel region. Accordingly, an electron current is injected from emitter electrode 7 into n ⁻ drift region 1 through n ⁺ emitter region 3 and n channel region.

When the injection of the electrons occurs, since the pn junction of the collector side is forward biased, the p ⁺ collector layer 10 n ^- hole which are minority carriers in the drift region 1 (holes) are injected, n ^- semiconductor substrate Contact It is extracted from the p base region 2 on the front surface. When injected into the drift region 1, n ^{- -} hole n the electron concentration are majority carriers increases in order to maintain the neutral condition of the carriers in the drift region 1, n ^- the electrical resistance of the drift region 1 is lower So-called conductivity modulation occurs. The voltage drop due to the collector current Ic flowing between the collector electrode 11 and the emitter electrode 7 is the on voltage, and the on voltage in the steady on state is reduced by conductivity modulation.

Next, the on-voltage of the semiconductor device according to the embodiment was verified. FIG. 2 is a characteristic diagram illustrating an on-voltage characteristic of the semiconductor device according to the embodiment. First, according to the embodiment, a trench gate type FS-IGBT having a rated voltage of 1200 V was manufactured (manufactured) (hereinafter referred to as an example). Specifically, an FZ substrate made of an n-type FZ (Float Zone) wafer having a specific resistance of 60 Ωcm was used as the n ⁻ semiconductor substrate to be the n ⁻ drift region 1. The thickness t of the n ⁻ semiconductor substrate was 120 μm. The thickness t of the n ⁻ semiconductor substrate is the total thickness of the n ⁻ drift region 1, n buffer region 9 and p ⁺ collector region 10.

The plurality of trenches to be the gate trenches 4 and the dummy trenches 14 are formed in a striped planar layout that is arranged at equal intervals in the lateral direction and extends in the longitudinal direction. The trench pitch d was set to 3.0 μm, and the width w1 of the trench was set to 1.2 μm. The thickness of the gate oxide film was 100 nm. The gate electrode 6 was formed of polysilicon doped with high concentration phosphorus. The dopant for forming the n ⁺ emitter region 3 was arsenic. The gate electrode 6 was connected to the gate pad G at the longitudinal end of the gate trench 4. The dummy gate electrode 16 is connected to the emitter pad E, for example, at the end of the dummy trench 14 in the longitudinal direction.

  For comparison, an FS-IGBT having a conventional incomplete floating p-floating region shown in FIG. 5 was fabricated (hereinafter referred to as a conventional example). In the conventional example, a p-floating region extending in the longitudinal direction to the cell end is provided in each mesa region sandwiched between adjacent dummy trenches. The cell end of the p floating region was brought into contact with the emitter electrode. Other configurations of the conventional example are the same as those of the example. For these examples and the conventional example, a positive voltage of about 15 V was applied to the gate electrode, and simultaneously, a positive voltage of several volts was applied to the collector electrode, and the collector-emitter voltage Vce (ON voltage) was measured. As shown in FIG.

From the results shown in FIG. 2, it was confirmed that the on-voltage of the example was reduced by 0.4 V or more than the on-voltage of the conventional example. The reason is as follows. In the conventional example, a part of the holes injected from the p collector layer into the n ⁻ drift region enters the p floating region and flows in a direction (lateral direction) parallel to the main surface of the n ⁻ semiconductor substrate to be the emitter at the cell end. It is pulled out from the contact part with the electrode. For this reason, the hole concentration near the cell edge has decreased. On the other hand, in the embodiment, since there is no p floating region in each mesa region 12 sandwiched between adjacent dummy trenches 14, the hole concentration at the cell edge does not decrease.

  Next, the relationship between the trench pitch d and the breakdown voltage of the semiconductor device according to the embodiment was verified. FIG. 3 is a characteristic diagram illustrating the breakdown voltage characteristics of the semiconductor device according to the embodiment. As described above, when the collector electrode 11 is increased in a state where the gate electrode 6 is set to the same potential with respect to the emitter electrode 7, a blocking state in which no current flows is obtained. At this time, the bottom surface of the gate trench 4 in the active region is a portion where the electric field concentrates, and a portion where avalanche breakdown occurs. In the conventional example, a p-floating region is provided in a region sandwiched between the gate trench and the dummy trench to reduce the electric field on the bottom surface of the gate trench. On the other hand, in the embodiment, since the trench pitch d is as narrow as 3.0 μm, it is possible to prevent the breakdown voltage from decreasing without providing the p floating region.

In the embodiment, an ideal one-dimensional breakdown voltage (hereinafter referred to as a planar junction breakdown voltage) of a planar junction (pn junction between the n ⁻ drift region 1 and the p base region 2) is, for example, 1310 V, and an edge structure The breakdown voltage of the region is preferably designed to be slightly lower than the flat junction breakdown voltage and 95% or more of the flat junction breakdown voltage. Furthermore, the breakdown voltage of the active region is desirably lower than the breakdown voltage of the edge structure region. This is because when the breakdown voltage of the active region is higher than the breakdown voltage of the edge structure region, an avalanche current is generated in the edge structure region before the active region, resulting in avalanche breakdown. By making the breakdown voltage of the active region lower than the breakdown voltage of the edge structure region, an avalanche current is generated in the active region having a large area before the edge structure region. Thereby, since the avalanche current density can be reduced, the breakdown tolerance can be improved.

On the other hand, when the withstand voltage of the active region is too low with respect to the withstand voltage of the edge structure region, it is necessary to increase the thickness of the n ⁻ drift region 1 in order to satisfy the withstand voltage standard, and the on-voltage increases. For this reason, the breakdown voltage of the active region is preferably 95% or more of the planar junction breakdown voltage. That is, it is preferable to design the device so that the breakdown voltage of the active region is 95% or more of the planar junction breakdown voltage and the breakdown voltage of the edge region is equal to or higher than the breakdown voltage of the active region. As shown in FIG. 3, when the planar junction breakdown voltage is set to 1310 V (indicated by the broken line 21) in the embodiment, the lower limit value of the breakdown voltage of the active region is 1244 V (indicated by the broken line 22) 5% lower than the planar junction breakdown voltage. The element design is performed as follows. Specifically, when the trench pitch d is 3.6 μm or less, the breakdown voltage of the active region can be 95% or more of the planar junction breakdown voltage, and a very high breakdown voltage can be realized. Accordingly, the trench pitch d is preferably 3.6 μm or less. Further, it is more preferable to set the trench pitch d to 3.0 μm as in the embodiment because the active region can have a breakdown voltage of 98% of the planar junction breakdown voltage.

  As described above, according to the embodiment, by providing the dummy trench in which the dummy gate electrode of the emitter potential is embedded so as to sandwich the gate trench in which the gate electrode is embedded, the gate potential is increased at the time of turn-on. It is possible to prevent and reduce the time change rate di / dt of the collector current. As a result, the gate-collector capacitance (Qgc) is reduced, and the switching operation is speeded up. In addition, gate driving with a gate driver having low driving capability is also possible.

  Further, according to the embodiment, the p floating region is not provided between the dummy trenches in which the dummy gate electrode of the emitter potential is embedded, and the mesa region sandwiched between the adjacent dummy trenches is depleted when the forward voltage is blocked. By narrowing the trench pitch, the impurity concentration of the mesa region sandwiched between adjacent dummy trenches can be lowered. For this reason, the electric field at the bottom of the trench where avalanche breakdown is likely to occur can be relaxed. Thereby, a pressure | voltage resistant fall can be prevented.

In addition, according to the embodiment, the trench pitch is narrowed to 3.6 μm or less, or the impurity concentration of the mesa region is set to 2.0 × 10 ¹⁰ cm ⁻² or less, whereby the breakdown voltage of the active region is planar bonded. The breakdown voltage can be 95% or more of the breakdown voltage, the breakdown voltage of the edge region can be higher than the breakdown voltage of the active region, and a high breakdown voltage can be realized. Since a high breakdown voltage can be realized, the thickness of the n ⁻ drift region can be reduced to a thickness necessary for realizing a desired breakdown voltage, and the on-voltage can be lowered. In addition, since the on-voltage can be reduced, the power conversion efficiency can be increased when used as a circuit such as an inverter.

  Further, according to the embodiment, the p floating region is not provided between the dummy trenches in which the dummy gate electrode of the emitter potential is embedded, so that the p floating region and the active region outer peripheral portion (for example, the edge structure) are conventionally provided. It is not necessary to separate the p-type region for hole extraction in the region with a trench (separation structure). Therefore, when the forward voltage is blocked (in a blocking state where no current flows), the electric field concentration in the separation structure portion does not occur, and a decrease in breakdown voltage can be prevented. In the steady-on state, holes are not extracted from the p-type region for hole extraction via the p floating region, so that it is possible to prevent the surface hole concentration from decreasing and the ON voltage from increasing.

  In the above description, the FS-IGBT is described as an example in the present invention. However, the present invention is not limited to the above-described embodiment, and can be applied to semiconductor devices having various configurations provided with dummy trenches. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the semiconductor device control method according to the present invention are useful for a power semiconductor device used in a power conversion device.

1 n ⁻ drift region 2 p base region 3 n ⁺ emitter region 4 gate trench 5 gate insulating film 6 gate electrode 7 emitter electrode 8 interlayer insulating film 9 n buffer region 10 p ⁺ collector region 11 collector electrode 14 dummy trench 15 dummy gate insulating Film 16 Dummy gate electrode E Emitter pad G Gate pad C Collector pad

Claims (4)

A plurality of trenches provided at a predetermined pitch on the first main surface of the first conductivity type semiconductor substrate;
A first insulating film provided inside the first trench along an inner wall of the first trench among the plurality of trenches;
A first control electrode provided inside the first trench via the first insulating film;
A second insulating film provided inside the second trench along an inner wall of the remaining second trench excluding the first trench among the plurality of trenches;
A second control electrode provided inside the second trench via the second insulating film and electrically insulated from the first control electrode;
A second conductivity type semiconductor region provided to be in contact with the first trench only in a portion of the first conductivity type semiconductor substrate sandwiched between the first trench and the second trench;
A first conductivity type semiconductor region formed in contact with the first trench inside the second conductivity type semiconductor region;
A first main electrode electrically connected to the second conductive semiconductor region and the first conductive semiconductor region;
A second conductivity type semiconductor layer provided on a second main surface of the first conductivity type semiconductor substrate;
A second main electrode in contact with the second conductivity type semiconductor layer;
With
The second control electrode is electrically connected to the first main electrode;
The semiconductor device according to claim 1, wherein the trenches are provided at the predetermined pitch at which a portion sandwiched between the adjacent second trenches of the first conductivity type semiconductor substrate is depleted when blocking forward voltage. A depth of the second conductive type semiconductor region is shallower than a depth of the trench;
2. The semiconductor device according to claim 1, wherein an impurity concentration of a portion sandwiched between the adjacent second trenches of the first conductivity type semiconductor substrate is 2.0 × 10 ¹⁰ cm ⁻² or less.   The semiconductor device according to claim 1, wherein the pitch of the trench is 3.6 μm or less. A plurality of trenches provided at a predetermined pitch on the first main surface of the first conductivity type semiconductor substrate, and provided inside the first trench along an inner wall of the first trench among the plurality of trenches. A first insulating film, a first control electrode provided inside the first trench through the first insulating film, and an inner wall of the remaining second trench excluding the first trench among the plurality of trenches A second insulating film provided in the second trench along the first insulating film, and a second insulating film provided in the second trench through the second insulating film and electrically insulated from the first control electrode. Two control electrodes, and a second conductive semiconductor region provided in contact with the first trench only in a portion of the first conductive semiconductor substrate sandwiched between the first trench and the second trench. , Inside the second conductive type semiconductor region A first conductive type semiconductor region formed in contact with the first trench; a first main electrode electrically connected to the second conductive type semiconductor region and the first conductive type semiconductor region; A second conductive type semiconductor layer provided on the second main surface of the conductive type semiconductor substrate; and a second main electrode in contact with the second conductive type semiconductor layer, adjacent to the first conductive type semiconductor substrate. A method for controlling a semiconductor device in which the trench is provided at the pitch at which a portion sandwiched between the matching second trenches is depleted when blocking forward voltage,
A voltage is applied between the second control electrode and the first main electrode so that the potential of the second control electrode becomes the same as that of the first main electrode during the operation of the semiconductor device. A method for controlling a semiconductor device.

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