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JP2013247236A - Component built-in substrate and manufacturing method thereof - Google Patents

Component built-in substrate and manufacturing method thereof Download PDF

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JP2013247236A
JP2013247236A JP2012119906A JP2012119906A JP2013247236A JP 2013247236 A JP2013247236 A JP 2013247236A JP 2012119906 A JP2012119906 A JP 2012119906A JP 2012119906 A JP2012119906 A JP 2012119906A JP 2013247236 A JP2013247236 A JP 2013247236A
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printed wiring
substrate
component
electronic component
adhesive layer
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JP5920716B2 (en
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Yoshio Nakao
吉男 中尾
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Fujikura Ltd
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Abstract

PROBLEM TO BE SOLVED: To restrain a void while thinning a substrate.SOLUTION: In a component built-in substrate, first to fourth printed wiring base materials 10-40 on which wiring patterns and vias are formed are laminated on an insulation base material, and an electronic component 90 is built in an opening 29 of the second printed wiring base material 20. The component built-in substrate manufacturing method is performed as follows. First, protection layers 92 are formed on an electrode formation face 9a and an opposite side face 9b of the electronic component 90 via an adhesive layer 9b. Next, an adhesive layer 9a is formed on one face of the first printed wiring base material 10. Then, the protection layers 92 and the adhesive layer 9a are opposed to each other, so as to crimp the electronic component 90 and the first printed wiring base material 10.

Description

この発明は、電子部品を内蔵する部品内蔵基板、及びその製造方法に関する。   The present invention relates to a component-embedded substrate that incorporates an electronic component and a method for manufacturing the same.

近年、携帯電話等の高度化や低コスト化が進み、その内部に設けられる電子部品、配線基板に更なる改良が要求されている。よって、配線基板の薄型化や製法の簡易化を達成するため様々な試みが行われている(特許文献1参照)。   In recent years, mobile phones and the like have become more sophisticated and lower in cost, and further improvements have been required for electronic components and wiring boards provided therein. Therefore, various attempts have been made to achieve thinning of the wiring board and simplification of the manufacturing method (see Patent Document 1).

そして、電子部品の高密度実装を実現するため、電子部品を配線基板に内蔵した部品内蔵基板が知られている。このような部品内蔵基板の製造工程おいては、配線基板及び電子部品に接着材を付着させておく。次に、配線基板に形成されたキャビティ(開口)に電子部品を入れ込み、配線基板と電子部品を圧着させる。これにより、キャビティと電子部品との間のクリアランス部(隙間)に接着材が流れこむようにさせる。   In order to realize high-density mounting of electronic components, a component-embedded substrate in which electronic components are embedded in a wiring substrate is known. In the manufacturing process of such a component built-in substrate, an adhesive is attached to the wiring substrate and the electronic component. Next, an electronic component is put into a cavity (opening) formed in the wiring board, and the wiring board and the electronic component are pressure-bonded. Thereby, the adhesive material flows into the clearance (gap) between the cavity and the electronic component.

特開2001−119148号公報JP 2001-119148 A

しかしながら、部品内蔵基板を薄型化させるために接着材の量を減少させると、クリアランス部に流れこむ接着材の量も減少し、クリアランス部にボイドが形成されるという問題がある。   However, if the amount of the adhesive is reduced in order to reduce the thickness of the component-embedded substrate, the amount of the adhesive flowing into the clearance portion also decreases, and there is a problem that a void is formed in the clearance portion.

この発明は、上述した従来技術による問題点を解消し、薄型化すると共にボイドの発生を抑制できる部品内蔵基板の製造方法を提供することを目的とする。   An object of the present invention is to provide a method for manufacturing a component-embedded substrate that eliminates the above-described problems caused by the prior art and can reduce the thickness and suppress the generation of voids.

本発明に係る部品内蔵基板の製造方法は、絶縁基材に配線パターンが形成されたプリント配線基材を複数積層すると共に電子部品を内蔵してなる部品内蔵基板の製造方法であって、前記電子部品の電極形成面と反対側の面に第1接着層を形成すると共に前記第1接着層を保護層で覆う工程と、前記プリント配線基材の少なくとも一方の面に第2接着層を形成する工程と、前記保護層と前記第2接着層とを対向させて、前記電子部品と前記プリント配線基材とを圧着させる工程とを備えることを特徴とする。   A method for manufacturing a component-embedded substrate according to the present invention is a method for manufacturing a component-embedded substrate, in which a plurality of printed wiring substrates each having a wiring pattern formed on an insulating substrate are stacked and an electronic component is embedded. Forming a first adhesive layer on a surface of the component opposite to the electrode forming surface and covering the first adhesive layer with a protective layer; and forming a second adhesive layer on at least one surface of the printed wiring substrate. And a step of pressing the electronic component and the printed wiring substrate so that the protective layer and the second adhesive layer are opposed to each other.

本発明に係る部品内蔵基板の製造方法によれば、電子部品とプリント配線基材とを圧着させた際に、両者の間に存在する第1及び第2接着層に圧力がかかるので、第1及び第2接着層が保護層に沿って流れ出る。これにより、クリアランス部に第1及び第2接着層が適切に入り込むので、薄型化すると共にボイドの発生を抑制できる。また、電子部品に第1接着層を形成する際には、第1接着層は保護層により覆われるので、電子部品とプリント配線基材とを圧着積層する際のハンドリングも良好である。   According to the method for manufacturing a component-embedded substrate according to the present invention, when the electronic component and the printed wiring substrate are pressure-bonded, pressure is applied to the first and second adhesive layers existing between them. And the second adhesive layer flows out along the protective layer. Thereby, since the 1st and 2nd adhesive layers enter into a clearance part appropriately, generation | occurrence | production of a void can be suppressed while reducing in thickness. Further, when the first adhesive layer is formed on the electronic component, the first adhesive layer is covered with the protective layer, so that the handling when the electronic component and the printed wiring substrate are pressure-bonded and laminated is also good.

部品内蔵基板の製造方法の一つの実施形態において、前記保護層は、前記電子部品と前記プリント配線基材とを圧着させる工程における圧着温度よりも高い融点を有する。これにより、保護層は圧着工程において溶け出すことはなく、第1及び第2接着層の物性は変化しない。   In one embodiment of the method for manufacturing a component-embedded substrate, the protective layer has a melting point higher than a pressure bonding temperature in a step of pressure bonding the electronic component and the printed wiring board. Thereby, a protective layer does not melt out in a press-bonding process, and the physical properties of the first and second adhesive layers do not change.

本発明に係る部品内蔵基板は、上述した本発明に係る製造方法により製造された部品内蔵基板であることを特徴とする。   The component-embedded substrate according to the present invention is a component-embedded substrate manufactured by the above-described manufacturing method according to the present invention.

本発明に係る部品内蔵基板によれば、保護層を介して第1及び第2接着層により電子部品とプリント配線基材とが圧着されている。よって、クリアランスに接着材を効率的に流し込むことができると共に、第1及び第2接着層が物性を変えることなく安定して電子部品とプリント配線基材とを接着させることができる。。   According to the component-embedded substrate according to the present invention, the electronic component and the printed wiring board are pressure-bonded by the first and second adhesive layers via the protective layer. Therefore, the adhesive can be efficiently poured into the clearance, and the first and second adhesive layers can stably adhere the electronic component and the printed wiring board without changing the physical properties. .

本発明によれば、薄型化すると共にボイドの発生を抑制できる。   According to the present invention, it is possible to reduce the thickness and suppress the generation of voids.

本発明の実施形態に係る部品内蔵基板の構造を示す断面図である。It is sectional drawing which shows the structure of the component built-in board | substrate which concerns on embodiment of this invention. 同部品内蔵基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the same component built-in board. 同部品内蔵基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the same component built-in board. 同部品内蔵基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the same component built-in board. 同部品内蔵基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the same component built-in board. 同部品内蔵基板の製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the same component built-in board. 同部品内蔵基板を製造工程毎に示す断面図である。It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. 同部品内蔵基板を製造工程毎に示す断面図である。It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process. 同部品内蔵基板を製造工程毎に示す断面図である。It is sectional drawing which shows the same component built-in board | substrate for every manufacturing process.

以下、添付の図面を参照して、この発明の実施の形態に係る部品内蔵基板及びその製造方法を詳細に説明する。   Hereinafter, a component-embedded substrate and a manufacturing method thereof according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図1は、本発明の実施形態に係る部品内蔵基板の構造を示す断面図である。図1に示すように、実施形態に係る部品内蔵基板は、第1プリント配線基材10と、第2プリント配線基材20と、第3プリント配線基材30と、第4プリント配線基材40とを熱圧着(接着層9a〜9d)により一括積層した構造を備えている。接着層9a,9bは、第1プリント配線基材10と第2プリント配線基材20との間を接着する。接着層9cは、第2プリント配線基材20と第3プリント配線基材30との間を接着し、接着層9dは、第3プリント配線基材30と第4プリント配線基材40との間を接着する。接着層9a〜9dは、例えばエポキシ系やアクリル系の接着剤など、揮発成分が含まれた有機系接着剤などからなる。   FIG. 1 is a cross-sectional view showing the structure of a component-embedded substrate according to an embodiment of the present invention. As shown in FIG. 1, the component-embedded substrate according to the embodiment includes a first printed wiring substrate 10, a second printed wiring substrate 20, a third printed wiring substrate 30, and a fourth printed wiring substrate 40. Are laminated together by thermocompression bonding (adhesive layers 9a to 9d). The adhesive layers 9 a and 9 b adhere between the first printed wiring substrate 10 and the second printed wiring substrate 20. The adhesive layer 9c adheres between the second printed wiring base material 20 and the third printed wiring base material 30, and the adhesive layer 9d is between the third printed wiring base material 30 and the fourth printed wiring base material 40. Glue. The adhesive layers 9a to 9d are made of, for example, an organic adhesive containing a volatile component, such as an epoxy adhesive or an acrylic adhesive.

また、部品内蔵基板は、第2プリント配線基材20の第2樹脂基材21に形成された開口部29内に、第1及び第3プリント配線基材10,30に挟まれた状態で内蔵された電子部品90を備えている。開口部29と電子部品90と間にはクリアランス部50(隙間)が存在する。なお、クリアランス部50は、後述する製造工程を用いて、ボイドの発生を抑えて接着層9a,9bで埋められている。   Further, the component-embedded substrate is embedded in the opening 29 formed in the second resin substrate 21 of the second printed wiring substrate 20 while being sandwiched between the first and third printed wiring substrates 10 and 30. The electronic component 90 is provided. A clearance 50 (gap) exists between the opening 29 and the electronic component 90. The clearance portion 50 is filled with the adhesive layers 9a and 9b by suppressing the generation of voids by using a manufacturing process described later.

第1〜第4プリント配線基材10〜40は、それぞれ第1樹脂基材11、第2樹脂基材21、第3樹脂基材31及び第4樹脂基材41と、これら第1〜第4樹脂基材11〜41の少なくとも片面に形成された信号用配線12,22,32,42とを備える。また、第1〜第4プリント配線基材10〜40は、それぞれ第1、第3及び第4樹脂基材11,31,41に形成されたビアホール内に充填形成された信号用ビア14,34,44と、第2樹脂基材21に形成されたビアホール内に第2樹脂基材21の両面を導通するように形成された信号用ビア24とを備える。信号用ビア14は信号用配線12,22間を電気的に接続し、信号用ビア34は信号用配線22,32間を電気的に接続し、信号用ビア44は信号用配線32,42間を電気的に接続する。   The 1st-4th printed wiring base materials 10-40 are the 1st resin base material 11, the 2nd resin base material 21, the 3rd resin base material 31, and the 4th resin base material 41, respectively, these 1st-4th. Signal wirings 12, 22, 32, and 42 formed on at least one surface of the resin base materials 11 to 41 are provided. In addition, the first to fourth printed wiring substrates 10 to 40 are signal vias 14 and 34 that are filled in via holes formed in the first, third, and fourth resin substrates 11, 31, and 41, respectively. , 44 and a signal via 24 formed so as to conduct both surfaces of the second resin substrate 21 in a via hole formed in the second resin substrate 21. The signal via 14 electrically connects the signal wirings 12 and 22, the signal via 34 electrically connects the signal wirings 22 and 32, and the signal via 44 connects between the signal wirings 32 and 42. Are electrically connected.

また、第1、第4プリント配線基材10、40は、それぞれ第1樹脂基材11、第4樹脂基材41上において、信号用配線12,42が形成されていない部分にソルダーレジスト18,48を有する。   Further, the first and fourth printed wiring base materials 10 and 40 are respectively formed on the first resin base material 11 and the fourth resin base material 41 at portions where the signal wirings 12 and 42 are not formed. 48.

上記の第1〜第4プリント配線基材10〜40は、例えば片面銅張積層板(片面CCL)や両面銅張積層板(両面CCL)などを用いることができる。本例では、第2プリント配線基材20が両面CCLに基づき形成され、それ以外が片面CCLに基づき形成されている。従って、第2プリント配線基材20の信号用配線22は第2樹脂基材21の両面に形成され、信号用ビア24は、これら両面の信号用配線22を層間接続している。   As the first to fourth printed wiring substrates 10 to 40, for example, a single-sided copper-clad laminate (single-sided CCL), a double-sided copper-clad laminate (double-sided CCL), or the like can be used. In this example, the second printed wiring board 20 is formed based on the double-sided CCL, and the other is formed based on the single-sided CCL. Accordingly, the signal wiring 22 of the second printed wiring substrate 20 is formed on both surfaces of the second resin substrate 21, and the signal via 24 connects the signal wirings 22 on both surfaces with each other.

第1〜第4樹脂基材11〜41は、それぞれ例えば厚さ25μm程度の樹脂フィルムにより構成されている。ここで、樹脂フィルムとしては、例えば熱可塑性のポリイミド、ポリオレフィン、液晶ポリマーなどからなる樹脂フィルムや、熱硬化性のエポキシ樹脂からなる樹脂フィルムなどを用いることができる。   The 1st-4th resin base materials 11-41 are each comprised by the resin film about 25 micrometers thick, for example. Here, as the resin film, for example, a resin film made of thermoplastic polyimide, polyolefin, liquid crystal polymer, or the like, or a resin film made of a thermosetting epoxy resin can be used.

信号用配線12,22,32,42は、銅箔などの導電材をパターン形成してなる。信号用ビア14,34,44は、ビアホール内にそれぞれ充填された導電ペーストからなり、信号用ビア24は、めっきにより形成される。   The signal wirings 12, 22, 32, and 42 are formed by patterning a conductive material such as copper foil. The signal vias 14, 34, and 44 are each made of a conductive paste filled in the via holes, and the signal via 24 is formed by plating.

導電ペーストは、例えばニッケル、金、銀、銅、アルミニウム、鉄などから選択される少なくとも1種類の低電気抵抗の金属粒子と、錫、ビスマス、インジウム、鉛などから選択される少なくとも1種類の低融点の金属粒子とを含み、エポキシ、アクリル、ウレタンなどを主成分とするバインダ成分を混合したペーストからなる。   The conductive paste is, for example, at least one kind of low electrical resistance metal particles selected from nickel, gold, silver, copper, aluminum, iron and the like, and at least one kind selected from tin, bismuth, indium, lead and the like. And a metal paste having a melting point and a paste in which a binder component mainly composed of epoxy, acrylic, urethane or the like is mixed.

このように構成された導電ペーストは、含有された低融点の金属が200℃以下で溶融し合金を形成することができ、特に銅や銀などとは金属間化合物を形成することができる特性を備える。なお、導電ペーストは、例えば粒子径がナノレベルの金、銀、銅、ニッケル等のフィラーが、上記のようなバインダ成分に混合されたナノペーストで構成することもできる。   The conductive paste thus configured has a characteristic that the contained low melting point metal can be melted at 200 ° C. or less to form an alloy, and in particular, can form an intermetallic compound with copper or silver. Prepare. Note that the conductive paste can also be formed of a nanopaste in which fillers such as gold, silver, copper, and nickel having a nanometer particle size are mixed with the binder component as described above.

その他、導電ペーストは、上記ニッケル等の金属粒子が、上記のようなバインダ成分に混合されたペーストで構成することもできる。この場合、導電ペーストは、金属粒子同士が接触することで電気的接続が行われる特性となる。導電ペーストのビアホールへの充填方法としては、例えば印刷法、スピン塗布工法、スプレー塗布工法、ディスペンス工法、ラミネート工法、及びこれらを併用した工法などを用いることができる。   In addition, the conductive paste can also be composed of a paste in which metal particles such as nickel are mixed with the binder component as described above. In this case, the conductive paste has a characteristic that electrical connection is made when metal particles come into contact with each other. As a method for filling the via holes with the conductive paste, for example, a printing method, a spin coating method, a spray coating method, a dispensing method, a laminating method, and a method using these in combination can be used.

電子部品90は、WLP(Wafer Level Package)により構成される。図1に示すように、電子部品90の電極形成面91bには電極91Bが設けられる。電子部品90の電極形成面91bの反対側の裏面91aには接着層9bが設けられ、その接着層9aの表面には保護層92が設けられる。そして、保護層92と第1プリント配線基材10に表面に設けられた接着層9aとを対向させて、電子部品90と第1プリント配線基材10は圧着されている。   The electronic component 90 is configured by WLP (Wafer Level Package). As shown in FIG. 1, an electrode 91 </ b> B is provided on the electrode formation surface 91 b of the electronic component 90. An adhesive layer 9b is provided on the back surface 91a opposite to the electrode forming surface 91b of the electronic component 90, and a protective layer 92 is provided on the surface of the adhesive layer 9a. The electronic component 90 and the first printed wiring substrate 10 are pressure-bonded so that the protective layer 92 and the adhesive layer 9a provided on the surface of the first printed wiring substrate 10 are opposed to each other.

ここで、上記の保護層92は、後述する第1〜第4プリント配線基材10〜40及び電子部品90を圧着させる工程における温度よりも高い融点を有する。例えば、保護層92は、融点が250℃以上の物質であれば良く、金属箔(銅、アルミニウム等)、又は絶縁層(PET,ポリイミド,液晶ポリマー等)にて構成される。また、保護層92は、金属箔、絶縁層を積層させたものであってもよい。   Here, said protective layer 92 has melting | fusing point higher than the temperature in the process of crimping | bonding the 1st-4th printed wiring base materials 10-40 and the electronic component 90 which are mentioned later. For example, the protective layer 92 may be a substance having a melting point of 250 ° C. or higher, and is composed of a metal foil (copper, aluminum, etc.) or an insulating layer (PET, polyimide, liquid crystal polymer, etc.). The protective layer 92 may be a laminate of a metal foil and an insulating layer.

次に、実施形態に係る部品内蔵基板の製造方法について説明する。図2〜5は、部品内蔵基板の製造工程を示すフローチャートである。図6〜図9は、部品内蔵基板を製造工程毎に示す断面図である。なお、図2及び図6は第3プリント配線基材30の製造工程を示し、図3及び図7は第2プリント配線基材20の製造工程を示す。図4及び図8は電子部品90の製造工程を示し、図5及び図9は部品内蔵基板の製造工程の最終工程を示す。   Next, a method for manufacturing the component-embedded substrate according to the embodiment will be described. 2 to 5 are flowcharts showing manufacturing steps of the component built-in substrate. 6 to 9 are cross-sectional views showing the component-embedded substrate for each manufacturing process. 2 and 6 show the manufacturing process of the third printed wiring substrate 30, and FIGS. 3 and 7 show the manufacturing process of the second printed wiring substrate 20. 4 and 8 show the manufacturing process of the electronic component 90, and FIGS. 5 and 9 show the final process of the manufacturing process of the component built-in substrate.

先ず、第1、第3及び第4プリント配線基材10,30,40の製造工程について説明する。なお、これらは同様の工程で製造することができるので、ここでは図2を参照しながら代表して第3プリント配線基材30の製造工程について説明するが、第1及び第4プリント配線基材10,40についても同様である。   First, the manufacturing process of the 1st, 3rd and 4th printed wiring base materials 10, 30, and 40 is demonstrated. Since these can be manufactured in the same process, here, the manufacturing process of the third printed wiring substrate 30 will be described as a representative with reference to FIG. 2, but the first and fourth printed wiring substrates will be described. The same applies to 10, 40.

図6(a)に示すように、第3樹脂基材31の一方の面に導体層8が形成された片面銅張積層板(片面CCL)を準備する(ステップS100)。次に、導体層8上にフォトリソグラフィによりエッチングレジストを形成した後にエッチングを行って、図6(b)に示すように、信号用配線32等の配線パターンを形成する(ステップS102)。   As shown in FIG. 6A, a single-sided copper-clad laminate (single-sided CCL) in which the conductor layer 8 is formed on one surface of the third resin base material 31 is prepared (step S100). Next, after forming an etching resist on the conductor layer 8 by photolithography, etching is performed to form a wiring pattern such as the signal wiring 32 as shown in FIG. 6B (step S102).

配線パターンを形成したら、図6(c)に示すように、第3樹脂基材31の信号用配線32形成面側と反対側の面に、接着層9cを加熱圧着により貼り付ける(ステップS104)。そして、図6(d)に示すように、信号用配線32に向かって接着層9c及び第3樹脂基材31を貫通するビアホール6を所定箇所に形成し(ステップS106)、ビアホール6内にプラズマデスミア処理を施す。   When the wiring pattern is formed, as shown in FIG. 6C, the adhesive layer 9c is attached to the surface of the third resin base 31 opposite to the signal wiring 32 forming surface by thermocompression bonding (step S104). . Then, as shown in FIG. 6D, the via hole 6 penetrating the adhesive layer 9c and the third resin base material 31 toward the signal wiring 32 is formed at a predetermined location (step S106), and plasma is formed in the via hole 6. Apply desmear treatment.

最後に、図6(e)に示すように、形成したビアホール6内に、例えばスクリーン印刷により導電ペーストを充填して信号用ビア34を形成し(ステップS108)、信号用配線32及び信号用ビア34と共に、接着層9cが備えられた第3樹脂基材31を有する第3プリント配線基材30を形成する。このような処理を行って、第1及び第4プリント配線基材10,40や、更に多層の場合はその他のプリント配線基材を形成して準備しておく。なお、第1及び第4プリント配線基材10,40には、接着層9a,9dが設けられる。   Finally, as shown in FIG. 6E, the signal via 34 is formed by filling the formed via hole 6 with a conductive paste, for example, by screen printing (step S108), and the signal wiring 32 and the signal via. 34, the third printed wiring board 30 having the third resin base 31 provided with the adhesive layer 9c is formed. By performing such a process, the first and fourth printed wiring substrates 10 and 40, and in the case of a multilayer, other printed wiring substrates are formed and prepared. The first and fourth printed wiring substrates 10 and 40 are provided with adhesive layers 9a and 9d.

次に、図3を参照しながら第2プリント配線基材20の製造工程について説明する。なお、既に説明した箇所には同一の符号を附して説明を割愛する場合があり、各ステップの具体的な処理内容については上述した内容を適用可能であるとする。まず、図7(a)に示すように、第2樹脂基材21の両面に導体層8が形成された両面銅張積層板(両面CCL)を準備し(ステップS110)、図7(b)に示すように、所定箇所にビアホール6を形成して(ステップS112)、プラズマデスミア処理を行う。   Next, the manufacturing process of the second printed wiring board 20 will be described with reference to FIG. In addition, the part already demonstrated may attach | subject the same code | symbol, and may omit description, and suppose that the content mentioned above is applicable to the specific processing content of each step. First, as shown in FIG. 7A, a double-sided copper-clad laminate (double-sided CCL) in which the conductor layer 8 is formed on both sides of the second resin base material 21 is prepared (step S110), and FIG. As shown in FIG. 5, via holes 6 are formed at predetermined locations (step S112), and plasma desmear processing is performed.

次に、図7(c)に示すように、第2樹脂基材21の全面にパネルめっき処理を施して(ステップS114)、ビアホール6が形成された導体層8上及びビアホール6内にめっき層23を形成する。なお、めっき層23は後に信号用ビア24として用いられ、第2樹脂基材21の両面の導体層8を電気的に導通している。   Next, as shown in FIG. 7C, panel plating is performed on the entire surface of the second resin base material 21 (step S114), and a plating layer is formed on the conductor layer 8 in which the via hole 6 is formed and in the via hole 6. 23 is formed. The plating layer 23 is later used as a signal via 24 and electrically connects the conductor layers 8 on both surfaces of the second resin base material 21.

そして、図7(d)に示すように、第2樹脂基材21上のめっき層23及び導体層8に対してエッチングを行って信号用配線22や信号用ビア24などの配線パターンを形成する(ステップS116)。最後に、図7(e)に示すように、電子部品90が内蔵される部分の第2樹脂基材21をUVレーザなどにより除去し、開口部29を形成して(ステップS118)、第2プリント配線基材20を形成する。   Then, as shown in FIG. 7D, the plating layer 23 and the conductor layer 8 on the second resin base material 21 are etched to form wiring patterns such as the signal wiring 22 and the signal via 24. (Step S116). Finally, as shown in FIG. 7 (e), the second resin base material 21 where the electronic component 90 is embedded is removed by a UV laser or the like to form an opening 29 (step S118), and the second The printed wiring board 20 is formed.

次に、図4を参照しながら電子部品90の製造工程について説明する。先ず、図8(a)に示すように、ウェハ94を準備し、ウェハ94の一方の面に所定パターンの電極91Bを形成する(ステップS120)。次に、図8(b)に示すように、ウェハ94の他方の面に接着層9bを介して保護層92を形成する(ステップS122)。続いて、図8(c)に示すように、ダイシングにより電子部品90を個片化して作製する(ステップS124)。   Next, the manufacturing process of the electronic component 90 will be described with reference to FIG. First, as shown in FIG. 8A, a wafer 94 is prepared, and an electrode 91B having a predetermined pattern is formed on one surface of the wafer 94 (step S120). Next, as shown in FIG. 8B, a protective layer 92 is formed on the other surface of the wafer 94 via the adhesive layer 9b (step S122). Subsequently, as shown in FIG. 8C, the electronic component 90 is produced by dicing into pieces (step S124).

上記図4のステップS122の工程は、接着層9b及び保護層92からなるフィルムをウェハ94の他方の面に貼ることにより実行される。また、ステップS122の工程は次に示す工程により実行しても良い。すなわち、先ず、接着層9b及び保護層92からなるフィルムをウェハ94の他方の面に貼る。次に、フィルムから保護層92を剥離させ、新たな保護層を接着層9bを介してウェハ94の他方の面に付着させる。   The process of step S122 in FIG. 4 is performed by sticking a film composed of the adhesive layer 9b and the protective layer 92 to the other surface of the wafer 94. Further, the process of step S122 may be executed by the following process. That is, first, a film composed of the adhesive layer 9 b and the protective layer 92 is attached to the other surface of the wafer 94. Next, the protective layer 92 is peeled off from the film, and a new protective layer is attached to the other surface of the wafer 94 via the adhesive layer 9b.

以上のように第1〜第4プリント配線基材10〜40及び電子部品90を作製したら、図5に示すステップS130,S132の製造工程を行う。すなわち、先ず、図9に示すように、各プリント配線基材10〜40及び電子部品90を位置決めし、積層する(ステップS130)。ここで、電子部品90は、第2プリント配線基材20の開口部29に入れ込まれ、開口部29と電子部品90と間にはクリアランス部50が生じる。   If the 1st-4th printed wiring base materials 10-40 and the electronic component 90 are produced as mentioned above, the manufacturing process of step S130, S132 shown in FIG. 5 will be performed. That is, first, as shown in FIG. 9, each printed wiring board 10-40 and the electronic component 90 are positioned and laminated (step S130). Here, the electronic component 90 is inserted into the opening 29 of the second printed wiring board 20, and a clearance 50 is generated between the opening 29 and the electronic component 90.

次に、例えば真空プレス機を用いて、1kPa以下の減圧雰囲気中にて加熱加圧することで熱圧着により一括積層し(ステップS132)、図1に示すような部品内蔵基板を製造する。このとき、層間の各接着層9a〜9dや各樹脂基材21,31等の硬化と同時に、ビアホール6に充填された導電ペーストの硬化及び合金化が行われる。   Next, for example, using a vacuum press machine, heat lamination is performed by heating and pressurizing in a reduced pressure atmosphere of 1 kPa or less (step S132), and a component built-in substrate as shown in FIG. 1 is manufactured. At this time, the conductive paste filled in the via hole 6 is cured and alloyed simultaneously with the curing of the adhesive layers 9a to 9d between the layers, the resin base materials 21 and 31, and the like.

上記図5及び図9に示す工程において、電子部品90と第1プリント配線基材10とを圧着させた際に、保護層92にかかる圧力により保護層92を境界として接着層9a、9bがクリアランス部に流れ出て、クリアランス部50に接着層9a、9bが適切に入りこむ。よって、本実施の形態は、クリアランス部50のボイドの発生を抑制すると共に薄型化できる。   In the steps shown in FIGS. 5 and 9, when the electronic component 90 and the first printed wiring substrate 10 are pressure-bonded, the pressure applied to the protective layer 92 causes the adhesive layers 9a and 9b to be cleared with the protective layer 92 as a boundary. The adhesive layers 9a and 9b appropriately enter the clearance portion 50. Therefore, this embodiment can suppress the generation of voids in the clearance portion 50 and can be thinned.

また、保護層92は、上記圧着工程(ステップS132)における温度より高い融点を有しているため、ステップS132において溶け出すことはない。したがって、接着層9a、9bの物性は変化しない。   Moreover, since the protective layer 92 has a melting point higher than the temperature in the pressure bonding step (step S132), it does not melt in step S132. Therefore, the physical properties of the adhesive layers 9a and 9b do not change.

6…ビアホール、 8…導体層、 9a〜9d…接着層、 10〜40…第1〜第4プリント配線基材、 11〜41…第1〜第4樹脂基材、 12〜42…第1〜第4信号用配線、14〜44…第1〜第4信号用ビア、 18、48…ソルダーレジスト、23…めっき層、 29…開口部、 50…クリアランス部、 90…電子部品、 91B…電極、 91a…裏面、 91b…電極形成面、 92…保護層、 94…ウェハ。   DESCRIPTION OF SYMBOLS 6 ... Via hole, 8 ... Conductor layer, 9a-9d ... Adhesion layer, 10-40 ... 1st-4th printed wiring base material, 11-41 ... 1st-4th resin base material, 12-42 ... 1st-1st 4th signal wiring, 14 to 44 ... 1st to 4th signal via, 18, 48 ... Solder resist, 23 ... Plating layer, 29 ... Opening, 50 ... Clearance part, 90 ... Electronic component, 91B ... Electrode, 91a ... back surface, 91b ... electrode formation surface, 92 ... protective layer, 94 ... wafer.

Claims (3)

絶縁基材に配線パターンが形成されたプリント配線基材を複数積層すると共にプリント配線基材に形成された開口部に電子部品を内蔵してなる部品内蔵基板の製造方法であって、
前記電子部品の電極形成面と反対側の面に第1接着層を形成すると共に前記第1接着層を保護層で覆う工程と、
前記プリント配線基材の少なくとも一方の面に第2接着層を形成する工程と、
前記保護層と前記第2接着層とを対向させて、前記電子部品と前記プリント配線基材とを圧着させる工程と
を備えることを特徴とする部品内蔵基板の製造方法。
A method of manufacturing a component-embedded substrate in which a plurality of printed wiring substrates having a wiring pattern formed on an insulating substrate are laminated and an electronic component is built in an opening formed in the printed wiring substrate,
Forming a first adhesive layer on a surface opposite to the electrode forming surface of the electronic component and covering the first adhesive layer with a protective layer;
Forming a second adhesive layer on at least one surface of the printed wiring board;
And a step of crimping the electronic component and the printed wiring substrate so that the protective layer and the second adhesive layer are opposed to each other.
前記保護層は、前記電子部品と前記プリント配線基材とを圧着させる工程における圧着温度よりも高い融点を有する
ことを特徴とする請求項1記載の部品内蔵基板の製造方法。
The method for manufacturing a component built-in substrate according to claim 1, wherein the protective layer has a melting point higher than a pressure bonding temperature in a step of pressure bonding the electronic component and the printed wiring substrate.
請求項1又は2の製造方法により製造された部品内蔵基板。


A component-embedded substrate manufactured by the manufacturing method according to claim 1.


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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288298A (en) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd Method for manufacturing printed-wiring board with built-in electronic part
JP2011077195A (en) * 2009-09-29 2011-04-14 Dainippon Printing Co Ltd Component mounting substrate and method of manufacturing component mounting substrate
WO2011062146A1 (en) * 2009-11-20 2011-05-26 株式会社村田製作所 Method of manufacturing rigid/flexible multilayered wiring substrate, and integrated substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008288298A (en) * 2007-05-16 2008-11-27 Toppan Printing Co Ltd Method for manufacturing printed-wiring board with built-in electronic part
JP2011077195A (en) * 2009-09-29 2011-04-14 Dainippon Printing Co Ltd Component mounting substrate and method of manufacturing component mounting substrate
WO2011062146A1 (en) * 2009-11-20 2011-05-26 株式会社村田製作所 Method of manufacturing rigid/flexible multilayered wiring substrate, and integrated substrate

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