JP2013175596A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

Embodiments provide a semiconductor device including a trench gate structure in which a withstand voltage between a gate electrode and a field plate electrode is improved, and a manufacturing method thereof.
A method of manufacturing a semiconductor device according to an embodiment includes a first insulating film covering an inner surface of a trench formed in a semiconductor layer, and a second insulating film laminated on the first insulating film. And a step of forming an insulating film. Forming a first control electrode opposite to the semiconductor layer via the first insulating film and the second insulating film under the trench; and a third insulating film on the first control electrode And a step of removing the first insulating film and the second insulating film formed on the upper wall surface of the trench to form a fourth insulating film. A second control electrode facing the semiconductor layer via the fourth insulating film and facing the first control electrode via the third insulating film is formed on the trench.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  Power semiconductors for power control are required to reduce power loss. For this reason, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench gate structure is widely used. The trench gate structure can reduce the on-resistance by miniaturizing the chip structure. In particular, the trench gate structure including the gate electrode and the field plate electrode inside the same trench realizes further reduction of the on-resistance.

  However, in a miniaturized trench gate structure, it is not easy to stably secure insulation between the gate electrode formed in one trench and the field plate electrode. Therefore, there is a demand for a semiconductor device having a trench gate structure in which the withstand voltage between the gate electrode and the field plate electrode is improved, and a manufacturing method thereof.

JP 2011-124578 A

  Embodiments provide a semiconductor device including a trench gate structure in which a withstand voltage between a gate electrode and a field plate electrode is improved, and a method for manufacturing the semiconductor device.

  The method for manufacturing a semiconductor device according to the embodiment includes a step of forming a first insulating film that covers an inner surface of a trench formed in a semiconductor layer, and a second insulating film stacked on the first insulating film. . Forming a first control electrode facing the semiconductor layer below the trench via the first insulating film and the second insulating film; and a third control electrode on the first control electrode. Forming the insulating film; removing the first insulating film and the second insulating film formed on the wall surface of the trench between the upper end of the first control electrode and the opening of the trench; And 4 forming an insulating film. A second control electrode facing the semiconductor layer via the fourth insulating film and facing the first control electrode via the third insulating film is formed on the trench.

1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. It is a schematic cross section showing the manufacturing process of the semiconductor device concerning a 1st embodiment. FIG. 3 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 5. It is a schematic cross section showing a semiconductor device according to a second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same number is attached | subjected to the same part in drawing, the detailed description is abbreviate | omitted suitably, and a different part is demonstrated. In the following embodiments, the first conductivity type is described as n-type and the second conductivity type is described as p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

[First Embodiment]
FIG. 1 is a schematic cross-sectional view showing a semiconductor device 100 according to the first embodiment. The semiconductor device 100 is, for example, a power MOSFET having a trench gate structure, and is formed using a silicon wafer.

  The semiconductor device 100 includes an n-type drift layer 13 that is a first semiconductor layer and a p-type base layer 21 that is a second semiconductor layer. The p-type base layer 21 is provided on the n-type drift layer 13. A field plate electrode 20 serving as a first control electrode and a second control electrode are provided in a trench 15 provided at a depth that penetrates the p-type base layer 21 and reaches the n-type drift layer 13. A gate electrode 30. The trench 15 is provided in a stripe shape extending in the depth direction of FIG.

  The field plate electrode 20 is opposed to the n-type drift layer 13 via the first insulating film 3 and the second insulating film 5 below the trench 15 (on the bottom surface side). The gate electrode 30 is provided on the upper portion (opening side) of the trench 15 and faces the p-type base layer 21 through the fourth insulating film (gate insulating film) 9. Further, the gate electrode 30 faces the field plate electrode 20 with the third insulating film 7 interposed therebetween.

  On the surface of the p-type base layer 21, an n-type source region 23 and a p-type contact region 27 adjacent thereto are selectively provided. A source electrode 40 electrically connected to the n-type source region 23 and the p-type contact region 27 is provided. The source electrode 40 covers the interlayer insulating film 33 provided on the gate electrode 30 and the upper surface of the p-type base layer 21.

  Further, a drain electrode 50 is provided on the lower surface side of the n-type drift layer 13. The drain electrode 50 is electrically connected to the n-type drift layer 13 via the n-type drain layer 17 in contact with the lower surface 13 b of the n-type drift layer 13.

  In the present embodiment, at least one of the first insulating film 3 and the second insulating film 5 that insulates between the field plate electrode 20 and the n-type drift layer 13 is the n-type drift layer 13 and the p-type base. The ability to prevent the entry of atoms or molecules that oxidize layer 21 is higher than the other. That is, the laminated first insulating film 3 and second insulating film 5 suppress the permeation of atomic or molecular oxidizing agents that reach the n-type drift layer 13 and the p-type base layer 21 in the heat treatment process of the wafer process. The oxidation of the n-type drift layer 13 and the p-type base layer 21 is suppressed.

  Next, a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. 2A to 6B are schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 according to the first embodiment.

As shown in FIG. 2A, a trench 15 is formed in the n-type semiconductor layer 10. The n-type semiconductor layer 10 is, for example, an n-type silicon layer epitaxially grown on a silicon substrate, and has an impurity concentration of 2 to 10 ^μm and 1 × 10 ^{16 to} 1 × 10 ¹⁷ cm ⁻³ .

The trench 15 is selectively provided using, for example, an RIE (Reactive Ion Etching) method. For example, the width W _{T of the} trench 15 is 0.15 to 2.0 μm, and the depth _DT is 1 to 10 μm.

Next, the first insulating film 3 covering the inner surface of the trench and the second insulating film 5 stacked thereon are formed in order. The first insulating film 3 is, for example, a silicon oxide film (SiO ₂ film) obtained by thermally oxidizing an n-type silicon layer, and is formed to a thickness of 50 to 1000 nm. The second insulating film 5 is, for example, a silicon nitride film (SiN _x film), and is formed using a CVD (Chemical Vapor Deposition) method. The thickness of the silicon nitride film is, for example, 10 nm to 100 nm.

  Subsequently, as shown in FIG. 2B, a polysilicon layer (polycrystalline silicon layer) 20a filling the inside of the trench 15 is formed. The polysilicon layer 20a is formed by using, for example, a CVD method. Further, n-type impurities are diffused into the polysilicon layer 20a to make it conductive.

  Next, as shown in FIG. 3A, the polysilicon layer 20 a is etched back to form a field plate electrode 20 below the trench 15. For example, CDE (Chemical Dry Etching) is used for etching the polysilicon layer 20a.

  The field plate electrode 20 faces the n-type semiconductor layer 10 with the first insulating film 3 and the second insulating film 5 interposed therebetween. That is, the first insulating film 3 and the second insulating film 5 are so-called field plate insulating films, and insulate the field plate electrode 20 from the n-type semiconductor layer 10. In addition, the field plate electrodes 20 provided respectively below the plurality of trenches 15 are electrically connected at portions not shown. Therefore, the surface of the polysilicon layer 20a serving as the connection portion is covered with a resist mask, and the exposed polysilicon layer 20a is selectively etched back.

  After the polysilicon layer 20a is etched, the resist mask is removed by, for example, oxygen ashing and wet processing. Subsequently, as shown in FIG. 3B, the third insulating film 7 is formed on the upper end of the field plate electrode 20.

  For example, a silicon wafer on which the field plate electrode 20 is formed is heat-treated in an oxygen atmosphere. Thereby, the upper end of the field plate electrode 20 is thermally oxidized, and the third insulating film 7 (silicon oxide film) is formed. At this time, the laminated film of the first insulating film 3 and the second insulating film 5 is exposed on the wall surface where the polysilicon layer 20a above the trench 15 is etched back. Then, at least one of the first insulating film 3 and the second insulating film 5 has a higher ability to prevent intrusion of atoms or molecules that oxidize the n-type semiconductor layer 10 than the other. For this reason, oxidation of the n-type semiconductor layer 10 is suppressed in the upper part of the trench 15, and oxidation of the upper end of the field plate electrode 20 proceeds.

  For example, when one of the first insulating film 3 and the second insulating film 5 is a silicon oxide film, the other is a silicon nitride film, and the n-type semiconductor layer 10 is an n-type silicon layer, the silicon nitride film is the trench 15. Oxidation of the inner surface of the film is suppressed and formation of a silicon oxide film is suppressed. That is, the growth of the insulating film in the upper part of the trench 15 is suppressed. Thereby, the third insulating film 7 thicker than both the first insulating film 3 and the second insulating film 5 can be formed. Preferably, the third insulating film 7 is formed thicker than the total thickness of the first insulating film 3 and the second insulating film 5.

  Next, as shown in FIG. 4A, the first insulating film 3 and the second insulating film 5 between the upper end of the field plate electrode 20 and the opening 15a of the trench 15 are removed by, for example, wet etching. To do. Subsequently, as shown in FIG. 4B, the fourth insulating film 9 is formed on the upper wall surface 15 b of the trench 15 and the first insulating film 3, the second insulating film 5, and the third insulating film 7. Form.

  The fourth insulating film 9 is a gate insulating film, is formed thinner than the field plate insulating film 20, and maintains the threshold voltage of the gate at a predetermined value. Further, by forming the field plate insulating film 20 thick, the withstand voltage between the field electrode 20 and the n-type drift layer 13 is increased. Further, the on-resistance is reduced by increasing the concentration of the n-type drift 13.

  For example, the fourth insulating film 9 is formed by thermally oxidizing the n-type semiconductor layer 10 exposed on the wall surface 15 b of the trench 15. That is, when the n-type semiconductor layer 10 is an n-type silicon layer, a silicon oxide film is formed on the wall surface 15 b of the trench 15.

  Next, as shown in FIG. 5 (a), the n-type semiconductor layer 10 is opposed to the upper portion of the trench 15 via the fourth insulating film 9, and the field plate electrode 20 is opposed via the third insulating film 7. A gate electrode 30 (second control electrode) to be formed is formed.

  For example, a conductive polysilicon layer that fills the upper portion of the trench 15 is formed on a silicon wafer, and the gate electrode 30 is formed by etching back the polysilicon layer formed on the upper surface 10a of the n-type semiconductor layer 10. Form.

  Subsequently, as shown in FIG. 5B, the p-type base layer 21 is formed in the depth direction from the upper surface 10 a of the n-type semiconductor layer 10. Further, an n-type source region 23 is selectively formed on the surface of the p-type base layer 21.

The p-type base layer 21 is formed by ion-implanting p-type impurities into the upper surface 10a of the n-type semiconductor layer 10, for example. In the process of forming the p-type base layer 21, a p-type impurity is activated by heat treatment after ion implantation, the depth D _B of the p-type base layer 21, to drive a depth not exceeding the lower end of the gate electrode 30.

  Thereby, a part of the n-type semiconductor layer 10 becomes the n-type drift layer 13, and a structure having the p-type base layer 21 on the n-type drift layer 13 is formed.

  The n-type source region 23 is formed by selectively ion-implanting n-type impurities into the surface of the p-type base layer 21. The n-type source region 23 faces the gate electrode 30 with the fourth insulating film 9 interposed therebetween.

  Next, as shown in FIG. 6A, an interlayer insulating film 33 is formed on the gate electrode 30, and a p-type contact region 27 is formed on the surface of the p-type base layer 21.

  The interlayer insulating film 33 is a silicon oxide film, for example, and is formed by a CVD method using TEOS (TetraEthOxySilane). The p-type contact region 27 is formed by, for example, an ion implantation method and contains a p-type impurity having a concentration higher than that of the p-type base layer 21.

  Subsequently, as shown in FIG. 6B, a source electrode 40 is formed. The source electrode 40 is in contact with the n-type source region 23 and the p-type contact region 27 and covers the interlayer insulating film 33.

  On the other hand, the drain electrode 50 is formed on the lower surface 13b side of the n-type drift layer 13 via the n-type drain layer 17 (see FIG. 1). Thereby, the wafer process of the semiconductor device 100 is completed.

  As shown in FIGS. 1 and 6B, the semiconductor device 100 includes a gate electrode 30 provided inside the trench 15 and a field plate electrode 20. The withstand voltage between the gate electrode 30 and the field plate electrode 20 is held by the third insulating film 7. Accordingly, it is desirable that the third insulating film 7 is formed thick and the withstand voltage between the gate electrode 30 and the field plate electrode 20 is increased.

  In the above manufacturing process, the third insulating film 7 formed on the upper end of the field plate electrode 20 is also etched in the process of removing the first insulating film 3 and the second insulating film 5 provided on the upper portion of the trench 15. However, if the third insulating film 7 on the field plate electrode 20 is thicker than both the first insulating film 3 and the second insulating film 5 on the trench sidewall, the first insulating film 3 or the second insulating film 5 is removed. The third insulating film 7 can be left on the feed plate electrode 20 later.

  In the present embodiment, a film having a high ability to prevent the entry of atoms or molecules that oxidize the n-type semiconductor layer 10 is used for at least one of the first insulating film 3 and the second insulating film 5. Thereby, formation of an oxide film on the side wall of the trench 15 is suppressed, and the third insulating film 7 can be formed thick.

That is, by suppressing the permeation of atoms or molecules that oxidize the n-type semiconductor layer 10, the thickness of the entire insulating film including the first insulating film 3 and the second insulating film 5 in the upper part of the trench 15 is suppressed, and the first 3 A trench gate with which the final film thickness d _I (see FIG. 4A) of the insulating film 7 can be increased and the withstand voltage between the gate electrode 30 and the field plate electrode 20 is improved. A structure can be realized.

Further, the field plate electrode 20 is electrically connected to the source electrode 40. Therefore, by increasing the thickness of the third insulating film 7 between the gate electrode 30 and the field plate electrode 20, the parasitic capacitance _Cgs between the gate and the source can be reduced and the switching speed can be increased.

As atoms and molecules that oxidize the n-type semiconductor layer 10, in addition to the oxygen O ₂ in the above example, for example, nitrous oxide (NO _x ), ozone (O ₃ ), oxygen radical (O ⁺ ), hydroxyl group (OH ⁻ ) and the like can be exemplified. In addition to the above silicon nitride film (SiN _x ), for example, a silicon carbide film (SiC), a silicon oxynitride film (SiON), a SiCO film, etc. are exemplified as a film for suppressing the intrusion of these atoms and molecules. can do. These films can be formed using, for example, a CVD method. One of two films selected from these films may be the first insulating film 3 and the other may be the second insulating film 5.

[Second Embodiment]
FIG. 7 is a schematic cross-sectional view showing a semiconductor device 200 according to the second embodiment. The semiconductor device 200 is, for example, an IGBT (Isolated Gate Bipolar Transistor) having a trench gate structure.

  The semiconductor device 200 includes an n-type base layer 63 that is a first semiconductor layer, and a p-type base layer 71 that is a second semiconductor layer provided on the n-type base layer 63. A field plate electrode 20 as a first control electrode and a second control electrode are provided in a trench 15 provided at a depth that penetrates the p-type base layer 71 and reaches the n-type base layer 63. A gate electrode 30. For example, the trench 15 is provided in a stripe shape extending in the depth direction of FIG.

  The field plate electrode 20 faces the n-type base layer 63 via the first insulating film 3 and the second insulating film 5 at the lower part (bottom side) of the trench 15. The gate electrode 30 is provided above the trench 15 and faces the p-type base layer 71 with the fourth insulating film 9 interposed therebetween. Further, the gate electrode 30 faces the field plate electrode 20 with the third insulating film 7 interposed therebetween.

  An n-type emitter region 73 and a p-type contact region 77 adjacent thereto are selectively provided on the surface of the p-type base layer 71. An emitter electrode 45 electrically connected to the n-type emitter region 73 and the p-type contact region 77 is provided. The emitter electrode 45 covers the interlayer insulating film 33 provided on the gate electrode 30 and the upper surface of the p-type base layer 71.

  Further, a collector electrode 55 is provided on the lower surface side of the n-type base layer 63. The collector electrode 55 is electrically connected to the n-type base layer 63 via the p-type collector layer 65 in contact with the lower surface 63 b of the n-type base layer 63.

  At least one of the first insulating film 3 and the second insulating film 5 that insulates between the field plate electrode 20 and the n-type base layer 63 oxidizes the n-type base layer 63 and the p-type base layer 71. The ability to prevent the intrusion of atoms or molecules is higher than the other. That is, the laminated first insulating film 3 and second insulating film 5 suppress the permeation of atomic or molecular oxidants reaching the n-type base layer 63 and the p-type base layer 71 in the heat treatment process of the wafer process. The oxidation of the n-type base layer 63 and the p-type base layer 71 is suppressed. Thereby, the third insulating film 7 can be formed thick, and the withstand voltage between the gate electrode 30 and the field plate electrode 20 can be improved. Further, when the field electrode 20 is connected to the emitter electrode 40, the parasitic capacitance between the gate and the emitter can be reduced.

  In the above embodiment, the insulating film provided between the field plate electrode 20 and the n-type drift layer 13 or the n-type base layer 63 is limited to the laminated film of the first insulating film 3 and the second insulating film 5. Alternatively, a laminated film including three or more layers may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 3 ... 1st insulating film, 5 ... 2nd insulating film, 7 ... 3rd insulating film, 9 ... 4th insulating film, 10 ... n-type semiconductor layer, 10a ... Upper surface , 13 ... n-type drift layer, 13b ... lower surface, 15 ... trench, 15a ... opening, 15b ... wall surface, 17 ... n-type drain layer, 20 ... field plate electrode 20a ... polysilicon layer, 21 ... p-type base layer, 23 ... n-type source region, 27, 77 ... p-type contact region, 30 ... gate electrode, 33 ... interlayer Insulating film, 40 ... Source electrode, 45 ... Emitter electrode, 50 ... Drain electrode, 55 ... Collector electrode, 63 ... N-type base layer, 63b ... Bottom surface, 65 ... p-type collector layer, 71... p-type base layer, 73 ·· n-type emitter region, 100, 200 ... semiconductor device

Claims (9)

Forming a first insulating film covering an inner surface of the trench formed in the semiconductor layer, and a second insulating film stacked on the first insulating film;
Forming a first control electrode facing the semiconductor layer via the first insulating film and the second insulating film under the trench;
Forming a third insulating film on the first control electrode;
Removing the first insulating film and the second insulating film formed on the wall surface of the trench between the upper end of the first control electrode and the opening of the trench to form a fourth insulating film When,
Forming a second control electrode facing the semiconductor layer via the fourth insulating film and facing the first control electrode via the third insulating film on the trench;
With
A method of manufacturing a semiconductor device, wherein at least one of the first insulating film and the second insulating film has a higher ability to prevent intrusion of atoms or molecules that oxidize the semiconductor layer than the other. Forming a first insulating film covering an inner surface of the trench formed in the semiconductor layer, and a second insulating film stacked on the first insulating film;
Forming a first control electrode facing the semiconductor layer via the first insulating film and the second insulating film under the trench;
Forming a third insulating film on the first control electrode;
Removing the first insulating film and the second insulating film formed on the wall surface of the trench between the upper end of the first control electrode and the opening of the trench, and forming a fourth insulating film; ,
Forming a second control electrode facing the semiconductor layer via the fourth insulating film and facing the first control electrode via the third insulating film on the trench;
A method for manufacturing a semiconductor device comprising:   3. The method of manufacturing a semiconductor device according to claim 2, wherein at least one of the first insulating film and the second insulating film has a higher ability to prevent intrusion of atoms or molecules that oxidize the semiconductor layer than the other.   4. The step of forming the third insulating film suppresses oxidation of the wall surface of the trench by the one of the first insulating film and the second insulating film, and promotes oxidation of the first control electrode. The manufacturing method of the semiconductor device of description.   5. The method of manufacturing a semiconductor device according to claim 2, wherein the third insulating film is formed thicker than both the first insulating film and the second insulating film.   The method for manufacturing a semiconductor device according to claim 2, wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. A first semiconductor layer of a first conductivity type;
A second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
A first control electrode facing the first semiconductor layer via a first insulating film and a second insulating film at a lower portion of a trench that penetrates the second semiconductor and reaches the first semiconductor layer;
A second control electrode provided on the trench, facing the first control electrode via a third insulating film and facing the second semiconductor layer via a fourth insulating film;
A semiconductor device comprising:   The at least one of the first insulating film and the second insulating film has a higher ability to prevent intrusion of atoms or molecules that oxidize the first semiconductor layer and the second semiconductor layer than the other. The semiconductor device described.   The semiconductor device according to claim 7, wherein the third insulating film is a silicon oxide film.

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