JP2013172516A - Dc-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current-mode-controlled DC-DC converter that generates a nonlinear slope voltage in a simple circuit configuration.SOLUTION: In a slope compensation circuit 14 of a current-mode-controlled DC-DC converter 1, a first transistor TR14 has a first main electrode connected to an input node ND1 or a ground node ND2. A second transistor TR13, which is diode-connected, has a first main electrode connected to the first main electrode of the first transistor TR14 via a capacitive element C2, and a control electrode connected to a control electrode of the first transistor TR14. A current source circuit 15 applies currents proportional to a size ratio of the first and second transistors TR14, TR13 to the first and second transistors TR14, TR13, respectively. A current flowing in a path branching from a second main electrode of the first transistor TR14 is converted to a voltage to produce a slope voltage.

Description

  The present invention relates to a DC-DC converter, and more particularly to a current mode control DC-DC converter.

  The control system of the DC-DC converter is roughly divided into voltage mode control and current mode control. The current mode control is characterized in that it responds to the output voltage fluctuation at a high speed and has excellent control stability as compared with the voltage mode control. However, in current mode control, it is known that the inductor current becomes unstable when the current-carrying rate of the inductor exceeds 50%. Usually, a technique called slope compensation is used to stabilize the inductor current.

  For example, in a DC-DC converter described in Japanese Unexamined Patent Application Publication No. 2009-153289 (Patent Document 1), a compensation voltage obtained by adding an inductor current detection signal and a slope voltage, a feedback voltage of an output voltage, and The error voltage corresponding to the difference from the reference voltage is compared. When the compensation voltage exceeds the error voltage, the switching circuit is turned off. Furthermore, in the example of this document, in the case of the boost converter, the slope of the slope voltage is set to be proportional to the difference between the output voltage and the input voltage, and in the case of the step-down converter, the slope of the slope voltage is proportional to the output voltage. Is set as follows.

  Unlike the above literature, a slope compensation circuit has been proposed that compensates for stable operation even when the output voltage changes by generating a non-linear slope voltage. For example, Japanese Patent Laying-Open No. 2005-229744 (Patent Document 2) changes the current value of the transistor secondarily by linearly changing the gate voltage of the transistor, and sets the slope voltage corresponding to the current value. The technology to create is disclosed. Japanese Patent Laying-Open No. 2008-72833 (Patent Document 3) discloses a technique for generating a slope voltage having a slope of a quadratic curve by integrating a current proportional to a current flowing through a switching element.

JP 2009-153289 A JP 2005-229744 A JP 2008-72833 A

  In the case of generating a non-linear slope voltage as described in Japanese Patent Application Laid-Open No. 2005-229744 (Patent Document 2) and Japanese Patent Application Laid-Open No. 2008-72833 (Patent Document 3), a non-linear gradient is generated with a circuit configuration as simple as possible. It is desirable to generate a desired slope voltage having

  An object of the present invention is to provide a current mode control type DC-DC converter capable of generating a non-linear slope voltage with a simple circuit configuration.

  In one aspect, the present invention is a DC-DC converter, wherein an input node to which an input voltage is applied, a ground node to which a ground voltage is applied, an output node for outputting an output voltage, a first switching element, An inductor, a slope compensation circuit that generates a slope current, and a control circuit are provided. One end of the first switching element is connected to the input node or the ground node. The inductor is connected to the other end of the first switching element. The control circuit compares the error voltage based on the difference between the voltage proportional to the current flowing through the inductor and the voltage proportional to the slope current and the error voltage based on the difference between the voltage proportional to the output voltage and a predetermined reference voltage. Current mode control is performed to switch the switching elements to the OFF state. The slope compensation circuit includes a capacitive element, a second switching element, a first transistor, a second transistor, and a current source circuit. The second switching element is connected in parallel with the capacitor element, and is turned off when the first switching element is on. In the first transistor, the first main electrode is connected to the input node or the ground node. The second transistor is diode-connected, the first main electrode is connected to the first main electrode of the first transistor via the capacitor, and the control electrode is connected to the control electrode of the first transistor. The current source circuit is connected to each second main electrode of the first and second transistors, and causes a current proportional to the ratio of the sizes of the first and second transistors to flow through the first and second transistors, respectively. The slope current flows into or out of the first transistor through a path branched from the connection path between the second main electrode of the first transistor and the current source circuit.

  Preferably, the current source circuit includes a third transistor, a fourth transistor, a fifth transistor, and a constant current source. The third transistor is connected in series with the first transistor between the input node and the ground node. The fourth transistor is connected in series with the second transistor between the input node and the ground node. The fifth transistor is diode-connected and forms a current mirror with the third and fourth transistors. The constant current source supplies a predetermined current to the fifth transistor. The size ratio of the first and second transistors is equal to the size ratio of the third and fourth transistors.

  Preferably, the DC-DC converter further includes a first resistance element inserted between the first switching element and the input node or the ground node. In this case, the control circuit includes a second resistance element and a comparator. One end of the second resistance element is connected to the connection node between the first resistance element and the first switching element, and the other end is connected to the slope compensation circuit, whereby a slope current flows. The comparator receives the voltage at the other end of the second resistance element as the total voltage and compares it with the error voltage. The first switching element is switched to an off state according to the output of the comparator.

  Preferably, the control circuit includes a third switching element, a resistance element, and a comparator. The third switching element is turned on when the first switching element is turned on. One end of the resistance element is connected to the connection node between the inductor and the first switching element via the third switching element, and the other end is connected to the slope compensation circuit, so that the first switching element is turned on. A slope current flows when The comparator receives the voltage at the other end of the resistance element as the total voltage and compares it with the error voltage. In this case, the first switching element is switched to the off state according to the output of the comparator.

  Preferably, the control circuit further performs overcurrent control for turning off the first switching element when a voltage proportional to a current flowing through the inductor exceeds a predetermined upper limit voltage.

  According to the present invention, it is possible to generate a non-linear slope voltage (voltage proportional to the slope current) with a simple circuit configuration.

1 is a circuit diagram showing a configuration of a DC-DC converter 1 according to a first embodiment of the present invention. It is a figure which shows the signal waveform of each part of FIG. It is a figure which shows the structure of the DC-DC converter 901 as a comparative example of the DC-DC converter 1 of FIG. It is a figure which shows the signal waveform of each part of FIG. It is a circuit diagram which shows the structure of the DC-DC converter 2 as a modification of the DC-DC converter 1 of FIG. It is a circuit diagram which shows the structure of the DC-DC converter 3 by Embodiment 2 of this invention. FIG. 7 is a circuit diagram showing a configuration of a modified example of the slope compensation circuit 24 of FIG. 6.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of DC-DC Converter 1]
FIG. 1 is a circuit diagram showing a configuration of a DC-DC converter 1 according to Embodiment 1 of the present invention.

  Referring to FIG. 1, DC-DC converter 1 includes an input node ND1, a ground node ND2, an output node ND3, a converter 10 that performs DC voltage conversion, a control circuit 11, and a slope compensation circuit 14. Including. Input voltage Vin is applied to input node ND1, and ground voltage GND is applied to ground node ND2. A load 9 is connected between output node ND3 for outputting output voltage Vout and ground node ND2.

(Configuration of the conversion unit 10)
The conversion unit 10 is a circuit called a so-called step-down chopper, and generates an output voltage Vout by stepping down the input DC voltage Vin. The conversion unit 10 detects a positive-channel metal oxide semiconductor (PMOS) transistor TR1, a negative-channel MOS (NMOS) transistor TR2, an inductor L, a smoothing capacitor C1, and an inductor current IL as switching elements. Resistance element R4.

  Transistors TR1 and TR2 are connected in series between input node ND1 and ground node ND2 in this order. Inductor L is connected between connection node ND4 of transistors TR1 and TR2 and output node ND3. Capacitor C1 is connected between output node ND3 and ground node ND2.

  The transistor TR2 is used as a synchronous rectifier, and is turned on / off by the control circuit 11 so that it is turned off when the transistor TR1 is turned on and turned on when the transistor TR1 is turned off. A diode may be provided instead of the transistor TR2. In this case, the cathode of the diode is connected to the connection node ND4, and the anode of the diode is connected to the ground node ND2.

  Resistance element R4 is inserted between the source of transistor TR1 and input node ND1. The resistance element R4 is provided for detecting the inductor current IL flowing through the inductor L when the transistor TR1 is in the on state.

(Configuration of control circuit 11)
The control circuit 11 generates a total voltage Vsum of a voltage proportional to the inductor current IL flowing through the inductor L and a voltage proportional to the slope current Is generated by the slope compensation circuit 14. Further, the control circuit 11 generates an error voltage Ve based on a difference between the voltage proportional to the output voltage Vout and a predetermined reference voltage Vref, and compares the error voltage Ve with the total voltage Vsum to switch the transistor TR1 to an off state. Perform mode control. Specifically, the control circuit 11 includes an error amplifier EAMP, a voltage shift circuit 12, a resistance element R1, a comparator CMP, an RS flip-flop FF, and a drive circuit DRV.

  The error amplifier EAMP receives the reference voltage Vref at the + terminal, receives the output voltage Vout or the voltage obtained by dividing the output voltage Vout by resistance at the − terminal, and outputs a voltage obtained by amplifying the difference to the voltage shift circuit 12. A feedback compensation circuit (phase compensation circuit) may be provided after the error amplifier EAMP so that the output of the feedback compensation circuit is output to the voltage shift circuit 12.

  The voltage shift circuit 12 is a circuit for converting the output of the error amplifier EAMP based on the ground voltage GND into a voltage based on the input voltage Vin.

  Specifically, the voltage shift circuit 12 includes resistance elements R2 and R3, an NPN bipolar transistor TR3, a PNP bipolar transistor TR4, and a constant current source 13. Resistance element R2, bipolar transistor TR3, and resistance element R3 are connected in series between input node ND1 and ground node ND2 in this order. Constant current source 13 and bipolar transistor TR4 are connected in series between input node ND1 and ground node ND2 in this order. The base of the bipolar transistor TR3 is connected to a connection node ND7 (the emitter of the bipolar transistor TR4) between the constant current source 13 and the bipolar transistor TR4. The output voltage of the error amplifier EAMP is input to the base of the bipolar transistor TR4.

  According to the voltage shift circuit 12 having the above configuration, when the output voltage of the error amplifier EAMP (that is, the base voltage of the bipolar transistor TR4) is increased, the collector current of the bipolar transistor TR4 is decreased, so that the base current of the bipolar transistor TR3 is increased. To do. As a result, the collector current (that is, the current flowing through the resistance element R2) of the bipolar transistor TR3 increases, so that the voltage applied to the resistance element R2 increases (that is, the potential of the connection node ND6 decreases). The voltage of the resistance element R2 (that is, the potential difference between the input node ND1 and the connection node ND6) is input to the comparator CMP as the error voltage Ve.

  The resistance element R1 is for converting the slope current Is generated by the slope compensation circuit 14 into a voltage. One end of the resistance element R1 is connected to a connection node ND9 between the resistance element R4 of the conversion unit 10 and the transistor TR1, and the other end (node ND5) of the resistance element R1 is connected to the slope compensation circuit 14. Therefore, in the case of FIG. 1, the slope current Is flows from the input node ND1 through the resistance element R4, the node ND9, and the resistance element R1 of the conversion unit 10 into the slope compensation circuit 14 in order. The potential of the other end (node ND5) of the resistance element R1 is obtained by subtracting, from the input voltage Vin, the total voltage Vsum of the voltage drop generated in the resistance element R4 due to the inductor current IL and the voltage drop generated in the resistance element R1 due to the slope current Is. (Vin−Vsum).

  Since the magnitude of the slope current Is is on the order of microamperes, it is much smaller than the inductor current IL. Therefore, a voltage drop generated in the resistance element R4 due to the slope current Is can be ignored. Since the resistance value of the resistance element R1 is sufficiently larger than the impedances of the inductor L and the load 9, the inductor current IL hardly flows through the resistance element R1.

  The comparator CMP compares the potential (Vin−Ve) of the node ND6 of the voltage shift circuit 12 with the potential (Vin−Vsum) of the end point (node ND5) of the resistance element R1, and compares the potential of the node ND5 with the potential of the node ND6. A high level (H level) signal is output when the potential (Vin−Vsum) of the signal becomes low. That is, the comparator CMP outputs an H level signal when the total voltage Vsum exceeds the error voltage Ve.

  The comparator CMP further compares the reference potential (Vin−Vocp) for overcurrent protection (OCP) with the potential (Vin−Vsum) of the end point (node ND5) of the resistance element R1. When the potential of the node ND5 becomes lower than the reference potential (Vin−Vocp), an H level signal is output. That is, the comparator CMP outputs an H level signal when the total voltage Vsum exceeds the overcurrent protection voltage Vocp.

  The RS flip-flop FF receives the clock signal CLK at the set terminal S and the output of the comparator CMP at the reset terminal R. The flip-flop FF is set when the clock signal CLK is switched to H level (at the rising edge of the clock signal CLK), and is reset when the output of the comparator CMP is switched to H level.

  Drive circuit DRV outputs a signal obtained by amplifying the inverted output / Q of flip-flop FF to the gates of transistors TR1 and TR2. Therefore, when the flip-flop FF is in the set state, the transistor TR1 is in the on state and the transistor TR2 is in the off state. When the flip-flop FF is in a reset state, the transistor TR1 is in an off state and the transistor TR2 is in an on state.

  When the flip-flop FF is switched from the set state to the reset state in order to prevent a through current through the transistors TR1 and TR2, the drive circuit DRV first turns off the transistor TR1, and then turns on the transistor TR2. It is desirable to control to turn on. When the flip-flop FF is switched from the reset state to the set state, it is desirable that the drive circuit DRV performs control so that the transistor TR2 is turned off first and then the transistor TR1 is turned on.

(Configuration of slope compensation circuit 14)
The slope compensation circuit 14 generates a slope current Is that gradually increases from the time when the transistor TR1 is switched on and is reset to 0 when the transistor TR1 is switched to the off state. In the current mode control, it is known that the inductor current becomes unstable when the conduction ratio of the inductor exceeds 50%, and the slope current Is is used for stabilization.

  Specifically, the slope compensation circuit 14 includes PMOS transistors TR10 to TR12, NMOS transistors TR13 to TR15, a capacitor C2, and a constant current source 16. The PMOS transistors TR10 to TR12 and the constant current source 16 constitute a current source circuit 15 that supplies currents I1 and I2 to the drains of the NMOS transistors TR13 and TR14, respectively. Hereinafter, the connection between each component which comprises the slope compensation circuit 14 is demonstrated.

  The transistor TR13 is a so-called diode-connected transistor whose gate and drain are connected to each other. The source of the transistor TR13 is connected to the ground node ND2 through the capacitor C2.

  The gate of transistor TR14 is connected to the gate of transistor TR13, and the source of transistor TR14 is connected to ground node ND2. Therefore, when the capacitor C2 is not provided, the transistors TR13 and TR14 constitute a normal current mirror.

  Transistor TR15 is connected in parallel with capacitor C2. The inverted output / Q of the flip-flop FF is input to the gate of the transistor TR15. Therefore, when the flip-flop FF is in the reset state (that is, when the transistor TR1 is in the off state), the transistor TR15 becomes conductive, and thereby the electric charge accumulated in the capacitor C2 is released.

  Transistor TR11 is connected in series with transistor TR13 between input node ND1 and ground node ND2. That is, the source of the transistor TR11 is connected to the input node ND1, and the drain of the transistor TR11 is connected to the drain of the transistor TR13.

  Transistor TR12 is connected in series with transistor TR14 between input node ND1 and ground node ND2. That is, the source of the transistor TR12 is connected to the input node ND1, and the drain of the transistor TR12 is connected to the drain of the transistor TR14.

  A connection node ND8 of the transistors TR12 and TR14 is connected to the end point (node ND5) of the resistor element R1. In other words, a current path is provided that branches from the node ND8 on the current path connecting the transistors TR12 and TR14 and reaches the end point (node ND5) of the resistance element R1. The slope current Is flows into the transistor TR14 through this current path.

  The transistor TR10 is a so-called diode-connected transistor whose gate and drain are connected to each other. The source of the transistor TR10 is connected to the input node ND1, and the gate of the transistor TR10 is connected to the gates of the transistors TR11 and TR12. That is, the transistors TR10, TR11, TR12 constitute a current mirror.

Constant current source 16 is connected between the drain of transistor TR10 and ground node ND2, and allows constant current I0 to flow through transistor TR10. Therefore, currents corresponding to the sizes of the transistors TR10, TR11, TR12 (the ratio W / L of the gate width W to the gate length L) flow through the transistors TR11, TR12 constituting the current mirror with the transistor TR10. If the currents flowing through the transistors TR11 and TR12 are I1 and I2, respectively, and the sizes of the transistors TR10, TR11 and TR12 are W10 / L10, W11 / L11 and W12 / L12, respectively,
I0: I1: I2 = W10 / L10: W11 / L11: W12 / L12 (1)
The relationship is established. When the sizes of the transistors TR10 to TR12 are equal to each other,
I0 = I1 = I2 (2)
It becomes.

  A current I1 from the transistor TR11 flows through the transistor TR13 connected in series with the transistor TR11. A current obtained by adding the current I2 from the transistor TR12 and the slope current Is flows through the transistor TR14 connected in series with the transistor TR12.

Here, the slope compensation circuit 14 of this embodiment is characterized in that the ratio of the sizes of the transistors TR13 and TR14 is made equal to the ratio of the sizes of the transistors TR11 and TR12. That is, assuming that the sizes of the transistors TR13 and TR14 are W13 / L13 and W14 / L14, respectively.
W11 / L11: W12 / L12 = W13 / L13: W14 / L14 (3)
The relationship is established. In other words, the current source circuit 15 supplies currents I1 and I2 proportional to the ratio of the sizes of the transistors TR13 and TR14 to the transistors TR13 and TR14, respectively. When the sizes of the transistors TR13 and TR14 are equal to each other, the sizes of the transistors TR11 and TR12 are also equal to each other. In this case, the relationship of I1 = I2 is established.

(Operation of the slope compensation circuit 14)
Next, the operation of the slope compensation circuit 14 will be described.

  In general, the current flowing through the MOS transistor is approximately equal to the square of the gate-source voltage of the MOS transistor. In the case of the slope compensation circuit 14 of FIG. 1, the gate-source voltage of the transistor TR14 is equal to the sum of the gate-source voltage of the transistor TR13 and the voltage of the capacitor C2. Therefore, the current flowing through the transistor TR14 changes according to the charging voltage of the capacitor C2.

  First, the case where the flip-flop FF is in the reset state (the PMOS transistor TR1 provided in the conversion unit 10 is in the off state) will be described. In this case, since the inverted output / Q of the flip-flop FF becomes H level, the transistor TR15 is turned on. As a result, the electric charge accumulated in the capacitor C2 is released and its voltage becomes almost zero. At this time, since the transistors TR13 and TR14 are the same as that constituting a current mirror circuit, the current flowing through the transistor TR14 is equal to the current I2 flowing through the transistor TR12 from the relationship of the above equation (3), and the slope The current Is becomes zero.

  Next, the case where the flip-flop FF is in the set state (the PMOS transistor TR1 provided in the conversion unit 10 is in the on state) will be described. When the inverted output / Q of the flip-flop FF is switched from the H level to the L level, the transistor TR15 provided in the slope compensation circuit 14 is switched to the OFF state, so that the capacitor C2 starts charging with the constant current I1. Thereby, the voltage of the capacitor C2 increases in proportion to the time after the flip-flop FF is switched to the set state. Since the current flowing through the transistor TR14 increases nonlinearly from the current I2 (approximately proportional to the square of time), the slope current Is also varies non-linearly from 0 (approximately proportional to the square of time). To increase. Thereafter, when the flip-flop FF returns to the reset state, the slope current Is returns to zero.

[Operation of DC-DC Converter 1]
FIG. 2 is a diagram showing signal waveforms at various parts in FIG. The graph of FIG. 2 shows, in order from the top, the waveform of the clock signal CLK input to the flip-flop FF of FIG. 1, the inverted output / Q of the flip-flop FF, the voltage V (C2) of the capacitor C2 of the slope compensation circuit 14, and the slope. The current Is, the inductor current IL, the negative terminal input of the comparator CMP (the potential of the node ND5), and the output of the comparator CMP are shown. Hereinafter, the operation of the DC-DC converter 1 will be described with reference to FIGS. 1 and 2.

  Before the time t1, the flip-flop FF is in the reset state (the PMOS transistor TR1 provided in the conversion unit 10 is in the off state). In this case, since the inverted output / Q of the flip-flop FF becomes H level, the voltage of the capacitor C2 becomes 0 and the slope current Is becomes 0. Since the transistor TR1 provided in the conversion unit 10 is in an off state, the potential of the node ND5 is equal to the potential Vin of the input node (the total voltage Vsum is 0).

  At time t1, the clock signal CLK is switched from the L level to the H level. As a result, the flip-flop FF is set, and the inverted output / Q of the flip-flop FF becomes L level. As a result, the transistor TR15 is turned off, so that the voltage of the capacitor C2 increases linearly from 0 as time passes, and the slope current Is increases from 0 to non-linear (almost time). Increases in proportion to the square). Further, since the transistor TR1 is turned on, the inductor current IL gradually increases. Therefore, if the resistance values of the resistance elements R4 and R1 are r4 and r1, respectively, the potential of the node ND5 is the voltage drop (IL × r4) due to the resistance element R4 and the voltage drop (Is) due to the resistance element R1 from the input voltage Vin. It is equal to a value obtained by subtracting xr1).

  When the potential of the node ND5 reaches the potential of the node ND6 (Vin−Ve) or the potential level of overcurrent protection (Vin−Vocp) at time t3, the output of the comparator CMP is switched from the L level to the H level. As a result, the flip-flop FF returns to the reset state. After time t4, the process is repeated from time t1.

[Effect of Embodiment 1]
As described above, according to the DC-DC converter 1 of the first embodiment, the non-linear slope current is generated by the slope compensation circuit 14 having a simple configuration, and the inductor current in the current control mode is stabilized by the generated slope current. can do. Hereinafter, the feature of the slope compensation circuit 14 in this embodiment will be supplemented while comparing with the slope compensation circuit 914 of the comparative example.

  FIG. 3 is a diagram showing a configuration of a DC-DC converter 901 as a comparative example of the DC-DC converter 1 of FIG. The DC-DC converter 901 in FIG. 3 differs from the DC-DC converter 1 in FIG. 1 in the configuration of the slope compensation circuit. The slope compensation circuit 914 of FIG. 3 is provided with a constant current source 17 that supplies a current I0 (= I1) to the transistor TR13 in place of the current source circuit 15 of FIG. And different. That is, the slope compensation circuit 914 includes NMOS transistors TR13 to TR15, a capacitor C2, and a constant current source 17.

  The source of the diode-connected transistor TR13 is connected to the ground node ND2 via the capacitor C2. A constant current source 17 is provided between the drain of the transistor TR13 and the input node ND1 to flow a current I0 (= I1) to the transistor TR13.

  Transistor TR14 has its gate connected to the gate of transistor TR13 and its source connected to ground node ND2. The drain of the transistor TR14 is connected to the end point ND5 of the resistance element R1.

  Transistor TR15 is connected in parallel with capacitor C2. The inverted output / Q of the flip-flop FF is input to the gate of the transistor TR15. Therefore, when the flip-flop FF is in the reset state (that is, when the transistor TR1 is in the off state), the transistor TR15 becomes conductive, and thereby the electric charge accumulated in the capacitor C2 is released.

  Other configurations in FIG. 3 are the same as those in FIG. 1, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof is not repeated.

  FIG. 4 is a diagram showing signal waveforms at various parts in FIG. The graph of FIG. 4 shows, from the top, the waveform of the clock signal CLK input to the flip-flop FF of FIG. The waveform of current Is is shown.

  Before the time t1, the flip-flop FF is in the reset state (the PMOS transistor TR1 provided in the conversion unit 10 is in the off state). In this case, since the inverted output / Q of the flip-flop FF becomes H level, the voltage of the capacitor C2 becomes zero. In this case, a current I2 proportional to the ratio of the sizes of the transistors TR13 and TR14 flows as the slope current Is. When the sizes of the transistors TR13 and TR14 are equal to each other, the current I2 is equal to the output current I0 of the constant current source 17.

  At time t1, the clock signal CLK is switched from the L level to the H level. As a result, the flip-flop FF is set, and the inverted output / Q of the flip-flop FF becomes L level. As a result, the transistor TR15 is turned off, so that the voltage of the capacitor C2 increases linearly from 0 as time passes, and the slope current Is changes from the initial value I2 to non-linear ( It increases (in proportion to the square of time).

  When the potential of the node ND5 reaches the potential of the node ND6 (Vin−Ve) or the potential level of overcurrent protection (Vin−Vocp) at time t3, the output of the comparator CMP is switched from the L level to the H level. As a result, the flip-flop FF returns to the reset state, and the slope current Is returns to the initial value I2. After time t4, the process is repeated from time t1.

  As described above, in the case of the DC-DC converter 901 of the comparative example, the value of the slope current Is does not return to 0 when the flip-flop FF is in the reset state. On the other hand, in the case of the DC-DC converter 1 of FIG. 1, the value of the slope current Is returns to 0 when the flip-flop FF is in the reset state. As a result, the error voltage Ve and the overcurrent protection voltage Vocp can be compared with higher accuracy.

<Modification of Embodiment 1>
FIG. 5 is a circuit diagram showing a configuration of a DC-DC converter 2 as a modification of the DC-DC converter 1 of FIG.

  5 is different from the converter 10 of the DC-DC converter 1 of FIG. 1 in that the converter 10A of the DC-DC converter 2 of FIG. 5 does not include the resistance element R4.

  The control circuit 11A in FIG. 5 differs from the control circuit 11 in FIG. 1 in that it further includes a resistance element R5 and a PMOS transistor TR5. Resistance element R5 and transistor TR5 are connected in series between input node ND1 and connection node ND4 in this order. One end of the resistor element R1 is connected to a connection node ND10 between the resistor element R5 and the transistor TR5. That is, one end of the resistance element R1 is connected to the connection node ND4 between the transistor TR1 and the inductor L via the transistor TR5. The output signal of the drive circuit DRV is input to the gate of the transistor TR5. Therefore, the transistor TR5 is turned on when the transistor TR1 is turned on.

  In the case of the DC-DC converter 2 shown in FIG. 5, the inductor current IL is detected using the on-resistance of the transistor TR1. A voltage proportional to the inductor current IL (a voltage drop due to the on-resistance of the transistor TR1) and a voltage proportional to the slope current Is are caused by the potential of the other end (node ND5) of the resistance element R1 when the transistor TR1 is in the on state. The total voltage (voltage drop due to the resistance element R1) is detected. When the transistor TR1 is in an off state, the transistor TR5 is also in an off state, and the resistance element R5 functions as a pull-up resistor, so that the potential of the node ND5 is equal to the input voltage Vin. Since the other points of FIG. 5 are the same as those of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  1 and 5 show the non-insulated DC-DC converter 1 as the conversion unit 10, but the present invention is also applied to an insulated DC-DC converter instead. Can do.

<Embodiment 2>
[Configuration of DC-DC Converter 3]
FIG. 6 is a circuit diagram showing a configuration of DC-DC converter 3 according to the second embodiment of the present invention. The DC-DC converter 3 of the second embodiment is different from that of the first embodiment in that a step-up chopper is provided as the conversion unit 20. Specifically, referring to FIG. 6, DC-DC converter 3 includes an input node ND1, a ground node ND2, an output node ND3, a converter 20 that performs DC voltage conversion, a control circuit 21, and slope compensation. Circuit 24.

(Configuration of the conversion unit 20)
The conversion unit 20 is a circuit called a so-called step-up chopper, generates the output voltage Vout by boosting the DC voltage Vin input to the input node ND1, and generates the output voltage Vout via the output node ND3. Output to. The conversion unit 20 includes an NMOS transistor TR21 as a switching element, an NMOS transistor TR22 as a synchronous rectification element, an inductor L, a smoothing capacitor C1, and a resistance element R4 for detecting the inductor current IL.

  Inductor L, transistor TR21, and resistance element R4 are connected in series between input node ND1 and ground node ND2 in this order. Transistor TR22 is connected between connection node ND4 and output node ND3 of inductor L and transistor TR21. Capacitor C1 is connected between output node ND3 and ground node ND2.

  A diode may be provided in place of the transistor TR22 as a synchronous rectifying element. In this case, the anode of the diode is connected to the connection node ND4, and the cathode of the diode is connected to the output node ND3.

(Configuration of control circuit 21)
As in the case of the first embodiment, the control circuit 21 switches the transistors TR21 and TR22 on and off by current mode control with slope compensation. Specifically, the control circuit 21 includes an error amplifier EAMP, a resistance element R1, a comparator CMP, an RS flip-flop FF, a drive circuit DRV, and an inverter 22.

  The error amplifier EAMP receives the reference voltage Vref at the + terminal, receives the output voltage Vout or the voltage obtained by dividing the output voltage Vout by resistance at the − terminal, and outputs a voltage obtained by amplifying the difference between them to the comparator CMP. A feedback compensation circuit (phase compensation circuit) may be provided after the error amplifier EAMP, and the output of the feedback compensation circuit may be output to the comparator CMP.

  The resistance element R1 is for converting the slope current Is generated by the slope compensation circuit 24 into a voltage. One end of the resistance element R1 is connected to a connection node ND9 between the resistance element R4 of the conversion unit 20 and the transistor TR21, and the other end (node ND5) of the resistance element R1 is connected to the slope compensation circuit 24. Therefore, in the case of FIG. 6, the slope current Is flows out of the slope compensation circuit 24, and flows into the ground node ND2 through the resistance element R1, the node ND9 of the conversion unit 20, and the resistance element R4 in this order. The potential of the other end (node ND5) of the resistance element R1 is equal to the total voltage Vsum of the voltage drop generated in the resistance element R4 by the inductor current IL and the voltage drop generated in the resistance element R1 by the slope current Is.

  The comparator CMP compares the error voltage Ve output from the error amplifier EAMP with the potential (total voltage Vsum) of the end point (node ND5) of the resistance element R1, and when the total voltage Vsum exceeds the error voltage Ve. An H level signal is output.

  The comparator CMP further compares the reference potential (overcurrent protection voltage Vocp) for overcurrent protection (OCP) with the potential (total voltage Vsum) of the end point (node ND5) of the resistor element R1. When the total voltage Vsum exceeds the overcurrent protection voltage Vocp, an H level signal is output.

  The RS flip-flop FF receives the clock signal CLK at the set terminal S and the output of the comparator CMP at the reset terminal R. The flip-flop FF is set when the clock signal CLK is switched to H level (at the rising edge of the clock signal CLK), and is reset when the output of the comparator CMP is switched to H level.

  Drive circuit DRV outputs a signal obtained by amplifying output Q of flip-flop FF to the gate of transistor TR21 and to the gate of transistor TR22 via inverter 22. Therefore, when the flip-flop FF is in the set state, the transistor TR21 is in the on state and the transistor TR22 is in the off state. When the flip-flop FF is in a reset state, the transistor TR21 is in an off state and the transistor TR22 is in an on state.

(Configuration of the slope compensation circuit 24)
The slope compensation circuit 24 generates a slope current Is that gradually increases from when the transistor TR21 switches to the on state and is reset to 0 when the transistor TR21 switches to the off state.

  Specifically, the slope compensation circuit 24 includes NMOS transistors TR30 to TR32, PMOS transistors TR33 to TR35, a capacitor C2, and a constant current source 36. The NMOS transistors TR30 to TR32 and the constant current source 36 constitute a current source circuit 25 that draws currents I1 and I2 from the drains of the PMOS transistors TR33 and TR34, respectively. Hereinafter, the connection between each component which comprises the slope compensation circuit 24 is demonstrated.

  The transistor TR33 is a so-called diode-connected transistor whose gate and drain are connected to each other. The source of the transistor TR33 is connected to the input node ND1 through the capacitor C2.

  The gate of transistor TR34 is connected to the gate of transistor TR33, and the source of transistor TR34 is connected to input node ND1. Therefore, when the capacitor C2 is not provided, the transistors TR33 and TR34 constitute a normal current mirror.

  Transistor TR35 is connected in parallel with capacitor C2. The output Q of the flip-flop FF is input to the gate of the transistor TR35. Therefore, when the flip-flop FF is in the reset state (that is, when the transistor TR21 is in the off state), the transistor TR35 is turned on, whereby the charge accumulated in the capacitor C2 is released.

  Transistor TR31 is connected in series with transistor TR33 between input node ND1 and ground node ND2. That is, the source of the transistor TR31 is connected to the ground node ND2, and the drain of the transistor TR31 is connected to the drain of the transistor TR33.

  Transistor TR32 is connected in series with transistor TR34 between input node ND1 and ground node ND2. That is, the source of the transistor TR32 is connected to the ground node ND2, and the drain of the transistor TR32 is connected to the drain of the transistor TR34.

  A connection node ND8 of the transistors TR32 and TR34 is connected to the end point (node ND5) of the resistor element R1. In other words, a current path is provided that branches from the node ND8 on the current path connecting the transistors TR32 and TR34 and reaches the end point (node ND5) of the resistance element R1. The slope current Is flows out of the transistor TR34 and flows into the resistance element R1 through this current path.

  The transistor TR30 is a so-called diode-connected transistor whose gate and drain are connected to each other. The source of transistor TR30 is connected to ground node ND2, and the gate of transistor TR30 is connected to the gates of transistors TR31 and TR32. That is, the transistors TR30, TR31, TR32 constitute a current mirror.

The constant current source 36 is connected between the drain of the transistor TR30 and the input node ND1, and supplies a constant current I0 to the transistor TR30. Therefore, currents according to the sizes of the transistors TR30, TR31, TR32 (ratio W / L of the gate width W to the gate length L) flow through the transistors TR31, TR32 constituting the current mirror with the transistor TR30. If the currents flowing through the transistors TR31 and TR32 are I1 and I2, respectively, and the sizes of the transistors TR30, TR31 and TR32 are W30 / L30, W31 / L31 and W32 / L32, respectively,
I0: I1: I2 = W30 / L30: W31 / L31: W32 / L32 (4)
The relationship is established.

  An equal current I1 flows through the transistors TR31 and TR33 connected in series with each other. A current obtained by adding the current I2 flowing through the transistor TR32 and the slope current Is flows through the transistor TR34.

Here, the slope compensation circuit 24 of this embodiment is characterized in that the ratio of the sizes of the transistors TR33 and TR34 is made equal to the ratio of the sizes of the transistors TR31 and TR32. That is, if the sizes of the transistors TR33 and TR34 are W33 / L33 and W34 / L34, respectively,
W31 / L31: W32 / L32 = W33 / L33: W34 / L34 (5)
The relationship is established. In other words, the current source circuit 25 supplies currents I1 and I2 proportional to the ratio of the sizes of the transistors TR33 and TR34 to the transistors TR33 and TR34, respectively. When the sizes of the transistors TR33 and TR34 are equal to each other, the sizes of the transistors TR31 and TR32 are also equal to each other. In this case, the relationship of I1 = I2 is established.

(Operation of the slope compensation circuit 24)
Next, the operation of the slope compensation circuit 24 will be described. The gate-source voltage of the transistor TR34 is equal to the sum of the gate-source voltage of the transistor TR33 and the voltage of the capacitor C2. Therefore, the current flowing through the transistor TR34 changes according to the charging voltage of the capacitor C2.

  First, the case where the flip-flop FF is in a reset state (the NMOS transistor TR21 provided in the conversion unit 20 is in an off state) will be described. In this case, since the output Q of the flip-flop FF becomes L level, the transistor TR35 is turned on. As a result, the electric charge accumulated in the capacitor C2 is released and its voltage becomes almost zero. At this time, since the transistors TR33 and TR34 are the same as that constituting a current mirror circuit, the current flowing through the transistor TR34 is equal to the current I2 flowing through the transistor TR32 from the relationship of the above equation (5), and the slope The current Is becomes zero.

  Next, the case where the flip-flop FF is in the set state (the NMOS transistor TR21 provided in the conversion unit 20 is on) will be described. When the output Q of the flip-flop FF is switched from the L level to the H level, the transistor TR35 provided in the slope compensation circuit 24 is switched to the OFF state, so that the capacitor C2 starts charging with the constant current I1. Thereby, the voltage of the capacitor C2 increases in proportion to the time after the flip-flop FF is switched to the set state. Since the current flowing through the transistor TR34 increases nonlinearly from the current I2 (approximately proportional to the square of time), the slope current Is also varies non-linearly from 0 (approximately proportional to the square of time). To increase. When the flip-flop FF returns to the reset state, the slope current Is returns to zero.

  According to the DC-DC converter 3 having the above configuration, the non-linear slope current Is is generated by the slope compensation circuit 24 having a simple configuration, and the inductor current in the current control mode is stabilized by the generated slope current Is. Can do.

  As described with reference to FIG. 5, also in the case of the DC-DC converter 3 in FIG. 6, the inductor current IL can be detected using the on-resistance of the NMOS transistor TR <b> 21 without providing the resistance element R <b> 4. .

<Modification of Embodiment 2>
FIG. 7 is a circuit diagram showing a configuration of a modification of the slope compensation circuit 24 of FIG. Referring to FIG. 7, a slope compensation circuit 34 is obtained by adding a current mirror composed of PMOS transistors TR16 and TR17 to the configuration of the slope compensation circuit 14 shown in FIG. The diode-connected transistor TR16 is connected between the input node ND1 and the node ND8. Transistor TR17 is connected between input node ND1 and node ND5 in FIG. 6, and its gate is connected to the gate of transistor TR16.

  The slope compensation circuit 14 in FIG. 1 is a current sink into which the slope current Is flows. The slope compensation circuit 34 in FIG. 7 functions as a current source that flows out the slope current Is by adding a current mirror constituted by PMOS transistors TR16 and TR17.

  The slope compensation circuit 14 of FIG. 1 that functions as a current sink can also be replaced with a circuit in which two NMOS transistors that constitute a current mirror are added to the slope compensation circuit 24 of FIG. 6 that functions as a current source.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 2, 3 DC-DC converter, 10, 10A, 20 converter, 11, 21 control circuit, 12 voltage shift circuit, 13, 16, 17, 36 constant current source, 14, 24, 34 slope compensation circuit, 15 , 25 Current source circuit, 22 Inverter, C1, C2 capacitor, CLK clock signal, CMP comparator, DRV drive circuit, EAMP error amplifier, FF flip-flop, GND ground voltage, IL inductor current, Is slope current, L inductor, ND1 Input node, ND2 ground node, ND3 output node, R1, R2, R3, R4, R5 resistance element, TR1, TR2, TR5, TR10 to TR17, TR21, TR22, TR30 to TR35 MOS transistor, TR3, TR4 bipolar transistor, Vin Input power , Vocp overcurrent protection voltage, Vout the output voltage, GND a ground voltage, Vsum total voltage.

Claims (5)

An input node to which an input voltage is applied;
A ground node to which a ground voltage is applied; and
An output node for outputting an output voltage;
A first switching element having one end connected to the input node or the ground node;
An inductor connected to the other end of the first switching element;
A slope compensation circuit for generating a slope current;
By comparing the total voltage of the voltage proportional to the current flowing through the inductor and the voltage proportional to the slope current, and the error voltage based on the difference between the voltage proportional to the output voltage and a predetermined reference voltage, the first voltage And a control circuit for performing current mode control for switching the switching element to an off state,
The slope compensation circuit is:
A capacitive element;
A second switching element connected in parallel with the capacitive element and in an off state when the first switching element is in an on state;
A first transistor having a first main electrode connected to the input node or the ground node;
A first main electrode is connected to the first main electrode of the first transistor via the capacitor, and a control electrode is connected to the control electrode of the first transistor. A transistor,
A current source circuit that is connected to each second main electrode of the first and second transistors and supplies a current proportional to a ratio of the sizes of the first and second transistors to the first and second transistors, respectively. Including
The slope current flows into or out of the first transistor through a path branched from a connection path between the second main electrode of the first transistor and the current source circuit. DC-DC converter. The current source circuit is:
A third transistor connected in series with the first transistor between the input node and the ground node;
A fourth transistor connected in series with the second transistor between the input node and the ground node;
A diode-connected fifth transistor forming a current mirror with the third and fourth transistors;
A constant current source for supplying a predetermined current to the fifth transistor,
2. The DC-DC converter according to claim 1, wherein a ratio of the sizes of the first and second transistors is equal to a ratio of the sizes of the third and fourth transistors. A first resistance element inserted between the first switching element and the input node or the ground node;
The control circuit includes:
A second resistance element through which the slope current flows by connecting one end to a connection node between the first resistance element and the first switching element and connecting the other end to the slope compensation circuit;
A comparator that receives the voltage at the other end of the second resistance element as the total voltage and compares the voltage with the error voltage;
The DC-DC converter according to claim 1 or 2, wherein the first switching element is switched to an off state in accordance with an output of the comparator. The control circuit includes:
A third switching element that is on when the first switching element is on;
One end is connected to the connection node between the inductor and the first switching element via the third switching element, and the other end is connected to the slope compensation circuit, so that the first switching element is turned on. A resistance element through which the slope current flows when in a state;
A comparator that receives the voltage at the other end of the resistance element as the total voltage and compares it with the error voltage;
The DC-DC converter according to claim 1 or 2, wherein the first switching element is switched to an off state in accordance with an output of the comparator.   5. The overcurrent control according to claim 1, wherein the control circuit further performs overcurrent control for turning off the first switching element when a voltage proportional to a current flowing through the inductor exceeds a predetermined upper limit voltage. The DC-DC converter of Claim 1.

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