JP2013162066A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form embedded bit lines of a vertical transistor in a simple method and with high accuracy.SOLUTION: A semiconductor device manufacturing method comprises: forming semiconductor pillars which are arranged at regular intervals in the past so as to be arranged at intervals alternately wide and narrow; filling an insulation film 3a in a narrow interval; forming conductive films to be embedded bit lines on respective sides of semiconductor pillars (1b, 1c) which face each other across a wide interval in sidewall-shape; further filling an insulation film 5 between the conductive film sidewalls; and forming embedded bit lines 6 by etch-back of the insulation film and etching of the conductive film.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a vertical transistor and a manufacturing method thereof.

  A vertical transistor using a columnar semiconductor (semiconductor pillar) as a channel is disclosed in Patent Document 1, for example.

  In Patent Document 1, a buried bit line is formed at the bottom between semiconductor pillars, and a lower diffusion layer of one of two adjacent semiconductor pillars is connected to the buried bit line.

JP 2011-77185 A

  In recent years, a method of forming a buried bit line only on one side of a semiconductor pillar has been studied. However, in order to form a conductor layer serving as a bit line only on one side of the semiconductor pillar, it is necessary to provide the conductor layer on one side of a space provided between the semiconductor pillars with a narrow interval. Therefore, patterning of the conductor layer requires patterning that requires a high aspect and high resolution, and there is a problem that fine processing is difficult.

  In the present invention, conventionally, semiconductor pillars arranged at equal intervals are formed so that wide intervals and narrow intervals alternate, and a conductor film that becomes buried bit lines on both sides of the semiconductor pillars facing the wide intervals is formed in a sidewall shape. In addition, an insulating film is embedded between the conductive film sidewalls, and a buried bit line is formed by insulating film etching back and conductive film etching.

That is, according to one embodiment of the present invention,
A first semiconductor pillar; a second semiconductor pillar provided at a first interval in the first direction from the first semiconductor pillar; and the first semiconductor pillar in the first direction from the second semiconductor pillar. A third semiconductor pillar provided at a second interval wider than the interval of
A first buried bit line extending in a second direction in contact with a lower portion of the second semiconductor pillar and intersecting the first direction in the region defining the second interval; A second buried bit line extending in the second direction in contact with a lower portion of the semiconductor pillar;
The semiconductor device is provided in which the first, second, and third semiconductor pillars are continuously provided in a straight line in the first direction.

Also, according to another embodiment of the present invention,
A plurality of grooves extending in a second direction is formed in the semiconductor substrate, and the first semiconductor fin and a first interval in the first direction intersecting the second direction from the first semiconductor fin A second semiconductor fin separated by a groove, and a third semiconductor fin separated from the second semiconductor fin by a groove having a second interval wider than the first interval in the first direction. A process to define;
The first insulating film is formed with a film thickness that fills the first gap groove and does not fill the second gap groove, and etch-back the first insulating film on the sidewalls of the first to third semiconductor fins. Forming insulating film sidewalls;
Selectively removing first insulating film sidewalls in the second spacing grooves;
A conductor film is formed on the entire surface with a film thickness that does not fill the groove with the second interval, and etched back to form a conductor film on the side surfaces of the second and third semiconductor fins facing each other within the groove with the second interval. Forming a sidewall;
Filling a second insulating film between the conductive film sidewalls in the second gap groove;
Etching back the second insulating film to a predetermined height;
And a step of forming a buried bit line by etching away the exposed conductive film sidewall.

  Since the conductor film to be a buried bit line is separated in a wide interval region, the aspect ratio is reduced and the processing becomes easy.

It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the DD line of (a), (c) is (a) ) Is a cross-sectional view taken along line AA, and FIG. 6D is a cross-sectional view taken along line A′-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b1) is sectional drawing in the DD line | wire of (a), (b2) is (a ) Is a sectional view taken along line D'-D ', (c) is a sectional view taken along line AA in (a), and (d) is a sectional view taken along line A'-A' in (a). . It is a figure explaining the modification of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b1) is sectional drawing in the DD line | wire of (a), (b2) is (a ) Is a sectional view taken along line D'-D ', (c) is a sectional view taken along line AA in (a), and (d) is a sectional view taken along line A'-A' in (a). .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments.

  FIGS. 1-10 is a figure explaining the manufacturing process of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view in each figure, (b) is the DD line of (a). Sectional drawing, (c) is a sectional view taken along line AA in (a), and (d) shows a sectional view taken along line A′-A ′ in (a). 10B1 is a cross-sectional view taken along the line D-D in FIG. 10A, and FIG. 10B2 is a cross-sectional view taken along the line D'-D 'in FIG. Here, a direction parallel to the DD line is defined as a first direction, and a direction parallel to the AA line and the A′-A ′ line is defined as a second direction.

Step of FIG. 1 First, a mask film 2 made of a silicon nitride film is formed on a silicon substrate as the semiconductor substrate 1, and the semiconductor substrate 1 is etched to form silicon fins 1a to 1d extending in the second direction. At this time, the interval (first interval) L1 between the silicon fins 1a and 1b, 1c and 1d is narrow, and the interval (second interval) L2 between 1b and 1c is increased. For example, the interval L1 is about 40 nm (0.7F), the interval L2 is about 80 nm (1.3F), and the fin width is about 60 nm (1F). Further, the height (etching depth) of the silicon fin is about 300 nm, for example. In the drawing, for convenience, an example in which four silicon fins 1a to 1d are formed is shown, but actually, a plurality of silicon fins are formed in the same manner. At this time, the silicon fin 1a is the first semiconductor fin, the silicon fin 1b is the second semiconductor fin, the silicon fin 1c is the third semiconductor fin, the silicon fin 1c is the first semiconductor fin, and the silicon fin 1d is The second semiconductor fin, the silicon fin 1e (not shown) is used as a third semiconductor fin, and the first semiconductor fin and the third semiconductor fin are overlapped and repeated.

2 Step Next, the surfaces of the semiconductor substrate 1, the silicon fins 1a to 1d, and the mask film 2 are oxidized. Next, a silicon nitride film 3 is formed as a first insulating film on the entire surface. The film thickness of the silicon nitride film 3 is set to a half or more of the interval L1 in order to make the interval L1 part fill with the silicon nitride film 3. Moreover, in order to make the space | interval L2 part into the thickness which is not filled, it shall be less than 1/2 of the space | interval L2. For example, the silicon nitride film 3 has a thickness of 25 nm.

3 and 4 Next, wet etching is performed on the nitride film to remove the silicon nitride film 3 formed on the opposing side surfaces of the silicon fins 1b and the silicon fins 1c, that is, in the grooves having the second distance L2. As a result, the sidewall silicon nitride film 3s filled in the interval L1 remains. Subsequently, the oxide film on the surface of the semiconductor substrate 1, the silicon fins 1a to 1d, and the mask film 2 is removed by wet etching.

Step of FIG. 5 Next, a conductor film 4 to be a buried bit line is formed on the entire surface. As the material of the conductor film 4, a metal material that does not form silicide, such as titanium nitride (TiN), can be used. The conductor film 4 has a film thickness (less than half the distance L2) that does not fill the groove between the silicon fins 1b and 1c, and is formed to a thickness of 25 nm, for example.

Step of FIG. 6 The conductor film 4 is etched back to leave side wall-like conductor films 4s on the side walls of the silicon fin.

Step of FIG. 7 A second insulating film 5 is formed on the entire surface. As the second insulating film 5, a silicon oxide film can be used.

Step of FIG. 8 Etch back to the height of the buried bit line where the second insulating film 5 is to be formed to expose the conductor film 4s. The height of the buried bit line is about 100 nm, for example.

Step in FIG. 9 The exposed conductor film 4s is removed by wet etching using ammonia or hydrogen peroxide. Thereby, the buried bit line 6 is formed below each of the silicon fins 1a to 1d. For example, paying attention to the interval L2 portion, the first embedded bit line formed on the side wall of the silicon fin 1b and the second embedded bit line formed on the side wall of the silicon fin 1c are arranged to face each other, and the interval L1. No buried bit line is formed in the portion.

Step of FIG. 10 After the third insulating film 7 is formed on the entire surface, the surface is flattened by CMP or the like using the mask film 2 as a stopper. A silicon oxide film can be used as the third insulating film 7.

FIG. 11 Step After forming a line mask (width 1F, not shown) extending in the first direction at equal intervals (1F) in the second direction, the mask film 2 and the sidewall silicon nitride film 3s are etched. Then, the upper surfaces of the silicon fins 1a to 1d are exposed at a predetermined interval.

  Subsequently, the third insulating film 7 is etched back to a depth at which the buried bit line 6 is not exposed, for example, to a depth of 150 nm from the upper surface of the silicon fin. Thereafter, each of the silicon fins 1a to 1d is etched back to the same depth and separated into silicon pillars 1a 'to 1d', respectively. Further, the mask film 2 and the sidewall silicon nitride film 2 are removed by dry etching or wet etching. The sidewall silicon nitride film 3s is preferably removed by dry etching in order to remove it with good controllability until it becomes almost the same height as the upper surface of the third insulating film 7. Note that the third insulating film 7 which is a silicon oxide film may be etched back simultaneously with the silicon etching.

  Subsequently, the exposed surface of the semiconductor substrate 1 is thermally oxidized to form a gate insulating film 8, and a conductor film 9 serving as a word line is formed on the sidewalls of the silicon pillars 1a 'to 1d'. As the conductor film 9, an impurity-doped polysilicon film, titanium nitride, or the like can be used. The conductor film 9 is etched back to be lower than the surface height of the silicon pillars 1a 'to 1d' in order to separate in the second direction. Thereafter, interlayer insulating films 10 and 11 are formed, contact holes exposing the upper surfaces of the respective silicon pillars 1a 'to 1d' are formed, and contact plugs 12 are embedded. Note that the contact holes are preferably formed at substantially equal intervals (2F pitch) in the first direction and the second direction. Further, diffusion layers are formed by introducing impurities into the upper and lower portions of the silicon pillars 1a 'to 1d' by a known method. In FIG. 11A, the insulating film is shown in a transparent state.

  Here, in the silicon pillars 1a ′ to 1d ′, similarly to the silicon fins 1a to 1d, the silicon pillar 1a ′ is the first semiconductor pillar, the silicon pillar 1b ′ is the second semiconductor pillar, and the silicon pillar 1c ′ is the third. The semiconductor pillar 1c ′ is the first semiconductor pillar, the silicon pillar 1d ′ is the second semiconductor pillar, and the silicon pillar 1e ′ (not shown) is the third semiconductor pillar. 3 semiconductor pillars overlap and repeat. Thus, a semiconductor device having a 4F2 array pattern can be obtained.

  FIG. 12 shows a modified example of the structure shown in FIG. 11, and a surround gate structure is formed by embedding a conductor film 9 serving as a word line in a groove formed in an insulating film. With such a surround gate structure, complete depletion can be achieved and the characteristics of the transistor can be improved.

  In the above description, the first direction and the second direction are orthogonal to each other. However, the present invention is not limited to this, and the first direction and the second direction may be any direction that intersects. Preferably, the acute angle side is 60 degrees or more, more preferably 80 degrees or more, and optimally orthogonal.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a-1d Silicon fin 1a'-1d 'Silicon pillar 2 Mask film | membrane 3 1st insulating film (silicon nitride film)
3s Silicon nitride film side wall 4 Conductor film 4s Conductor film side wall 5 Second insulating film 6 Embedded bit line 7 Third insulating film 8 Gate insulating film 9 Conductive films 10, 11 Interlayer insulating film 12 Contact plug

Claims (12)

A first semiconductor pillar; a second semiconductor pillar provided at a first interval in the first direction from the first semiconductor pillar; and the first semiconductor pillar in the first direction from the second semiconductor pillar. A third semiconductor pillar provided at a second interval wider than the interval of
A first buried bit line extending in a second direction in contact with a lower portion of the second semiconductor pillar and intersecting the first direction in the region defining the second interval; A second buried bit line extending in the second direction in contact with a lower portion of the semiconductor pillar;
The semiconductor device according to claim 1, wherein the first, second, and third semiconductor pillars are continuously provided linearly in the first direction.   2. The semiconductor device according to claim 1, further comprising: an insulating film extending in the second direction on a lower side surface of the first semiconductor pillar and the second semiconductor pillar in a region defining the first interval.   The semiconductor device according to claim 1, wherein a plurality of the first, second, and third semiconductor pillars are provided at equal intervals in the second direction.   A word line extending in the first direction is provided above the first and second buried bit lines and on at least one side surface of the first, second, and third semiconductor pillars. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The semiconductor device according to claim 4, wherein a contact plug electrically isolated from the word line is connected to each upper surface of the semiconductor pillar.   The semiconductor device according to claim 1, wherein the second direction is a direction perpendicular to the first direction. A plurality of grooves extending in a second direction is formed in the semiconductor substrate, and the first semiconductor fin and a first interval in the first direction intersecting the second direction from the first semiconductor fin A second semiconductor fin separated by a groove, and a third semiconductor fin separated from the second semiconductor fin by a groove having a second interval wider than the first interval in the first direction. A process to define;
The first insulating film is formed with a film thickness that fills the first gap groove and does not fill the second gap groove, and etch-back the first insulating film on the sidewalls of the first to third semiconductor fins. Forming insulating film sidewalls;
Selectively removing first insulating film sidewalls in the second spacing grooves;
A conductor film is formed on the entire surface with a film thickness that does not fill the groove with the second interval, and etched back to form a conductor film on the side surfaces of the second and third semiconductor fins facing each other within the groove with the second interval. Forming a sidewall;
Filling a second insulating film between the conductive film sidewalls in the second gap groove;
Etching back the second insulating film to a predetermined height;
And a step of etching the exposed conductive film sidewall to form a buried bit line.   2. The mask insulating film according to claim 1, wherein at least the mask insulating film is left until the step of forming the embedded bit line after forming the first to third semiconductor fins by forming a mask insulating film on the semiconductor substrate. A method for manufacturing a semiconductor device. After the step of forming the buried bit line, filling the second spacing groove on the buried bit line with a third insulating film;
The first to third semiconductor fins, the first insulating film sidewalls, and the third insulating film are etched at a predetermined interval in the second direction to a depth at which the buried bit line is not exposed, Forming first, second and third semiconductor pillars that are linearly continuous in the direction of
Forming a gate insulating film on the exposed surface of the semiconductor pillar;
Forming a word line extending in the first direction so as to face at least one side surface of the first, second, and third semiconductor pillars that are linearly continuous in the first direction;
The method for manufacturing a semiconductor device according to claim 7, further comprising:   A plurality of the first, second and third semiconductor pillars are formed in the second direction by dividing the first, second and third semiconductor fins in the second direction at equal intervals. A method for manufacturing a semiconductor device according to claim 9. After forming the word line, a gap between the semiconductor pillars is filled with a fourth insulating film, a top surface of each semiconductor pillar is exposed, a fifth insulating film is formed on the entire surface, and the top surface of the semiconductor pillar is formed. Forming an exposed contact hole;
The method for manufacturing a semiconductor device according to claim 9, further comprising a step of filling the contact hole with a conductor to form a contact plug.   The method for manufacturing a semiconductor device according to claim 7, wherein the second direction is a direction orthogonal to the first direction.