JP2013157365A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

Provided is a technique capable of suppressing a decrease in reliability of a semiconductor device even when miniaturization of a MISFET is advanced.
The surface of the drain region of the high breakdown voltage MISFET Q1 has an inclined portion SLP that is inclined downward from the surface (main surface) of the semiconductor substrate 1S below the gate electrode G1 in a direction away from the gate electrode G1. doing. Therefore, the inclination angle between the surface of the drain region and the surface of the semiconductor substrate 1S under the gate electrode G1 is larger than the inclination angle between the surface of the source region and the surface of the semiconductor substrate 1S under the gate electrode G1. ing.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof. Particularly, the present invention relates to a semiconductor device including a low breakdown voltage MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a high breakdown voltage MISFET having a breakdown voltage larger than that of the low breakdown voltage MISFET, and to a technology effective when applied to a manufacturing technique thereof.

  Japanese Patent Laid-Open No. 11-340453 (Patent Document 1) describes an insulated gate transistor having the following configuration. Specifically, the insulated gate transistor described in Patent Document 1 includes a semiconductor substrate having a convex portion having a substantially trapezoidal cross section in the gate length direction, a gate insulating film formed on the upper surface of the convex portion, A gate electrode formed on the gate insulating film. Further, the insulated gate transistor has a pair of LDD regions formed in the inclined portion of the convex portion, and a source region and a drain region formed in an outer region of the pair of LDD regions.

  In Japanese Patent Application Laid-Open No. 07-153943 (Patent Document 2), a semiconductor portion constituting a transistor constitutes a convex portion having a trapezoidal shape, and a gate electrode is formed on the upper surface of the convex portion via a gate insulating film. The structure that is formed is described. A source region and a drain region are formed on both side surfaces of the convex portion.

  Japanese Patent Laid-Open No. 05-343673 (Patent Document 3) describes a MOS transistor having a structure in which a recess is formed in a substrate and a portion where a gate electrode is formed is raised. Specifically, in the substrate, a recess is formed in the source region and the drain region, and a channel region is formed in the raised portion. A gate electrode is formed on the raised portion via a gate insulating film. Furthermore, a high concentration source region and a high concentration drain region are formed at the bottom of the recess, and a low concentration source region and a low concentration drain region are formed on the side surface of the raised portion.

  Japanese Patent Application Laid-Open No. 60-183771 (Patent Document 4) describes a technique of performing high dose ion implantation to form a source region and a drain region after performing taper etching on a substrate portion. Yes. According to this technique, in a single ion implantation step, a high dose amount of ion can be implanted into the flat portion of the substrate, and a low dose amount of ion can be implanted in the inclined portion. .

  Japanese Patent Application Laid-Open No. 03-155676 (Patent Document 5) describes a technique in which inclined portions are formed on both side surfaces of a channel region, and a source region and a drain region are formed on the inclined portions.

  Japanese Patent Laying-Open No. 2009-099712 (Patent Document 6) describes a technique for realizing a p-channel MOSFET having excellent driving capability. Specifically, the source region and the drain region of the p-channel MOSFET are configured to have an inclined surface with respect to the main surface of the semiconductor substrate.

Japanese Patent Laid-Open No. 11-340453 Japanese Patent Application Laid-Open No. 07-153943 Japanese Patent Laid-Open No. 05-343673 JP 60-183771 A Japanese Patent Laid-Open No. 03-155676 JP 2009-099712 A

  In recent years, the demand for miniaturization of semiconductor devices has increased, and in order to meet this demand, miniaturization of semiconductor chips constituting semiconductor devices has been promoted. Miniaturization of a semiconductor chip has been realized mainly by miniaturization of a MISFET which is a component of an integrated circuit formed on the semiconductor chip. However, when the miniaturization of the MISFET is advanced, the electric field strength in the vicinity of the drain region of the MISFET increases, and this increase in the electric field strength has become a problem. That is, when the electric field strength in the vicinity of the drain region of the MISFET is increased, hot carriers having large energy are likely to be generated. When hot carriers having a large energy are generated, the hot carriers enter the gate insulating film and change the threshold voltage of the MISFET. In other words, when the miniaturization of the MISFET is advanced, the electric field strength in the vicinity of the drain region increases, and as a result, a decrease in reliability of the semiconductor device becomes a problem.

  An object of the present embodiment is to provide a technique capable of suppressing a decrease in reliability of a semiconductor device even when miniaturization of a MISFET is promoted.

  The above and other objects and novel features of the present embodiment will become apparent from the description of the present specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the semiconductor device of one embodiment, the surface of the drain region of the MISFET is inclined downward from the surface of the semiconductor substrate (the surface of the channel region) below the gate electrode in the direction away from the gate electrode. Yes. In particular, the inclination angle between the surface of the drain region and the surface of the semiconductor substrate under the gate electrode is larger than the inclination angle between the surface of the source region and the surface of the semiconductor substrate under the gate electrode.

  In one embodiment, a method for manufacturing a semiconductor device includes a step of forming an inclined portion on a surface for forming a drain region by anisotropically etching the surface for forming a drain region of a surface of a semiconductor substrate. Is included.

  The effects obtained by typical ones of the embodiments disclosed in the present application will be briefly described as follows.

  According to one embodiment, even when miniaturization of the MISFET is advanced, it is possible to suppress a decrease in reliability of the semiconductor device.

3 is a diagram showing a layout configuration of a semiconductor chip in the first embodiment. FIG. It is a figure which shows the cross-section of MISFET in the prior art which this inventor examined. 1 is a cross-sectional view illustrating a configuration of a semiconductor device in a first embodiment. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device in a second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., unless otherwise specified, and in principle, it is not considered that it is clearly apparent in principle. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
<Semiconductor chip layout configuration>
The first embodiment is a semiconductor device having a low breakdown voltage MISFET (Metal Insulator Semiconductor) driven at a relatively low voltage and a high breakdown voltage MISFET driven at a relatively high voltage in order to enable high voltage driving. The present invention is applied. In the MISFET, the breakdown voltage refers to a pn junction breakdown voltage generated at the boundary between the source region and the semiconductor substrate (well) or the drain region and the semiconductor substrate (well) constituting the MISFET, or a breakdown voltage of the gate insulating film. In the first mode, a high breakdown voltage MISFET having a relatively high breakdown voltage and a low breakdown voltage MISFET having a relatively low breakdown voltage are formed on a semiconductor substrate.

  FIG. 1 is a diagram showing a layout configuration of the semiconductor chip CHP in the first embodiment. In FIG. 1, a semiconductor chip CHP includes a CPU (Central Processing Unit) 1, a RAM (Random Access Memory) 2, an analog circuit 3, an EEPROM (Electrically Erasable Programmable Read Only Memory) 4, a flash memory 5 and an I / O (Input / Input). Output) circuit 6 is provided.

  The CPU (circuit) 1 is also called a central processing unit and is the heart of a computer or the like. The CPU 1 reads out and decodes instructions from the storage device, and performs various operations and controls based on the instructions, and requires high-speed processing. Accordingly, the MISFET constituting the CPU 1 requires a relatively large current driving force among the elements formed on the semiconductor chip CHP. That is, it is formed of a low breakdown voltage MISFET.

  The RAM (circuit) 2 is a memory that can read stored information at random, that is, read stored information at any time, or write new stored information, and is also called a memory that can be written and read at any time. There are two types of RAM as an IC memory: DRAM (Dynamic RAM) using a dynamic circuit and SRAM (Static RAM) using a static circuit. DRAM is an occasional writing / reading memory that requires a memory holding operation, and SRAM is an occasional writing / reading memory that does not require a memory holding operation. Since these RAMs 2 are also required to operate at high speed, the MISFETs constituting the RAMs 2 require a relatively large current driving force. That is, it is formed of a low breakdown voltage MISFET.

  The analog circuit 3 is a circuit that handles a voltage or current signal that changes continuously in time, that is, an analog signal, and includes, for example, an amplifier circuit, a conversion circuit, a modulation circuit, an oscillation circuit, and a power supply circuit. These analog circuits 3 use a high breakdown voltage MISFET having a relatively high breakdown voltage among elements formed on the semiconductor chip CHP.

  The EEPROM 4 and the flash memory 5 are a kind of non-volatile memory that can be electrically rewritten for both writing and erasing operations, and are also called electrically erasable programmable read-only memories. The memory cells of the EEPROM 4 and the flash memory 5 are composed of, for example, MONOS (Metal Oxide Nitride Oxide Semiconductor) type transistors or MNOS (Metal Nitride Oxide Semiconductor) type transistors for storage (memory). For example, the Fowler-Nordheim tunneling phenomenon is used for the writing operation and the erasing operation of the EEPROM 4 and the flash memory 5. Note that a write operation or an erase operation can be performed using hot electrons or hot holes. The difference between the EEPROM 4 and the flash memory 5 is that the EEPROM 4 is a non-volatile memory that can be erased in byte units, for example, whereas the flash memory 5 is a non-volatile memory that can be erased in word word units, for example. is there. In general, the flash memory 5 stores a program for the CPU 1 to execute various processes. On the other hand, the EEPROM 4 stores various data with high rewrite frequency. For example, taking an IC card semiconductor chip of a mobile phone as an example, the EEPROM 4 stores data such as a telephone number, billing information, and a call memo. Since these EEPROM 4 and flash memory 5 require a high voltage for performing the write operation and the erase operation, for example, the peripheral circuit for driving the EEPROM 4 and the flash memory 5 includes a booster circuit and the like. In this booster circuit, a high breakdown voltage MISFET having a relatively high breakdown voltage is used.

  The I / O circuit 6 is an input / output circuit, and outputs data from the semiconductor chip CHP to a device connected to the outside of the semiconductor chip CHP, or from a device connected to the outside of the semiconductor chip CHP to the semiconductor chip. This is a circuit for inputting the data. The I / O circuit 6 also uses a high breakdown voltage MISFET having a relatively high breakdown voltage among elements formed on the semiconductor chip CHP.

<Details of problems found by the inventor>
As described above, transistors used in SOC (System On Chip) and MCU (Micro Controller Unit) are roughly classified into low breakdown voltage MISFETs and high breakdown voltage MISFETs. For example, the low withstand voltage MISFET is used in a circuit that requires high speed such as a CPU (Central Processing Unit), while the high withstand voltage MISFET is an I / O that interfaces an internal circuit and an external circuit of a semiconductor chip. It is used in an O (Input / Output) circuit or an analog circuit that operates with a relatively high power supply voltage. The high voltage MISFET often uses one of 1.8V, 2.5V, 3.3V, and 5V, or two of them as the power supply voltage, depending on the application. .

  In recent years, there is a demand for downsizing of semiconductor devices, and in order to cope with downsizing of semiconductor devices, downsizing of semiconductor chips on which integrated circuits are formed has been promoted. A semiconductor chip used in the above-described SOC or MCU is formed with a low breakdown voltage MISFET or a high breakdown voltage MISFET, and in particular, downsizing of the semiconductor chip has been promoted by downsizing of the low breakdown voltage MISFET. That is, in the low withstand voltage MISFET, the gate length of the gate electrode is formed with the minimum processing dimension, and the miniaturization of the low withstand voltage MISFET has progressed with the progress of miniaturization of the minimum processing dimension.

  However, in recent years, the miniaturization of the low breakdown voltage MISFET has already progressed, and the ratio of the area of the core region in which the low breakdown voltage MISFET is formed to the entire semiconductor chip has been reduced. For this reason, even if the miniaturization of the low breakdown voltage MISFET is advanced in the future, it is becoming difficult to efficiently reduce the area of the entire semiconductor chip. Therefore, in order to efficiently reduce the area of the entire semiconductor chip, it is considered that the high voltage MISFET must be downsized.

  However, since a high voltage MISFET uses a relatively high power supply voltage as described above, the following problems become apparent when the gate size is simply reduced. That is, when a high breakdown voltage MISFET is operated, a relatively high power supply voltage is applied to the drain region, so that the electric field strength near the drain region increases. Thus, when the electric field strength in the vicinity of the drain region is increased, hot carriers having large energy are likely to be generated. When hot carriers having large energy are generated, the hot carriers enter the gate insulating film, and the threshold voltage of the high voltage MISFET is changed.

  In particular, when the gate size of the high voltage MISFET is simply reduced, the electric field strength in the vicinity of the drain region increases. Since the generation probability of hot carriers increases with an increase in electric field strength, it is necessary to consider a decrease in reliability due to an increase in hot carriers when miniaturizing a high voltage MISFET. That is, when the miniaturization of the high breakdown voltage MISFET is advanced, it is necessary to suppress an increase in electric field strength in the vicinity of the drain region and suppress a decrease in reliability due to hot carriers.

<Examination of the mechanism that causes the problem>
First, in order to elucidate the cause of the decrease in reliability that occurs as the MISFET is miniaturized, the present inventor has studied the mechanism that causes the problem of decreased reliability. .

  FIG. 2 is a diagram showing a cross-sectional structure of a MISFET in the prior art studied by the present inventors. In FIG. 2, a plurality of element isolation regions STI are formed on the main surface side of the semiconductor substrate 1S. For example, a p-type well PWL1 is formed in an active region (active region) defined by these element isolation regions STI. Has been. A gate insulating film GOX1 is formed on the p-type well PWL1, and a gate electrode G1 is formed on the gate insulating film GOX1. Sidewalls SW are formed on the side walls on both sides of the gate electrode G1. Further, in the p-type well PWL1, a low concentration impurity region EX1D and a low concentration impurity region EX1S are formed in alignment with the gate electrode G1. Then, a high concentration impurity region NR1D is formed outside the low concentration impurity region EX1D, and a high concentration impurity region NR1S is formed outside the low concentration impurity region EX1S so as to match the sidewall SW. At this time, a drain region is formed by the low concentration impurity region EX1D and the high concentration impurity region NR1D, and a source region is formed by the low concentration impurity region EX1S and the high concentration impurity region NR1S. In order to prevent punch-through, the halo region HAL1 is usually formed so as to surround the low-concentration impurity region EX1S and the low-concentration impurity region EX1D.

  Focusing on the high voltage MISFET configured as described above, a large drain voltage is applied to the drain region in the high voltage MISFET. Here, for example, considering an n-channel type high breakdown voltage MISFET, the drain region is composed of an n-type semiconductor region, and the well is composed of a p-type well PWL1. At this time, when a drain voltage consisting of a large positive voltage is applied to the drain region of the n-channel type high breakdown voltage MISFET, the electric field strength of the drain region is the boundary region between the p-type well PWL1 and the low concentration impurity region EX1D. The maximum value is taken near the bent region of the low-concentration impurity region EX1D. In other words, the electric field strength becomes the maximum in the vicinity of the region having a large curvature of the low concentration impurity region EX1D. The electric field strength increases as the curvature of the low concentration impurity region EX1D increases.

  When such a region where the electric field strength increases is generated, hot carriers having large energy are likely to be generated. When hot carriers having large energy are generated, the hot carriers enter the gate insulating film GOX1 and change the threshold voltage of the high voltage MISFET. In particular, when the miniaturization of the high breakdown voltage MISFET is advanced, the curvature of the low concentration impurity region EX1D increases, and the electric field strength in the vicinity of the drain region increases. Therefore, when the miniaturization of the high breakdown voltage MISFET is advanced, the electric field strength in the vicinity of the drain region increases in addition to the large drain voltage. For this reason, hot carriers having large energy are likely to be generated, and this causes a decrease in reliability of the semiconductor device as a problem. Furthermore, if the miniaturization of the high-breakdown-voltage MISFET is advanced, the channel current (drain current) flowing through the channel region also increases, and from this point, hot carriers are likely to be generated.

  From the above, it can be seen that, when the miniaturization of the high voltage MISFET is advanced, the reliability degradation of the semiconductor device becomes obvious mainly due to the increase of the electric field strength in the vicinity of the drain region. A factor that increases the electric field strength in the vicinity of the drain region is that the curvature of the low-concentration impurity region EX1D is increased. Therefore, reducing the curvature of the low-concentration impurity region EX1D as much as possible increases the electric field strength. It is understood that it is important to suppress Therefore, in the first embodiment, in order to suppress an increase in the electric field strength in the vicinity of the drain region, a contrivance is given focusing on reducing the curvature of the low concentration impurity region EX1D. The configuration of the semiconductor device according to the first embodiment to which this device has been applied will be described below.

<Configuration of semiconductor device>
FIG. 3 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. As shown in FIG. 3, in the semiconductor device according to the first embodiment, the high breakdown voltage MISFET Q1 is formed in the region AR1 of the semiconductor substrate 1S, and the low breakdown voltage MISFET Q2 is formed in the region AR2 of the semiconductor substrate 1S. At this time, the high breakdown voltage MISFET Q1 and the low breakdown voltage MISFET Q2 are assumed to be n-channel MISFETs. Hereinafter, first, the configuration of the high voltage MISFET Q1 will be described.

  In FIG. 3, a plurality of element isolation regions STI are formed on the main surface side (front surface side) of the semiconductor substrate 1S, and the regions AR1 and AR2 are partitioned by these element isolation regions STI. A p-type well PWL1 is formed in the region AR1 of the semiconductor substrate 1S, and a high breakdown voltage MISFET Q1 is formed on the p-type well PWL1.

  Specifically, the high voltage MISFET Q1 has a gate insulating film GOX1 on the p-type well PWL1, and has a gate electrode G1 on the gate insulating film GOX1. At this time, the gate insulating film GOX1 is formed of, for example, a silicon oxide film, but is not limited thereto, and may be formed of, for example, a high dielectric constant film having a higher dielectric constant than a silicon oxide film such as a hafnium oxide film. Good. The gate electrode G1 is formed of, for example, a polysilicon film PF (n-type polysilicon film) into which phosphorus is introduced and a silicide film SL formed on the polysilicon film PF. The silicide film SL is a film formed for reducing the resistance of the gate electrode G1, and the silicide film SL is, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide. It is formed from a film or the like.

  Next, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G1. The sidewall SW is formed from, for example, a silicon oxide film or a silicon nitride film. A channel region is formed near the surface of the semiconductor substrate 1S (p-type well PWL1) immediately below the gate electrode G1, and a source region and a drain region are formed so as to sandwich the channel region.

  The source region has a low concentration impurity region EX1S adjacent to the channel region and a high concentration impurity region NR1S formed in a region outside the low concentration impurity region EX1S. The low concentration impurity region EX1S and the high concentration impurity region NR1S are semiconductor regions in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S. In particular, the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1S is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1S.

  That is, the source region includes a low concentration impurity region EX1S formed at a position close to the gate electrode G1, and a high concentration impurity region NR1S formed at a position farther from the gate electrode G1 than the low concentration impurity region EX1S. The impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1S is smaller than the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1S, and the deepest portion of the low-concentration impurity region EX1S is It is shallower than the deepest portion of the high concentration impurity region NR1S.

  A silicide film SL for reducing the resistance of the source region is formed on the surface of the high concentration impurity region NR1S. The silicide film SL can be formed of, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide film.

  A halo region HAL1 (pocket region) is formed so as to surround the periphery of the low-concentration impurity region EX1S constituting a part of the source region. The halo region HAL1 is a semiconductor region in which a p-type impurity such as boron (B) is introduced into the semiconductor substrate 1S, and the impurity concentration of the halo region HAL1 is higher than the impurity concentration of the p-type well PWL1. As a result, when a drain voltage is applied to the drain region, the depletion layer extending from the drain region can be prevented from reaching the source region, thereby preventing punch-through.

  Next, the configuration of the drain region will be described. The first embodiment is characterized by the configuration of the drain region. First, as shown in FIG. 3, the surface of the drain region of the high breakdown voltage MISFET Q1 in the first embodiment is directed from the surface (main surface) of the semiconductor substrate 1S below the gate electrode G1 in the direction away from the gate electrode G1. Also has an inclined portion SLP inclined downward. Therefore, the inclination angle between the surface of the drain region and the surface of the semiconductor substrate 1S under the gate electrode G1 is larger than the inclination angle between the surface of the source region and the surface of the semiconductor substrate 1S under the gate electrode G1. ing. That is, as shown in FIG. 3, the surface of the source region is substantially flush with the surface of the semiconductor substrate 1S under the gate electrode G1. On the other hand, as shown in FIG. 3, the surface of the drain region is inclined downward from the surface of the semiconductor substrate 1S below the gate electrode G1 in the direction away from the gate electrode G1. In other words, the high voltage MISFET in the first embodiment is formed between the pair of element isolation regions STI in a cross-sectional view, and the surface of the drain region faces the element isolation region STI close to the drain region side. Inclined to be continuously deeper. From this, it is apparent that the inclination angle between the surface of the drain region and the surface of the semiconductor substrate 1S under the gate electrode G1 is the inclination angle between the surface of the source region and the surface of the semiconductor substrate 1S under the gate electrode G1. It becomes larger than the angle.

  Thus, according to the high breakdown voltage MISFET in the first embodiment, the inclined portion SLP is provided in the drain region, and the drain region is formed along the inclined portion SLP. As a result, it can be seen that the curvature of the drain region can be made as small as possible. That is, since the drain region is formed so as to be parallel to the linearly inclined portion SLP, it is difficult to form a portion with a large curvature in the drain region, and thus the curvature can be reduced over the entire drain region. In consideration of the fact that the increase in electric field strength becomes significant in a region with a large curvature, according to the high voltage MISFET Q1 in the first embodiment shown in FIG. 3, the increase in electric field strength in the vicinity of the drain region is caused. It means that it can be suppressed. That is, in the first embodiment, since the drain region is formed along the inclined portion SLP, an increase in the electric field strength in the vicinity of the drain region can be suppressed, and the electric field strength can be reduced. As a result, hot carriers are generated. Can be reduced. For this reason, according to the high breakdown voltage MISFET Q1 in the first embodiment, since the generation of hot carriers can be reduced, fluctuations in threshold voltage caused by hot carriers can be suppressed, and the reliability of the semiconductor device can be improved. Can be planned. That is, according to the high withstand voltage MISFET Q1 in the first embodiment, even if miniaturization is advanced, an increase in electric field strength can be suppressed, so that the high withstand voltage MISFET Q1 can be made fine without reducing the reliability of the semiconductor device. Can be promoted. That is, according to the first embodiment, the high breakdown voltage MISFET Q1 can be miniaturized, and a remarkable effect can be obtained that the semiconductor device including the high breakdown voltage MISFET Q1 can be efficiently downsized.

  Here, as shown in FIG. 3, the drain region described above is formed of a low concentration impurity region EX1D and a high concentration impurity region NR1D. At this time, the low concentration impurity region EX1D and the high concentration impurity region NR1D are semiconductor regions in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S. In particular, the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1D is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1D. That is, as shown in FIG. 3, the drain region has a low concentration impurity region EX1D formed deep from the surface of the drain region and a high concentration impurity region NR1D formed shallower than the low concentration impurity region EX1D from the surface of the drain region. Are included. In other words, the low-concentration impurity region EX1D and the high-concentration impurity region NR1D are formed in parallel with the inclined portion SLP formed in the drain region.

  A silicide film SL for reducing the resistance of the drain region is formed on the surface of the high concentration impurity region NR1D. The silicide film SL can be formed of, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide film.

  A further feature of the first embodiment resides in that in the drain region formed so as to be parallel to the inclined portion SLP, the low concentration impurity region EX1D is formed in a region deeper than the high concentration impurity region NR1D. The drain region forms a pn junction with the p-type well PWL1. At this time, since the low concentration impurity region EX1D is formed deeper than the high concentration impurity region NR1D in the drain region, the low concentration impurity region EX1D is in direct contact with the p-type well PWL1. As a result, a pn junction is formed between the low-concentration impurity region EX1D and the p-type well PWL1, and when a relatively high positive drain voltage is applied to the drain region, a reverse bias is applied to the pn junction. It will be. At this time, since the impurity concentration of the low concentration impurity region EX1D is low, the depletion layer extends from the boundary region in the low concentration impurity region EX1D. The extension of the depletion layer means that the electric field density is reduced accordingly. Therefore, in the high breakdown voltage MISFET Q1 in the first embodiment, an increase in electric field strength in the vicinity of the drain region can be suppressed.

  Further, the first embodiment is characterized in that the halo region HAL1 is not formed so as to be adjacent to the drain region. That is, in the high breakdown voltage MISFET Q1 in the first embodiment, the halo region HAL1 is formed only on the source region side, and the halo region HAL1 is not formed on the drain region side.

  This is due to the following reason. For example, when the halo region HAL1 is formed so as to be adjacent to the drain region, a pn junction is formed between the halo region HAL1 and the drain region, not between the p-type well and the drain region. At this time, the impurity concentration of the p-type impurity introduced into the halo region HAL1 is higher than the impurity concentration of the p-type impurity introduced into the p-type well PWL1. For this reason, in the halo region HAL1, the depletion layer is difficult to extend from the boundary region. The fact that the depletion layer becomes difficult to extend means that the electric field density increases accordingly. That is, when the halo region HAL1 is formed so as to be adjacent to the drain region, the electric field strength in the vicinity of the drain region increases. Therefore, in the high breakdown voltage MISFET Q1 in the first embodiment, the halo region HAL1 is not formed on the drain region side. Thereby, in the high voltage MISFET Q1 in the first embodiment, an increase in electric field strength in the vicinity of the drain region can be suppressed.

  Even if the halo region HAL1 is not formed on the drain region side, in the case of the high breakdown voltage MISFET Q1, the gate length of the gate electrode G1 is relatively longer than that of the low breakdown voltage MISFET Q2, and the halo region HAL1 is formed on the source region side. By forming, punch through can be sufficiently suppressed.

  As described above, according to the first embodiment, (1) the drain region is provided with the inclined portion SLP, and the drain region is formed in parallel with the inclined portion SLP, and (2) the low-concentration impurity region. And EX1D formed deeper than the high concentration impurity region NR1D. Furthermore, according to the first embodiment, (3) a configuration in which the halo region HAL1 is not formed on the drain region side is also provided. Therefore, according to the first embodiment, the synergistic effect of these configurations (1) to (3) can suppress an increase in electric field strength in the vicinity of the drain region in the high voltage MISFET Q1 in the first embodiment. it can.

  For this reason, according to the high breakdown voltage MISFET Q1 in the first embodiment, since the generation of hot carriers can be reduced, fluctuations in threshold voltage caused by hot carriers can be suppressed, and the reliability of the semiconductor device can be improved. Can be planned. That is, according to the high withstand voltage MISFET Q1 in the first embodiment, even if miniaturization is advanced, an increase in electric field strength can be suppressed, so that the high withstand voltage MISFET Q1 can be made fine without reducing the reliability of the semiconductor device. Can be promoted. That is, according to the first embodiment, the high breakdown voltage MISFET Q1 can be miniaturized, and the semiconductor device including the high breakdown voltage MISFET Q1 can be efficiently downsized.

  Subsequently, in the first embodiment, as shown in FIG. 3, the inclined portion SLP is provided only on the drain region side, and the inclined portion SLP is not provided on the source region side. That is, in the high breakdown voltage MISFET Q1 in the first embodiment, the structure of the source region and the structure of the drain region are asymmetric. The reason for this will be described below.

  First, when the high breakdown voltage MISFET Q1 is operated, a reference potential (GND potential) is normally applied to the source region and the p-type well PWL1, and a positive drain voltage is applied to the drain region. Therefore, a voltage having the same potential is applied to the source region and the p-type well PWL1, so that a large electric field is applied to the pn junction formed in the boundary region between the source region and the p-type well PWL1. I don't think it will happen. On the other hand, since a relatively large drain voltage (positive voltage) is applied to the drain region, a reverse bias is applied to the pn junction between the drain region and the p-type well PWL1. The electric field strength in the vicinity of the region tends to increase. From this, it can be seen that the electric field strength increases in the vicinity of the drain region in the high voltage MISFET Q1. For this reason, it is necessary to suppress an increase in electric field strength, particularly in the vicinity of the drain region. In other words, on the source region side, the increase in the electric field strength is not so much a problem as compared with the drain region side. Therefore, in the first embodiment, the inclined portion SLP is provided in the drain region where the increase in the electric field strength becomes obvious, and the increase in the electric field strength in the vicinity of the drain region is suppressed. In other words, in the vicinity of the source region, the increase in the electric field strength is not a problem, so it is not necessary to provide the inclined portion SLP in the source region. Therefore, in the first embodiment, as shown in FIG. 3, an asymmetric structure is adopted in which the inclined portion SLP is provided only on the drain region side and the inclined portion SLP is not provided on the source region side. .

  Providing the inclined portion SLP means adding a step of providing the inclined portion SLP to the manufacturing process. At this time, it is desirable that changes or corrections from the normal manufacturing process should not be large as much as possible from the viewpoint of preventing a yield reduction due to the changes or corrections in the manufacturing process. Therefore, in the first embodiment, only the minimum necessary process change is required.

  The inclined portion SLP is not provided on the source region side for the following reason. That is, in the semiconductor device according to the first embodiment, in order to reduce the area of the semiconductor chip, it is necessary to reduce the size of the high voltage MISFET Q1. In order to improve the short channel characteristics accompanying the reduction of the high breakdown voltage MISFET Q1, it is useful to form the halo region HAL1 on the source region side. At this time, if the inclined portion SLP is also provided on the source region side so that a bent portion in the source region is eliminated as much as possible or not, the impurity introduced into the halo region HAL1 is introduced into the source region ( It becomes susceptible to the influence of impurities in the low concentration impurity region EX1S). As a result, the effect of forming the halo region HAL1 is weakened, and the tendency for the short channel characteristics to deteriorate becomes obvious. Therefore, if the amount of impurity (dose amount) introduced into the halo region HAL1 is increased in order to improve the short channel characteristics, there is a concern that the sheet resistance of the low concentration impurity region EX1S constituting the source region will increase. Furthermore, the effective impurity concentration at the portion where the silicide film SL is in contact with the high-concentration impurity region NR1S decreases, so that the portion that should be an ohmic junction becomes a Schottky junction, leading to an increase in parasitic resistance and consequently a decrease in drain current. It will be. Therefore, if the inclined portion SLP is provided also on the source region side, the above-described disadvantages occur. Therefore, it is desirable that the inclined portion SLP is not provided on the source region side.

  Here, when the inclined portion SLP is provided, the reason why the impurity introduced into the halo region HAL1 is easily influenced by the low-concentration impurity region EX1S constituting the source region can be explained as follows. In other words, eliminating the bent portion in the source region as much as possible or reducing the bending even if it cannot be eliminated means that, for example, the semiconductor substrate 1S is dug obliquely as in the drain region side. It is none other than forming the inclined portion SLP using means. That is, the low concentration impurity region EX1S and the high concentration impurity region NR1S are formed in parallel with the inclined portion SLP. The halo region HAL1 is mainly performed by an oblique ion implantation method (in some cases, a vertical ion implantation method may be used). In this case, if a source region having an impurity concentration distribution parallel to an oblique direction is formed, it is difficult to form a substantially functioning halo region HAL1. Therefore, the halo region HAL1 can be formed without deterioration of the sheet resistance or ohmic junction of the source region because the source region does not have the inclined portion SLP and the surface of the source region as shown in FIG. However, it is necessary to be substantially flush with the surface of the semiconductor substrate 1S under the gate electrode G1. From the above, in the first embodiment, the inclined portion SLP is not provided on the source region side.

  The high breakdown voltage MISFET Q1 in the first embodiment is configured as described above. Next, the configuration of the low breakdown voltage MISFET Q2 in the first embodiment will be described. First, as shown in FIG. 3, a p-type well PWL2 is formed in the region AR2 of the semiconductor substrate 1S, and a low breakdown voltage MISFET Q2 is formed on the p-type well PWL2.

  Specifically, the low breakdown voltage MISFET Q2 has a gate insulating film GOX2 on the p-type well PWL2, and has a gate electrode G2 on the gate insulating film GOX2. At this time, the gate insulating film GOX2 is formed of, for example, a silicon oxide film, but is not limited thereto, and may be formed of, for example, a high dielectric constant film having a higher dielectric constant than a silicon oxide film such as a hafnium oxide film. Good. The gate electrode G2 is formed of, for example, a polysilicon film PF (n-type polysilicon film) into which phosphorus is introduced and a silicide film SL formed on the polysilicon film PF. The silicide film SL is a film formed for reducing the resistance of the gate electrode G2. The silicide film SL is, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide. It is formed from a film or the like.

  Here, the film thickness of the gate insulating film GOX2 of the low voltage MISFET Q2 is smaller than the film thickness of the gate insulating film GOX1 of the high voltage MISFET Q1. That is, in the low breakdown voltage MISFET Q2, the gate breakdown voltage may be lower than that in the high breakdown voltage MISFET Q1, and the film thickness of the gate insulating film GOX2 is reduced in order to improve the controllability by the gate electrode G2. In addition, the gate length of the gate electrode G2 of the low breakdown voltage MISFET Q2 is smaller than the gate length of the gate electrode G1 of the high breakdown voltage MISFET Q1. This is because in the low breakdown voltage MISFET Q2, the drain voltage is low, and even if the drain voltage is low, the drain current is increased as much as possible to improve the current driving capability.

  Next, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G2. The sidewall SW is formed from, for example, a silicon oxide film or a silicon nitride film. A channel region is formed in the vicinity of the surface of the semiconductor substrate 1S (p-type well PWL2) immediately below the gate electrode G2, and a source region and a drain region are formed so as to sandwich the channel region.

  The source region has a low-concentration impurity region EX2 adjacent to the channel region and a high-concentration impurity region NR2 formed in a region outside the low-concentration impurity region EX2. The low concentration impurity region EX2 and the high concentration impurity region NR2 are semiconductor regions in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S. In particular, the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR2 is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX2.

  That is, the source region includes a low concentration impurity region EX2 formed at a position close to the gate electrode G2, and a high concentration impurity region NR2 formed at a position farther from the gate electrode G2 than the low concentration impurity region EX2. The impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX2 is smaller than the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR2, and the deepest portion of the low-concentration impurity region EX2 is It is shallower than the deepest portion of the high concentration impurity region NR2.

  A silicide film SL for reducing the resistance of the source region is formed on the surface of the high concentration impurity region NR2. The silicide film SL can be formed of, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide film.

  A halo region HAL2 (pocket region) is formed so as to surround the periphery of the low-concentration impurity region EX2 constituting a part of the source region. The halo region HAL2 is a semiconductor region in which a p-type impurity such as boron (B) is introduced into the semiconductor substrate 1S, and the impurity concentration of the halo region HAL2 is higher than the impurity concentration of the p-type well PWL2. As a result, when a drain voltage is applied to the drain region, the depletion layer extending from the drain region can be prevented from reaching the source region, thereby preventing punch-through.

  Similarly, the drain region also has a low concentration impurity region EX2 adjacent to the channel region and a high concentration impurity region NR2 formed in a region outside the low concentration impurity region EX2. The low concentration impurity region EX2 and the high concentration impurity region NR2 are semiconductor regions in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S. In particular, the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR2 is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX2.

  That is, the drain region includes a low concentration impurity region EX2 formed at a position close to the gate electrode G2, and a high concentration impurity region NR2 formed at a position farther from the gate electrode G2 than the low concentration impurity region EX2. The impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX2 is smaller than the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR2, and the deepest portion of the low-concentration impurity region EX2 is It is shallower than the deepest portion of the high concentration impurity region NR2.

  A silicide film SL for reducing the resistance of the drain region is formed on the surface of the high concentration impurity region NR2. The silicide film SL can be formed of, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide film.

  A halo region HAL2 (pocket region) is formed so as to surround the periphery of the low-concentration impurity region EX2 constituting a part of the drain region. The halo region HAL2 is a semiconductor region in which a p-type impurity such as boron (B) is introduced into the semiconductor substrate 1S, and the impurity concentration of the halo region HAL2 is higher than the impurity concentration of the p-type well PWL2. As a result, when a drain voltage is applied to the drain region, the depletion layer extending from the drain region can be prevented from reaching the source region, thereby preventing punch-through.

  Here, in the low breakdown voltage MISFET Q2, as shown in FIG. 3, the surface of the source region is substantially flush with the surface of the semiconductor substrate 1S under the gate electrode G2. Similarly, the surface of the drain region of the low breakdown voltage MISFET Q2 is substantially flush with the surface of the semiconductor substrate 1S under the gate electrode G2. Therefore, it can be said that the surface of the source region of the low breakdown voltage MISFET Q2 and the surface of the drain region of the low breakdown voltage MISFET Q2 are flush with each other. On the other hand, as shown in FIG. 3, the surface of the drain region of the high breakdown voltage MISFET Q1 is inclined downward from the surface of the semiconductor substrate 1S below the gate electrode G1 in the direction away from the gate electrode G1. . In other words, the high voltage MISFET in the first embodiment is formed between the pair of element isolation regions STI in a cross-sectional view, and the surface of the drain region faces the element isolation region STI close to the drain region side. Inclined to be continuously deeper. From this, it is apparent that the inclination angle between the surface of the drain region of the high breakdown voltage MISFET Q1 and the surface of the semiconductor substrate 1S below the gate electrode G1 is the surface of the drain region of the low breakdown voltage MISFET Q2 and the semiconductor substrate below the gate electrode G2. It becomes larger than the inclination angle between the surface of 1S.

  On the semiconductor substrate 1S covering the semiconductor elements (the high breakdown voltage MISFET Q1 and the low breakdown voltage MISFET Q2) thus configured, for example, as shown in FIG. 3, a contact interlayer insulating film made of a silicon oxide film using TEOS as a raw material is formed. CIL is formed. A contact hole CNT is formed so as to penetrate through the contact interlayer insulating film CIL and reach the silicide film SL formed on the surface of the source region and the drain region of the high breakdown voltage MISFET Q1. Similarly, a contact hole CNT is formed so as to penetrate through the contact interlayer insulating film CIL and reach the silicide film SL formed on the surface of the source region and the drain region of the low breakdown voltage MISFET Q2. Inside the contact hole CNT, a laminated film of a titanium film and a titanium nitride film serving as a barrier conductor film and a tungsten film formed on the barrier conductor film are embedded to form a plug PLG. A wiring L1 is formed on the contact interlayer insulating film CIL in which the plug PLG is formed. This wiring L1 can be formed from, for example, a damascene wiring using a copper film. Specifically, by forming a groove in the interlayer insulating film IL1 and embedding a copper film in the groove through a tantalum film and a tantalum nitride film, the wiring L1 made of damascene wiring can be formed. The wiring L1 is not limited to the damascene wiring using a copper film, and an aluminum wiring using an aluminum film may be employed.

<Method for Manufacturing Semiconductor Device>
The semiconductor device according to the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 4, a semiconductor substrate 1S made of a silicon single crystal into which a p-type impurity such as boron (B) is introduced is prepared. At this time, the semiconductor substrate 1S is in a state of a substantially wafer-shaped semiconductor wafer. Then, an element isolation region STI for isolating elements is formed in the semiconductor substrate 1S. The element isolation region STI is provided to prevent the elements from interfering with each other. The element isolation region STI can be formed using, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. For example, in the STI method, the element isolation region is formed as follows. That is, the element isolation trench is formed in the semiconductor substrate 1S by using the photolithography technique and the etching technique. Then, a silicon oxide film is formed on the semiconductor substrate so as to fill the element isolation trench, and then an unnecessary silicon oxide film formed on the semiconductor substrate 1S by chemical mechanical polishing (CMP). Remove. As a result, the element isolation region STI in which the silicon oxide film is buried only in the element isolation trench can be formed. In the first embodiment, a region AR1 that is a high breakdown voltage MISFET formation region and a region AR2 that is a low breakdown voltage MISFET formation region are partitioned by the element isolation region STI.

  Next, an impurity is introduced into the active region (active region) of the region AR1 partitioned by the element isolation region STI to form the p-type well PWL1. Further, an impurity is introduced into the active region of the region AR2 to form the p-type well PWL2. The p-type well PWL1 and the p-type well PWL2 are formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by an ion implantation method.

  Subsequently, a semiconductor region (not shown) for forming a channel is formed in the surface region of the p-type wells PWL1 to PWL2. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

  Next, as shown in FIG. 5, a silicon oxide film is formed on the main surface of the semiconductor substrate 1S by using, for example, a thermal oxidation method. Specifically, a gate insulating film GOX1 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1S in the region AR1, and a gate insulating film GOX2 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1S in the region AR2. At this time, the gate insulating film GOX1 is formed to have a thickness greater than that of the gate insulating film GOX2. Specifically, for example, a first silicon oxide film is formed on the entire surface of the semiconductor substrate 1S, and then the first silicon oxide film formed in the region AR2 is removed. Thereafter, a second silicon oxide film is again formed on the entire surface of the semiconductor substrate 1S. Thereby, the gate insulating film GOX1 made of the first silicon oxide film and the second silicon oxide film is formed in the region AR1, and the gate insulating film GOX2 made of the second silicon oxide film is formed in the region AR2. In the first embodiment, an example in which the gate insulating film GOX1 and the gate insulating film GOX2 are formed from a silicon oxide film has been described. You may form from a high dielectric constant film | membrane with a high rate.

  Thereafter, a polysilicon film PF is formed on the semiconductor substrate 1S. As a result, a polysilicon film PF is formed on the gate insulating film GOX1 in the region AR1. On the other hand, in the region AR2, the polysilicon film PF is formed on the gate insulating film GOX2.

  Subsequently, as shown in FIG. 6, by using the photolithography technique and the etching technique, the polysilicon film PF is patterned to form the gate electrode G1 in the region AR1, and form the gate electrode G2 in the region AR2. . At this time, the gate length of the gate electrode G1 is formed to be longer than the gate length of the gate electrode G2.

  Next, as shown in FIG. 7, a photosensitive resist film FR1 is applied on the semiconductor substrate 1S. The resist film FR1 is patterned by subjecting the resist film FR1 to exposure / development processing. The patterning of the resist film FR1 is performed so as to cover the region AR1 and expose the region AR2. Then, by ion implantation using the patterned resist film FR1 as a mask, the halo region HAL2 and the low concentration impurity region EX2 are formed inside the source region forming surface and the drain region forming surface in alignment with the gate electrode G2. To do. Specifically, first, for example, a halo region HAL2 is formed by introducing a p-type impurity such as boron (B) into the semiconductor substrate 1S by an ion implantation method. The impurity concentration of the p-type impurity introduced into the halo region HAL2 is higher than the impurity concentration of the p-type impurity introduced into the p-type well PWL2. Thereafter, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by an ion implantation method, thereby forming the low concentration impurity region EX2. The low concentration impurity region EX2 is formed so as to be included in the halo region HAL2. As a result, the halo region HAL2 is formed so as to surround the periphery of the low concentration impurity region EX2.

  Then, after removing the patterned resist film FR1, an insulating film made of, for example, a silicon oxide film is formed on the entire main surface of the semiconductor substrate 1S. Thereafter, as shown in FIG. 8, the insulating film is anisotropically etched to form side walls SW made of an insulating film on the side walls on both sides of the gate electrode G1 and the side walls on both sides of the gate electrode G2. In the first embodiment, the sidewall SW is formed from a single layer film of a silicon oxide film. However, the present invention is not limited to this. For example, the sidewall SW composed of a laminated film of a silicon nitride film and a silicon oxide film is formed. It may be formed.

  Subsequently, as shown in FIG. 9, a photosensitive resist film FR2 is applied on the semiconductor substrate 1S. Then, the resist film FR2 is patterned by subjecting the resist film FR2 to exposure / development processing. The patterning of the resist film FR2 is performed so as to cover the region AR1 and expose the region AR2. Then, by ion implantation using the patterned resist film FR2 as a mask, the high concentration impurity region NR2 is formed inside the source region forming surface and the drain region forming surface in alignment with the sidewall SW. Specifically, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by an ion implantation method, thereby forming the high concentration impurity region NR2. The high concentration impurity region NR2 is formed outside the low concentration impurity region EX2. The impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR2 is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX2. Note that the deepest portion of the high concentration impurity region NR2 is formed deeper than the deepest portion of the low concentration impurity region EX2. Thereby, the source region and the drain region of the low breakdown voltage MISFET composed of the low concentration impurity region EX2 and the high concentration impurity region NR2 can be formed.

  Next, as shown in FIG. 10, after removing the patterned resist film FR2, a photosensitive resist film FR3 is applied again on the semiconductor substrate 1S. Then, the resist film FR3 is patterned by performing exposure / development processing on the resist film FR3. Patterning of the resist film FR3 is performed so as to open a minute region adjacent to the element isolation region STI on the drain formation region side in the region AR1 and cover the other regions AR1 and AR2. Thereafter, a minute region opened from the resist film FR3 is recessed by etching using the patterned resist film FR3 as a mask. Specifically, a hole pattern that opens the resist film FR3 is formed by a photolithography technique, and then a small groove DIT is formed in the opened minute region by a dry etching technique.

  Subsequently, as shown in FIG. 11, after the patterned resist film FR3 is removed, the surface of the semiconductor substrate 1S is anisotropically etched by performing anisotropic wet etching using the small groove DIT as a starting point. For anisotropic wet etching, a solution containing TMAH (tetramethylammonium hydroxide) as a main component is used, thereby exposing the crystal plane (111) of silicon constituting the semiconductor substrate 1S. As a result, the inclined portion SLP can be formed in the drain formation region of the region AR1. The anisotropic wet etching of the semiconductor substrate 1S is, for example, a well-known technique in the process of forming a p-channel type MISFET. That is, anisotropic wet etching is a technique well known as a method of applying compressive stress by replacing silicon (Si) in the source region and drain region with silicon germanium (SiGe), and is not a special technique.

  Thereafter, as shown in FIG. 12, a photosensitive resist film FR4 is applied on the semiconductor substrate 1S. Then, the resist film FR4 is patterned by subjecting the resist film FR4 to exposure / development processing. The patterning of the resist film FR4 is performed so that the drain formation region of the high voltage MISFET formed in the region AR1 is exposed and the other region is covered. Then, the low concentration impurity region EX1D is formed inside the inclined portion SLP which is the inside of the drain region forming surface by ion implantation using the patterned resist film FR4 as a mask. Specifically, the low concentration impurity region EX1D is performed by one vertical ion implantation, a plurality of oblique ion implantations, or an appropriate combination thereof. As a result, it is possible to form the low concentration impurity region EX1D having an impurity concentration distribution parallel to the inclined portion SLP etched obliquely and having as little a pn junction shape as possible. Here, when there is a step in the boundary region between the element isolation region STI and the inclined portion SLP, shadowing occurs. Therefore, the low concentration impurity region EX1D parallel to the inclined portion SLP can be obtained by appropriately combining a plurality of ion implantations. Form.

  Next, as shown in FIG. 13, a high-concentration impurity region NR1D is formed inside the drain region formation surface by ion implantation using the patterned resist film FR4 as a mask. Specifically, the high concentration impurity region NR1D having an impurity concentration distribution parallel to the inclined portion SLP as much as possible by one vertical ion implantation, a plurality of oblique ion implantations, or an appropriate combination thereof. Form. However, the region where parallelism is required is an upper region close to the gate electrode G1 through which the drain current mainly flows. It is considered that almost no drain current flows in the lower region far from the gate electrode G1, and further, punch-through is affected by the impurity concentration distribution in the upper region and hardly depends on the impurity concentration distribution in the lower region. is there. Of course, the impurity concentration distribution may be parallel over the lower region, but when the impurity concentration distribution in the lower region is not limited to this, the degree of freedom in designing the impurity concentration distribution in the high concentration impurity region NR1D increases. Benefits are gained.

  In the first embodiment, the drain region of the high breakdown voltage MISFET is formed by the low concentration impurity region EX1D and the high concentration impurity region NR1D described above. At this time, in the drain region formed so as to be parallel to the inclined portion SLP, the low concentration impurity region EX1D is formed in a region deeper than the high concentration impurity region NR1D.

  Subsequently, as shown in FIG. 14, after removing the patterned resist film FR4, a photosensitive resist film FR5 is applied over the semiconductor substrate 1S. Then, the resist film FR5 is patterned by subjecting the resist film FR5 to exposure / development processing. The patterning of the resist film FR5 is performed so as to expose the source formation region of the high breakdown voltage MISFET formed in the region AR1 and cover the other regions. Then, the halo region HAL1 and the low-concentration impurity region EX1S are formed inside the surface for forming the source region in alignment with the gate electrode G1 by ion implantation using the patterned resist film FR5 as a mask. Specifically, first, for example, a halo region HAL1 is formed by introducing a p-type impurity such as boron (B) into the semiconductor substrate 1S by an oblique ion implantation method. The impurity concentration of the p-type impurity introduced into the halo region HAL1 is higher than the impurity concentration of the p-type impurity introduced into the p-type well PWL1. Thereafter, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by a combination of vertical ion implantation and oblique ion implantation, thereby forming the low-concentration impurity region EX1S. The low concentration impurity region EX1S is formed so as to be included in the halo region HAL1. As a result, the halo region HAL1 is formed so as to surround the periphery of the low concentration impurity region EX1S.

  After that, as shown in FIG. 15, a high-concentration impurity region NR1S is formed inside the source region formation surface by vertical ion implantation using the patterned resist film FR5 as a mask so as to align with the sidewall SW. To do. Specifically, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by the vertical ion implantation method, thereby forming the high concentration impurity region NR1S. The high concentration impurity region NR1S is formed outside the low concentration impurity region EX1S. The impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1S is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1S. The deepest portion of the high concentration impurity region NR1S is formed to be deeper than the deepest portion of the low concentration impurity region EX1S. Thereby, the source region of the high breakdown voltage MISFET composed of the low concentration impurity region EX1S and the high concentration impurity region NR1S can be formed.

  Next, as shown in FIG. 16, after removing the patterned resist film FR5, for example, a nickel platinum film (not shown) is formed on the semiconductor substrate 1S. At this time, the nickel platinum film is formed so as to be in direct contact with the upper surfaces of the gate electrodes G1 to G2. Similarly, the nickel platinum film is in direct contact with the surfaces of the high concentration impurity regions NR1D and NR1S and the surface of the high concentration impurity region NR2.

  The nickel platinum film can be formed using, for example, a sputtering method. Then, after the nickel platinum film is formed, heat treatment is performed to react the polysilicon film PF constituting the gate electrodes G1 to G2 with the nickel platinum film, thereby forming a silicide film SL made of a nickel platinum silicide film. Thereby, the gate electrodes G1 to G2 have a laminated structure of the polysilicon film PF and the silicide film SL. The silicide film SL is formed to reduce the resistance of the gate electrodes G1 to G2. Similarly, by the heat treatment described above, silicon and a nickel platinum film react with each other on the surfaces of the high concentration impurity regions NR1D and NR1S and the surface of the high concentration impurity region NR2 to form a silicide film SL made of a nickel platinum silicide film. Therefore, the resistance can be reduced also in the high concentration impurity regions NR1D and NR1S and the high concentration impurity region NR2.

  Then, the unreacted nickel platinum film is removed from the semiconductor substrate 1S. In the first embodiment, the silicide film SL made of a nickel platinum silicide film is formed. For example, instead of the nickel platinum silicide film, a nickel silicide film, a titanium silicide film, a cobalt silicide film, Alternatively, the silicide film SL may be formed from a platinum silicide film or the like. As described above, for example, the high breakdown voltage MISFET Q1 and the low breakdown voltage MISFET Q2 can be formed on the semiconductor substrate 1S.

  Next, the wiring process will be described with reference to FIG. As shown in FIG. 3, a contact interlayer insulating film CIL is formed on the main surface of the semiconductor substrate 1S. The contact interlayer insulating film CIL is made of, for example, an ozone TEOS film formed by a thermal CVD method using ozone and TEOS (tetraethyl orthosilicate) as raw materials, and TEOS provided on the ozone TEOS film as raw materials. It is formed from a laminated film with a plasma TEOS film formed by the plasma CVD method used. Thereafter, the surface of the contact interlayer insulating film CIL is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, contact holes CNT are formed in the contact interlayer insulating film CIL by using a photolithography technique and an etching technique.

  Thereafter, a titanium / titanium nitride film is formed on the contact interlayer insulating film CIL including the bottom surface and inner wall of the contact hole CNT. The titanium / titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. This titanium / titanium nitride film has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later process, from diffusing into silicon.

  Then, a tungsten film is formed on the entire main surface of the semiconductor substrate 1S so as to fill the contact holes CNT. This tungsten film can be formed using, for example, a CVD method. Then, the plug PLG can be formed by removing unnecessary titanium / titanium nitride films and tungsten films formed on the contact interlayer insulating film CIL by, for example, CMP.

  Next, as shown in FIG. 3, an interlayer insulating film IL1 is formed on the contact interlayer insulating film CIL on which the plug PLG is formed. Then, a trench is formed in the interlayer insulating film IL1 by using a photolithography technique and an etching technique. Thereafter, a tantalum / tantalum nitride film is formed on the interlayer insulating film IL1 including the inside of the trench. This tantalum / tantalum nitride film can be formed by sputtering, for example. Subsequently, after a seed film made of a thin copper film is formed on the tantalum / tantalum nitride film by, for example, a sputtering method, an electrolytic plating method using this seed film as an electrode is formed on the interlayer insulating film IL1 in which the groove is formed. A copper film is formed. Thereafter, the copper film exposed on the interlayer insulating film IL1 other than the inside of the trench is removed by polishing, for example, by CMP, thereby leaving the copper film only in the trench formed in the interlayer insulating film IL1. . Thereby, the wiring L1 can be formed. Furthermore, although wiring is formed in the upper layer of wiring L1, description here is abbreviate | omitted. In this way, the semiconductor device according to the first embodiment can be finally manufactured.

  In the first embodiment, the example of forming the wiring L1 made of a copper film has been described. However, for example, the wiring L1 made of an aluminum film may be formed. In this case, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are sequentially formed on the contact interlayer insulating film CIL and the plug PLG. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique to form the wiring L1. Thereby, the wiring L1 made of an aluminum film can be formed.

(Embodiment 2)
In the second embodiment, an example in which the high breakdown voltage MISFET has an inclined portion inclined from the surface of the semiconductor substrate, and the inclined portion is formed from directly under the gate electrode to the drain region will be described.

  FIG. 17 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment. In FIG. 17, the semiconductor substrate 1S is divided into a region AR1 and a region AR2 by a plurality of element isolation regions STI formed on the front surface side (main surface side) of the semiconductor substrate 1S. A high breakdown voltage MISFET Q1 is formed in the region AR1, and a low breakdown voltage MISFET Q2 is formed in the region AR2. Here, the configuration of the low breakdown voltage MISFET Q2 formed in the region AR2 is the same as the configuration of the low breakdown voltage MISFET Q2 described in the first embodiment, and a description thereof will be omitted. Hereinafter, the configuration of the high breakdown voltage MISFET Q1 formed in the region AR1 will be described. A p-type well PWL1 is formed in the region AR1 of the semiconductor substrate 1S, and a high breakdown voltage MISFET Q1 is formed on the p-type well PWL1.

  Specifically, the high voltage MISFET Q1 has a gate insulating film GOX1 on the p-type well PWL1, and has a gate electrode G1 on the gate insulating film GOX1. At this time, the gate insulating film GOX1 is formed of, for example, a silicon oxide film, but is not limited thereto, and may be formed of, for example, a high dielectric constant film having a higher dielectric constant than a silicon oxide film such as a hafnium oxide film. Good. The gate electrode G1 is formed of, for example, a polysilicon film PF (n-type polysilicon film) into which phosphorus is introduced and a silicide film SL formed on the polysilicon film PF. The silicide film SL is a film formed for reducing the resistance of the gate electrode G1, and the silicide film SL is, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide. It is formed from a film or the like.

  Next, sidewalls SW are formed on the sidewalls on both sides of the gate electrode G1. The sidewall SW is formed from, for example, a silicon oxide film or a silicon nitride film. A channel region is formed near the surface of the semiconductor substrate 1S (p-type well PWL1) immediately below the gate electrode G1, and a source region and a drain region are formed so as to sandwich the channel region.

  The source region has a low concentration impurity region EX1S adjacent to the channel region and a high concentration impurity region NR1S formed in a region outside the low concentration impurity region EX1S. The low concentration impurity region EX1S and the high concentration impurity region NR1S are semiconductor regions in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S. In particular, the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1S is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1S.

  That is, the source region includes a low concentration impurity region EX1S formed at a position close to the gate electrode G1, and a high concentration impurity region NR1S formed at a position farther from the gate electrode G1 than the low concentration impurity region EX1S. The impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1S is smaller than the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1S, and the deepest portion of the low-concentration impurity region EX1S is It is shallower than the deepest portion of the high concentration impurity region NR1S.

  A silicide film SL for reducing the resistance of the source region is formed on the surface of the high concentration impurity region NR1S. The silicide film SL can be formed of, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide film.

  A halo region HAL1 (pocket region) is formed so as to surround the periphery of the low-concentration impurity region EX1S constituting a part of the source region. The halo region HAL1 is a semiconductor region in which a p-type impurity such as boron (B) is introduced into the semiconductor substrate 1S, and the impurity concentration of the halo region HAL1 is higher than the impurity concentration of the p-type well PWL1. As a result, when a drain voltage is applied to the drain region, the depletion layer extending from the drain region can be prevented from reaching the source region, thereby preventing punch-through.

  Next, the configuration of the drain region will be described. The second embodiment is characterized by the configuration of the drain region. As shown in FIG. 17, the surface of the drain region of high breakdown voltage MISFET Q1 in the second embodiment is inclined downward from the surface (main surface) of semiconductor substrate 1S in the direction away from gate electrode G1. Part SLP2. That is, the high voltage MISFET Q1 in the second embodiment is formed between the pair of element isolation regions STI in a cross-sectional view, and the surface of the inclined portion SLP2 faces the element isolation region STI close to the drain region side. Inclined to be continuously deeper. In the second embodiment, the inclined portion SLP2 extends to a region immediately below the gate electrode G1. That is, in plan view, one end portion of the inclined portion SLP2 exists in a region immediately below the gate electrode G1. In other words, the gate electrode G1 is formed so as to cover one end of the inclined portion SLP2 in plan view. Thereby, the gate length of the gate electrode G1 in a plan view can be shortened while ensuring the effective channel region length. That is, the channel region formed in the region immediately below the gate electrode G1 extends from the source region to the region immediately below the gate electrode G1, and further along the inclination of the inclined portion SLP2 formed from the central portion immediately below the gate electrode G1. It extends to the drain region. For this reason, the length of the channel region is longer than the gate length of the gate electrode G1 in plan view by the amount along the inclination of the inclined portion SLP2. That is, the effective length of the channel region is longer than the gate length of the gate electrode G1. As a result, according to the high voltage MISFET Q1 in the second embodiment, the gate length of the gate electrode G1 can be reduced while ensuring the effective length of the channel region. Therefore, according to the second embodiment, the high breakdown voltage MISFET Q1 can be reduced while suppressing deterioration of the short channel characteristics.

  Here, as shown in FIG. 17, the drain region described above is formed of a low concentration impurity region EX1D and a high concentration impurity region NR1D. At this time, the low concentration impurity region EX1D and the high concentration impurity region NR1D are semiconductor regions in which an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S. In particular, the impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1D is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1D. That is, as shown in FIG. 17, the drain region has a low concentration impurity region EX1D formed deep from the surface of the drain region, and a high concentration impurity region NR1D formed shallower than the low concentration impurity region EX1D from the surface of the drain region. Are included. In other words, the high concentration impurity region NR1D is formed so as to be included in the low concentration impurity region EX1D.

  A silicide film SL for reducing the resistance of the drain region is formed on the surface of the high concentration impurity region NR1D. The silicide film SL can be formed of, for example, a cobalt silicide film, a titanium silicide film, a nickel silicide film, a platinum silicide film, or a nickel platinum silicide film.

  Further, the second embodiment also includes (1) a configuration in which the low concentration impurity region EX1D is formed deeper than the high concentration impurity region NR1D, and (2) a configuration in which the halo region HAL1 is not formed on the drain region side. Therefore, in the second embodiment, similarly to the first embodiment, the electric field strength in the vicinity of the drain region in the high voltage MISFET Q1 in the second embodiment is obtained by the synergistic effect of the configurations (1) to (2). The increase can be suppressed.

  For this reason, according to the high breakdown voltage MISFET Q1 in the second embodiment, since the generation of hot carriers can be reduced, fluctuations in threshold voltage due to hot carriers can be suppressed, and the reliability of the semiconductor device can be improved. Can be planned. That is, according to the high withstand voltage MISFET Q1 in the second embodiment, even if miniaturization is advanced, an increase in electric field strength can be suppressed. Therefore, the high withstand voltage MISFET Q1 can be made fine without reducing the reliability of the semiconductor device. Can be promoted. That is, according to the second embodiment, the high breakdown voltage MISFET Q1 can be miniaturized, and the semiconductor device including the high breakdown voltage MISFET Q1 can be efficiently downsized.

  In the second embodiment, in the region sandwiched between the inclined portion SLP2 and the element isolation region STI close to the drain region side, the same type of polysilicon as the polysilicon film PF (conductor film) constituting the gate electrode G1 is used. The silicon film PF (conductor film) remains. Then, an insulating film of the same type as the sidewall SW is formed so as to cover the polysilicon film PF remaining in the region sandwiched between the inclined portion SLP2 and the element isolation region STI close to the drain region side. .

<Method for Manufacturing Semiconductor Device>
The semiconductor device according to the second embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, as shown in FIG. 18, a plurality of element isolation regions STI are formed on the surface side (main surface side) of the semiconductor substrate 1S. Thereby, the region AR1 which is a high breakdown voltage MISFET formation region and the region AR2 which is a low breakdown voltage MISFET formation region are partitioned by the element isolation region STI. Thereafter, an impurity is introduced into the active region (active region) of the region AR1 partitioned by the element isolation region STI to form the p-type well PWL1. Further, an impurity is introduced into the active region of the region AR2 to form the p-type well PWL2. The p-type well PWL1 and the p-type well PWL2 are formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by an ion implantation method. Subsequently, a semiconductor region (not shown) for forming a channel is formed in the surface region of the p-type wells PWL1 to PWL2. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

  Next, as shown in FIG. 19, a photosensitive resist film FR6 is applied on the semiconductor substrate 1S. Then, the resist film FR6 is patterned by subjecting the resist film FR6 to exposure / development processing. The patterning of the resist film FR6 is performed so as to open a minute region adjacent to the element isolation region STI on the drain formation region side in the region AR1 and cover the other regions AR1 and AR2. Thereafter, a minute region opened from the resist film FR6 is recessed by etching using the patterned resist film FR6 as a mask. Specifically, a hole pattern for opening the resist film FR6 is formed by a photolithography technique, and then a small groove DIT is formed in the opened minute region by a dry etching technique.

  Subsequently, as shown in FIG. 20, after the patterned resist film FR6 is removed, the surface of the semiconductor substrate 1S is anisotropically etched by performing anisotropic wet etching using the small groove DIT as a starting point. For anisotropic wet etching, a solution containing TMAH (tetramethylammonium hydroxide) as a main component is used, thereby exposing the crystal plane (111) of silicon constituting the semiconductor substrate 1S. As a result, the inclined portion SLP2 can be formed in the drain formation region of the region AR1.

  Thereafter, as shown in FIG. 21, a silicon oxide film is formed on the main surface of the semiconductor substrate 1S by using, for example, a thermal oxidation method. Specifically, the gate insulating film GOX1 made of a silicon oxide film is formed from the surface of the semiconductor substrate 1S in the region AR1 to the inclined portion SLP2, and the gate insulating film GOX2 made of a silicon oxide film is formed on the surface of the semiconductor substrate 1S in the region AR2. To do. At this time, the gate insulating film GOX1 is formed to have a thickness greater than that of the gate insulating film GOX2. In the second embodiment, the example in which the gate insulating film GOX1 and the gate insulating film GOX2 are formed from a silicon oxide film has been described. However, the present invention is not limited to this. For example, the dielectric is more dielectric than a silicon oxide film such as a hafnium oxide film. You may form from a high dielectric constant film | membrane with a high rate.

  Thereafter, a polysilicon film PF is formed on the semiconductor substrate 1S. As a result, a polysilicon film PF is formed on the gate insulating film GOX1 in the region AR1. On the other hand, in the region AR2, the polysilicon film PF is formed on the gate insulating film GOX2.

  Next, as shown in FIG. 22, by using the photolithography technique and the etching technique, the polysilicon film PF is patterned to form the gate electrode G1 in the region AR1 and the gate electrode G2 in the region AR2. . At this time, the gate length of the gate electrode G1 is formed to be longer than the gate length of the gate electrode G2. Here, a polysilicon film PF (conductor film) of the same type as the polysilicon film PF (conductor film) constituting the gate electrode G1 is sandwiched between the inclined portion SLP2 and the element isolation region STI close to the drain region side. ) Remains.

  Subsequently, as shown in FIG. 23, a photosensitive resist film FR7 is applied on the semiconductor substrate 1S. Then, the resist film FR7 is patterned by subjecting the resist film FR7 to exposure / development processing. The patterning of the resist film FR7 is performed so that the drain formation region of the high voltage MISFET formed in the region AR1 is exposed and the other region is covered. Then, the low concentration impurity region EX1D is formed inside the inclined portion SLP2 which is the inside of the surface for forming the drain region by ion implantation using the patterned resist film FR7 as a mask. Specifically, the low concentration impurity region EX1D is performed by one vertical ion implantation, a plurality of oblique ion implantations, or an appropriate combination thereof. As a result, the low concentration impurity region EX1D having an impurity concentration distribution parallel to the inclined portion SLP2 etched obliquely can be formed. Here, when there is a step in the boundary region between the element isolation region STI and the inclined portion SLP2, since shadowing occurs, the low concentration impurity region EX1D parallel to the inclined portion SLP2 can be obtained by appropriately combining a plurality of ion implantations. Form.

  Next, as shown in FIG. 24, after removing the patterned resist film FR7, a photosensitive resist film FR8 is applied on the semiconductor substrate 1S. Then, the resist film FR8 is patterned by subjecting the resist film FR8 to exposure / development processing. The patterning of the resist film FR8 is performed so as to expose the source formation region of the high breakdown voltage MISFET formed in the region AR1 and cover the other regions. Then, the halo region HAL1 and the low-concentration impurity region EX1S are formed inside the surface for forming the source region in alignment with the gate electrode G1 by ion implantation using the patterned resist film FR8 as a mask. Specifically, first, for example, a halo region HAL1 is formed by introducing a p-type impurity such as boron (B) into the semiconductor substrate 1S by an oblique ion implantation method. The impurity concentration of the p-type impurity introduced into the halo region HAL1 is higher than the impurity concentration of the p-type impurity introduced into the p-type well PWL1. Thereafter, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by the vertical ion implantation method, thereby forming the low concentration impurity region EX1S. The low concentration impurity region EX1S is formed so as to be included in the halo region HAL1. As a result, the halo region HAL1 is formed so as to surround the periphery of the low concentration impurity region EX1S.

  Then, as shown in FIG. 25, after removing the patterned resist film FR8, a photosensitive resist film FR9 is applied on the semiconductor substrate 1S. Then, the resist film FR9 is patterned by subjecting the resist film FR9 to exposure / development processing. The patterning of the resist film FR9 is performed so as to cover the region AR1 and expose the region AR2. Then, by ion implantation using the patterned resist film FR9 as a mask, the halo region HAL2 and the low concentration impurity region EX2 are formed inside the source region forming surface and the drain region forming surface in alignment with the gate electrode G2. To do. Specifically, first, for example, a halo region HAL2 is formed by introducing a p-type impurity such as boron (B) into the semiconductor substrate 1S by an ion implantation method. The impurity concentration of the p-type impurity introduced into the halo region HAL2 is higher than the impurity concentration of the p-type impurity introduced into the p-type well PWL2. Thereafter, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by an ion implantation method, thereby forming the low concentration impurity region EX2. The low concentration impurity region EX2 is formed so as to be included in the halo region HAL2. As a result, the halo region HAL2 is formed so as to surround the periphery of the low concentration impurity region EX2.

  Subsequently, after removing the patterned resist film FR9, an insulating film made of, for example, a silicon oxide film is formed on the entire main surface of the semiconductor substrate 1S. Thereafter, as shown in FIG. 26, the insulating film is anisotropically etched to form side walls SW made of an insulating film on the side walls on both sides of the gate electrode G1 and the side walls on both sides of the gate electrode G2. In the second embodiment, the sidewall SW is formed of a single layer film of a silicon oxide film. However, the present invention is not limited to this, and for example, the sidewall SW formed of a laminated film of a silicon nitride film and a silicon oxide film is formed. It may be formed. At this time, an insulating film of the same type as the sidewall SW is formed so as to cover the polysilicon film PF remaining in the region sandwiched between the inclined portion SLP2 and the element isolation region STI close to the drain region side. . As a result, the conductive polysilicon film PF formed on the side wall of the element isolation region STI close to the drain region side is covered with the same type of insulating film (sidewall SW) as the sidewall SW. It is possible to prevent the occurrence of short circuit failure and leakage current due to the polysilicon film PF.

  Next, as shown in FIG. 27, a photosensitive resist film FR10 is applied on the semiconductor substrate 1S. Then, the resist film FR10 is patterned by performing exposure / development processing on the resist film FR10. The patterning of the resist film FR10 is performed so that the drain formation region of the high voltage MISFET formed in the region AR1 is exposed and the other region is covered. Then, a high concentration impurity region NR1D is formed inside the surface for forming the drain region by ion implantation using the patterned resist film FR10 as a mask. Specifically, the high concentration impurity region NR1D having an impurity concentration distribution parallel to the inclined portion SLP2 as much as possible by one vertical ion implantation, a plurality of oblique ion implantations, or an appropriate combination thereof. Form. Thereby, in the second embodiment, the drain region of the high breakdown voltage MISFET is formed by the low concentration impurity region EX1D and the high concentration impurity region NR1D. At this time, in the drain region formed so as to be parallel to the inclined portion SLP2, the low concentration impurity region EX1D is formed in a region deeper than the high concentration impurity region NR1D.

  Then, as shown in FIG. 28, after removing the patterned resist film FR10, a photosensitive resist film FR11 is applied on the semiconductor substrate 1S. Then, the resist film FR11 is patterned by subjecting the resist film FR11 to exposure / development processing. The patterning of the resist film FR11 is performed so as to expose the source formation region of the high breakdown voltage MISFET formed in the region AR1 and cover the other regions. Then, a high concentration impurity region NR1S is formed inside the surface for forming the source region in alignment with the sidewall SW by a vertical ion implantation method using the patterned resist film FR11 as a mask. Specifically, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by the vertical ion implantation method, thereby forming the high concentration impurity region NR1S. The high concentration impurity region NR1S is formed outside the low concentration impurity region EX1S. The impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR1S is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX1S. The deepest portion of the high concentration impurity region NR1S is formed to be deeper than the deepest portion of the low concentration impurity region EX1S. Thereby, the source region of the high breakdown voltage MISFET composed of the low concentration impurity region EX1S and the high concentration impurity region NR1S can be formed.

  Subsequently, as shown in FIG. 29, after removing the patterned resist film FR11, a photosensitive resist film FR12 is applied on the semiconductor substrate 1S. Then, the resist film FR12 is patterned by subjecting the resist film FR12 to exposure / development processing. The patterning of the resist film FR12 is performed so as to cover the region AR1 and expose the region AR2. Then, by ion implantation using the patterned resist film FR12 as a mask, the high concentration impurity region NR2 is formed inside the source region forming surface and the drain region forming surface in alignment with the sidewall SW. Specifically, for example, an n-type impurity such as phosphorus (P) or arsenic (As) is introduced into the semiconductor substrate 1S by an ion implantation method, thereby forming the high concentration impurity region NR2. The high concentration impurity region NR2 is formed outside the low concentration impurity region EX2. The impurity concentration of the n-type impurity introduced into the high-concentration impurity region NR2 is higher than the impurity concentration of the n-type impurity introduced into the low-concentration impurity region EX2. Note that the deepest portion of the high concentration impurity region NR2 is formed deeper than the deepest portion of the low concentration impurity region EX2. Thereby, the source region and the drain region of the low breakdown voltage MISFET composed of the low concentration impurity region EX2 and the high concentration impurity region NR2 can be formed. The order of the step of forming the high concentration impurity region NR1D shown in FIG. 27, the step of forming the high concentration impurity region NR1S shown in FIG. 28, and the step of forming the high concentration impurity region NR2 shown in FIG. The order is not limited to the order shown in Embodiment 2, and may be performed in other orders.

  Next, as shown in FIG. 30, after removing the patterned resist film FR12, for example, a nickel platinum film (not shown) is formed on the semiconductor substrate 1S. At this time, the nickel platinum film is formed so as to be in direct contact with the upper surfaces of the gate electrodes G1 to G2. Similarly, the nickel platinum film is in direct contact with the surfaces of the high concentration impurity regions NR1D and NR1S and the surface of the high concentration impurity region NR2.

  The nickel platinum film can be formed using, for example, a sputtering method. Then, after the nickel platinum film is formed, heat treatment is performed to react the polysilicon film PF constituting the gate electrodes G1 to G2 with the nickel platinum film, thereby forming a silicide film SL made of a nickel platinum silicide film. Thereby, the gate electrodes G1 to G2 have a laminated structure of the polysilicon film PF and the silicide film SL. The silicide film SL is formed to reduce the resistance of the gate electrodes G1 to G2. Similarly, by the heat treatment described above, silicon and a nickel platinum film react with each other on the surfaces of the high concentration impurity regions NR1D and NR1S and the surface of the high concentration impurity region NR2 to form a silicide film SL made of a nickel platinum silicide film. Therefore, the resistance can be reduced also in the high concentration impurity regions NR1D and NR1S and the high concentration impurity region NR2.

  Then, the unreacted nickel platinum film is removed from the semiconductor substrate 1S. In the second embodiment, the silicide film SL made of a nickel platinum silicide film is formed. For example, instead of the nickel platinum silicide film, a nickel silicide film, a titanium silicide film, a cobalt silicide film, Alternatively, the silicide film SL may be formed from a platinum silicide film or the like. As described above, for example, the high breakdown voltage MISFET Q1 and the low breakdown voltage MISFET Q2 can be formed on the semiconductor substrate 1S. Thereafter, through the wiring process described in the first embodiment, the semiconductor device in the second embodiment can be finally manufactured.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1 CPU
1S semiconductor substrate 2 RAM
3 Analog circuit 4 EEPROM
5 Flash memory 6 I / O circuit AR1 region AR2 region CHP semiconductor chip CIL contact interlayer insulating film CNT contact hole DIT trench EX1D low concentration impurity region EX1S low concentration impurity region EX2 low concentration impurity region FR1 resist film FR2 resist film FR3 resist film FR4 Resist film FR5 Resist film FR6 Resist film FR7 Resist film FR8 Resist film FR9 Resist film FR10 Resist film FR11 Resist film FR12 Resist film G1 Gate electrode G2 Gate electrode GOX1 Gate insulating film GOX2 Gate insulating film HAL1 Halo region HAL1 Halo region HAL1 Halo region HAL1 Halo region HAL1 L1 wiring NR1D high concentration impurity region NR1S high concentration impurity region NR2 high concentration impurity region PF polysilicon film PLG plastic PWL1 p-type well PWL2 p-type well Q1 high breakdown voltage MISFET
Q2 Low voltage MISFET
SL Silicide film SLP Inclined portion SLP2 Inclined portion STI Element isolation region SW Side wall

Claims (28)

A first MISFET is provided on the semiconductor substrate,
The first MISFET is
(A) a first gate insulating film formed on the semiconductor substrate;
(B) a first gate electrode formed on the first gate insulating film;
(C) a first source region formed in the semiconductor substrate;
(D) a first drain region formed in the semiconductor substrate;
The surface of the first drain region is inclined downward from the surface of the semiconductor substrate below the first gate electrode in a direction away from the first gate electrode.
The inclination angle between the surface of the first drain region and the surface of the semiconductor substrate under the first gate electrode is between the surface of the first source region and the surface of the semiconductor substrate under the first gate electrode. A semiconductor device characterized by being larger than the inclination angle between them. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a surface of the first source region is flush with a surface of the semiconductor substrate under the first gate electrode. The semiconductor device according to claim 2,
The first MISFET is formed between a pair of element isolation regions in a cross-sectional view,
The semiconductor device is characterized in that the surface of the first drain region is inclined so as to be continuously deeper toward the element isolation region close to the first drain region side. The semiconductor device according to claim 1,
The first drain region is
(D1) a first low-concentration impurity region formed deep from the surface of the first drain region;
(D2) a first high concentration impurity region formed shallower than the first low concentration impurity region from the surface of the first drain region,
A semiconductor device, wherein a concentration of impurities introduced into the first low concentration impurity region is lower than a concentration of impurities introduced into the first high concentration impurity region. The semiconductor device according to claim 4,
The first source region is
(C1) a second low-concentration impurity region formed at a position close to the first gate electrode;
(C2) a second high concentration impurity region formed at a position farther from the first gate electrode than the second low concentration impurity region,
The concentration of the impurity introduced into the second low concentration impurity region is smaller than the concentration of the impurity introduced into the second high concentration impurity region,
The deepest portion of the second low concentration impurity region is shallower than the deepest portion of the second high concentration impurity region. The semiconductor device according to claim 1,
The semiconductor device further includes a second MISFET,
The semiconductor device according to claim 1, wherein the first MISFET is a higher voltage MISFET than the second MISFET. The semiconductor device according to claim 6,
The second MISFET is
(E) a second gate insulating film formed on the semiconductor substrate and having a thickness smaller than that of the first gate insulating film;
(F) a second gate electrode formed on the second gate insulating film, wherein the second gate electrode has a gate length shorter than that of the first gate electrode;
(G) a second source region formed in the semiconductor substrate;
(H) a semiconductor device comprising a second drain region formed in the semiconductor substrate. The semiconductor device according to claim 7,
The inclination angle between the surface of the first drain region and the surface of the semiconductor substrate under the first gate electrode is between the surface of the second drain region and the surface of the semiconductor substrate under the second gate electrode. A semiconductor device characterized by being larger than the inclination angle between them. The semiconductor device according to claim 8,
A semiconductor device, wherein a surface of the second drain region and a surface of the semiconductor substrate under the second gate electrode are flush with each other. The semiconductor device according to claim 7,
The surface of the second source region and the surface of the second drain region are flush with each other. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first MISFET is an n-channel MISFET. The semiconductor device according to claim 1,
A semiconductor device, wherein a halo region having a conductivity type opposite to that of the first source region is formed in the semiconductor substrate in contact with the first source region. The semiconductor device according to claim 1,
Having an inclined portion inclined from the surface of the semiconductor substrate;
The inclined portion is formed from directly under the first gate electrode to the first drain region. The semiconductor device according to claim 13,
In plan view, one end portion of the inclined portion exists in a region immediately below the first gate electrode. The semiconductor device according to claim 13,
The semiconductor device, wherein the first gate electrode is formed so as to cover one end of the inclined portion in plan view. The semiconductor device according to claim 13,
The first MISFET is formed between a pair of element isolation regions in a cross-sectional view,
The surface of the inclined portion is inclined so as to be continuously deeper toward the element isolation region close to the first drain region side. The semiconductor device according to claim 16,
A semiconductor device characterized in that a conductive film of the same type as the first gate electrode remains in a region sandwiched between the inclined portion and the element isolation region close to the first drain region side. The semiconductor device according to claim 17,
A sidewall made of an insulating film is formed on the sidewall of the first gate electrode,
An insulating film of the same type as the sidewall is formed so as to cover the conductor film remaining in a region sandwiched between the inclined portion and the element isolation region close to the first drain region side. A semiconductor device. (A) preparing a semiconductor substrate;
(B) after the step (a), forming a gate insulating film on the semiconductor substrate;
(C) after the step (b), a step of forming a first conductor film on the gate insulating film;
(D) after the step (c), patterning the first conductor film to form a gate electrode;
(E) after the step (d), forming a sidewall on the side wall of the gate electrode;
(F) After the step (e), by performing anisotropic etching on the drain region forming surface of the surface of the semiconductor substrate, a step of forming an inclined portion on the drain region forming surface;
(G) after the step (f), forming a drain region inside the inclined portion;
(H) forming a source region inside the surface for forming a source region of the surface of the semiconductor substrate, and a method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 19,
The drain region includes a low concentration impurity region for a drain region, and a high concentration impurity region for a drain region having a larger impurity concentration than the low concentration impurity region for the drain region,
The step (g)
(G1) forming the drain region low-concentration impurity region inside the inclined portion;
(G2) after the step (g1), forming a high concentration impurity region for the drain region inside the inclined portion,
The step (g2) is characterized in that the high concentration impurity region for the drain region is formed so that the high concentration impurity region for the drain region is disposed above the low concentration impurity region for the drain region. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 20,
The step (g1) and the step (g2) include a step of introducing impurities into the inclined portion from a direction inclined obliquely to the surface of the semiconductor substrate under the gate electrode. A method of manufacturing a semiconductor device, comprising forming a low concentration impurity region for a drain region and the high concentration impurity region for a drain region. A method of manufacturing a semiconductor device according to claim 19,
(I) A method for manufacturing a semiconductor device, comprising the step of forming a halo region having a conductivity type opposite to that of the source region in a region deeper than the source region before the step (h). A method of manufacturing a semiconductor device including a first MISFET and a second MISFET having a lower withstand voltage than the first MISFET,
(A) forming a first gate insulating film in a first MISFET forming region of a semiconductor substrate and forming a second gate insulating film having a thickness smaller than that of the first gate insulating film in a second MISFET forming region;
(B) after the step (a), forming a first conductor film on the first gate insulating film and the second gate insulating film;
(C) After the step (b), by patterning the first conductor film, a first gate electrode is formed on the first gate insulating film, and the first gate is formed on the second gate insulating film. Forming a second gate electrode having a gate length smaller than the gate length of the electrode;
(D) After the step (c), in the second MISFET forming region, a second source region low concentration impurity region is formed inside the second source region forming surface, and inside the second drain region forming surface. Forming a low concentration impurity region for the second drain region;
(E) after the step (d), forming a sidewall on each of the sidewall of the first gate electrode and the sidewall of the second gate electrode;
(F) After the step (e), anisotropic etching is performed on the first drain region forming surface of the surface of the semiconductor substrate in the first MISFET forming region, thereby forming the first drain region. Forming a slope on the surface;
(G) after the step (f), forming a first drain region inside the inclined portion;
(H) After the step (e), in the first MISFET formation region, a step of forming a first source region inside the surface for forming the first source region of the surface of the semiconductor substrate;
(I) After the step (e), in the second MISFET formation region, in the second source region formation surface, the second source region has a higher impurity concentration than the second source region low concentration impurity region. Forming a high concentration impurity region, and forming a high concentration impurity region for the second drain region having an impurity concentration larger than that of the low concentration impurity region for the second drain region inside the surface for forming the second drain region; A method for manufacturing a semiconductor device, comprising: (A) preparing a semiconductor substrate;
(B) After the step (a), by performing anisotropic etching on the drain region forming surface of the surface of the semiconductor substrate, a step of forming an inclined portion on the drain region forming surface;
(C) after the step (b), forming a gate insulating film on the semiconductor substrate;
(D) after the step (c), forming a first conductor film on the gate insulating film;
(E) after the step (d), by patterning the first conductor film, in a plan view, forming a gate electrode that covers one end of the inclined portion;
(F) After the step (e), forming a low concentration impurity region for the drain region inside the inclined portion exposed from the gate electrode;
(G) after the step (e), forming a source region low concentration impurity region inside the source region forming surface;
(H) After the step (f) and the step (g), forming a sidewall on the side wall of the gate electrode;
(I) After the step (h), forming a high concentration impurity region for a drain region having an impurity concentration larger than that of the low concentration impurity region for the drain region inside the inclined portion exposed from the sidewall;
(J) after the step (h), forming a source region high concentration impurity region having an impurity concentration higher than that of the source region low concentration impurity region inside the source region formation surface. A method of manufacturing a semiconductor device. 25. A method of manufacturing a semiconductor device according to claim 24, comprising:
The step (i) forms the drain region high concentration impurity region so that the drain region high concentration impurity region is included in the drain region low concentration impurity region,
In the step (j), the source region high concentration impurity region is formed so that the deepest portion of the source region high concentration impurity region is deeper than the deepest portion of the source region low concentration impurity region. A method of manufacturing a semiconductor device. 25. A method of manufacturing a semiconductor device according to claim 24, comprising:
The step (f) and the step (i) include a step of introducing impurities into the inclined portion from a direction inclined obliquely with respect to the thickness direction of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising forming a low concentration impurity region and a high concentration impurity region for the drain region. 25. A method of manufacturing a semiconductor device according to claim 24, comprising:
(K) Before the step (g), a step of forming a halo region having a conductivity type opposite to that of the source region low concentration impurity region in a region deeper than the source region low concentration impurity region is provided. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device including a first MISFET and a second MISFET having a lower withstand voltage than the first MISFET,
(A) forming an inclined portion on the drain region forming surface by anisotropically etching the drain region forming surface of the surface of the semiconductor substrate in the first MISFET forming region of the semiconductor substrate; ,
(B) After the step (a), a first gate insulating film is formed in the first MISFET forming region of the semiconductor substrate, and a second gate insulating film having a thickness smaller than that of the first gate insulating film is formed in the second MISFET forming region. Forming a film;
(C) after the step (b), forming a first conductor film on the first gate insulating film and the second gate insulating film;
(D) After the step (c), by patterning the first conductor film, a first gate electrode is formed on the first gate insulating film so as to cover one end of the inclined portion in plan view. Forming a second gate electrode having a gate length smaller than the gate length of the first gate electrode on the second gate insulating film;
(E) after the step (d), in the first MISFET formation region, forming a low-concentration impurity region for the first drain region inside the inclined portion exposed from the first gate electrode;
(F) After the step (d), forming a first source region low-concentration impurity region inside the first source region formation surface in the first MISFET formation region;
(G) After the step (d), in the second MISFET formation region, a second source region low concentration impurity region is formed inside the second source region formation surface, and the inside of the second drain region formation surface. Forming a low concentration impurity region for the second drain region;
(H) After the step (e), the step (f), and the step (g), a sidewall is formed on each of the sidewall of the first gate electrode and the sidewall of the second gate electrode. Process,
(I) After the step (h), in the first MISFET formation region, a step of forming a high concentration impurity region for the first drain region inside the inclined portion exposed from the sidewall;
(J) After the step (h), in the first MISFET formation region, a step of forming a first source region high-concentration impurity region inside the first source region formation surface of the surface of the semiconductor substrate; ,
(K) After the step (h), in the second MISFET formation region, in the second source region formation surface, the second source region has a higher impurity concentration than the second source region low concentration impurity region. Forming a high concentration impurity region, and forming a high concentration impurity region for the second drain region having an impurity concentration larger than that of the low concentration impurity region for the second drain region inside the surface for forming the second drain region; A method for manufacturing a semiconductor device, comprising:

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