JP2013030913A - Photoelectric converter, focus detector, and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric converter capable of obtaining excellent output linearity, a stable driving current, and/or uniform sensitivity.SOLUTION: A photoelectric converter comprises: a sensor cell section (100) for outputting a signal, photoelectrically converted by a photoelectric conversion element, to a common output line by a first normal-rotation amplifier in a normal-rotation manner; a memory cell section (101) for storing the signal inputted from the common output line in a first memory capacity, and outputting the signal stored in the first memory capacity to the common output line by a second normal-rotation amplifier in a normal-rotation manner; a transfer section (113) for outputting the signal on the common output line by an amplifier in a normal-rotation or reverse-rotation manner; a transfer switch (121) arranged between an input terminal of the transfer section and the common output line; and a feedback switch (120) arranged between an output terminal of the transfer section and the common output line.

Description

  The present invention relates to a photoelectric conversion device, a focus detection device, and an imaging system.

  An imaging system generally includes a focus detection (AF) sensor that detects a focus. Recent AF sensors are required not only to increase the number of distance measuring points but also to increase the accuracy and speed of focus detection. As means for increasing the number of distance measuring points, an area type is adopted in which a plurality of linear sensors constituting the distance measuring points are arranged in parallel and connected in the column direction with a common wiring. As a circuit configuration of an area type AF sensor, Patent Document 1 describes a solid-state imaging device including a transfer system that transfers a signal output from a sensor cell unit to a memory cell unit. In order to improve the AF ranging accuracy by increasing the SN ratio of the sensor signal, it is necessary to remove sensor reset noise and fixed pattern noise. In Patent Document 1, the sensor cell unit and the memory cell unit have a signal inversion output function to remove fixed pattern noise of the sensor cell unit and the memory cell unit itself.

Japanese Patent Laid-Open No. 9-200614

  However, if the sensor cell unit and the memory cell unit have a signal inversion output function as in Patent Document 1, a trade-off between signal input / output linearity and circuit area occurs. For example, a switched capacitor often used as an inverting output circuit is composed of a differential circuit and a feedback capacitor, so that the circuit scale becomes very large. In addition, when a common source inverting amplifier is used as in Patent Document 1, the following three problems are raised. First, the linearity of the output signal deteriorates due to the semiconductor substrate bias effect. Secondly, since the driving current of the inverting amplifier varies depending on the amplitude of the input signal, the current consumption increases when the circuit response is increased. Third, since the gain of the inverting amplifier varies due to the relative variation of the transistors, the nonuniformity of the output voltage is deteriorated.

  An object of the present invention is to provide a photoelectric conversion device, a focus detection device, and an imaging system that can obtain good output linearity, stable drive current, and / or good sensitivity uniformity.

  The photoelectric conversion device according to the present invention includes a sensor cell unit that outputs a signal photoelectrically converted by a photoelectric conversion element to a common output line by a first normal amplifier, and a signal input from the common output line to a first memory. A first memory cell unit which holds the signal held in the capacitor and outputs the signal held in the first memory capacitor to the common output line by the second normal amplifier, and the signal of the common output line is positive by the amplifier. A transfer unit that rotates or inverts and outputs to the common output line, a transfer switch provided between the input terminal of the transfer unit and the common output line, and provided between the output terminal of the transfer unit and the common output line The sensor cell unit outputs a normal output of the first normal amplifier to the common output line via a first switch, and the first memory cell unit includes a first switch. of The signal of the common output line is input to the first memory capacity via the memory cell unit write switch, and the normal output of the second normal amplifier is output to the common output line via the second switch. It is characterized by doing.

  By using a normal amplifier for the sensor cell portion and the first memory cell portion, good output linearity, stable driving current, and / or good sensitivity uniformity can be obtained.

It is a schematic diagram of the imaging surface of the photoelectric conversion apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram of a line sensor part concerning a 1st embodiment of the present invention. 1 is a circuit diagram of a photoelectric conversion apparatus according to a first embodiment of the present invention. FIG. 3 is a timing chart according to the first embodiment of the present invention. 1 is a first layout diagram of a photoelectric conversion apparatus according to a first embodiment of the present invention. It is a 2nd layout figure of the photoelectric conversion apparatus which concerns on the 1st Embodiment of this invention. It is a circuit diagram of the photoelectric conversion apparatus which concerns on the 2nd Embodiment of this invention. FIG. 6 is a timing diagram according to the second embodiment of the present invention. It is a block diagram of the focus detection apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram of the imaging system which concerns on the 4th Embodiment of this invention.

(First embodiment)
The first embodiment of the present invention shows an example applied to a photoelectric conversion device for phase difference focus detection (AF: Auto Focusing). FIG. 1 is a diagram schematically illustrating an imaging surface in a photoelectric conversion device for phase difference AF. On the imaging surface, there are paired line sensor portions L1A and L1B, L2A and L2B,... LNA and LNB. A pair of line sensor units are used to measure the defocus amount of the subject in an area on the imaging surface. By arranging a plurality of pairs of the line sensor units, a plurality of distance measuring points are provided to improve AF accuracy. It is intended. A configuration in which the arrangement interval of the pixel openings in the line sensor unit is narrowed and arranged in a two-dimensional array is called an area type AF sensor. Each line sensor unit L1A, L2A,..., LNA has a plurality of unit pixels 11A, 12A,..., And each line sensor unit L1B, L2B,. 12B, etc.

  FIG. 2 is a block diagram showing in more detail the portions related to the line sensor portions L1A, L2A,. The line sensor unit L1A includes unit pixels 11A, 12A,. The line sensor unit L2A includes unit pixels 21A, 22A,. The unit pixels 11A, 12A, 21A, 22A, etc. each have a sensor cell unit 100, a first memory cell unit 101, and a second memory cell unit 102. The sensor cell unit 100, the first memory cell unit 101, and the second memory cell unit 102 are connected to the transfer unit 113 via the common output line 112. Unit pixels 11A and 21A existing at the same column position of different line sensor units L1A and L2A are connected to a common transfer unit 113 via a common output line 112. Similarly, the unit pixels 12A and 22A existing at the same column position in different line sensor units L1A and L2A are connected to the common transfer unit 113 via the common output line 112. Each transfer unit 113 is connected to a common buffer amplifier 123. The line sensor portions L1B, L2B,... Have the same configuration as that in FIG.

  FIG. 3 shows a part of the configuration shown in FIG. 2, and will be described by focusing on the unit pixel 11A and the transfer unit 113 connected thereto. The unit pixel 11 </ b> A includes a sensor cell unit 100, a first memory cell unit 101, and a second memory cell unit 102. In FIG. 3, “φ” attached to the control electrode and the switch of the MOS transistor means a signal supplied from a control unit (not shown).

  Focusing on the unit pixel 11A, the sensor cell unit 100 includes a photodiode (PD) 103 which is a photoelectric conversion element, a sensor cell unit writing switch 106, and transistors M11 and M12. The anode of the photodiode 103 is connected to one terminal of the sensor cell unit write switch 106 and the control electrode of the transistor M11, and the cathode is connected to the power supply voltage node. Since the transistor M11 is self-biased, when the MOS transistor M12 is turned on, it forms a self-bias source follower having a gain of 1, that is, a normal amplifier, together with the load MOS transistor M13. The sensor cell unit 100 outputs an accumulation signal based on the amount of charge photoelectrically converted by the photodiode 103 to the common output line 112 via the source follower. That is, the MOS transistor M12 functions as a selection switch for selecting the sensor cell unit 100. The sensor cell unit writing switch 106 switches between conduction and non-conduction between the anode of the photodiode 103 and the common output line 112, and can be constituted by a PMOS transistor, an NMOS transistor, a CMOS transistor, or the like. The memory cell units 101 and 102 have a configuration in which the photodiode 103 in the sensor cell unit 100 is replaced with memory capacitors 104 and 105. In the first memory cell unit 101, the transistors M31 and M32 and the switch 107 correspond to the transistors M11 and M12 and the switch 106 of the sensor cell unit 100, respectively. In the second memory cell unit 102, the transistors M41 and M42 and the switch 108 correspond to the transistors M11 and M12 and the switch 106 of the sensor cell unit 100, respectively. The sensor cell unit 100 outputs the signal photoelectrically converted by the photoelectric conversion element 103 to the common output line 112 by the first normal amplifier M11. The first memory cell unit 101 holds the signal input from the common output line 112 in the first memory capacitor 104, and the signal held in the first memory capacitor 104 is output by the second normal amplifier M31 to the common output line. The normal output is output to 112. The second memory cell unit 105 holds the signal input from the common output line 112 in the second memory capacitor 105, and the signal held in the second memory capacitor 105 is shared by the third normal amplifier M41. The normal output is output to 112. The sensor cell unit 100 outputs the normal output of the first normal amplifier M11 to the common output line 112 via the first switch M12. The first memory cell unit 101 inputs the signal of the common output line 112 to the first memory capacitor 104 via the first memory cell unit write switch 107 and the second positive electrode via the second switch M32. The normal output of the rotation amplifier M31 is output to the common output line 112. The second memory cell unit 102 inputs the signal of the common output line 112 to the second memory capacitor 105 via the second memory cell unit write switch 108, and outputs the third positive electrode via the third switch M42. The normal output of the rotation amplifier M41 is output to the common output line 112.

  Next, the transfer unit 113 will be described. The transfer unit 113 includes MOS transistors M21 and M23, a transfer capacitor 117, and a constant current source 124. The MOS transistor M21 and the constant current source 124 form a source follower. The common output line 112 is connected to the transfer switch 121 and the feedback switch 120. The other terminal of the transfer switch 121 is connected to one terminal A of the transfer capacitor 117, one main electrode of the MOS transistor M22, and one main electrode of the MOS transistor M24. The other main electrode of the MOS transistor M22 is connected to the node of the reference voltage VRS. The other main electrode of the MOS transistor M24, which is an optical signal readout switch, is connected to the buffer amplifier 123. The other terminal B of the transfer capacitor 117 is connected to the control electrode of the MOS transistor M21 and one main electrode of the MOS transistor M23. One main electrode of the MOS transistor M21 is connected to the node of the power supply voltage VDD, and the other main electrode is connected to the constant current source 124, the other terminal of the feedback switch 120, and the monitor unit 130 disposed outside the sensor array. The The transfer unit 113 performs (1) a process for inverting the output of the sensor cell unit 100, and (2) a signal output from the sensor cell unit 100, reset noise written in the memory cell units 101 and 102, and a transfer unit by operations described later. Difference processing with noise generated in 113 is performed. The transfer unit 113 performs normal rotation or inversion on the signal of the common output line 112 by the amplifier M21 and outputs the signal to the common output line 112. The transfer switch 121 is provided between the input terminal of the transfer unit 113 and the common output line 112. The feedback switch 120 is provided between the output terminal of the transfer unit 113 and the common output line 112.

  FIG. 4 shows signals applied to the switches and the control electrodes of the MOS transistors shown in FIG. Hereinafter, the operation of the photoelectric conversion apparatus according to the present embodiment will be described with reference to FIGS. 3 and 4. Each switch and the MOS transistor conduct when the signal shown in FIG. 4 is at a high level. Signal φL is set to a gate potential at which load MOS transistor M13 drives a constant current when it is at a high level.

  In FIG. 4, in a period T1, an operation of resetting the photodiode 103 and the memory capacitors 104 and 105 is performed. Thereafter, an operation of writing the fixed pattern noise Ns of the source follower of the sensor cell unit 100 into the transfer capacitor 117 is performed. Specifically, in the period T1, first, the signals φRS, φFT, φPS1, φPS2_1, φPS2_2, and φGR are at a high level. As a result, the sensor cell unit write switch 106, the memory cell unit write switches 107 and 108, the transfer switch 121, the MOS transistor M22, and the MOS transistor M23 are turned on. The MOS transistor M22 is a reset unit for resetting the input terminal A of the transfer unit 113 to the reference voltage VRS. As a result, the photodiode 103 and the memory capacitors 104 and 105 are reset to the reference voltage VRS, and the terminal A of the transfer capacitor 117 is reset to the reference voltage VRS and the terminal B to the clamp voltage VGR. Here, the potential of the clamp voltage VGR is set to VGR = VRS + Vth obtained by adding the threshold Vth of the self-bias source follower of the sensor cell unit 100, the memory cell units 101 and 102 or the transfer unit 113 to the reference potential VRS.

  Next, after the signals φPS1, φPS2_1, φPS2_2, and φRS become low level, the signals φSL1 and φL become high level. Then, VRS−Vth + Ns obtained by adding the threshold Vth of the source follower of the sensor cell unit 100 and the fixed pattern noise Ns of the sensor cell unit 100 to the reset potential VRS is written to the terminal A of the transfer capacitor 117. Then, when the signal φGR becomes low level, the terminal B of the transfer capacitor 117 becomes floating. Further, since the signal φFT becomes low level after the signal φRS becomes high level, the terminal A of the transfer capacitor 117 changes to the reference voltage VRS, so that the potential of the terminal B becomes VGR + Vth−Ns = VRS + 2 × Vth−Ns. become. As described above, the transfer unit 113 is clamped by the output of the sensor cell unit 100 by the high level of the signals φSL1 and φFT, and after being released by the low level of the signal φGR, the reference voltage VRS is input by the high level of the signal φRS. To do.

  In the period T2, when the signal φFB becomes high level, the voltage VRS + Vth−Ns + Nt in which the threshold value Vth of the source follower of the transfer unit 113 and the noise Nt are superimposed on the voltage VRS + 2 × Vth−Ns held at the terminal B of the transfer capacitor 117 is It is output to the common output line 112. During this period, the signal φPS1 temporarily becomes a high level, so that the voltage VRS + Vth−Ns + Nt is written in the sensor cell unit 100. The accumulation operation period of the sensor cell unit 100 starts from the timing when the signal φPS1 becomes low level. That is, the transfer unit 113 outputs the fixed pattern noise Ns of the sensor cell unit 100 and the noise Nt caused by the transfer unit 113 to the sensor cell unit 100 according to the high levels of the signals φPS1 and φFB.

  In the period T3, when the signal φRS is at a high level and the signal φGR is at a high level, the reference potential VRS is applied to the terminal A of the transfer capacitor 117, and the clamp voltage VGR (= VRS + Vth) is applied to the other terminal B. When the signal φGR becomes low level, the terminal B of the transfer capacitor 117 becomes floating. The transfer unit 113 is clamped at the reference voltage VRS by the high level of the signal φRS, and is then released by the low level of the signal φGR.

  In the period T4, when the signals φSL1, φL, and φFT become high level, the threshold voltage Vth of the source follower of the memory cell units 101 and 102 and the fixed pattern noise Ns are added to the voltage VRS + Vth−Ns + Nt held in the sensor cell unit 100. Is output. That is, the output of the sensor cell unit 100 is the voltage VRS + Vth−Ns + Nt−Vth + Ns = VRS + Nt. At this time, the noise Ns of the sensor cell unit 100 is canceled. Since the potential of the terminal A of the transfer capacitor 117 becomes VRS + Nt and fluctuates by the transfer unit noise Nt, the potential of the terminal B becomes VRS + Vth + Nt. When the signal φFB becomes high level after the signal φFT becomes low level, the voltage VRS + 2 × Nt is output from the source follower of the transfer unit 113. Although not explicitly shown in the equation, in addition to the noise 2 × Nt, random noise (hereinafter referred to as reset noise) generated by initializing the sensor cell unit 100 in the period T1 is also superimposed. After releasing the clamp, the transfer unit 113 inputs the output of the sensor cell unit 100 according to the high level of the signals φSL1 and φFT, and resets the noise of the sensor cell unit 100 according to the high level of the signals φPS2_1 and φFB to the first memory cell. Output to the unit 101. The first memory cell unit 101 holds reset noise of the sensor cell unit 100.

  Further, in the period T4, since the signals φPS2_1 and φPS2_2 are both at the high level, the voltage VRS + 2 × Nt is simultaneously written into the memory cell portions 101 and 102 via the switches 107 and 108. Here, simultaneous means that the voltage VRS + 2 × Nt is written to both the memory cell portions 101 and 102 by the signals φPS2_1 and φPS2_2 in the period T4 in which the signal φFB is at a high level. It is not always necessary for the signals φPS2_1 and φPS2_2 to simultaneously transition to the low level.

  In the period T5, since the signals φSL1, φL, and φFT are at a high level, the source follower of the sensor cell unit 100 operates and a level corresponding to the signal S1 photoelectrically converted by the sensor cell unit 100 appears on the common output line 112. Since the voltage VRS + Vth−Ns + Nt is written in the sensor cell unit 100 by the operation up to the period T5, the signal output from the sensor cell unit 100 and input to the terminal A of the transfer capacitor 117 becomes the voltage VRS + Nt + S1. Further, since the signal φGR is set to the high level, the terminal B is reset to the clamp voltage VGR (= VRS + Vth). Thereafter, the signals φFT and φGR become low level, and the terminals A and B of the transfer capacitor 117 are floated. As described above, the transfer unit 113 is clamped by the output of the sensor cell unit 100 by the high level of the signals φSL1 and φFT, and then is released by the low level of the signal φGR.

  An auto gain control (AGC) operation is started from the period T6. During this period, the signal φRS is at a high level and the terminal A of the transfer capacitor 117 is fixed to the reference voltage VRS, so that the potential of the terminal B of the transfer capacitor 117 is VRS + Vth−Nt−S1. Since the voltage VRS-S1 to which the source follower threshold voltage Vth of the transfer unit 113 and the fixed pattern noise Nt are added is input to the monitor unit 130, the monitor unit 130 monitors only the optical signal S1 that is not affected by noise. Can do. The output of the sensor cell unit 100 in the period T6 is observed by the monitor unit 130 in real time. The monitor unit 130 includes a variable gain amplifying unit, and the gain is varied in accordance with a contrast detection result to be described later. This is called auto gain control (AGC). By periodically repeating the period T5 and the period T6, the monitor 130 can monitor the charge accumulation state of the photodiode 103 in real time. As a result of the monitoring operation by the monitor unit 130, an optical signal output from the sensor cell unit 100 at the time when the charge accumulation operation in the period T6 is finished is S2. As described above, the transfer unit 113 inputs the reference voltage VRS according to the high level of the signal φRS after releasing the clamp, and outputs the output voltage of the sensor cell unit 100 to the external monitor unit 130.

  In the period T7, when the signals φSL2_1, φL, φGR, and φFT are at a high level, the noise Nm1 of the first memory cell unit 101 is added to the noise 2Nt held in the first memory cell unit 101. Then, the voltage VRS−Vth + 2Nt + Nm1 is applied to the terminal A of the transfer capacitor 117, and the potential of the terminal B becomes the clamp voltage VGR (= VRS + Vth). Thereafter, when the signal φGR becomes low level, the terminal B of the transfer capacitor 117 becomes floating. As described above, the transfer unit 113 is clamped at the output of the first memory cell unit 101 by the high level of the signals φSL2_1 and φFT, and then is released by the low level of the signal φGR.

  In the period T8, when the signals φFT, φSL1, and φL are at a high level, the voltage VRS + S2 + Nt is input to the terminal A of the transfer capacitor 117, and the voltage VRS + 2Vth + S2-Nt−Nm appears at the terminal B of the transfer capacitor 117. As described above, the transfer unit 113 inputs the output of the sensor cell unit 100 according to the high levels of the signals φSL1 and φFT after releasing the clamp.

  In the period T9, the signal φFT is at a low level. When the signal φPS2_1 becomes high level while the signal φFB is high level, the threshold value Vth and noise Nt of the transfer unit 113 are added from the transfer unit 113, and the voltage VRS + Vth + S2-Nm1 is applied to the first memory cell unit 101. As described above, the transfer unit 113 removes the reset noise held in the first memory cell unit 101 from the output voltage of the sensor cell unit 100 by the high level of the signals φPS2_1 and φFB. Output to the unit 101.

  In the period T10, the signal φFB is at a low level and the signal φFT is at a high level. During this period, the signals φL and φSL2_1 become high level, and thus the voltage VRS + Vth + S2-Nm1 held in the first memory cell portion 101 is output. Further, the threshold value Vth and noise Nm1 of the first memory cell portion 101 are added, and the voltage VRS + S2 is applied to the terminal A of the transfer capacitor 117. That is, as a result, a signal in which the influence of noise is reduced is output. During this period, when a signal φH is supplied from a shift register (not shown), the signal S2 is transmitted to the buffer amplifier 123 and output to a signal processing circuit at a subsequent stage (not shown).

  In the operations in the periods T11 to T14, the operations in the periods T7 to T10 are performed on the second memory cell portion 102. Thereby, signals based on different charge accumulation times can be acquired from the sensor cell unit 100 in one charge accumulation sequence. As a result, since a plurality of distance measuring points can be provided on the same line in one charge accumulation sequence, multiple points of distance measuring points or high-speed focus detection operation can be realized.

  As described above, the following two points are characteristic of this embodiment. First, the outputs of the sensor cell unit 100 and the memory cell units 101 and 102 are changed from the inverted output of Patent Document 1 to the normal output of the self-biased source follower. Second, even if the sensor cell unit 100 and the memory cell units 101 and 102 are normal outputs, the transfer unit 113 can remove fixed pattern noise generated in the sensor cell unit 100, the memory cell units 101 and 102, and the transfer unit 113. Is to perform a clamping operation.

  The inverting amplifier used in Patent Document 1 is difficult to achieve both layout saving and output characteristics. That is, when a switched capacitor composed of a differential amplifier and a feedback capacitor is used, the layout area increases. The AF sensor uses an optical system to limit the pixel aperture position on the sensor due to the arrangement of the distance measurement points on the viewfinder. Therefore, if the layout of the inverting amplifier is increased, the distance measurement points cannot be densely arranged and the AF characteristics deteriorate. become. Further, the common-source inverting amplifier used in Patent Document 1 can be mounted in a smaller area than a switched capacitor. However, the linearity of the output of the common source inverting amplifier is deteriorated due to the substrate bias effect. In addition, since the drive current changes greatly according to the input of the inverting amplifier, it is difficult to achieve both the power saving of the sensor and the circuit response. Further, there is a characteristic that the output gain is changed due to the relative variation of the transistors of the inverting amplifier and the sensitivity non-uniformity (PRNU) is easily deteriorated.

  On the other hand, by using the normal output of the self-biased source follower as in this embodiment, good linearity, stable drive current, and relative variation are non-uniform in sensitivity (PRNU) with respect to the common-source inverting amplifier. The advantage that it is difficult to affect As a result, high accuracy and high speed can be realized even if the auto focus distance measuring points are increased by the area type AF sensor. In the present embodiment, an example in which two memory cell units are provided has been described, but the number of memory cell units may be one or three or more. In the case of three or more, an operation corresponding to the operation in the periods T7 to T10 is also performed on the added memory cell unit.

  A layout example of the photoelectric conversion device illustrated in FIG. 3 is illustrated in FIGS. In FIG. 5, the sensor cell unit 100, the first memory cell unit 101, and the second memory cell unit 102 are set as one set 132, and the set 132 is arranged in a matrix. The transfer unit 113 and the shift register 131 are provided in common for the plurality of sensor cell units 100 and the memory cell units 101 and 102 provided in each column.

  FIG. 6 is a diagram in the case where the layout is divided into an area in which only the sensor cell unit 100 is arranged and an area in which only the memory cell units 101 and 102 are arranged. Also in this layout, the transfer unit 113 and the shift register 131 are provided in common for the plurality of sensor cell units 100 and the memory cell units 101 and 102 provided in each column.

(Second Embodiment)
Hereinafter, the operation of the photoelectric conversion apparatus according to the second embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 is a circuit diagram of a photoelectric conversion apparatus according to the second embodiment of the present invention, and FIG. 8 is a timing chart according to the second embodiment of the present invention. In FIG. 7, the description of the common parts with FIG. 3 is omitted. The output amplifiers of the sensor cell unit 100 and the memory cell units 101 and 102 of FIG. 7 use source follower transistors M11, M31, and M41 that are not self-biased, and the gain is Gsf. The transfer unit 113 includes a differential amplifier 126, a feedback capacitor 125, and a transfer capacitor 117. The transfer capacitor 117 and the feedback capacitor 125 constitute a feedback system. The gain of the feedback system is the reciprocal 1 / Gsf of the aforementioned source follower gain Gsf. In the present embodiment, the normal input terminal of the differential amplifier 126 is connected to the node of the reference voltage VRS. Hereinafter, Vth is a threshold voltage of a source follower that is not self-biased in the sensor cell unit 100 and the memory cell units 101 and 102.

  In the period T1, an operation for resetting the photodiode 103 and the memory capacitors 104 and 105 is performed. Thereafter, an operation of writing the fixed pattern noise Ns of the output amplifier of the sensor cell unit 100 into the transfer capacitor 117 is performed. Specifically, first, the signals φRS, φFT, φPS1, φPS2_1, φPS2_2, and φGR become high level. As a result, the sensor cell unit write switch 106, the memory cell unit write switches 107 and 108, the transfer switch 121, the MOS transistor M22, and the switch 133 become conductive. As a result, the photodiode 103 and the memory capacitors 104 and 105 are reset to the reference voltage VRS, and both electrodes of the transfer capacitor 117 are reset to a potential obtained by adding the output offset noise Nt of the differential amplifier 126 to the reference voltage VRS. . Both electrodes of the feedback capacitor 125 are reset by the voltage VRS + Nt. As described above, the transfer unit 113 is clamped at the reference voltage VRS by the high level of the signal φRS.

  Next, when the signal φGR becomes low level, the terminal B of the transfer capacitor 117 becomes floating. Then, after the signals φPS1, φPS2_1, φPS2_2, and φRS become low level, the signals φSL1 and φL become high level. Then, the potential VRS−Vth + Ns to which the gain of the source follower, the threshold value Vth, and the fixed pattern noise Ns are applied from the sensor cell unit 100 is written to the terminal A of the transfer capacitor 117. As described above, the transfer unit 113 releases the clamp by the low level of the signal φGR and then inputs the output of the sensor cell unit 100 by the high level of the signals φSL1 and φFT.

  In the period T2, when the signal φFB becomes high level, the gain −1 / Gsf of the transfer unit 113 is applied to the variation −Vth + Ns of the terminal B of the transfer capacitor 117. Further, since the noise Nt of the transfer unit 113 is superimposed, the voltage VRS + (Vth−Ns) / Gsf + Nt is output to the common output line 112. During this period, the signal φPS1 temporarily becomes a high level, whereby the voltage VRS + (Vth−Ns) / Gsf + Nt is written in the sensor cell unit 100. The charge accumulation operation period of the sensor cell unit 100 starts from the timing when the signal φPS1 becomes low level. As described above, the transfer unit 113 generates the noise obtained by adding the gain of the sensor cell unit 100 to the fixed pattern noise Ns of the sensor cell unit 100 due to the high levels of the signals φPS1 and φFB, and the noise Nt caused by the transfer unit 113. Output to the sensor cell unit 100.

  In the period T3, when the signals φSL1 and φL become high level, the gain Gsf is applied to the voltage VRS + (Vth−Ns) / Gsf + Nt held in the sensor cell unit 100, and then the fixed pattern noise Ns is added and output. That is, the output of the sensor cell unit 100 is the voltage VRS + Gsf × Nt. At this time, the noise Ns of the sensor cell unit 100 is canceled. At this time, when the signals φGR and φFT are at a high level, the above-described voltage is applied to the terminal A of the transfer capacitor 117 and the voltage VRS + Nt is applied to the terminal B. Thereafter, when the signal φGR becomes a low level, the terminal B of the transfer capacitor 117 is in a floating state. As described above, the transfer unit 113 is clamped by the output of the sensor cell unit 100 by the high level of the signals φSL1 and φFT, and then is released by the low level of the signal φGR.

  In the period T4, when the signal φRS becomes high level, the terminal A of the transfer capacitor 117 becomes the reference voltage VRS. At this time, since the signal φFB is at a high level, the voltage VRS + 2 × Nt is output from the output terminal of the transfer unit 113. Although not explicitly shown in the equation, in addition to the noise 2 × Nt, random noise (hereinafter referred to as reset noise) generated by initializing the sensor cell unit 100 in the period T1 is also superimposed.

  Further, in the period T4, since the signals φPS2_1 and φPS2_2 are both at the high level, the voltage VRS + 2 × Nt is simultaneously written into the memory cell portions 101 and 102 via the switches 107 and 108. Here, simultaneous means that the signals φPS2_1 and φPS2_2 are written to both the memory cell portions 101 and 102 during the period T4 when both the signals φRS and φFB are at a high level. It is not always necessary for the signals φPS2_1 and φPS2_2 to simultaneously transition to the low level. As described above, the transfer unit 113 inputs the reference voltage VRS according to the high level of the signal φRS after releasing the above clamp, and resets the reset noise of the sensor cell unit 100 according to the high level of the signals φPS2_1 and φFB to the first memory. Output to the cell unit 101. The first memory cell unit 101 holds reset noise of the sensor cell unit 100.

  In the period T5, the signal φFT is at a high level. When the signals φRS and φGR become high level during the period T5, the common output line 112 and the terminal A of the transfer capacitor 117 become the reference voltage VRS, and the terminal B becomes the voltage VRS + Nt. Thereafter, by setting the signals φRS and φGR to the low level, the terminal B of the transfer capacitor 117 becomes floating. As described above, the transfer unit 113 is clamped at the reference voltage VRS by the high level of the signal φRS, and the clamp is released by the low level of the signal φGR.

  The AGC operation is started from the period T6. During this period, since the signals φSL1 and φL are at a high level, the source follower of the sensor cell unit 100 operates and a level corresponding to the signal S1 photoelectrically converted by the sensor cell unit 100 appears on the common output line 112. In the operation up to the period T5, the voltage VRS + (Vth−Ns) / Gsf + Nt is written in the sensor cell unit 100, so that the signal output from the sensor cell unit 100 is the voltage VRS + Gsf × (Nt + S1). As a result, the terminal B of the transfer capacitor 117 fluctuates by the potential Gsf × (Nt + S1), so that the output of the transfer unit 113 becomes the voltage VRS−S1. That is, the monitor unit 130 can monitor only the optical signal -S1 that is not affected by noise. Thus, the output change of the sensor cell unit 100 in the period T6 is observed by the monitor unit 130 in real time. The monitor unit 130 includes a variable gain amplifying unit, and the gain is varied in accordance with a contrast detection result to be described later. This is called auto gain control (AGC). As a result of the monitoring operation by the monitor unit 130, the optical signal output from the sensor cell unit 101 at the time when the charge accumulation operation in the period T6 is completed is set to −S2. As described above, the transfer unit 113 inputs the output of the sensor cell unit 100 according to the high levels of the signals φSL1 and φFT after releasing the clamp, and outputs the output voltage of the sensor cell unit 100 to the monitor unit 130.

  In the period T7, the signals φFT, φSL1, φL, and φGR are at a high level, so that the terminal A of the transfer capacitor 117 becomes the voltage VRS + Gsf × (Nt + S2) and the terminal B becomes the voltage VRS + Nt. That is, the transfer unit 113 is clamped by the output of the sensor cell unit 100 by the high level of the signals φSL1 and φFT, and is released by the low level of the signal φGR.

  In the period T8, the signals φSL2_1 and φL are at a high level. Then, the noise Nm1 of the first memory cell unit 101 is added to the voltage VRS + 2 × Nt held in the first memory cell unit 101, and the voltage VRS + Gsf × 2 × Nt−Vth + Nm1 is given to the terminal A of the transfer capacitor 117. It is done. That is, the terminal B of the transfer capacitor 117 varies by the potential Gsf × (Nt−S2) −Vth + Nm1. As described above, the transfer unit 113 inputs the output of the first memory cell unit 101 in accordance with the high levels of the signals φSL2_1 and φFT after releasing the clamp.

  In the period T9, the signal φFT is at a low level. When the signal φPS2_1 becomes high level while the signal φFB is high level, the voltage VRS + (Vth−Nm1) × 1 / Gsf + S2 is supplied from the transfer unit 113 to the first memory cell portion 101. That is, the transfer unit 113 supplies the first memory cell unit 101 with a voltage obtained by removing the reset noise held in the first memory cell unit 101 from the output voltage of the sensor cell unit 100 by the high level of the signals φPS2_1 and φFB. Output.

  In the period T10, the signal φFB becomes low level, the signal φFT becomes high level, and the signals φL and φSL2_1 become high level during this period. As a result, the gain Vs + and the noise Nm1 of the first memory cell unit 101 are added to the voltage VRS + (Vth−Nm1) × 1 / Gsf + S2 held in the first memory cell unit 101, and the voltage VRS + Gsf × S2 becomes the transfer capacity. 117 is provided to terminal A. That is, as a result, a signal from which the influence of noise is removed is output. During this period, when a signal φH is supplied from a shift register (not shown), the signal S2 × Gsf is transmitted to the buffer amplifier 123 and output to a signal processing circuit at a subsequent stage (not shown).

  In the operations in the periods T11 to T14, the operations in the periods T7 to T10 are performed on the second memory cell portion 102. Thereby, signals based on different charge accumulation times can be acquired from the sensor cell unit 100 in one charge accumulation sequence. As a result, since a plurality of distance measuring points can be provided on the same line in one charge accumulation sequence, multiple points of distance measuring points or high-speed focus detection operation can be realized.

  As described above, the present embodiment is characterized by the following three points with respect to the first embodiment. First, the outputs of the sensor cell unit 100 and the memory cell units 101 and 102 are changed from the self-bias source follower of the first embodiment to a source follower that is not self-biased. Second, the transfer unit 113 includes a switched capacitor amplifier configured by a feedback system of a differential amplifier 126 and a feedback capacitor 125. Third, the clamp timing of the transfer capacitor 117 is changed.

  In this embodiment, by using a source follower that is not self-biased, the area occupied by the source follower in the sensor cell unit 100 and the memory cell units 101 and 102 can be reduced. At that time, since the output of the source follower is reduced by the gain Gsf (usually <× 1), the transfer unit 113 having a relatively large area is provided with an inverting amplifier of gain−1 / Gsf. Furthermore, the drive timing is changed so that each fixed pattern noise of the sensor cell unit 100, the memory cell units 101 and 102, and the transfer unit 113 can be removed. Further, by applying a sufficient gain with the buffer amplifier 123 of FIG. 7, it is possible to prevent a decrease in the S / N ratio due to circuit noise in the subsequent stage. In the present embodiment, by adopting such a configuration and a driving method, the pixel opening area of the sensor cell unit 100 can be increased as compared with the first embodiment, so that the sensitivity of the sensor can be improved. In addition, since the memory capacities 104 and 105 of the memory cell units 101 and 102 can be increased, switch noise can be reduced and an SN ratio can be improved.

(Third embodiment)
A focus detection apparatus according to a third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration example of the third embodiment in which the photoelectric conversion device according to the first or second embodiment is applied to a phase difference detection type focus detection device (hereinafter referred to as an AF sensor). is there. The AF sensor 811 includes a sensor block 820, a logic block 801 having a function of generating a timing signal of the external interface and the AF sensor, and an analog circuit block 810. In the sensor block 820, line sensor portions L1A, L2A,... And L1B, L2B,. The analog circuit block 810 includes AGC circuits 802 to 805, and performs monitoring of signals from the line sensor unit and control of charge accumulation time. A plurality of line sensor units correspond to one of the AGC circuits 802 to 805. In this embodiment, four AGC circuits 802 to 805 are mounted, but the number of AGC circuits can be optimized from the viewpoint of circuit scale and charge accumulation processing speed. The analog circuit block 810 further includes a reference voltage / current generation circuit 806 that generates a reference voltage and a reference current used in the photoelectric conversion device, a thermometer circuit 807, and the like. Reference numerals 813 and 814 denote external communication terminals. The logic block 801 controls the driving timing of the AF sensor 811 through serial communication with the outside via the serial communication terminal 812. The signal of the line sensor unit is gain-applied by an AF gain circuit 808 and taken out from an analog signal output terminal 815 through an output multiplexer 809. Also in this embodiment, by using the photoelectric conversion device described in the first or second embodiment, a high-speed and high-precision focus detection operation can be realized.

(Fourth embodiment)
FIG. 10 is a block diagram illustrating a configuration example of an imaging system (camera) according to the fourth embodiment of the present invention. Reference numeral 901 denotes a barrier that protects the lens 902, reference numeral 902 denotes a lens that forms an optical image of a subject on the solid-state imaging device 904, and reference numeral 903 denotes an aperture for adjusting the amount of light that has passed through the lens 902. Reference numeral 904 denotes a solid-state imaging device that acquires an optical image of a subject formed by the lens 902 as an image signal. Reference numeral 905 denotes an AF sensor (focus detection apparatus) of the third embodiment using the photoelectric conversion apparatus described in each of the above-described embodiments. Reference numeral 906 denotes an analog signal processing device that processes signals output from the solid-state imaging device 904 and the AF sensor 905, and reference numeral 907 denotes an A / D converter that performs analog-digital conversion on the signals output from the signal processing device 906. A digital signal processing unit 908 performs various corrections on the image data output from the A / D converter 907 and compresses the data. Reference numeral 909 denotes a memory unit for temporarily storing image data, 910 denotes an external I / F circuit for communicating with an external computer, and 911 denotes a timing generation unit that outputs various timing signals to the digital signal processing unit 908 and the like. Reference numeral 912 denotes an overall control / arithmetic unit for controlling various calculations and the entire camera, 913 denotes a recording medium control I / F unit, 914 denotes a removable recording medium such as a semiconductor memory for recording or reading the acquired image data. , 915 are external computers.

  Next, the operation at the time of shooting of the above imaging system will be described. Based on the signal output from the AF sensor 905 when the barrier 901 is opened, the overall control / calculation unit 912 calculates the distance to the subject by detecting the phase difference. Thereafter, the overall control / arithmetic unit 912 drives the lens 902 based on the calculation result, determines whether or not it is in focus again, and determines that the lens 902 is not in focus. Perform focus control. Next, after the in-focus state is confirmed, the charge accumulation operation by the solid-state imaging device 904 starts. When the charge accumulation operation of the solid-state imaging device 904 is completed, the image signal output from the solid-state imaging device 904 is analog-digital converted by the A / D converter 907, passes through the digital signal processing unit 908, and is controlled by the overall control / calculation unit 912. It is written in the memory unit 909. Thereafter, the data stored in the memory unit 909 is recorded on the recording medium 914 via the recording medium control I / F unit 910 under the control of the overall control / arithmetic unit 912. The data stored in the memory unit 909 is directly output to the computer 915 or the like through the external I / F unit 910.

  In the first to fourth embodiments, normal amplifiers M11, M31, and M41 are used for the sensor cell unit 100 and the memory cell units 101 and 102, respectively. As a result, it is possible to obtain good output linearity, stable drive current, small gain variation, small circuit scale, and / or good sensitivity uniformity.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100 Sensor cell part, 101 1st memory cell part, 102 2nd memory cell part, 103 Photoelectric conversion element, 104 1st memory capacity, 105 2nd memory capacity, 107 1st memory cell part write switch, 108 Second memory cell unit write switch, 112 common output line, 113 transfer unit, 120 feedback switch, 121 transfer switch

Claims (13)

A sensor cell unit that outputs the signal photoelectrically converted by the photoelectric conversion element to the common output line by the first normal amplifier;
A first memory cell that holds a signal input from the common output line in a first memory capacity, and outputs a signal held in the first memory capacity to the common output line by a second normal amplifier. And
A transfer unit that forwards or inverts the signal of the common output line by an amplifier and outputs the signal to the common output line;
A transfer switch provided between an input terminal of the transfer unit and the common output line;
A feedback switch provided between the output terminal of the transfer unit and the common output line;
The sensor cell unit outputs a normal output of the first normal amplifier to the common output line via a first switch,
The first memory cell unit inputs a signal of the common output line to the first memory capacity via a first memory cell unit write switch, and the second positive cell via the second switch. A photoelectric conversion device that outputs a normal rotation output of a rotation amplifier to the common output line.   The photoelectric conversion device according to claim 1, further comprising a reset unit configured to reset an input terminal of the transfer unit to a reference voltage.   The transfer unit is clamped by an output of the sensor cell unit, and after releasing the clamp, inputs the reference voltage and outputs a fixed pattern noise of the sensor cell unit to the sensor cell unit. The photoelectric conversion device described.   The transfer unit is clamped at the reference voltage, releases the clamp, inputs the output of the sensor cell unit, and outputs reset noise of the sensor cell unit to the first memory cell unit. The photoelectric conversion device according to claim 2.   The transfer unit is clamped by an output of the sensor cell unit, and after releasing the clamp, inputs the reference voltage and outputs an output voltage of the sensor cell unit to a monitor unit. The photoelectric conversion apparatus of any one of these.   The transfer unit is clamped by the output of the first memory cell unit, and after releasing the clamp, inputs the output of the sensor cell unit and holds the output from the output voltage of the sensor cell unit in the first memory cell unit The photoelectric conversion device according to claim 1, wherein the voltage from which the reset noise that has been removed is removed is output to the first memory cell unit.   The photoelectric conversion apparatus according to claim 2, wherein the transfer unit includes a differential amplifier.   The transfer unit is clamped by the reference voltage, and after releasing the clamp, inputs the output of the sensor cell unit and outputs fixed pattern noise of the sensor cell unit to the sensor cell unit. The photoelectric conversion device described.   The transfer unit is clamped by the output of the sensor cell unit, and after releasing the clamp, inputs the reference voltage and outputs reset noise of the sensor cell unit to the first memory cell unit. The photoelectric conversion device according to claim 7 or 8.   The transfer unit is clamped by the reference voltage, and after releasing the clamp, inputs the output of the sensor cell unit and outputs the output voltage of the sensor cell unit to the monitor unit. The photoelectric conversion apparatus of any one of these.   The transfer unit is clamped by the output of the sensor cell unit, and after releasing the clamp, inputs the output of the first memory cell unit and holds the output from the output voltage of the sensor cell unit in the first memory cell unit The photoelectric conversion device according to claim 7, wherein a voltage from which the reset noise that has been removed is removed is output to the first memory cell unit.   A focus detection apparatus comprising the photoelectric conversion apparatus according to claim 1.   An imaging system comprising the focus detection device according to claim 12.

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