JP2013030730A5 - - Google Patents

Description

Alternatively, as shown in FIG. 3B and FIG. 4B , the protective film 16 may be provided with a recess 160 as a notch region. Specifically, the cutout region (recessed portion 160) is formed along the Y-axis direction, and the organic semiconductor layer 14 and the source / drain electrodes 15A and 15B are overlapped in the cutout region (FIG. 4 (B) and FIG. 5 ( refer to reference sign P12 in the cross-sectional view taken along line III-III in FIG. 3 (B) ). However, the above-described misalignment absorbing region 150 of the source / drain electrodes 15A and 15B is arranged so as not to overlap the recess 160. Even when such a concave portion 160 is provided, although details will be described later, disconnection (step disconnection) of the wiring layers 17A and 17B near the end portion (edge portion of the semiconductor island) of the organic semiconductor layer 14 is less likely to occur. (Preferably, the occurrence of such disconnection is avoided).

First, as shown in FIG. 6A, the gate electrode 12 and the gate wiring 12L are formed on the substrate 11 ( not shown ), and the gate insulating film 13 (not shown) is formed on the gate electrode 12 and the gate wiring 12L. To do.

Next, as shown in FIG. 6D, the protective film 16 made of the above-described material is formed on the organic semiconductor layer 14 and the source / drain electrodes 15A and 15B. Specifically, for example, by applying a fluororesin such as (C ₆ F ₁₀ ) _n over the entire surface, a general photoresist is applied on the film, and a desired pattern is formed using a photolithography technique. Then, the protective film 16 is formed. At the time of pattern formation using this photolithography technique, the fluororesin film is dry-etched using, for example, oxygen plasma. This dry etching is performed until the above-described misalignment absorbing region 150 is exposed in the source / drain electrodes 15A and 15B. Then, after the etching process, the photoresist is removed. Note that pattern formation by a photolithography technique using a photosensitive fluororesin is also possible. Here, the pattern formation using the photolithography technique has been described as an example, but the present invention is not limited to this. Furthermore, it is also possible to directly form the protective film 16 using a printing method such as a reverse offset printing method.

The thin film transistor 1C of the present embodiment has basically the same configuration as the thin film transistor 1. However, in the thin film transistor 1 C, as described in detail below, the source-drain electrodes 15A, 15B and the wiring layers 17A, both of 17B, are formed by a vacuum deposition process and a photolithography technique (Vacuum deposition Film formation).

Then, as shown in FIG. 18 (B), the wiring layer 170 is formed on the entire surface by, for example, a sputtering method or the like. Thereafter, as shown in FIG. 18C, the resist film 8 is pattern printed in the shape of the wiring layers 17A and 17B. Subsequently, the wiring layer 170 is wet-etched using, for example, a mixed acid of nitric acid, hydrofluoric acid, and phosphoric acid, and then the resist film 8 is dissolved and removed, so that the wiring layer 17A as shown in FIG. , 17B are formed.

Next, as shown by a symbol P4 in FIG. 19B, ink made of the constituent materials of the source / drain electrodes 15A and 15B is dropped into the bank 19 using a printing process (here, an inkjet method). Then fill. Thus, for example, as shown in FIG. 19 (C), by spreading wet ink which is dropped into the bank 19, the source-drain electrodes 15A, 15B are formed in a self-aligned manner by using the bank 19. At this time, here, each end (one end) of the source / drain electrodes 15A, 15B protrudes (protrudes) from the bank 19 through the opening 190 toward the wiring portions 17A, 17B. Such protrusions (protruding portions) function as electrical connection portions (contact portions) between the source / drain electrodes 15A and 15B and the wiring portions 17A and 17B.

In the thin film transistor 1E, the source / drain electrodes 15A and 15B are filled with the constituent material (ink) of the source / drain electrodes 15A and 15B in a predetermined shape (bank 19 or 19A). It is formed by. In the thin film transistor 1E, the organic semiconductor layer 14 is formed on the source / drain electrodes 15A and 15B after the removal of the bank. That is, unlike the thin film transistor 1D , in the thin film transistor 1E, the bank is finally removed so that it does not remain. However, the source and drain electrodes 15A using such a bank, not limited to the case of forming the 15B, the source-drain electrode 15A without a bank, may be formed to 15B.

In this display device 2 , a substrate 11, a TFT layer 22, a display layer 23, and a transparent substrate 24 are laminated in this order. Specifically, the TFT layer 22, the display layer 23, and the transparent substrate 24 are stacked on the display region 20 </ b> A in the substrate 11, while these TFTs are formed on the frame region (non-display region) 20 </ b> B in the substrate 11. The layer 22, the display layer 23, and the transparent substrate 24 are not laminated.

In the above-described embodiment and the like, in the above-described embodiment and the like, a thin film transistor (organic TFT) including an organic semiconductor layer, a gate electrode, a pair of source / drain electrodes, and a wiring layer is provided as an example of the semiconductor element of the present disclosure. Although it has been described, it is not limited to this. That is, for example, organic semiconductor layer, even for other semiconductor devices such as a pair of electrodes (an anode electrode and a cathode electrode) and wiring layers comprising a diode (rectifying device), can be applied to the technology is there.

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