JP2013026424A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology of simply repairing the phase defect of a mask for EUV photolithography.SOLUTION: When a phase defect is detected in the phase defect inspection process of a mask blank used for manufacturing a mask for EUV lithography, a determination is made as to whether the phase defect is a concave defect or a convex defect. A part of the mask for EUV lithography including the phase defect is exposed by being locally defocused, depending on a concave or convex state of the phase defect, thus suppressing abnormal transfer of a circuit pattern to a semiconductor wafer without correcting the phase defect of the mask for EUV lithography.

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to the manufacture of a semiconductor device having an optical lithography process using extreme ultraviolet (Extreme Ultra-Violet: hereinafter referred to as EUV) as an exposure light source. is there.

  Semiconductor devices such as LSI and IC irradiate a mask, which is an original on which a circuit pattern is drawn, with exposure light, and the circuit pattern is placed on a semiconductor substrate (hereinafter referred to as a “wafer”) via a reduction optical system. It is mass-produced by repeatedly using a photolithographic process for transferring.

  In recent years, the miniaturization of semiconductor devices has progressed, and methods for increasing the resolution by shortening the exposure wavelength of photolithography have been studied. That is, until now, ArF lithography using an argon fluoride (ArF) excimer laser beam having a wavelength of 193 nm as a light source has been developed, but recently, EUV light having a much shorter wavelength (wavelength = 13.5 nm). Development of lithography using) is underway.

  In the wavelength range of the EUV light, a conventional transmission mask for optical lithography cannot be used due to the light absorption of the substance. Therefore, as a mask blank for EUV lithography, for example, a multilayer film reflective substrate using reflection by a multilayer film in which Mo (molybdenum) films and Si (silicon) films are alternately stacked is used. This multilayer film reflection is a reflection utilizing a kind of interference.

  A mask for EUV lithography is composed of a multilayer film blank in which the above multilayer film is deposited on a substrate made of quartz glass or low thermal expansion glass, and an absorber pattern formed on the multilayer film blank. . In EUV lithography, since the exposure wavelength is as short as 13.5 nm, even if a slight height abnormality of about a fraction of the exposure wavelength occurs on the mask surface, the reflectance is caused by the height abnormality. This causes a local difference and causes defects during transfer. Thus, since EUV optical lithography masks have a large qualitative difference with respect to defect transfer when compared with conventional transmission masks for optical lithography, transfer of phase defects has become a large practical problem.

  As a representative example of the above-described phase defect inspection method, a laser inspection method for irradiating a mask blank from an oblique direction and detecting foreign matter from the irregularly reflected light, and the same wavelength as that used for mask pattern exposure The same wavelength (at wavelength or actinic) defect inspection method for detecting defects using EUV light is known. Of these, the latter having the high phase defect inspection sensitivity is the latter, and this at-wavelength defect inspection method is considered indispensable in the phase defect inspection corresponding to the fine pattern of half pitch 22 nm or later.

  In addition, the same wavelength defect inspection method includes a method using a dark field image (for example, see Patent Documents 1 and 5), an X-ray microscope method using a bright field (for example, see Patent Document 2), and detecting a defect using a dark field. In addition, there is a dark field bright field combination method (for example, see Patent Document 3) in which defect identification is performed in a bright field system using a Fresnel zone plate.

  Among the above-mentioned defect inspection methods for the same wavelength, X-ray microscopy using a bright field has high sensitivity, but the inspection signal is likely to be buried in noise. Therefore, it is necessary to reduce the pixel size used for the inspection. There is a problem that inspection is difficult from the viewpoint of throughput. On the other hand, the method using a dark field image has high inspection sensitivity and low noise, so that the pixel size used for the inspection can be relatively large and is suitable for full-field inspection.

  Further, as a defect correction method for an EUV light lithography mask based on the above-described various phase inspection methods, a method of correcting the contour of an absorber pattern and improving a projected image when the pattern is transferred by an exposure apparatus (for example, Patent Document 4). Reference). The reason for adopting such a method for defect correction of an EUV photolithographic mask is that it is difficult to directly correct phase defects caused by nuclei generated in the lower layer or the lower layer of a multilayer film of 40 layers or more. .

JP 2003-114200 A JP-A-6-349715 US Patent Application Publication No. 2004-0057107 Japanese translation of PCT publication No. 2002-532738 JP 2007-219130 A

  When a phase defect is found in a mask for EUV light lithography, as shown in Patent Document 4, the location of the phase defect is specified and the contour of the absorber pattern in the vicinity thereof is corrected, or the defect location is A remedy is taken such as using a mask directly under the absorber pattern.

  These remedies do not directly correct the phase defect itself, but adjust the light intensity distribution of the projected image by processing and correcting the absorber pattern adjacent to the phase defect to obtain a desired transfer size and pattern. It is something to do.

  However, when these remedies are actually implemented, the absorber pattern becomes an obstacle, and the magnitude and impact of the phase defect cannot be simply specified. There was a problem of inefficiency.

  In other words, with these remedies, the entire phase defect cannot be grasped, so that each time an additional processing of the absorber pattern is performed, the shadow of the absorber pattern or the phase defect hidden immediately below becomes obvious, and the defect correction is not completed easily. There was a problem. In addition to the problem of the correction efficiency, since the correction is performed by trial and error, the man-hours and time required for the correction cannot be read, and there is a problem from the viewpoint of time management of mask manufacturing.

  As described above, phase defect correction of a mask for EUV optical lithography is not easy, and there are significant problems in terms of efficiency, time, and cost. A method of manufacturing a semiconductor device with a high yield even when there is a defect is strongly desired.

  An object of the present invention is to provide a technique for easily relieving a phase defect of a mask for EUV light lithography.

  Another object of the present invention is to provide a technique for improving the manufacturing yield of a semiconductor device using a mask for EUV light lithography.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, one aspect of a typical one will be briefly described as follows.

This one aspect is a method of manufacturing a semiconductor device having an exposure step of transferring a circuit pattern to a semiconductor wafer using an EUV lithography mask having at least a substrate, a multilayer film, and an absorber pattern,
(A) a step of performing phase defect inspection of the mask for EUV lithography or a mask blank used for manufacturing the mask;
(B) when a phase defect is detected in the step (a), determining whether the phase defect is a concave defect or a convex defect;
(C) After the step (b), in accordance with the unevenness of the phase defect, a step of performing exposure by locally defocusing a portion including the phase defect of the EUV lithography mask;
Is included.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  Abnormal transfer of the circuit pattern to the semiconductor wafer can be suppressed without correcting the phase defect of the EUV lithography mask.

(A) is a top view of the mask for EUV lithography used in Embodiment 1 of this invention, (b) is the sectional view on the AA line of (a). 1 is a schematic block diagram of an EUV projection exposure apparatus used in Embodiment 1 of the present invention. (A) is a top view which shows the wafer stage of EUV projection exposure apparatus, (b) is the BB sectional drawing of (a). (A) is principal part sectional drawing in the manufacturing process which shows the state in which the concave-shaped phase defect produced in the mask blank of the mask for EUV lithography, (b) is a buffer layer and a pattern in the mask blank shown to (a). FIG. 4C is a cross-sectional view of a main part of an EUV lithography mask in which a buffer layer and a pattern are formed on a mask blank having a convex phase defect. It is a schematic block diagram of the mask blank inspection apparatus used in Embodiment 1 of the present invention. It is a flowchart which shows the exposure process of the semiconductor device by Embodiment 1 of this invention. It is the top view which looked at the wafer stage at the time of exposure from the upper direction. (A) is sectional drawing of the principal part of the wafer stage which shows the phase defect relief method when a phase defect is concave shape, (b) is the wafer stage which shows the phase defect relief method when a phase defect is convex shape FIG. It is a graph which shows the relationship between the defocus amount of a wafer, and the dimension error from the design value of the pattern transcribe | transferred to the wafer. (A), (b) is principal part sectional drawing of the mask for EUV lithography which shows an example of the phase defect relief method which is Embodiment 2 of this invention. (A), (b) is principal part sectional drawing of the mask for EUV lithography which shows another example of the phase defect relief method which is Embodiment 2 of this invention. It is a flowchart which shows an example of the exposure process of the semiconductor device by Embodiment 2 of this invention. (A) is principal part sectional drawing of the mask stage used in Embodiment 2 of this invention, (b) is principal part sectional drawing of the mask stage which shows the phase defect relief method in case a phase defect is concave shape, (C) is principal part sectional drawing of the mask stage which shows the phase defect relief method in case a phase defect is convex shape. It is a flowchart which shows another example of the exposure process of the semiconductor device by Embodiment 2 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. Furthermore, in the drawings for describing the embodiments, hatching may be applied even in a plan view or hatching may be omitted even in a cross-sectional view for easy understanding of the configuration.

(Embodiment 1)
First, the configuration of the EUV lithography mask used in the first embodiment will be described. Fig.1 (a) is a top view which shows the surface in which the absorber pattern of the mask for EUV lithography was formed, FIG.1 (b) is the sectional view on the AA line of the same figure (a).

  As shown in FIG. 1A, a device pattern area 11 is arranged at the center of the EUV lithography mask 10. Although not shown, a circuit pattern of the semiconductor device is formed in the device pattern area 11. Outside the device pattern area 11, alignment mark areas 12a, 12b, 12c, and 12d in which marks for aligning the EUV lithography mask 10 and wafer alignment marks are formed are arranged.

  As shown in FIG. 1B, the mask blank of the EUV lithography mask 10 is formed on a substrate 13 made of quartz glass or low thermal expansion glass and having a thickness of about 7 to 8 mm, and the main surface of the substrate 13, and a Mo film A multilayer film 14 having a thickness of about 300 nm in which about 40 layers of Si and Si films are alternately laminated, a capping layer 15 formed on the multilayer film 14, and a back surface of the substrate 13. And a metal film 16 for chucking by an electrostatic adsorption method. Further, an absorber pattern 18 having a thickness of about 50 to 70 nm is formed on the uppermost layer (capping layer 15) of the mask blank with a buffer layer 17 interposed therebetween. The circuit patterns in the device pattern area 11 and the marks in the alignment mark areas 12 a, 12 b, 12 c, and 12 d are constituted by the absorber pattern 18.

  Next, the configuration of an EUV projection exposure apparatus using the EUV lithography mask 10 will be described with reference to FIG.

  As shown in FIG. 2, EUV light EL having a central wavelength of 13.5 nm emitted from a light source 21 of the EUV projection exposure apparatus 20 is patterned on the EUV lithography mask 10 via an illumination optical system 22 composed of a plurality of multilayer mirrors. The surface (the surface on which the absorber pattern 18 shown in FIG. 1 is formed) is irradiated. The EUV lithography mask 10 is attracted and held on the lower surface of the mask stage 60 by electrostatic attraction.

  The EUV light EL reflected by the pattern surface of the EUV lithography mask 10 passes through the reduction projection optical system 23 composed of a plurality of multilayer mirrors and is irradiated onto the main surface of the wafer 24 to form the EUV lithography mask 10. The circuit pattern thus transferred is transferred to the wafer 24. Then, the circuit pattern is sequentially transferred to a plurality of regions (chip shots described later) of the wafer 24 by moving the wafer stage 25 on which the wafer 24 is mounted and repeating the pattern transfer described above.

  The incident angle of the EUV light EL with respect to the pattern surface of the EUV lithography mask 10 is such that the light incident on the EUV lithography mask 10 from the illumination optical system 22 is reflected by the pattern surface of the EUV lithography mask 10 and reduced projection optical system 23. Is set to about 6 degrees so that light incident on the light source is separated from each other. For this reason, the multilayer film 14 formed on the EUV lithography mask 10 has a periodic length so that the reflectance is substantially maximized when the EUV light EL is incident at an incident angle of 6 degrees.

  Next, the configuration of the wafer stage 25 of the EUV projection exposure apparatus 20 shown in FIG. 2 will be described with reference to FIG. 3A is a plan view of the wafer stage 25 on which the wafer 24 is mounted as viewed from above, and FIG. 3B is a cross-sectional view taken along line BB in FIG. 3A.

  As shown in FIG. 3, the wafer stage 25 includes a wafer stage frame 26 and a plurality of chuck pins 27 erected vertically on the upper surface of the wafer stage frame 26, and the wafer 24 is an electrostatic chuck type. Are attracted and held by these chuck pins 27. Each of the plurality of chuck pins 27 can be moved up and down independently of each other by a drive mechanism (not shown).

  Next, phase defects generated in the mask blank of the EUV lithography mask 10 will be described with reference to FIG. 4A is a cross-sectional view of the main part in the manufacturing process showing a state in which a phase defect has occurred in the mask blank of the EUV lithography mask 10, and FIG. 4B is a view of the mask blank shown in FIG. FIG. 3 is a cross-sectional view of a main part of an EUV lithography mask 10 on which a buffer layer 17 and an absorber pattern 18 are formed.

  FIG. 4A shows a concave shape as a result of depositing the multilayer film 14 in a state where fine depressions are formed on the main surface of the substrate 13 when the multilayer film 14 is deposited on the substrate 13 of the mask blank. An example in which a (pit-like) phase defect 19a has occurred is shown. In FIG. 4B, the buffer layer 17 and the absorber pattern 18 are formed on the mask blank in which such a concave phase defect 19a is generated, and the phase defect 19a is exposed in a region between the adjacent absorber patterns 18. Shows the state.

  On the other hand, FIG. 4C shows that a buffer layer 17 and an absorber pattern 18 are formed on a mask blank in which a convex (bump-like) phase defect 19b is generated when the multilayer film 14 is deposited, and adjacent absorbers are formed. 2 is a cross-sectional view of a main part of an EUV lithography mask 10 in which a phase defect 19b is exposed in a region between patterns 18. FIG.

  Here, when the depth of the concave phase defect 19 a is about 2 to 3 nm, or when the height of the convex phase defect 19 b is about 2 to 3 nm, it is transferred to the main surface of the wafer 24. Therefore, the integrated image formed on the wafer 24 is defective. Therefore, in the manufacturing process of the EUV lithography mask 10, it is necessary to detect the phase defects 19 a and 19 b at the stage of the mask blank before forming the buffer layer 17 and the absorber pattern 18.

  Next, the configuration of the mask blank inspection apparatus will be described with reference to FIG. In the following description, the inspection object is described as a mask blank, but the mask on which the absorber pattern 18 is formed is also included in the inspection object. That is, since the defect to be actually detected is mainly the phase defect generated in the multilayer film 14, even in the mask on which the absorber pattern 18 is formed, the defect in the mask blank portion is detected. Because.

  As shown in FIG. 5, the mask blank inspection apparatus 30 is an inspection apparatus that collects a dark field inspection image using EUV light as inspection light, and includes a light source 31 that generates an inspection EUV light BM and a mask blank 10M. Mask stage 32, illumination optical system 33, imaging optical system 34, two-dimensional array sensor (image detector) 35, sensor circuit 36, pattern memory 37, signal processing circuit 38, timing control circuit 39, mask stage A control circuit 40 and a system control computer 41 that controls the operation of the entire apparatus are configured. The mask blank inspection apparatus 30 is provided with a data file 42 for storing various data relating to the mask pattern.

  The light source 31 that generates the inspection EUV light BM is provided with a wavelength selection filter, a pressure partition unit, a scattered particle suppression unit, or the like as necessary. The imaging optical system 34 includes a concave mirror L1 and a convex mirror L2, and a Schwarzschild optical system that constitutes a dark field imaging optical system with a condensing NA = 0.25, a central shielding MA = 0.1, and a magnification of 26 times. It is.

  The mask blank 10M to be inspected for the presence of the phase defect 19 is placed on a mask stage 32 that can move in the three-axis directions of XYZ. The inspection EUV light BM having a central wavelength of 13.5 nm emitted from the light source 31 is converted into a convergent beam through the illumination optical system 33, and then bent by the multilayer mirror 43 to enter a predetermined region of the mask blank 10M. The position of the mask blank 10M is obtained as position information of the mask stage 32 by reading the position of the mirror 44 fixed to the mask stage 32 with the laser length measuring device 45. This position information is sent to the position circuit 46 and recognized by the system control computer 41.

  The multilayer mirror 43 is supported by mirror attitude control means 47 that controls its position and angle. In addition, it can be exchanged with a different mirror. Further, a part of the EUV light BM is branched by a beam splitter or a small area mirror, and the amount of light is monitored by the EUV light sensor 48, and a threshold for signal processing can be set in the illumination intensity correction circuit 49. In the case of using this beam splitter, the multilayer mirror 43 can be constituted by a multilayer film in which, for example, Mo film and Si film are alternately stacked from several pairs to about 10 pairs.

  Of the reflected light from the mask blank 10M, the light scattered by the defective portion of the mask blank 10M forms a convergent beam SLI via the imaging optical system 34 and is condensed on the two-dimensional array sensor 35. That is, as a result of forming a dark field inspection image of the mask blank 10M on the two-dimensional array sensor 35, the phase defect remaining on the mask blank 10M is detected as a bright spot in the inspection image. Information on the detected phase defect, such as its position and the intensity of the defect signal, is stored in the storage device 51, and various information can be observed via the pattern monitor 52 or the image output unit 53. Whether the phase defect has a concave shape (pit shape) or a convex shape (bump shape) is determined by measuring the signal intensity of the defective portion by moving the mask stage 32 in the vertical direction and focusing characteristics of the intensity peak. Can be determined by examining. Such a method for determining the type of phase defect is described in detail in the above-mentioned Patent Document 5 (Japanese Patent Laid-Open No. 2007-219130).

  Next, an exposure process of the semiconductor device according to the first embodiment will be described with reference to FIG. 6 (flow diagram).

  First, a mask blank 10M (or mask) having at least deposition of the multilayer film 14 is prepared (S101), and phase defect inspection is performed using the mask blank inspection apparatus 30 shown in FIG. 5 at this stage (S102). .

  If there is no phase defect, the absorber pattern 18 and the like are formed on the mask blank 10M to complete the EUV lithography mask 10, and then exposure is performed using the EUV projection exposure apparatus 20 shown in FIG. Then, the circuit pattern of the EUV lithography mask 10 is transferred to the wafer 24 (S109).

On the other hand, if a phase defect is found in the mask blank 10M, the location is registered in the storage device 51 (see FIG. 5) of the mask blank inspection apparatus 30 (S103), and the signal intensity I of the phase defect at that location is set. Compare with predetermined signal levels I ₀ and I ₁ (> I ₀ ). When the signal intensity I is I ₀ or less (I ≦ I ₀ ), it is determined that the phase defect does not become a fatal defect, and the EUV lithography mask 10 is completed. Then, exposure is performed (S109). If the signal intensity I exceeds I ₁ (I> I ₁ ), it is determined as an abnormal defect that is difficult to correct, and the mask is remanufactured (S105). Proceed to step (S102). Further, when the signal intensity I exceeds I ₀ and is equal to or less than I ₁ (I ₀ <I ≦ I ₁ ), the mask stage 32 of the mask blank inspection apparatus 30 is moved in the vertical direction as described above. Then, the focus characteristic of the signal intensity I is examined to determine whether the shape of the phase defect is a concave shape or a convex shape (S106).

  Next, after the absorber pattern 18 and the like are formed on the mask blank 10M to complete the EUV lithography mask 10, the EUV lithography mask 10 is mounted on the EUV projection exposure apparatus 20, and the wafer 24 is mounted on the wafer stage. 25.

  Then, according to the determination result obtained in the step (S106), exposure is performed while operating the wafer stage 25 as follows.

  FIG. 7 is a plan view of the wafer stage 25 as viewed from above during exposure. As shown in FIG. 7, the main surface of the wafer 24 mounted on the wafer stage 25 is partitioned into a plurality of chip shots 28. Each chip shot 28 is an area where the circuit pattern of the EUV lithography mask 10 is transferred by a single exposure, and a semiconductor chip is obtained by dicing the wafer 24 along the boundary between adjacent chip shots 28. .

  When normal exposure is performed using the EUV lithography mask 10 having a phase defect, the phase defect is transferred to the wafer 24, so that a transfer defect 29 is generated on each chip shot 28 of the wafer 24.

  The location of the phase defect existing in the EUV lithography mask 10 is registered in the storage device 51 of the mask blank inspection apparatus 30 in the step (103) described above. Therefore, it is possible to know in advance where the transfer defect 29 occurs in the chip shot 28 of the wafer 24 by referring to the location of the phase defect registered in the storage device 51.

  Therefore, when it is determined in the above-described step (S106) that the phase defect has a concave shape, as shown in FIG. 8A, among the plurality of chuck pins 27 that attract and hold the wafer 24. Then, the chuck pins 27 located below the region where the transfer defect 29 occurs (phase defect corresponding portion) are retracted downward (S107), and the surface of the wafer 24 in this region is recessed. That is, when the phase defect has a concave shape, the wafer 24 is locally moved so that the distance between the phase defect corresponding portion of the wafer 24 and the reduction projection optical system 23 (see FIG. 2) of the EUV projection exposure apparatus 20 is increased. Then, exposure is performed with defocusing (S109).

  On the other hand, when it is determined that the phase defect has a convex shape, as shown in FIG. 8B, the chuck pin 27 located below the region where the transfer defect 29 occurs is protruded upward (S108). The surface of the wafer 24 in this region is raised. That is, when the phase defect has a convex shape, exposure is performed by locally defocusing the wafer 24 so that the distance between the phase defect corresponding portion of the wafer 24 and the reduction projection optical system 23 is shortened (S109). .

  FIG. 9 shows a mask for EUV lithography in which a convex phase defect 19b having a Gaussian shape with a maximum height = 1.2 nm and a width = 40 nm exists at a position equidistant from two adjacent absorber patterns 18. 10 is a graph showing 10 transfer characteristics.

  Here, the horizontal axis of the graph represents the defocus amount of the wafer 24, and the vertical axis represents the dimensional error from the design value of the pattern transferred to the wafer 24. A curve A in the graph indicates transfer characteristics when the line (L) / space (S) of the absorber pattern 18 is 16 nm, and a curve B indicates the line (L) / space of the absorber pattern 18. The transfer characteristics when (S) is 26 nm are shown. Note that the positive defocus amount of the wafer 24 means that the phase defect corresponding portion of the wafer 24 is defocused in the direction in which the distance from the reduction projection optical system 23 is shortened, and the defocus amount is negative. “Present” means that the phase defect corresponding portion of the wafer 24 is defocused in a direction in which the distance from the reduction projection optical system 23 becomes longer.

  As shown in FIG. 9, the abnormal transfer (dimensional error from the design value) due to the convex phase defect 19b can be reduced by positively defocusing the phase defect corresponding portion of the wafer 24.

  As described above, according to the first embodiment, the wafer 24 mounted on the wafer stage 25 of the EUV projection exposure apparatus 20 is defocused locally positively or negatively to perform exposure, whereby the EUV lithography mask 10. The abnormal transfer of the circuit pattern to the wafer 24 can be suppressed without correcting the phase defects present in the wafer 24.

  In this case, the area to be defocused is only the phase defect corresponding portion of the wafer 24, and the other areas are not defocused. Therefore, there is no possibility that the transfer characteristic of the circuit pattern is deteriorated in the other areas of the wafer 24. In addition, there is no problem that the exposure time is longer than that of a normal exposure method. Thus, unlike conventional methods in which defects are corrected by trial-and-error, the time management of mask manufacturing and the TAT (Turn Around Time) estimate of semiconductor manufacturing can be easily established.

  Therefore, according to the first embodiment, a high effect can be obtained in terms of manufacturing yield, manufacturing cost, and TAT of the semiconductor device.

(Embodiment 2)
In the phase defect relief method of the first embodiment, a part of the wafer 24 (phase defect corresponding part) mounted on the wafer stage 25 of the EUV projection exposure apparatus 20 is deformed, so that a part of the wafer 24 is subjected to EUV lithography. The mask 10 for defocusing was defocused.

  In the second embodiment, a phase defect relief method for deforming a part of the EUV lithography mask 10 will be described. There are the following two methods for deforming a part of the EUV lithography mask 10, but both can be used in combination.

  First, the first method is to locally change the thickness of the EUV lithography mask 10 by providing a concave or convex portion on a part of the back surface of the EUV lithography mask 10. That is, when a concave phase defect 19a occurs in the EUV lithography mask 10, a recess 13a is provided on the back surface of the substrate 13 corresponding to the phase defect 19a as shown in FIG. On the other hand, when the convex phase defect 19b occurs, as shown in FIG. 10B, the convex portion 13b is provided on the back surface of the substrate 13 corresponding to the phase defect 19b. Such concave portions 13 a and convex portions 13 b are formed by grinding a part of the back surface of the substrate 13.

  Further, in place of the means for providing the recess 13a on the back surface of the substrate 13, as shown in FIG. 11A, the film thickness of the metal film 16 corresponding to the phase defect 19a may be made thinner than other regions. Furthermore, instead of the means for providing the convex portion 13b on the back surface of the substrate 13, as shown in FIG. 11B, the film thickness of the metal film 16 corresponding to the phase defect 19b may be made thicker than other regions. In this case, after depositing the thick metal film 16 on the back surface of the substrate 13, a part thereof may be etched and thinned.

  When the EUV lithography mask 10 whose thickness is locally changed by the above-described method is attached to the EUV projection exposure apparatus 20, when the concave phase defect 19a is generated in the EUV lithography mask 10, EUV lithography is performed. Defocus occurs in the direction in which the distance between the phase defect portion of the mask 10 and the optical system (reduction projection optical system 22, reduction projection optical system 23) becomes longer. Further, when the convex phase defect 19b occurs, defocus occurs in the direction in which the distance between the phase defect portion of the EUV lithography mask 10 and the optical system is shortened.

  An exposure process of the semiconductor device using the EUV lithography mask 10 will be described with reference to FIG. 12 (flow diagram).

  First, a mask blank 10M (or mask) having at least deposition of the multilayer film 14 is prepared (S201), and phase defect inspection is performed at this stage using the mask blank inspection apparatus 30 shown in FIG. 5 (S202). .

  If there is no phase defect, the EUV lithography mask 10 is completed by a normal method, and then the circuit pattern of the EUV lithography mask 10 is transferred to the wafer 24 by exposure using the EUV projection exposure apparatus 20. (S209).

On the other hand, if a phase defect is found in the mask blank 10M, the location where the phase defect has occurred is registered in the storage device 51 (see FIG. 5) of the mask blank inspection apparatus 30 (S203), and the phase defect at that location is detected. The signal intensity I is compared with predetermined signal levels I ₀ and I ₁ (> I ₀ ). If the signal intensity I is I ₀ or less (I ≦ I ₀ ), it is determined that the phase defect does not become a fatal defect, and the EUV lithography mask 10 is completed by a normal method. Then, exposure is performed by a normal method (S209). When the signal intensity I exceeds I ₁ (I> I ₁ ), it is determined as an abnormal defect that is difficult to correct, and the mask is remanufactured (S205). Proceed to inspection step (S202). Further, when the signal intensity I exceeds I ₀ and is equal to or less than I ₁ (I ₀ <I ≦ I ₁ ), the signal intensity I is moved by moving the mask stage 32 of the mask blank inspection apparatus 30 in the vertical direction. The focus characteristic is examined to determine whether the phase defect has a concave shape or a convex shape (S206).

  Next, when it is determined in the above step (S206) that the phase defect has a concave shape, the EUV lithography for which the back surface has been recessed by the method shown in FIG. 10 (a) or FIG. 11 (a). A mask 10 is prepared (S207), and exposure is performed using the EUV lithography mask 10 (S209). On the other hand, if it is determined that the phase defect has a convex shape, the EUV lithography mask 10 having the back surface processed by the method shown in FIG. 10B or FIG. 11B is manufactured (S208). Then, exposure is performed using the EUV lithography mask 10 (S209). When the EUV lithography mask 10 is subjected to the concave or convex processing as described above, the location of the phase defect registered in the storage device 51 of the mask blank inspection apparatus 30 is referred to, and the processing location is determined.

  A second method for deforming a part of the EUV lithography mask 10 is to provide a movable chuck pin on the mask stage of the EUV projection exposure apparatus 20.

  As shown in FIG. 13A, the mask stage 60 of the EUV projection exposure apparatus 20 includes a mask stage pedestal 61 and a plurality of chuck pins 62 erected vertically to the mask holding surface of the mask stage pedestal 61. The EUV lithography mask 10 is attracted and held on these chuck pins 62 by an electrostatic chuck method. Further, each of the plurality of chuck pins 62 can be moved up and down independently of each other by a drive mechanism (not shown).

  FIG. 14 is a flowchart showing an exposure process of a semiconductor device using the mask stage 60 described above. Steps (S301) to (S306) shown in the figure are the same as steps (S201) to (S206) shown in FIG.

  Next, when it is determined in the step (S306) that the phase defect has a concave shape, the EUV lithography mask 10 is manufactured by a normal method, and the EUV lithography mask 10 is shown in FIG. The chuck pin 62 of the mask stage 60 is sucked and held.

  Next, as shown in FIG. 13B, among the plurality of chuck pins 62 that suck and hold the EUV lithography mask 10, the chuck pins 62 located above the phase defect 19 a are retracted upward. (S307) The surface of the EUV lithography mask 10 in this region is recessed. That is, when the phase defect has a concave shape, the EUV lithography mask is set so that the distance between the phase defect portion of the EUV lithography mask 10 and the optical system (reduction projection optical system 22 and reduction projection optical system 23) is increased. 10 is locally defocused to perform exposure (S309).

  On the other hand, when it is determined that the phase defect has a convex shape, as shown in FIG. 13C, the chuck pin 62 positioned above the phase defect 19b is protruded downward (S308), and EUV in this region is obtained. The surface of the lithography mask 10 is raised. That is, when the phase defect has a convex shape, exposure is performed by locally defocusing the EUV lithography mask 10 so that the distance between the phase defect portion of the EUV lithography mask 10 and the optical system is shortened ( S309).

  As described above, according to the second embodiment, exposure is performed by locally defocusing the EUV lithography mask 10 adsorbed and held on the mask stage 60 of the EUV projection exposure apparatus 20 positively or negatively. The abnormal transfer of the circuit pattern to the wafer 24 can be suppressed without correcting the phase defects present in the EUV lithography mask 10.

  In this case, the area to be defocused is only the phase defect corresponding portion of the EUV lithography mask 10 and the other areas are not defocused. Therefore, abnormal transfer of the circuit pattern occurs in other areas of the EUV lithography mask 10. There is no fear. In addition, there is no problem that the exposure time is longer than that of a normal exposure method. Thus, unlike conventional methods in which defects are corrected by trial-and-error, the time management of mask manufacturing and the TAT (Turn Around Time) estimate of semiconductor manufacturing can be easily established.

  Therefore, according to the second embodiment, a high effect can be obtained in terms of manufacturing yield, manufacturing cost, and TAT of the semiconductor device.

  It should be noted that the phase defect relief method of the second embodiment described above and the phase defect relief method of the first embodiment described above can be used in combination. That is, the exposure may be performed in a state where the phase defect corresponding portion of the wafer 24 and the phase defect corresponding portion of the EUV lithography mask 10 are deformed. In this case, an equivalent defocus amount can be obtained with a smaller amount of deformation than when only one of the wafer 24 and the EUV lithography mask 10 is deformed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a lithography technique using EUV as an exposure light source.

10 EUV lithography mask 10M Mask blank 11 Device pattern area 12a, 12b, 12c, 12d Alignment mark area 13 Substrate 13a Recess 13b Protrusion 14 Multilayer film 15 Capping layer 16 Metal film 17 Buffer layer 18 Absorber pattern 19a Phase defect (concave Shape phase defect)
19b Phase defect (convex phase defect)
20 EUV projection exposure apparatus 21 Light source 22 Illumination optical system 23 Reduction projection optical system 24 Wafer 25 Wafer stage 26 Wafer stage mount 27 Chuck pin 28 Chip shot 29 Transfer defect 30 Mask blank inspection apparatus 31 Light source 32 Mask stage 33 Illumination optical system 34 Image optical system 35 Two-dimensional array sensor (image detector)
36 sensor circuit 37 pattern memory 38 signal processing circuit 39 timing control circuit 40 mask stage control circuit 41 system control computer 42 data file 43 multilayer mirror 44 mirror 45 laser length measuring device 46 position circuit 47 mirror attitude control means 48 sensor for EUV light 49 Illumination intensity correction circuit 51 Storage device 52 Pattern monitor 53 Image output unit 60 Mask stage 61 Mask stage mount 62 Chuck pin BM Inspection EUV light EL EUV light L1 Convex mirror L2 Convex mirror SLI Converging beam

Claims (6)

A method for manufacturing a semiconductor device comprising an exposure step of transferring a circuit pattern to a semiconductor wafer using an EUV lithography mask having at least a substrate, a multilayer film and an absorber pattern,
(A) a step of performing phase defect inspection of the mask for EUV lithography or a mask blank used for manufacturing the mask;
(B) when a phase defect is detected in the step (a), determining whether the phase defect is a concave defect or a convex defect;
(C) After the step (b), in accordance with the unevenness of the phase defect, a step of performing exposure by locally defocusing a portion including the phase defect of the EUV lithography mask;
A method for manufacturing a semiconductor device, comprising: When the phase defect is a concave defect, defocus in a direction in which the distance between the part including the phase defect of the EUV lithography mask and the optical system of the exposure apparatus becomes longer,
2. The semiconductor according to claim 1, wherein when the phase defect is a convex defect, defocusing is performed in a direction in which a distance between the portion including the phase defect of the EUV lithography mask and the optical system is shortened. Device manufacturing method. The exposure apparatus used in the exposure step has a mask stage having a plurality of chuck pins that suck and hold the EUV lithography mask,
Each of the plurality of chuck pins is configured to be movable independently of each other along a direction perpendicular to the mask holding surface of the mask stage,
By moving one of the plurality of chuck pins in a direction perpendicular to the mask holding surface in accordance with the unevenness of the phase defect, the portion of the EUV lithography mask containing the phase defect is optically applied to the exposure apparatus. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the system is locally defocused.   According to the unevenness of the phase defect, by forming unevenness on the back surface of the EUV lithography mask corresponding to the region including the phase defect, the region including the phase defect of the EUV lithography mask can be optically applied to an exposure apparatus. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the system is locally defocused. If the phase defect is a concave defect, defocus in the direction that the distance between the semiconductor wafer and the optical system of the exposure apparatus becomes longer,
2. The method of manufacturing a semiconductor device according to claim 1, wherein when the phase defect is a convex defect, defocusing is performed in a direction in which a distance between the semiconductor wafer and the optical system is shortened. An exposure apparatus used in the exposure step has a wafer stage having a plurality of chuck pins for sucking and holding the semiconductor wafer,
Each of the plurality of chuck pins is configured to be movable independently of each other along a direction perpendicular to the wafer holding surface of the wafer stage,
By moving any of the plurality of chuck pins in a direction perpendicular to the wafer holding surface in accordance with the unevenness of the phase defect, a part of the semiconductor wafer is locally localized with respect to the optical system of the exposure apparatus. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is defocused.