JP2013020661A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve reduction in a circuit area.SOLUTION: A semiconductor memory device comprises: a first word line CG1 connected to a first memory cell; a second word line CG2 connected to a second memory cell; a control circuit 2 having a power supply circuit 21 that controls writing operation with respect to each memory cell and is electrically connected to the first word line CG1 and the second word line CG2; a first transfer switch CGSW1 disposed between the first word line CG1 and the power supply circuit 21; and a second transfer switch CGSW2 disposed between the second word line CG2 and the power supply circuit 21. In the writing operation with respect to the first memory cell, at a first time, the control circuit 2 turns on the first transfer switch CGSW1 and the second transfer switch CGSW2 and boosts the first word line CG1 and the second word line CG2. At a second time subsequent to the first time, the control circuit 2 cuts off an electrical connection between the power supply circuit 21 and the second word line CG2 and causes the second word line CG2 to be in a floating state. A voltage of the second word line CG2 reaches a writing pass voltage.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  In the NAND flash memory, a manufacturing process for realizing miniaturization has been proposed. As the NAND flash memory becomes finer, problems such as deterioration of transistor stress and erroneous writing and erasing due to coupling with adjacent cells become more prominent. For this reason, in the NAND flash memory, higher reliability with respect to operations such as writing and erasing is required.

JP 2005-285185 A

  Provided is a semiconductor memory device capable of reducing a circuit area.

  The semiconductor memory device according to the present embodiment controls the first word line connected to the first memory cell, the second word line connected to the second memory cell, and the write operation to each memory cell, and the first word line A control circuit having a power supply circuit electrically connected to the line and the second word line, a first transfer switch provided between the first word line and the power supply circuit, and between the second word line and the power supply circuit And a second transfer switch provided. In the write operation to the first memory cell, the control circuit turns on the first transfer switch and the second transfer switch at the first time, boosts the first word line and the second word line, and after the first time At the second time, the electrical connection between the power supply circuit and the second word line is disconnected to make the second word line floating, and the second word line reaches the write pass voltage.

1 is a block diagram showing an example of the overall configuration of a semiconductor memory device according to an embodiment. FIG. 2 is a circuit diagram showing a row decoder and a memory cell array shown in FIG. 1. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment. 4 is a timing chart showing a write operation of the semiconductor memory device according to the first embodiment. A circuit diagram showing a semiconductor memory device in a 2nd embodiment. 9 is a timing chart illustrating a write operation of the semiconductor memory device according to the second embodiment. A circuit diagram showing a semiconductor memory device in a 3rd embodiment. 10 is a timing chart showing a write operation of the semiconductor memory device according to the third embodiment. A circuit diagram showing a semiconductor memory device in a 4th embodiment. 10 is a timing chart showing a write operation of the semiconductor memory device according to the fourth embodiment.

  The present embodiment will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals.

<Example of overall configuration>
The overall configuration of the semiconductor memory device (NAND flash memory) according to the present embodiment will be described below with reference to FIGS.

  FIG. 1 is a block diagram showing an example of the overall configuration of the semiconductor memory device according to the present embodiment.

  As shown in FIG. 1, the semiconductor memory device includes a control circuit 2, a row decoder 3, a column decoder 4, a sense amplifier S / A 5, and a memory cell array 6.

  Control circuit 2 is connected to row decoder 3, column gate 4, sense amplifier S / A 5, and memory cell array 6. The control circuit 2 controls these with a control signal. In addition, the control circuit 2 generates a voltage for a word line or a bit line at the time of data writing, and generates a voltage supplied to the well. This control signal and control voltage generation circuit 7 includes a booster circuit such as a charge pump circuit, for example, and can generate a program voltage and other high voltages.

  The row decoder 3 selects a word line at the time of writing, reading and erasing, and applies a voltage supplied from the control circuit 2 to the selected word line. Details of the row decoder 3 will be described later with reference to FIG.

  The column decoder 4 selects a bit line at the time of writing, reading and erasing, and applies a voltage supplied from the control circuit 2 to the selected bit line.

  The sense amplifier S / A5 amplifies data read from the memory cell to the bit line. Note that the sense amplifier S / A 5 may be integrated with the column decoder 3.

  The memory cell array 6 includes a plurality of blocks BLK0 to BLKs. Each of the blocks BLK0 to BLKs has a plurality of memory cell transistors. The memory cell transistor is provided at a location corresponding to the intersection position of the plurality of bit lines and the plurality of word lines intersecting therewith. In the following description, when the blocks BLK0 to BLKs are not distinguished, they may be simply referred to as blocks BLK. Details of the memory cell array 6 will be described later with reference to FIG.

  FIG. 2 is a circuit diagram showing row decoder 3 and memory cell array 6 shown in FIG. Here, the column decoder 4 shown in FIG. 1 is omitted.

  First, the memory cell array 6 will be described.

  As shown in FIG. 2, the memory cell array 6 includes a plurality of blocks BLK0 to BLKs. Each block BLK includes a plurality of NAND strings (memory strings) 61 arranged in the row direction. Each NAND string 61 has a plurality of nonvolatile memory cell transistors MT whose current paths are connected in series in the column direction and can hold data, a select transistor ST1 connected to one end thereof, and a select transistor connected to the other end. It is composed of ST2. Each NAND string 61 includes, for example, 64 memory cell transistors MT, but may be 128, 256, 512, and the number is not limited.

  Memory cell transistor MT includes a floating gate (conductive layer) formed on a p-type semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. It is an FG structure. A tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode functioning as a word line are sequentially formed on a semiconductor substrate (not shown) and may have a MONOS structure. The drain of the memory cell transistor MT is electrically connected to the bit line BL, and the source is electrically connected to the source line SL.

  The selection transistor ST1 is connected to the drain region on one end side of the plurality of memory cell transistors MT whose source regions are connected in series, and the drain region is connected to the bit line BL. On the other hand, the select transistor ST2 is connected to the source region on the other end side of the plurality of memory cell transistors MT whose drain regions are connected in series, and the source region is connected to the source line SL. Note that both the selection transistors ST1 and ST2 are not necessarily required, and only one of them may be provided as long as the NAND string 61 can be selected.

  The plurality of memory cell transistors MT in the same row are commonly connected to any one of the word lines WL1 to WLn, and the plurality of selection transistors ST1 in the same row are commonly connected to the select gate line SGD1 and are in the same row. The select transistors ST2 are commonly connected to a select gate line SGS1. In the following description, when the word lines WL1 to WLn are not distinguished, they may be simply referred to as word lines WL.

  Data is collectively written in the plurality of memory cell transistors MT connected to the same word line WL, and this unit is called a page. Further, in the plurality of NAND strings 61, data is erased collectively in units of blocks BLK.

  Next, the row decoder 3 will be described.

  As shown in FIG. 2, the row decoder 3 includes a block decoder 30 and transistors 31 to 33. The block decoder 30 decodes the block address designated at the time of data write operation, read operation and erase, and selects the block BLK based on the result. More specifically, the block decoder 30 selects the transistors 31 to 33 corresponding to the block BLK including the selected memory cell transistor MT via the control line TG, and turns on the transistors 31 to 33. .

  At this time, the block decoder 30 outputs a block selection signal. The block selection signal is a signal for the row decoder 3 to select one of the plurality of blocks BLK0 to BLKs when reading, writing, and erasing data. Thereby, the row decoder 3 selects the row direction of the memory cell array 6 corresponding to the selected block BLK. That is, based on a selection signal supplied from the block decoder 30, the row decoder 3 applies a voltage supplied from the power supply circuit 21 described later to the select gate lines SGD1, SGS1 and the word lines WL1 to WLn.

  Thus, the word lines WL1 to WLn in the memory cell array 6 are connected to the control gates CG1 to CGn via the row decoder 3, respectively, and a voltage is supplied from the power supply circuit 21 via the control gates CG1 to CGn. Here, the power supply circuit 21 is included in the control circuit 2 shown in FIG. In the following description, when the control gates CG1 to CGn are not distinguished, they may be simply referred to as control gates CG.

  The control gates CG1 to CGn and the power supply circuit 21 will be described in detail in each embodiment described later.

<Write operation>
The write operation of the semiconductor memory device in this embodiment will be described below. Here, a case where data is written to the memory cell transistor MT connected to the control gate CG2 (word line WL2) will be described.

  During the write operation, the control gates CG1 to CGn are boosted to optimum voltage levels. More specifically, the write voltage VPGM is applied to the control gate CG2 to be written, and the write pass voltages VUSELH, VUSEL, VUSEL (VPGM> VUSELH> VUSEL are applied to the control gates CG1, CG3 to CGn to be non-written. > VUSELL) is applied. That is, a plurality of different write pass voltages can be applied to the control gates CG1, CG3 to CGn depending on the reliability (for example, the number of times of writing and the number of erasing) of the memory cell transistor MT connected thereto.

  By applying the write voltage VPGM to the control gate CG2, the control gate CG2 is boosted to the voltage level VPGM at which writing is performed. As a result, data is written to the memory cell transistor MT connected to the control gate CG2. On the other hand, when any of the write pass voltages VUSELH, VUSEL, and VUSEL is applied to the control gates CG1, CG3 to CGn, the control gates CG1, CG3 to CGn are not written, and the voltage level at which the memory cell transistor MT is turned on. The voltage is boosted to any one of VUSELH, VUSEL, and VUSEL. As a result, the channels of the memory cell transistors MT connected to the control gates CG1, CG3 to CGn are boosted, and erroneous writing to these memory cell transistors MT is prevented.

  At this time, the write pass voltage may be one type. However, the boost efficiency varies depending on the threshold value of the non-write target cell. Therefore, in order to prevent a decrease in boost efficiency, it is desirable that a write pass voltage corresponding to the cell is applied as described above. Although an example using three types of write pass voltages has been described, two types or four or more types may be used.

<First Embodiment>
The semiconductor memory device according to the first embodiment will be described below with reference to FIGS. In the first embodiment, the power supply voltage at the time of writing is unified, and the on / off timing of the switch in the control gate connected to the power supply voltage is controlled to apply the write voltage to the control gate to be written. In this example, the write pass voltage is applied to the non-write target control gate.

[Circuit configuration and write operation]
FIG. 3 is a circuit diagram showing the semiconductor memory device according to the first embodiment. Here, the circuit configuration of the sense amplifier S / A5 and the row decoder 3 and the circuit configuration of the memory cell array 6 shown in FIG. 2 are omitted, and particularly the connection between the power supply circuit 21 and the control gates CG1 to CGn is shown. Yes.

  As shown in FIG. 3, the control gates CG1 to CGn are connected to the word lines WL1 to WLn in the memory cell array 6 via the row decoder 3, respectively. The control gates CG1 to CGn are connected to the power supply circuit 21 via control gate switches (transfer switches) CGSW1 to CGSWn, respectively. Further, a parasitic capacitance (coupling capacitance) is generated between two adjacent control gates CG. In the following description, when the control gate switches CGSW1 to CGSWn are not distinguished, they may be simply referred to as control gate switches CGSW. Further, a parasitic capacitance similar to that between the control gates CG is generated between two adjacent word lines WL, but is omitted in FIG.

  The control gate switches CGSW1 to CGSWn are independently controlled by the control circuit 2. In other words, the control circuit 2 can switch on / off the control gate switches CGSW1 to CGSWn at an arbitrary timing.

  Here, in the first embodiment, all of the control gates CG <b> 1 to CGn are connected to a single power supply circuit 21. The power supply circuit 21 generates a write voltage VPGM during a write operation, and charges (boosts) the control gates CG1 to CGn. That is, by controlling the on / off timing of the control gate switches CGSW1 to CGSWn in anticipation of the coupling capacitance (parasitic capacitance) between two adjacent control gates CG, each control gate CG1 is controlled by the single power supply circuit 21. ~ CGn is boosted to an appropriate voltage level.

  FIG. 4 is a timing chart showing the write operation of the semiconductor memory device according to the first embodiment. Here, data is written to the memory cell transistor MT connected to the control gate CG2, the control gates CG1, CG5 to CGn are boosted to the voltage level VUSEL, the control gate CG3 is boosted to the voltage level VUSELH, and the control gate An example in which CG4 is boosted to voltage level VUSELL will be described.

  As shown in FIG. 4, first, at time t0, all of the control gate switches CGSW1 to CGSWn are turned on. Thereby, charging by the power supply circuit 21 is started in all of the control gates CG1 to CGn.

  Next, at time t1, the control gate switch CGSW4 is turned off. As a result, the control gate CG4 enters a floating state. At this time, the direct charging by the power supply circuit 21 of the control gate CG4 is completed, but the control gate CG4 receives coupling noise through the coupling capacitance of the adjacent control gate CG until the boosting of the control gate CG2 is completed. to continue. At this time t1, the voltage of the control gate CG4 is boosted by the coupling noise received from the control gate CG1 and the like from the voltage VUSELL (the voltage reached by the control gate CG4 when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage is shown.

  The control gate switch CGSW4 is controlled according to the coupling noise from the control gate CG2. That is, when the control gate CG2 is boosted to the voltage level VPGM (after time t4 described later), the control gate switch CGSW4 is turned off at a timing (time t1) at which the control gate CG4 is boosted to the voltage level VUSELL. To control.

  Next, at time t2, the control gate switches CGSW1, CGSW5 to CGSWn are turned off. Thereby, the control gates CG1, CG5 to CGn are in a floating state. At this time, the direct charging by the power supply circuit 21 of the control gates CG1, CG5 to CGn is completed, but the control gates CG1, CG5 to CGn are connected to the control gate CG2 via the coupling capacitance of the adjacent control gate CG. Continue to receive coupling noise until boosting is complete. At this time t2, the voltages of the control gates CG1, CG5 to CGn are controlled from the voltage VUSEL (the voltage reached by the control gates CG1, CG5 to CGn when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage boosted by the coupling noise received from is shown.

  As in the case of the control gate CG4, the control gate switches CGSW1, CGSW5 to CGSWn are controlled according to the coupling noise from the control gate CG2. That is, when the control gate CG2 is boosted to the voltage level VPGM (after time t4 described later), the control gate switch CGSW1 is timing (time t2) at which the control gates CG1, CG5 to CGn are boosted to the voltage level VUSEL. , CGSW5 to CGSWn are controlled to be turned off.

  Next, at time t3, the control gate switch CGSW3 is turned off. As a result, the control gate CG3 enters a floating state. At this time, direct charging of the control gate CG3 by the power supply circuit 21 is completed, but the control gate CG3 receives coupling noise until the boosting of the control gate CG2 is completed via the coupling capacitance of the adjacent control gate CG. to continue. At this time t3, the voltage of the control gate CG3 is boosted by the coupling noise received from the control gate CG2 from the voltage VUSELH (the voltage reached by the control gate CG3 when the control gate CG2 is boosted to the voltage level VPGM). Indicates the time when the voltage reached by subtracting the voltage is reached.

  As in the case of the control gate CG4 and CG1, CG5 to CGn, the control gate switch CGSW3 is controlled according to the coupling noise from the control gate CG2. That is, when the control gate CG2 is boosted to the voltage level VPGM (after time t4 described later), the control gate switch CGSW3 is turned off at a timing (time t3) at which the control gate CG3 is boosted to the voltage level VUSELH. To control.

  Thereafter, at time t4, the control gate CG2 is boosted to the voltage level VPGM. Accordingly, the boosting of control gates CG1, CG3 to CGn due to coupling noise from control gate CG2 is completed. That is, the control gate CG4 is boosted to the voltage level VUSEL, the control gates CG1, CG5 to CGn are boosted to VUSEL, and the control gate CG3 is boosted to VUSELH.

  The on / off timing control of the control gate switches CGSW1 to CGSWn described above can be controlled by the control circuit 2. In addition, the timing from time t1 to time t3 includes the magnitude of the boosted voltage level of the non-write target control gate CG and the coupling noise (coupling) from the write target control gate CG to the non-write target control gate CG. The time is preset according to the size of the (capacity). More specifically, the time from time t0 to time t1 to t3 increases when the boosted voltage level of the non-write target control gate CG is large, and decreases when the voltage level is small. Further, when the coupling noise from the write target control gate CG to the non-write target control gate CG is small, the time from the time t0 to the time t1 to t3 becomes long, and the write target control gate CG is not subjected to the non-write target. It becomes shorter when the coupling noise to the control gate CG is large.

[Effect of the first embodiment]
As an example of improving the reliability of the memory cell, there is a method of selectively using a plurality of types of word line boost levels for non-write cells at the time of writing. In order to generate these plural types of word line boost levels, the power source type (the number of power sources) increases, and the circuit scale and circuit area increase.

  However, according to the first embodiment, the semiconductor memory device has the single power supply circuit 21 that generates the write voltage VPGM and is connected to each control gate CG via the control gate switch CGSW. In the write operation, the single power supply circuit 21 boosts the write target control gate CG to the voltage level VPGM, and boosts the non-write target control gate CG to any one of the voltage levels VUSELH, VUSEL, and VUSEL. This is because the control gate switch CGSW is turned on / off according to the magnitude of the voltage level and the magnitude of the coupling noise from the write target control gate CG in boosting the voltage level of the non-write target control gate CG. Control timing. As a result, each control gate CG can be boosted to a plurality of voltage levels by the unified power supply circuit 21. Therefore, it is possible to reduce the power supply circuit size without increasing the type of power supply while improving the reliability of the memory cell.

  Accordingly, since only the control gate switch CGSW that connects the single power supply circuit 21 and the control gate CG is necessary, the switch circuit size can be reduced and the circuit scale can be further reduced. Can be planned.

<Second Embodiment>
The semiconductor memory device according to the second embodiment will be described below with reference to FIGS. The second embodiment is a modification of the first embodiment, in which an equalizer is provided between the control gates to increase the coupling ratio of the non-write target control gate with respect to the write target control gate. It is. Note that in the second embodiment, description of the same points as in the first embodiment will be omitted, and different points will be described.

[Circuit configuration and write operation]
FIG. 5 is a circuit diagram showing a semiconductor memory device according to the second embodiment. Here, the circuit configuration of the sense amplifier S / A5 and the row decoder 3 and the circuit configuration of the memory cell array 6 shown in FIG. 2 are omitted, and particularly the connection between the power supply circuit 21 and the control gates CG1 to CGn is shown. Yes.

  As shown in FIG. 5, the second embodiment is different from the first embodiment in that MOS transistors (equalizer switches) EQ1 to EQn functioning as equalizers are connected between the control gates CG. . In other words, the potentials of the control gates CG can be equalized by the MOS transistors EQ1 to EQn. Further, MOS transistors CGSW1 to CGSWn are connected as control gate switches CGSW1 to CGSWn between the control gates CG1 to CGn and the power supply circuit 21.

  In the following description, the MOS transistors CGSW1 to CGSWn and the control gate switches CGSW1 to CGSWn are synonymous. Further, when the MOS transistors EQ1 to EQn are not distinguished from each other, they may be simply referred to as MOS transistors EQ.

  One ends of the MOS transistors CGSW1 to CGSWn are connected to the control gates CG1 to CGn, respectively, and the other ends are connected to the single power supply circuit 21, respectively. The MOS transistors CGSW1 to CGSWn are on / off controlled by control signals VSW1 to VSWn, respectively. That is, when the control signals VSW1 to VSWn are “H”, the MOS transistors CGSW1 to CGSWn are turned on, and when the control signals VSW1 to VSWn are “L”, the MOS transistors CGSW1 to CGSWn are turned off. MOS transistors CGSW1 to CGSWn are independently controlled by control circuit 2. In other words, the control circuit 2 can switch the MOS transistors CGSW1 to CGSWn on / off at an arbitrary timing.

  Here, the “H” state of the control signals VSW1 to VSWn is “VPGM + threshold value of the transfer gate transistors (MOS transistors CGSW1 to CGSWn)”, and the “L” state is “VSS”.

  MOS transistors EQ1 to EQn are arranged to connect control gates CG1 to CGn. More specifically, one end of the MOS transistor EQ1 is connected to the control gate CG1, and the other end is connected to the control gate CG2. The MOS transistor EQ1 is on / off controlled by a control signal VEQ1. That is, when the control signal VEQ1 is “H”, the MOS transistor EQ1 is turned on, and the potential of the control gate CG1 and the potential of the control gate CG2 are equalized.

  MOS transistors EQ2 to EQn also have the same function as MOS transistor EQ1. That is, the MOS transistor EQ2 equalizes the potential of the control gate CG2 and the potential of the control gate CG3 by on / off control of the control signal VEQ2, and the MOS transistor EQ3 controls the potential of the control gate CG4 by controlling on / off of the control signal VEQ3. The potential of the gate CG3 is equalized, the MOS transistor EQn-1 equalizes the potential of the control gate CGn-1 and the potential of the control gate CGn by the on / off control of the control signal VEQn-1, and the MOS transistor EQn The potential of the control gate CGn and the potential of the control gate CG1 are equalized by the on / off control of the control signal VEQn. MOS transistors EQ1 to EQn are independently controlled by control circuit 2. In other words, the control circuit 2 can switch on / off the MOS transistors EQ1 to EQn at an arbitrary timing.

  Here, the “H” state of the control signals VEQ1 to VEQn is “VPGM + threshold value of the transfer gate transistors (MOS transistors EQ1 to EQn)”, and the “L” state is “VSS”.

  FIG. 6 is a timing chart showing a write operation of the semiconductor memory device according to the second embodiment. In this example, data is written in the memory cell transistor MT connected to the control gate CG2, the control gates CG1, CG4 to CGn are boosted to the voltage level VUSEL, and the control gate CG3 is boosted to the voltage level VUSEL. explain. Also, the times t0 to t3 in FIG. 6 are not necessarily the same times as the times t0 to t3 in FIG.

  As shown in FIG. 6, first, at time t0, the control signals VSW1 to VSWn are set to the “H” level. Thereby, all of the MOS transistors CGSW1 to CGSWn are turned on, and charging by the power supply circuit 21 is started in all of the control gates CG1 to CGn.

  At this time, the control signals VEQ1 to VEQn are set to the “H” level in advance. That is, all the MOS transistors EQ1 to EQn are turned on, and the potentials of the control gates CG1 to CGn are equalized. Note that the control signals VEQ1 to VEQn may be set to the “H” level simultaneously with the control signals VSW1 to VSWn at time t0 even if they are not set to the “H” level in advance.

  Next, at time t1, the control signal VSW3 is set to the “L” level, and the MOS transistor CGSW3 is turned off. At the same time, control signals VEQ2 and VEQ3 are also set to "L" level, and MOS transistors EQ2 and EQ3 are turned off. As a result, the control gate CG3 enters a floating state.

  At this time, direct charging of the control gate CG3 by the power supply circuit 21 is completed, but the control gate CG3 receives coupling noise until the boosting of the control gate CG2 is completed via the coupling capacitance of the adjacent control gate CG. to continue. At this time t1, the voltage of the control gate CG3 is boosted by the coupling noise received from the control gate CG1 and the like from the voltage VUSELL (the voltage reached by the control gate CG3 when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage is shown.

  The MOS transistor CGSW3 is controlled according to the coupling noise from the control gate CG2. That is, when the control gate CG2 is boosted to the voltage level VPGM (after time t3 described later), the MOS transistor CGSW3 is turned off at a timing (time t1) at which the control gate CG3 is boosted to the voltage level VUSELL. Control.

  Next, at time t2, the control signals VSW1, VSW4 to VSWn are set to the “L” level, and the MOS transistors CGSW1, CGSW4 to CGSWn are turned off. At the same time, the control signal VEQ1 is also set to the “L” level, and the MOS transistor EQ1 is turned off. Thereby, the control gates CG1, CG4 to CGn are in a floating state.

  At this time, direct charging by the power supply circuit 21 of the control gates CG1, CG4 to CGn is completed, but coupling noise continues to be received until the boosting of the control gate CG2 is completed. At this time t2, the voltage of the control gates CG1, CG4 to CGn is from the control gate CG2 from the voltage VUSEL (the voltage reached by the control gates CG1, CG4 to CGn when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage boosted by the coupling noise received is shown.

  However, since the potentials of the control gates CG1, CG4 to CGn are equalized with each other, the coupling ratio is larger than that of the control gate CG2. For this reason, the coupling noise from the control gate CG2 to the control gates CG1, CG4 to CGn is reduced (substantially negligible). In other words, without considering the coupling noise from the control gate CG2, the MOS transistors CGSW1, CGSW4 to CGSWn are controlled to be turned off at a timing at which the control gates CG1, CG4 to CGn are boosted to the voltage level VUSEL.

  Thereafter, at time t3, the control gate CG2 is boosted to the voltage level VPGM. Accordingly, the boosting of control gates CG1, CG3 to CGn due to coupling noise from control gate CG2 is completed. That is, the control gate CG3 is boosted to VUSEL, and the control gates CG1, CG4 to CGn are boosted to VUSEL.

  The on / off timing control of the control gate switches CGSW1 to CGSWn described above can be controlled by the control circuit 2. Also, from time t1 to time t2, the magnitude of the boosted voltage level of the non-write target control gate CG and the coupling noise (coupling capacitance) from the write target control gate CG to the non-write target control gate CG The time is preset according to the size. Here, the time t2 is a time that can be set relatively easily without considering the coupling noise because the influence of the coupling noise on the control gates CG1, CG4 to CGn is small.

[effect]
According to the second embodiment, the same effect as in the first embodiment can be obtained.

  Furthermore, in the second embodiment, a MOS transistor EQ that functions as an equalizer is provided between the control gates CG. This makes it possible to equalize the potential of the non-write target control gate CG boosted to the same voltage level during the write operation. That is, the coupling ratio of the plurality of equalized non-write target control gates CG can be increased with respect to the write target control gate CG, and the coupling noise can be substantially ignored. Therefore, the on / off timing of the MOS transistor CGSW can be easily controlled as compared with the first embodiment.

  In the second embodiment, when the voltage is boosted to one different voltage level as in the control gate CG3, the controllability is the same as in the first embodiment. However, when two or more non-write target control gates CG charged to the same voltage level are adjacent to each other, the above-described control method for turning on the equalizer can increase the coupling ratio to the write target control gate CG. it can. For this reason, coupling noise can be reduced and controllability can be improved.

  Further, when the voltage levels of all the non-write target control gates CG are the same (for example, VUSEL), all the non-write target control gates CG are connected by an equalizer, so that the cup to the write target control gate CG is connected. The ring ratio can be maximized and further controllability can be improved.

<Third Embodiment>
The semiconductor memory device according to the third embodiment will be described below with reference to FIGS. The third embodiment is a modification of the second embodiment, and is an example in which the ON / OFF timing control of the MOS transistors CGSW1 to CGSWn and the MOS transistors EQ1 to EQn is performed by detecting the voltage of the control gate. is there. Note that in the third embodiment, a description of the same points as in the above-described embodiments will be omitted, and different points will be described.

[Circuit configuration and write operation]
FIG. 7 is a circuit diagram showing a semiconductor memory device according to the third embodiment. Here, the circuit configuration of the sense amplifier S / A5 and the row decoder 3 and the circuit configuration of the memory cell array 6 shown in FIG. 2 are omitted, and particularly the connection between the power supply circuit 21 and the control gates CG1 to CGn is shown. Yes.

  As shown in FIG. 7, the third embodiment is different from the second embodiment in that a control gate voltage detection circuit 22 and a VSW / VEQ control circuit 23 are connected to a control gate CG. Here, the control gate voltage detection circuit 22 and the VSW / VEQ control circuit 23 are included in the control circuit 2 shown in FIG.

  The control gate voltage detection circuit 22 includes resistors R11, R12, R21 and R22, and operational amplifiers AMP1 and AMP2.

  A control gate CG1 is connected to one end of the resistor R11. One end of the resistor R12 is connected to the other end of the resistor R11, and these are connected in series. A ground point is connected to the other end of the resistor R12. A node MON1, which is a connection point between the resistors R11 and R12, is connected to the negative side input terminal of the voltage comparison circuit AMP1. A reference voltage VREF is connected to the positive side input terminal of the voltage comparison circuit AMP1. That is, the voltage of the control gate CG1 is detected by being divided by the resistors R11 and R12 and then compared with the reference voltage VREF by the voltage comparison circuit AMP1.

  In the voltage comparison circuit AMP1, the FLG signal 1 is output as “L” level if the voltage of the node MON1 is higher than the reference voltage VREF, and is output as “H” level if it is smaller. The FLG signal 1 is a detection signal for detecting the voltage level VUSEL.

  On the other hand, a control gate CG1 is connected to one end of the resistor R21. One end of the resistor R22 is connected to the other end of the resistor R21, and these are connected in series. A ground point is connected to the other end of the resistor R22. A node MON2, which is a connection point between the resistors R21 and R22, is connected to the negative side input terminal of the voltage comparison circuit AMP2. A reference voltage VREF is connected to the positive side input terminal of the voltage comparison circuit AMP2. That is, the voltage of the control gate CG2 is detected by being divided by the resistors R21 and R22 and then compared with the reference voltage VREF by the voltage comparison circuit AMP2.

  In the voltage comparison circuit AMP2, if the voltage of the node MON2 is larger than the reference voltage VREF, the FLG signal 2 is outputted as “L” level, and if smaller, it is outputted as “H” level. The FLG signal 2 is a detection signal for detecting the voltage level VUSEL.

  Thus, the voltage of the node MON1 is determined by the ratio of R11 and R12, and the voltage of the node MON2 is determined by the ratio of R21 and R22. VREF is a constant voltage. That is, the detection level of VUSEL and VUSEL can be changed by changing the voltage of the control gate CG1 to the respective voltages of the nodes MON1 and MON2.

  In other words, the voltage comparison circuit AMP1 is a circuit that detects whether or not the voltage of the control gate CG1 exceeds VUSEL, and the voltage comparison circuit AMP2 is a circuit that detects whether or not the voltage of the control gate CG1 exceeds VUSEL. . Although FIG. 7 shows an example in which the voltage of the control gate CG1 is detected by the control gate voltage detection circuit 22, the control gate voltage detection circuit 22 can be connected to the control gates CG2 to CGn. For example, in the write operation, the control gate voltage detection circuit 22 can be appropriately connected so as to detect the voltage of the control gate CG to be written. That is, by detecting the voltage of the control gate CG to be written, it is possible to recognize the voltage of the control gate CG to be non-written that is boosted in synchronization therewith. As a result, charging can be stopped when the non-write target control gate CG is boosted to a desired voltage level.

  The VSW / VEQ control circuit 23 is connected to the output terminals of the voltage comparison circuit AMP1 and the voltage comparison circuit AMP2. That is, the FLG signal 1 and the FLG signal 2 output from the voltage comparison circuit AMP1 and the voltage comparison circuit AMP2 are input to the VSW / VEQ control circuit 23. The VSW / VEQ control circuit 23 controls the “H” level / “L” level of the control signals VSW1 to VSWn and the control signals VEQ1 to VEQn according to the FLG signal 1 and the FLG signal 2.

  The control of the control signals VSW1 to VSWn and the control signals VEQ1 to VEQn by the VSW / VEQ control circuit 23 corresponding to the FLG signal 1 and the FLG signal 2 will be described in detail below.

  FIG. 8 is a timing chart showing the write operation of the semiconductor memory device according to the third embodiment. In this example, data is written in the memory cell transistor MT connected to the control gate CG2, the control gates CG1, CG4 to CGn are boosted to the voltage level VUSEL, and the control gate CG3 is boosted to the voltage level VUSEL. explain. Further, the times t0 to t3 in FIG. 8 are not necessarily the same times as the times t0 to t3 in FIGS.

  As shown in FIG. 8, first, at time t0, the control signals VSW1 to VSWn are set to the “H” level. Thereby, all of the MOS transistors CGSW1 to CGSWn are turned on, and charging by the power supply circuit 21 is started in all of the control gates CG1 to CGn.

  At this time, the control signals VEQ1 to VEQn are set to the “H” level in advance. Further, since the voltages of the nodes MON1 and MON2 are smaller than the reference voltage VREF, the FLG signal 1 and the FLG signal 2 are set to the “H” level.

  Next, at time t1, the voltage level VUSELL-VGBL is detected by the voltage comparison circuit AMP2, and the FLG signal 2 is set to the “L” level. That is, the voltage of the node MON2 becomes larger than the reference voltage VREF. As a result, the VSW / VEQ control circuit 23 sets the control signal VSW3 to the “L” level and turns off the MOS transistor CGSW3. Note that VGBL is a voltage for correcting in anticipation of a potential difference in which the control gate CG3 is boosted by the coupling capacitor after time t1, and the correction amount can be adjusted by the ratio of R21 and R22. At the same time, control signals VEQ2 and VEQ3 are set to "L" level, and MOS transistors EQ2 and EQ3 are turned off. As a result, the control gate CG3 enters a floating state.

  That is, at time t1, the voltage of the control gate CG3 is boosted by the coupling noise received from the control gate CG1 and the like from the voltage VUSELL (the voltage reached by the control gate CG3 when the control gate CG2 is boosted to the voltage level VPGM). The time at which the voltage obtained by subtracting the applied voltage is reached is shown.

  Next, at time t2, the voltage level VUSEL-VGB is detected by the voltage comparison circuit AMP1, and the FLG signal 1 is set to the “L” level. That is, the voltage of the node MON1 becomes higher than the reference voltage VREF. Accordingly, the VSW / VEQ control circuit 23 sets the control signals VSW1, VSW4 to VSWn to the “L” level, and turns off the MOS transistor CGSW3. At the same time, the control signal VEQ1 is also set to the “L” level, and the MOS transistor EQ1 is turned off. Thereby, the control gates CG1, CG4 to CGn are in a floating state. VGB is a voltage for correcting in anticipation of a potential difference in which the control gates 1 and CG4 to CGn are boosted by the coupling capacitance after t2, and the correction amount can be adjusted by the ratio of R11 and R12.

  That is, at time t2, the voltage of the control gates 1, CG4 to CGn is controlled from the voltage VUSEL (the voltage reached by the control gates 1, CG4 to CGn when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage boosted by the coupling noise received from is shown.

  Thereafter, at time t3, the control gate CG2 is boosted to the voltage level VPGM. Accordingly, the boosting of control gates CG1, CG3 to CGn due to coupling noise from control gate CG2 is completed.

  The above-described on / off timing control of the control gate switches CGSW1 to CGSWn can be controlled by the control gate voltage detection circuit 22 and the VSW / VEQ control circuit 23 included in the control circuit 2. Here, in the third embodiment, times t1 to t2 are times set by boosting while detecting the voltage level of the control gate CG. That is, when the voltage level of the non-write target control gate CG reaches a desired level, the MOS transistors CGSW1 to CGSWn are turned on / off according to the “H” level / “L” level of the FLG signal 1 and the FLG signal 2. Off timing control is performed.

[effect]
According to the third embodiment, the same effect as in the second embodiment can be obtained.

  Furthermore, in the third embodiment, a control gate voltage detection circuit 22 and a VSW / VEQ control circuit 23 are provided. Thereby, it is possible to increase the voltage while detecting the voltage level of the non-write target control gate CG during the write operation. That is, on / off timing control of the MOS transistors CGSW1 to CGSWn can be performed after determining that the voltage level of the non-write target control gate CG has actually reached a desired level. Therefore, it is possible to control the voltage level boost of the non-write target control gate CG more accurately.

<Fourth Embodiment>
The semiconductor memory device according to the fourth embodiment will be described below with reference to FIGS. The fourth embodiment is a modification of the second embodiment. In the second embodiment, every time charging is completed, the control gate is disconnected from the power supply circuit as needed. For this reason, the load capacity for the power supply circuit is gradually reduced. When the load capacity to the power supply circuit is reduced, the control gate CG to be written is rapidly boosted, and it becomes difficult to suppress the coupling noise to the non-write control gate.

  On the other hand, in the fourth embodiment, the load capacity for the power supply circuit corresponding to the number of control gates to be charged is detected, and the current supply by the power supply circuit (such as a charge pump) is made variable according to this additional capacity. It is an example. Note that in the fourth embodiment, a description of the same points as in the above-described embodiments will be omitted, and different points will be described.

[Circuit configuration and write operation]
FIG. 9 is a circuit diagram showing a semiconductor memory device according to the fourth embodiment. Here, the circuit configuration of the sense amplifier S / A5 and the row decoder 3 and the circuit configuration of the memory cell array 6 shown in FIG. 2 are omitted, and particularly the connection between the power supply circuit 21 and the control gates CG1 to CGn is shown. Yes.

  As shown in FIG. 9, the fourth embodiment is different from the second embodiment in that a VSW control circuit 24 and a clock generation circuit 25 are connected to a power supply circuit (charge pump) 21. Here, the VSW control circuit 24 and the clock generation circuit 25 are included in the control circuit 2 shown in FIG.

  The VSW control circuit 24 is connected to the gates of the MOS transistors CGSW1 to CGSWn, and controls the “H” level / “L” level of the control signals VSW1 to VSWn. More specifically, during the write operation, the VSW control circuit 24 increases the voltage level of the non-write target control gate CG and the write target control gate CG to the non-write target control gate CG. On / off timing control is performed at a preset time according to the magnitude of the coupling noise.

  At this time, the VSW control circuit 24 measures the number of MOS transistors CGSW1 to CGSWn that are turned on. In other words, the number of control gates CG charged by the power supply circuit 21 is measured. Thereby, the VSW control circuit 24 detects the load capacity with respect to the power supply circuit 21 according to the number of control gates CG to be charged. For example, the load capacity for the power supply circuit 21 increases when the number of charged control gates CG is large, and decreases when the number is small. The VSW control circuit 24 outputs information (signal) related to the load capacity for the power supply circuit 21 detected as described above to the clock generation circuit 25.

  The clock generation circuit 25 receives a signal related to the load capacity for the power supply circuit 21 output from the clock generation circuit 25. The clock generation circuit 25 generates a clock with an appropriate period based on a signal related to the load capacity for the power supply circuit 21. More specifically, when the number of charged control gates CG is large (the load capacity for the power supply circuit 21 is large), the clock cycle is shortened. On the other hand, when the number of charged control gates CG is small (the load capacity for the power supply circuit 21 is small), the clock cycle is delayed.

  The power supply circuit 21 supplies current to the control gates CG1 to CGn according to the clock generated by the clock generation circuit 25 and charges them. More specifically, when the clock cycle generated by the clock generation circuit 25 is early, the peak current supplied from the power supply circuit 21 to the control gates CG1 to CGn increases, and the control gates CG1 to CGn are charged (boost) quickly. Is done. On the other hand, when the clock cycle generated by the clock generation circuit 25 is slow, the peak current supplied from the power supply circuit 21 to the control gates CG1 to CGn decreases, and the control gates CG1 to CGn are charged (boosted) slowly.

  FIG. 10 is a timing chart showing a write operation of the semiconductor memory device according to the fourth embodiment. In this example, data is written in the memory cell transistor MT connected to the control gate CG2, the control gates CG1, CG4 to CGn are boosted to the voltage level VUSEL, and the control gate CG3 is boosted to the voltage level VUSEL. explain. Further, the times t0 to t3 in FIG. 10 are not necessarily the same times as the times t0 to t3 in FIGS.

  As shown in FIG. 10, first, at time t0, the control signals VSW1 to VSWn are set to the “H” level. Thereby, all of the MOS transistors CGSW1 to CGSWn are turned on, and charging by the power supply circuit 21 is started in all of the control gates CG1 to CGn.

  At this time, a first clock having a first period is generated from the clock generation circuit based on the load capacity to the power supply circuit 21 detected by the VSW control circuit 24, and the power supply circuit 21 supplies current according to the first clock. doing.

  Next, at time t1, the control signal VSW3 is set to the “L” level, and the MOS transistor CGSW3 is turned off. At the same time, control signals VEQ2 and VEQ3 are also set to "L" level, and MOS transistors EQ2 and EQ3 are turned off. As a result, the control gate CG3 enters a floating state.

  At this time, direct charging by the power supply circuit 21 of the control gate CG3 is completed, but coupling noise continues to be received until the boosting of the control gate CG2 is completed. At this time t1, the voltage of the control gate CG3 is boosted by the coupling noise received from the control gate CG1 and the like from the voltage VUSEL (the voltage reached by the control gate CG3 when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage is shown.

  At this time, a second clock having a second period is generated from the clock generation circuit based on the load capacity to the power supply circuit 21 detected by the VSW control circuit 24, and the power supply circuit 21 supplies current according to the second clock. To do. The second clock is a clock having a slower cycle than the first clock. That is, the current supplied from the power supply circuit 21 is smaller than when the first clock is generated. However, since the number of control gates CG to which current from the power supply circuit 21 is supplied (charged) is decreasing, the boosting speed of the control gate CG is constant. Here, the control gates CG1, CG2, CG4 to CGn are then boosted.

  Next, at time t2, the control signals VSW1, VSW4 to VSWn are set to the “L” level, and the MOS transistors CGSW1, CGSW4 to CGSWn are turned off. At the same time, the control signal VEQ1 is also set to the “L” level, and the MOS transistor EQ1 is turned off. Thereby, the control gates CG1, CG4 to CGn are in a floating state.

  At this time, direct charging by the power supply circuit 21 of the control gates CG1, CG4 to CGn is completed, but coupling noise continues to be received until the boosting of the control gate CG2 is completed. At this time t2, the voltage of the control gates CG1, CG4 to CGn is from the control gate CG2 from the voltage VUSEL (the voltage reached by the control gates CG1, CG4 to CGn when the control gate CG2 is boosted to the voltage level VPGM). The time when the voltage reached by subtracting the voltage boosted by the coupling noise received is shown.

  At this time, a third clock having a third period is generated from the clock generation circuit based on the load capacity to the power supply circuit 21 detected by the VSW control circuit 24, and the power supply circuit 21 supplies a current according to the third clock. To do. The third clock is a clock having a slower cycle than the second clock. That is, the current supplied from the power supply circuit 21 is smaller than when the second clock is generated. However, since the number of control gates CG to which current from the power supply circuit 21 is supplied (charged) is decreasing, the boosting speed of the control gate CG is constant. Here, only the control gate CG2 is boosted thereafter.

  Thereafter, at time t3, the control gate CG2 is boosted to the voltage level VPGM. Accordingly, the boosting of control gates CG1, CG3 to CGn due to coupling noise from control gate CG2 is completed. That is, the control gate CG3 is boosted to VUSEL, and the control gates CG1, CG4 to CGn are boosted to VUSEL.

  The on / off timing control of the control gate switches CGSW1 to CGSWn described above can be controlled by the VSW control circuit 24 included in the control circuit 2. Here, in the fourth embodiment, the time t1 to t2 includes the magnitude of the boosted voltage level of the non-write target control gate CG and the cup from the write target control gate CG to the non-write target control gate CG. The time is preset according to the magnitude of the ring noise (coupling capacitance).

[effect]
According to the fourth embodiment, the same effect as in the second embodiment can be obtained.

  Furthermore, in the fourth embodiment, a VSW control circuit 24 and a clock generation circuit 25 are provided. As a result, during the write operation, the supply of current by the power supply circuit 21 can be made variable according to the number of control gates CG to be charged. That is, the voltage can be boosted to the voltage level VPGM while keeping the boosting speed of the control gate CG to be written constant. Thereby, after the MOS transistor CGSW of the non-write target control gate CG is turned off, the coupling noise from the write target control gate CG to the non-write target control gate CG can be easily assumed. Therefore, the on / off timing control of the non-write target MOS transistors CGSW1 to CGSWn can be easily performed.

  In the present embodiment, the current supplied from the power supply circuit 21 is adjusted using the clock generation circuit 25, but the current adjustment method is not limited to this. For example, a charge pump may be used as the power supply circuit 21. More specifically, in the charge pump, the number of pump stages is dynamically changed based on the number of control gates CG to be charged. Thereby, the supplied current can be made variable, and the boosting speed of the control gate CG to be written can be made constant.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  MT: Memory cell transistor, WL1 to WLn: Word line, CG1 to CGn: Control gate, CGSW1 to CGSWn: MOS transistor (control gate switch), EQ1 to EQn: MOS transistor (equalizer switch), 2 ... Control circuit, 21 ... Power supply circuit, 22 ... control gate voltage circuit, 23 ... VSW / VEQ control circuit, 24 ... VSW control circuit, 25 ... clock generation circuit.

Claims (6)

A first word line connected to the first memory cell;
A second word line connected to the second memory cell;
A third word line connected to the third memory cell;
A control circuit that controls a write operation to each of the memory cells and includes a power supply circuit electrically connected to the first word line, the second word line, and the third word line;
A first transfer switch provided between the first word line and the power supply circuit;
A second transfer switch provided between the second word line and the power supply circuit;
A third transfer switch provided between the third word line and the power supply circuit;
Comprising
The control circuit includes:
Driving the power supply circuit in a write operation to the first memory cell;
At the first time, the first transfer switch, the second transfer switch, and the third transfer switch are turned on to supply current to the first word line, the second word line, and the third word line. Boosting the first word line, the second word line, and the third word line,
At a second time after the first time, the electrical connection between the power supply circuit and the second word line is cut off to place the second word line in a floating state, and the second word line passes through the first write path. At a third time after reaching the voltage and at the third time, the electrical connection between the power supply circuit and the third word line is cut off so that the third word line is in a floating state, and the third word line is A semiconductor memory device that reaches the second write pass voltage. A first equalizer switch that connects between the first word line and the second word line and equalizes potentials of the first word line and the second word line;
A second equalizer switch that connects between the second word line and the third word line and equalizes potentials of the second word line and the third word line;
Further comprising
When the first write pass voltage and the second write pass voltage are the same, and the second time and the third time are the same, the control circuit, in the write operation of the first memory cell transistor, After turning on the first equalizer switch and the second equalizer switch at the first time and turning on the second equalizer switch at the second time, the first equalizer switch is turned off and the second word is turned on. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is in a floating state in a state where a line is connected to the third word line. The control circuit further includes a voltage detection circuit that detects a voltage of the first word line during a write operation,
In the write operation of the first memory cell transistor, the voltage detection circuit detects that the second word line has reached the first write pass voltage level to set the second time, and the third word 3. The semiconductor memory device according to claim 1, wherein the third time is set by detecting that a line has reached the second write pass voltage level. 4. The control circuit further includes a transfer switch control circuit that detects the number of switches that are on among the first transfer switch, the second transfer switch, and the third transfer switch,
In the write operation of the first memory cell transistor, the first word line is set so that the boosting speed of the first word line is constant according to the number of switches in the on state detected by the transfer switch control circuit. The semiconductor memory device according to claim 1, wherein a supply current by the power supply circuit is made variable.   3. The semiconductor according to claim 2, wherein the first transfer switch, the second transfer switch, the third transfer switch, the first equalizer switch, and the second equalizer switch are configured by MOS transistors. Storage device. A first word line connected to the first memory cell;
A second word line connected to the second memory cell;
A control circuit that controls a write operation to each of the memory cells and includes a power supply circuit electrically connected to the first word line and the second word line;
A first transfer switch provided between the first word line and the power supply circuit;
A second transfer switch provided between the second word line and the power supply circuit;
Comprising
The control circuit includes:
Driving the power supply circuit in a write operation to the first memory cell;
At a first time, the first transfer switch and the second transfer switch are turned on, current is supplied to the first word line and the second word line, and the first word line and the second word line are boosted Let me
At a second time after the first time, the electrical connection between the power supply circuit and the second word line is disconnected to make the second word line floating, and the second word line reaches the write pass voltage. A semiconductor memory device characterized by arriving.

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