JP2013004870A - Method of manufacturing electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an electronic component which can form a protrusion-like conductor having high connection reliability on a surface layer electrode.SOLUTION: A cover layer part 108 of a ceramic capacitor is formed in a state that a plurality of level difference correcting insulation layers 151 are interposed between ceramic insulation layers 150 at positions corresponding to a circumference of each via-conductor 131. During exposure of a photoresist film 180, the exposure is performed so that a laser 202 entered in order to expose to light an outside region R2 of a predetermined formation region R1 for forming a protrusion-like conductor hits a surface layer electrode 111 and changes its orientation, and is reflected toward the outside region R2 opposite the predetermined formation region R1. A plating resist for obtaining an opening is formed by developing the photoresist film 180, and the protrusion-like conductor is formed by plating the surface layer electrode 111 that is exposed via the opening.

Description

  The present invention includes an electrode laminate portion, a cover layer portion provided so as to cover the outer surface of the electrode laminate portion, a surface layer electrode provided on the surface of the cover layer portion, and a protruding shape protruding on the surface layer electrode The present invention relates to a method for manufacturing an electronic component including a conductor.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard. In a wiring board for mounting an IC chip constituting this type of package, it has been proposed to provide a capacitor (also referred to as a “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. . For example, a wiring substrate in which a capacitor is embedded in a resin core substrate, and a wiring substrate in which a capacitor is embedded in a buildup layer formed on the front surface or the back surface of the resin core substrate have been conventionally proposed (see, for example, Patent Document 1). .

  Patent Document 1 discloses a via array type ceramic capacitor as a capacitor built in a wiring board. This ceramic capacitor includes a capacitor body in which a plurality of ceramic dielectric layers and a plurality of internal electrode layers are alternately stacked. In this capacitor body, a plurality of in-capacitor via conductors (via electrodes) that are electrically connected to the internal electrode layers through the ceramic dielectric layers are arranged in an array. Furthermore, the surface layer electrode connected to the edge part of the via conductor in a capacitor | condenser is provided in the surface and back surface of a capacitor | condenser main body.

  Each surface layer electrode in this ceramic capacitor is made of a metallized metal layer formed mainly of nickel. Further, in order to improve the connection reliability with the wiring board, a protruding conductor (copper post) made of copper is projected on the surface layer electrode by plating. Specifically, a photosensitive dry film is provided on the main surface of the capacitor main body on which the surface layer electrode is formed, and exposure / development is performed to form a plating resist having an opening. Thereafter, electrolytic copper plating is applied to the surface layer electrode exposed through the opening of the dry film to form a protruding conductor, and the plating resist is peeled off from the main surface of the capacitor body.

  Providing the protruding conductor on the surface layer electrode in this way prevents the protruding conductor from biting into the resin insulating layer constituting the wiring board when incorporated in the wiring board, thereby preventing the displacement of the ceramic capacitor. Moreover, since the contact area between the ceramic capacitor and the resin insulating layer is increased by forming the protruding conductor, the adhesion between the two is improved.

JP 2009-152415 A

  By the way, in the via array type ceramic capacitor, the clearance holes are provided in every other region in the plurality of internal electrode layers through which the via electrodes penetrate. Therefore, the number of internal electrode layers is halved around the via electrode in the capacitor body, and only that portion is formed thin. Similarly to the surface layer electrode, the via electrode is made of a metallized metal layer formed mainly of nickel. For this reason, the shrinkage of the via electrode during firing is greater than that of the surrounding ceramic dielectric layer. As the via electrode contracts, part of the surface layer electrode is also drawn inside the capacitor body. As a result, the upper surface of the via electrode and the surface layer electrode in the vicinity thereof are formed in a state where the surface is recessed. In the case where the protruding conductor is formed on the surface layer electrode having a concave surface as described above, the following problems occur.

  Specifically, when a negative type plating resist dry film is used, a portion remaining as the plating resist (a portion other than the opening for forming the protruding conductor) is exposed. At this time, if the electrode surface 115 is recessed, the incident light 202 exposed to the dry film 180 in the vicinity of the boundary with the unexposed portion should be reflected by the electrode surface 115 of the surface electrode 111 and be an unexposed portion. The portion (the portion that becomes the opening 182) is exposed (see FIG. 17). When the exposed dry film 180 is developed to form a plating resist having an opening 182, irregularities are formed on the side surface of the opening of the plating resist. In particular, as in Patent Document 1, when the plating resist dry film 180 is exposed using a direct drawing exposure machine, the incident light 202 becomes relatively strong, so that unevenness due to reflection becomes remarkable.

  After this, when electrolytic copper plating is performed to form a protruding conductor on the surface electrode 111 through the plating resist, the protruding conductor plating layer is formed so as to bite into the irregularities formed on the side surface of the opening of the plating resist. The When the plating resist is removed after the formation of the protruding conductor, a part of the plating resist (resist residue) remains on the side surface of the protruding conductor, and it becomes difficult to completely remove the plating resist.

  When the ceramic capacitor is built in the substrate, the surface of the protruding conductor is roughened by the roughening process, and the adhesion between the resin insulating layer constituting the wiring substrate and the protruding conductor is improved. However, if there is a resist residue on the side surface of the protruding conductor, the roughening treatment cannot be performed sufficiently, and the adhesion with the resin insulating layer is deteriorated. In addition, since the plating resist is inferior in water resistance as compared with the resin insulating layer of the wiring board, if a resist residue is present on the side surface of the protruding conductor, moisture easily enters from that portion.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing an electronic component capable of forming a protruding conductor having high connection reliability on a surface layer electrode.

  As means for solving the above problems (means 1), at least one main surface, an electrode laminated portion formed by laminating a plurality of ceramic insulating layers and a plurality of internal electrode layers, and lamination of the electrode laminated portions A cover layer portion made of a plurality of ceramic insulating layers provided so as to cover an outer surface in a direction; a plurality of via electrodes extending in a stacking direction of the electrode stack portion and connected to the plurality of internal electrode layers; A method of manufacturing an electronic component, comprising: a surface layer electrode provided on a surface of the cover layer portion on a surface side, connected to an end portion of the via electrode; and a protruding conductor projecting on the surface layer electrode A cover layer portion forming step of forming the cover layer portion with a step correction layer interposed between the ceramic insulating layers at positions around the via electrode; and on the surface of the cover layer portion, Shape surface electrode A surface layer electrode forming step, a film setting step of providing a photosensitive negative plating resist dry film on the cover layer portion on which the surface layer electrode is formed, and a laser using a direct drawing exposure machine. When the dry film is exposed to light, the incident laser beam is irradiated so as to sensitize the outer region of the region to be formed for forming the protruding conductors and strikes the surface layer electrode to change the direction to the outer region. An exposure step of performing exposure so as to reflect, a development step of developing the exposed dry film to form a plating resist having an opening that exposes the planned formation region on the surface of the surface electrode; and Conducting a plating process on the surface layer electrode exposed through the opening to form the protruding conductor, and forming the plating layer. There are a method of manufacturing an electronic component which comprises a stripping step to remove strike.

  According to the invention described in Means 1, in the cover layer portion forming step, the cover layer portion is formed in a state where the step correction layer is interposed between the ceramic insulating layers at positions around the via electrode. In this case, the surface around the via electrode in the cover layer portion has a shape without a dent. And in a surface layer electrode formation process, since a surface layer electrode is formed in the surface of a cover layer part, an electrode surface can be formed in convex shape. Then, in the film installation process, after a negative-type plating resist dry film having photosensitivity is provided on the cover layer, in the exposure process, irradiation is performed while scanning with a laser using a direct drawing exposure machine. The resist dry film is exposed. At this time, in the plating resist dry film, the laser is incident on the outer region of the projected conductor formation region, and the outer region is exposed. At this time, the laser which has exposed the outer region of the region to be formed hits the surface layer electrode and is reflected. Here, the incident light of the laser is not reflected to the formation planned region side (the unexposed portion side of the dry film) due to the inclination of the electrode surface of the convex surface layer electrode, but on the opposite side of the formation planned region. Reflects reliably toward a certain outer region side (the photosensitive part side of the dry film). Accordingly, when the dry resist is developed to form a plating resist in the development step, an opening having a smooth side surface with no irregularities is provided in a region where the protruding conductor is to be formed. After that, in the conductor forming step, when the surface layer electrode is plated through the opening of the plating resist, there is no unevenness on the side surface of the opening, so that the protruding conductor is formed without the plating layer biting into the side surface. Can be formed. Therefore, in the peeling step, the plating resist can be reliably removed without leaving the plating resist on the side surface of the protruding conductor. As a result, the surface roughening treatment of the protruding conductor can be reliably performed, and the connection reliability of the protruding conductor can be sufficiently ensured.

  The surface layer electrode formed in the surface layer electrode forming step may have an island-shaped electrode and a plane electrode having a larger area than the island-shaped electrode. The surface layer electrode is generally formed by a printing method using a conductive paste. In this case, the island electrode is easily formed in a convex shape, and the plane electrode is more easily formed in a flat shape than the island electrode. Accordingly, the thickness of the step correction layer corresponding to the plane electrode is formed thicker than the step correction layer corresponding to the island electrode, or the step correction layer corresponding to the plane electrode is formed more than the step correction layer corresponding to the island electrode. It is more preferable to increase the number of layers. Furthermore, the area of the step correction layer corresponding to the plane electrode may be made larger than the step correction layer corresponding to the island electrode. In this way, the convex electrode surface can be more reliably formed in the island-like electrode and the plain-like electrode having different pattern shapes.

  In the surface layer electrode forming step, it is preferable to form the surface layer electrode so that the electrode surface corresponding to the outer region of the region to be formed is inclined toward the outer side of the region to be formed with respect to the main surface. When the surface layer electrode is formed in this way, during exposure of the dry film, the laser incident on the outside of the formation region is reliably reflected toward the outside of the formation region due to the inclination of the surface layer electrode. Therefore, the opening part which has a smooth side surface without an unevenness | corrugation can be provided in the formation plan area | region of the protruding conductor in a plating resist.

  Examples of the electronic component include a ceramic capacitor in which a ceramic insulating layer functions as a dielectric layer. In addition, as a ceramic capacitor, a via array type ceramic capacitor in which a plurality of via electrodes are arranged in an array as a whole, and clearance holes are provided so as to surround the via electrodes with a plurality of internal electrode layers in the electrode stacking portion. Is more preferable. In this ceramic capacitor, the inductance of the capacitor is reduced, and high-speed power supply for absorbing noise and smoothing power fluctuations becomes possible. In addition, it is easy to reduce the size of the entire capacitor. Furthermore, it is easy to achieve a high capacitance for a small amount, and more stable power supply is possible.

  The electronic component is preferably a substrate built-in component housed in a resin core substrate having a core main surface and a core back surface, or in a wiring laminated portion having a structure in which a resin interlayer insulating layer and a conductor layer are laminated. In this case, since the resist residue on the side surface of the protruding conductor in the electronic component is reliably removed, the roughening process of the protruding conductor can be reliably performed when the substrate is incorporated. As a result, sufficient adhesion with the resin interlayer insulating layer constituting the wiring board can be ensured. In addition, since the plating resist having poor water resistance does not remain on the side surfaces of the protruding conductor, the intrusion of moisture from the portion is avoided, and the water resistance of the wiring board can be ensured.

  The step correction layer may be the same insulating layer as the ceramic insulating layer constituting the cover layer portion, or may be the same metal layer as the internal electrode layer. In this case, it is not necessary to separately prepare a new material as a material for forming the step correction layer. Moreover, since it can bake simultaneously with a cover layer part, the increase in manufacturing cost can be suppressed.

  The step correction layer preferably has a width corresponding to the width of the clearance hole. More specifically, the step correction layer preferably has a diameter substantially equal to that of the clearance hole and is disposed at a position overlapping the clearance hole in the stacking direction of the electrode stack portion. If it does in this way, the difference in thickness by providing a clearance hole in an electrode lamination part can be controlled certainly.

  In the conductor forming step, it is preferable to form a protruding conductor having a thickness of 100 μm or more on the surface layer electrode. By forming such a protruding conductor on the surface layer electrode, the protruding conductor bites into a resin insulating layer constituting the wiring board when the wiring board is built in, thereby preventing displacement of the electronic component. Moreover, since the contact area between the electronic component and the resin insulating layer is increased by forming the protruding conductor, the adhesion between the two is improved.

  As the ceramic insulating layer constituting the electrode laminated portion and the cover layer portion, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride is preferably used, and a borosilicate type A sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding inorganic ceramic filler such as alumina to glass or lead borosilicate glass is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a capacitor having a large capacitance can be easily realized.

  The internal electrode layer, via electrode, and surface electrode are preferably metallized conductors. The metallized conductor is formed by applying a conductive paste containing metal powder by a conventionally well-known method, for example, a metallized printing method, followed by baking. When the metallized conductor and the ceramic insulating layer are formed by the simultaneous firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic insulating layer. For example, when the ceramic insulating layer is made of a so-called high-temperature fired ceramic (for example, alumina), as the metal powder in the metallized conductor, nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), etc. Those alloys can be selected. When the ceramic insulating layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu) or silver (Ag) or an alloy thereof can be selected as the metal powder in the metallized conductor.

  The resin interlayer insulating layer constituting the wiring laminated portion can be appropriately selected in consideration of insulation, heat resistance, moisture resistance and the like. Preferred examples of the material for forming the resin interlayer insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, and thermoplastic resins such as polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. Etc. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The conductor layer constituting the wiring laminated portion is mainly made of copper, and is formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. Note that a conductor layer can be formed by etching after forming a thin film by a technique such as sputtering or CVD, or a conductor layer can be formed by printing a conductive paste or the like.

1 is a schematic cross-sectional view showing a wiring board of an embodiment embodying the present invention. The schematic sectional drawing which shows a ceramic capacitor. The top view which shows a ceramic capacitor. Sectional drawing which shows the via electrode and internal electrode layer of a ceramic capacitor. The expanded sectional view which shows the principal part of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. The block diagram which shows a direct drawing exposure machine. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing of the manufacturing method of a ceramic capacitor. Explanatory drawing which shows the angle which the incident light of a laser and the electrode surface make. The top view which shows the ceramic capacitor of another embodiment. The expanded sectional view which shows the ceramic capacitor of another embodiment. The expanded sectional view which shows the ceramic capacitor of another embodiment. The schematic sectional drawing which shows the wiring board in another embodiment. Explanatory drawing which shows the exposure method in a prior art.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, the wiring board 10 of the present embodiment is a wiring board for mounting an IC chip. The wiring substrate 10 includes a resin core substrate 11 made of glass epoxy, a first buildup layer 31 formed on the core main surface 12 (upper surface in FIG. 1) of the resin core substrate 11, and a core back surface of the resin core substrate 11. 13 (lower surface in FIG. 1).

  Through holes 15 penetrating in the thickness direction are formed at a plurality of locations in the resin core substrate 11, and through hole conductors 16 are formed in the through hole 15. The through-hole conductor 16 connects the core main surface 12 side and the core back surface 13 side of the resin core substrate 11. Further, a conductor layer 41 made of copper is patterned on the core main surface 12 and the core back surface 13 of the resin core substrate 11, and each conductor layer 41 is electrically connected to the through-hole conductor 16.

  The first buildup layer 31 formed on the core main surface 12 of the resin core substrate 11 includes two resin interlayer insulating layers 33 and 35 made of thermosetting resin (epoxy resin), and a conductor layer 42 made of copper. Are alternately stacked. Terminal pads 44 are formed in an array at a plurality of locations on the surface of the second resin interlayer insulation layer 35. Further, the surface of the resin interlayer insulating layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21 having a rectangular flat plate shape. The region where each terminal pad 44 and each solder bump 45 is formed is an IC chip mounting region 23 on which the IC chip 21 can be mounted. A plurality of via conductors 43 are formed in the resin interlayer insulating layer 33, and a plurality of via conductors 43 are also formed in the resin interlayer insulating layer 35. Each via conductor 43 electrically connects the conductor layers 41 and 42 and the terminal pad 44 to each other.

  The second buildup layer 32 formed on the core back surface 13 of the resin core substrate 11 has substantially the same structure as the first buildup layer 31 described above. That is, the second buildup layer 32 has a structure in which two resin interlayer insulating layers 34 and 36 made of thermosetting resin (epoxy resin) and conductor layers 42 are alternately laminated. A plurality of via conductors 43 are formed in the resin interlayer insulating layer 34, and a plurality of via conductors 43 are also formed in the resin interlayer insulating layer 36. BGA pads 48 electrically connected to the conductor layer 42 via the via conductors 43 are formed in an array at a plurality of locations on the lower surface of the resin interlayer insulating layer 36. The lower surface of the resin interlayer insulating layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. A plurality of solder bumps 49 that can be electrically connected to a mother board (not shown) are disposed on the surface of the BGA pad 48. The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  The resin core substrate 11 has a substantially rectangular plate shape in plan view of 25 mm in length × 25 mm in width × 0.9 mm in thickness, and has a rectangular shape in plan view that opens at the center of the core main surface 12 and the center of the core back surface 13. The receiving hole 90 is provided. That is, the accommodation hole 90 is a through hole. The accommodating hole 90 has chamfered portions with chamfer dimensions of 0.1 mm or more and 2.0 mm or less at the four corners. The ceramic capacitor 101 (electronic component) is housed in the housing hole 90 in an embedded state. The ceramic capacitor 101 is accommodated with the capacitor back surface 103 facing the same side as the core main surface 12 and the capacitor main surface 102 facing the same side as the core back surface 13.

  The ceramic capacitor 101 according to the present embodiment has a substantially rectangular plate shape in plan view of 12.0 mm long × 12.0 mm wide × 0.9 mm thick. The ceramic capacitor 101 is disposed in a region immediately below the IC chip mounting region 23 in the resin core substrate 11. The area of the IC chip mounting region 23 (the area of the surface on which the surface connection terminals 22 are formed in the IC chip 21) is set to be smaller than the area of the capacitor main surface 102 of the ceramic capacitor 101. When viewed from the thickness direction of the ceramic capacitor 101, the IC chip mounting region 23 is located in the capacitor main surface 102 of the ceramic capacitor 101.

  As shown in FIG. 1, the gap between the inner surface of the accommodation hole 90 and the capacitor side surface 106 of the ceramic capacitor 101 is a resin filler made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). It is filled with 92. The resin filler 92 has a function of fixing the ceramic capacitor 101 to the resin core substrate 11. The resin filler 92 may be added with ceramic powder such as silica in order to relieve the thermal expansion difference from the ceramic capacitor 101. Moreover, in order to improve heat dissipation, metal powders, such as Cu, may be added.

  Hereinafter, the configuration of the ceramic capacitor 101 of the present embodiment will be described in detail. 2 is a cross-sectional view of the ceramic capacitor 101, and FIG. 3 is a plan view of the ceramic capacitor 101 viewed from the capacitor main surface 102 side.

  The ceramic capacitor 101 shown in FIGS. 2 and 3 is a so-called via array type ceramic capacitor. The capacitor main body 104 constituting the ceramic capacitor 101 has one capacitor main surface 102 (upper surface in FIG. 2), one capacitor rear surface 103 (lower surface in FIG. 2), and four capacitor side surfaces 106. The capacitor main body 104 includes a power laminated internal electrode layer 141, a ground internal electrode layer 142, and a ceramic dielectric layer 105 (ceramic insulating layer). And two cover layer portions 108 provided to cover the outer surface in the stacking direction.

  In the electrode laminated portion 107, the ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and is a dielectric (insulation) between the power internal electrode layer 141 and the ground internal electrode layer 142. Body). That is, the power supply internal electrode layer 141 and the ground internal electrode layer 142 are electrically insulated via the ceramic dielectric layer 105. Further, the power supply internal electrode layers 141 and the ground internal electrode layers 142 are alternately arranged via the ceramic dielectric layers 105 in the stacking direction of the ceramic dielectric layers 105. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a metallized conductor formed mainly of nickel. The number of internal electrode layers 141 and 142 is about 100.

  A large number of vias 130 are formed in the capacitor body 104. These vias 130 penetrate the capacitor main body 104 in the thickness direction (stacking direction) and are arranged in a lattice shape (array shape) over the entire surface of the capacitor main body 104. In each via 130, a plurality of in-capacitor via conductors 131 and 132 (via electrodes) that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the capacitor main body 104 are formed using nickel as a main material. In the present embodiment, since the diameter of the via 130 is set to about 100 μm, the diameter of the via conductors 131 and 132 is also set to about 100 μm.

  Each power supply capacitor internal via conductor 131 extends in the stacking direction of the electrode laminated portion 107 and penetrates each power supply internal electrode layer 141, and is electrically connected to each other (see FIG. 2). Each ground capacitor via conductor 132 extends in the stacking direction of the electrode stacked portion 107 and penetrates each ground internal electrode layer 142, and is electrically connected to each other (see FIG. 2). Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole. 3 and 4, the via conductors 131 and 132 in the capacitor are illustrated in 5 columns × 5 columns for convenience of explanation, but there are actually more columns. Further, in the plurality of internal electrode layers 141 and 142 in the electrode laminated portion 107, clearance holes 133 and 134 are provided in every other layer in a region through which the via conductors 131 and 132 pass.

  Specifically, as shown in FIGS. 2, 4, and 5, a clearance hole 133 is formed in the internal electrode layer 141 in a region through which the via conductor 132 passes, and the internal electrode layer 141 and the via conductor 132 are separated from each other. It is electrically insulated. Similarly, a clearance hole 134 is formed in the internal electrode layer 142 in a region through which the via conductor 131 passes, and the internal electrode layer 142 and the via conductor 131 are electrically insulated. The ceramic dielectric layer 105 is interposed between the internal electrode layers 141 and 142 and the via conductors 131 and 132 in the clearance holes 133 and 134.

  The cover layer portion 108 is disposed so as to be exposed at the surface layer portion of the capacitor main body 104. That is, the upper cover layer portion 108 is provided so as to cover the upper end surface of the electrode laminated portion 107, and the lower cover layer portion 108 is provided so as to cover the lower end surface of the electrode laminated portion 107. Each cover layer portion 108 includes a plurality of ceramic insulating layers 150 and a plurality of step correction insulating layers 151 (step correction layers) interposed between the ceramic insulating layers 150. Specifically, the cover layer portion 108 of the present embodiment has a structure in which four ceramic insulating layers 150 and three step correction insulating layers 151 are stacked. Each ceramic insulating layer 150 is formed using the same material (specifically, barium titanate) as the ceramic dielectric layer 105 in the electrode laminated portion 107 and is thicker than the ceramic dielectric layer 105 in the electrode laminated portion 107. . In the present embodiment, the thickness of the ceramic dielectric layer 105 is about 3 μm, and the thickness of the ceramic insulating layer 150 is about 20 μm.

  Similar to the ceramic insulating layer 150, the step correction insulating layer 151 of the present embodiment is a ceramic layer (insulating layer) formed using barium titanate as a main material. Each step correction insulating layer 151 has a width corresponding to the clearance holes 133 and 134 formed in the internal electrode layers 141 and 142, and is connected to the outer peripheral portions of the in-capacitor via conductors 131 and 132. More specifically, each of the step correction insulating layers 151 is formed in a disk shape having a diameter substantially equal to that of the clearance holes 133 and 134 and is disposed at a position around the via conductors 131 and 132 in the capacitor. In other words, each step correction insulating layer 151 is disposed at a position overlapping the clearance holes 133 and 134 in the stacking direction of the electrode stacking portion 107.

  A plurality of main surface side power surface electrode layers 111 and a plurality of main surface side ground surface layer electrodes 112 are provided on the upper surface of the cover layer portion 108 serving as the capacitor main surface 102. The main surface side power surface layer electrode 111 is directly connected to the end surface of the power source capacitor inner via conductor 131 on the capacitor main surface 102 side, and the main surface side ground surface electrode 112 is connected to the ground inner capacitor via conductor. The capacitor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  On the lower surface of the cover layer portion 108 to be the capacitor back surface 103, a plurality of back surface side power surface electrodes 121 and a plurality of back surface ground surface electrodes 122 are provided. The back surface side power surface layer electrode 121 is directly connected to the end surface of the power source capacitor via conductor 131 on the capacitor back surface 103 side, and the back surface ground surface electrode 122 is a capacitor in the ground capacitor internal via conductor 132. It is directly connected to the end surface on the back surface 103 side. Therefore, the power surface layer electrodes 111 and 121 are electrically connected to the power source capacitor via conductor 131 and the power source internal electrode layer 141, and the ground surface layer electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode. Conductive to layer 142.

  Each surface layer electrode 111, 112, 121, 122 is a circular island electrode formed of nickel as a main material, and is entirely covered with a copper plating layer 152 (see FIG. 5). Each surface layer electrode 111, 112, 121, 122 has a thickness of 10 to 20 μm and a diameter of about 300 μm. Furthermore, the surface of the copper plating layer 152 of each surface layer electrode 111, 112, 121, 122 is roughened, and the arithmetic average roughness Ra of the surface of the copper plating layer 152 is set to 0.2 μm to 0.4 μm. Yes. The “arithmetic average roughness Ra” is an arithmetic average roughness Ra defined in JIS B0601. The measurement method of arithmetic average roughness Ra shall be in accordance with JIS B0651.

  On the capacitor main surface 102 side, projecting conductors 50 are provided on the surface layer electrodes 111 and 112, respectively. These protruding conductors 50 are provided at positions corresponding to the via conductors 131 and 132 in the capacitor. Each protruding conductor 50 is a cylindrical conductor (copper post) formed by copper plating. That is, the protruding conductor 50 is formed in a columnar shape mainly composed of copper, which is the same metal material as the copper plating layer 152 of the surface layer electrodes 111 and 112. The diameter of each protruding conductor 50 is set smaller than the diameter of each surface layer electrode 111, 112 (about 300 μm) and larger than the diameter of the via conductors 131, 132 in the capacitor (about 100 μm). In this embodiment, it is set to about 250 μm. The height of the protruding conductor 50 is set to 150 μm to 200 μm. Further, the surface of each protruding conductor 50 is roughened. The arithmetic average roughness Ra of the surface of the protruding conductor 50 is set to 0.4 μm to 0.6 μm.

  As shown in FIG. 1, the surface layer electrodes 111 and 112 on the capacitor main surface 102 side are connected to a mother board (not shown) through a protruding conductor 50, a via conductor 43, a conductor layer 42, a BGA pad 48 and a solder bump 49. Is electrically connected to the electrodes of the. On the other hand, the surface layer electrodes 121 and 122 on the capacitor back surface 103 side are electrically connected to the IC chip 21 via the via conductor 43, the conductor layer 42, the terminal pad 44, the solder bump 45, and the surface connection terminal 22 of the IC chip. Is done.

  For example, when energization is performed from the motherboard side via the surface layer electrodes 111 and 112 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges are accumulated in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. In the ceramic capacitor 101, the via-conductor 131 for power supply capacitor and the via-conductor 132 for ground capacitor are alternately arranged adjacent to each other, and the via-conductor 131 for power-supply capacitor and the via-conductor 132 for ground capacitor are connected to each other. The directions of the flowing currents are set to be opposite to each other. Thereby, the inductance component is reduced.

  The ceramic capacitor 101 of the present embodiment is manufactured as follows. That is, a ceramic first green sheet having a thickness of about 5 μm (about 3 μm after firing) is formed, and a ceramic second green sheet having a thickness of about 30 μm (about 20 μm after firing) is formed. . Then, the internal electrode nickel paste is screen-printed on the first green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Also, the step-correcting ceramic paste is screen-printed on the second green sheet and dried. As a result, a step correction insulating portion that will later become the step correction insulating layer 151 is formed.

  Next, in a portion corresponding to the electrode stacking portion 107, the first green sheet on which the power supply internal electrode portion is formed and the first green sheet on which the ground internal electrode portion is formed are alternately stacked. Further, in a portion corresponding to the cover layer portion 108, the second green sheet on which the step correction insulating portion is formed is laminated (cover layer portion forming step). Here, the step correction insulating portion is disposed around a position where the via conductors 131 and 132 are formed later. Then, by applying a pressing force in the sheet stacking direction, the green sheets are integrated to form a green sheet stack.

  Further, a large number of vias 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via 130 using a paste press-fitting and filling device (not shown). Next, nickel paste for surface layer electrodes is printed on the upper surface of the green sheet laminate that is the surface of the cover layer portion 108, and the upper end surface of the conductor portion in the via 130 is mainly covered on the upper surface side of the green sheet laminate. The surface-side power surface layer electrode 111 and the main surface-side ground surface layer electrode 112 are formed (surface layer electrode forming step). Also, the nickel paste for the surface layer electrode is printed on the lower surface of the green sheet laminate, and the back surface power supply surface electrode 121 and the back surface ground are provided so as to cover the lower end surface of the conductor in the via 130 on the lower surface side of the green sheet laminate. The surface layer electrode 122 is formed.

  Thereafter, the green sheet laminate is dried to solidify the surface electrodes 111, 112, 121, and 122 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104A. The ceramic sintered body 104A includes a plurality of product regions 155 in which a plurality of product regions 155 to be the capacitor main body 104 are arranged vertically and horizontally along the plane direction, and break grooves 156 for dividing the product regions 155 are formed. Ceramic substrate (see FIG. 6).

  Next, electrolytic copper plating (thickness of about 18 μm) is performed on each surface layer electrode 111, 112, 121, 122 of the obtained ceramic sintered body 104A. As a result, a shiny copper plating layer 152 is formed on each surface layer electrode 111, 112, 121, 122. Each surface layer electrode 111, 112, 121, 122 has a surface curved in a convex shape with respect to the capacitor main surface 102 (see FIG. 7 and the like).

  Next, as shown in FIG. 7, on the capacitor main surface 102 of the ceramic sintered body 104A, a 200 μm-thick negative photoresist film 180 (plating resist dry film) having a photosensitivity is laminated (film). Installation process). Here, one having a sensitivity to light having a wavelength of 405 nm is used.

  Then, using the direct drawing exposure machine 201 shown in FIG. 8, the capacitor main surface 102 of the ceramic sintered body 104A laminated with the photoresist film 180 is irradiated while scanning the laser 202 to expose the photoresist film 180. (Exposure process). The direct drawing exposure machine 201 includes a light source 203 that emits a blue-violet laser 202 having a wavelength of 405 nm, an XY stage 204 for fixing the ceramic sintered body 104A, and an XY stage in the horizontal X and Y directions. A driving device 205 for moving 204, a CCD camera 206 for detecting dimensional variations of the ceramic sintered body 104A, a CCD camera 206 and a light source 203, a control device 207 for controlling the driving device 205, and the like are provided.

  The control device 207 photographs the markings 158 (see FIG. 6) written at the four corners of the ceramic sintered body 104A with the CCD camera 206, and detects the positions of the markings 158 in the plane direction of the ceramic sintered body 104A. The dimensions are measured for each of the X and Y directions. The control device 207 moves the XY stage 204 by driving the drive device 205 according to the dimensional variation of the ceramic sintered body 104A. Thereby, the irradiation point of the laser 202 is scanned and exposure is performed. Of course, a scanning method other than the XY stage driving method, for example, a method of moving the laser beam itself may be employed.

  When the photoresist film 180 is exposed by the direct exposure machine 201 described above, as shown in FIG. 9, a laser is used to sensitize the outer region R2 of the formation region R1 for forming the protruding conductor 50. 202 is incident. Then, the laser 202 hits the surface layer electrodes 111 and 112 to be reflected. Here, the electrode surface 115 of the surface layer electrodes 111 and 112 is formed in a convex shape, and the electrode surface 115 corresponding to the outer region R2 of the planned formation region R1 is outside the planned formation region R1 with respect to the capacitor main surface 102. It is formed to incline toward. For this reason, the laser 202 does not reflect to the formation planned region R1 side (the unexposed portion side of the film 180), but goes to the outer region R2 (the photosensitive portion side of the film 180) on the opposite side of the formation planned region R1. Reflects reliably.

  Further, as shown in FIG. 10, the photoresist film 180 exposed by the direct exposure process is developed, and a plating resist 181 (thickness 200 μm) having an opening 182 (inner diameter 250 μm) exposing the surface layer electrodes 111 and 112 is obtained. ) Is formed (development process).

  Then, as shown in FIG. 11, electrolytic copper plating is performed on the surface layer electrodes 111 and 112 via the plating resist 181 (conductor formation step). Further, the plating resist 181 on the capacitor main surface 102 is removed (peeling process). As a result, as shown in FIG. 5, the protruding conductor 50 having a height of 150 μm or more and 200 μm or less is formed on the surface layer electrodes 111 and 112. Thereafter, each product region 155 is divided by the break grooves 156 of the ceramic sintered body 104A, whereby a plurality of ceramic capacitors 101 are completed.

In the above manufacturing method, the inventors changed the number of step correction insulating layers 151 in the cover layer portion 108 (step correction amounts of 0 to 4 layers) to change the ceramic capacitor 101 (samples A to E). The effect of the step correction insulating layer 151 was confirmed. Here, the inclination degree of the electrode surface 115 of the surface layer electrodes 111 and 112 formed on the capacitor main surface 102 and the presence or absence of a film residue remaining on the side surface of the protruding conductor 50 after the plating resist 181 was peeled off were confirmed. The confirmation results are shown in Table 1.

  As a method for confirming the degree of inclination of the electrode surface 115, the ceramic capacitor 101 is cut so as to pass through the center of the protruding conductor 50, and the cut surface of the cut surface is polished. Then, as shown in FIG. 12, the incident light of the laser 202 and the normal line L <b> 1 of the electrode surface 115 at the outer peripheral portion of the protruding conductor 50 (contact point between the outer peripheral surface of the protruding conductor 50 and the electrode surface 115). The angle θ formed was measured. Here, a case where the normal line L1 of the electrode surface 115 is on the protruding conductor 50 side is a negative angle, and a case where the normal line L1 is on the opposite side of the protruding conductor 50 is a positive angle. In addition, angle (theta) is calculated | required as an average value of 20 about each ceramic capacitor 101 of samples A-E. In addition, regarding the presence or absence of film residue, 20 ceramic capacitors 101 were observed, and the ratio of film residue was confirmed.

  In the ceramic capacitor 101 (sample A) in which the step correction insulating layer 151 is not formed, since the electrode surface 115 of the surface layer electrodes 111 and 112 is recessed, the normal line L1 between the laser 202 and the electrode surface 115 in the outer peripheral portion of the protruding conductor 50. The angle θ formed by is 11 °. That is, the electrode surface 115 is inclined toward the protruding conductor 50 with respect to the capacitor main surface 102. For this reason, when the photoresist film 180 is exposed, the laser 202 is reflected to the formation planned region R1 side which is the unexposed portion side of the film 180. In this case, the formation planned region R1 that should originally be the unexposed portion of the film 180 is partially exposed, and the side surfaces of the protruding conductor 50 are uneven. As a result, a part of the plating resist 181 remains on the side surface of the protruding conductor 50 after the peeling process.

  Specifically, as shown in Table 1, in the ceramic capacitor 101 of Sample A, it was confirmed that 19 out of 20 (95%) had a film residue on the side surface of the protruding conductor 50. Further, in the ceramic capacitor 101 of Sample B, the formation of the single step correction insulating layer 151 in the cover layer portion 108 reduces the angle θ of the normal L1 to −7 °, and the ratio of the film residue is 20 pieces. It decreased to 13 (65%). Further, in the ceramic capacitor 101 of the sample C, the two steps of the step correction insulating layer 151 are formed, so that the angle θ of the normal line L1 is reduced to −3 °, and the film residue ratio is 5 out of 20 ( 25%).

  In the ceramic capacitors 101 of Samples D and E in which three or more step correction insulating layers 151 are formed, the angle θ between the laser 202 and the normal L1 of the electrode surface 115 is a positive angle (2 °, 5 °). It has become. That is, the electrode surface 115 is inclined to the opposite side of the protruding conductor 50 with respect to the capacitor main surface 102. For this reason, when performing exposure of the photoresist film 180, the laser 202 reflects to the outer region R2 (the photosensitive portion side of the film 180) of the formation scheduled region R1. As a result, the side surface of the opening 182 of the plating resist 181 has no unevenness, and the protruding conductor 50 can be patterned in the opening 182. Accordingly, no film residue remains on the side surface of the protruding conductor 50, and the ratio of the film residue is 0%.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) The cover layer portion 108 of the ceramic capacitor 101 according to the present embodiment is formed in a state in which the step correction insulating layer 151 is interposed between the ceramic insulating layers 150 at the positions around the via conductors 131 and 132 in the capacitor. Has been. In this case, in the cover layer portion 108, the surface surrounding the via conductors 131 and 132 in the capacitor can be shaped without a dent. The surface layer electrodes 111 and 112 are formed by printing nickel paste on the surface of the cover layer portion 108. Therefore, the electrode surface 115 of each surface layer electrode 111, 112 can be formed in a convex shape. In the exposure step, the laser 202 is incident on the outer region R2 of the region R1 where the protruding conductor 50 is to be formed in the photoresist film 180, and the outer region R2 is exposed. At this time, the laser 202 that has exposed the outer region R <b> 2 is reflected by the surface layer electrodes 111 and 112. Here, the electrode surface 115 of the surface layer electrodes 111 and 112 has a convex shape, and the laser 202 strikes the inclined surface and changes its direction. This laser 202 does not reflect to the formation scheduled region R1 side (the unexposed portion side of the film 180), and reliably goes to the outer region R2 side (the photosensitive portion side of the film) on the opposite side of the formation scheduled region R1. Reflect on. Therefore, when the photoresist film 180 is developed and the plating resist 181 is formed in the development step, the opening 182 having a smooth side surface with no irregularities can be provided in the region R1 where the protruding conductor 50 is to be formed. When the surface layer electrodes 111 and 112 exposed through the plating resist 181 are plated, the side surface of the opening 182 is not uneven, and therefore the plating conductor 50 does not bite into the side surface. Can be formed. Therefore, in the plating resist 181 peeling step, the plating resist 181 can be reliably removed without leaving the side surface of the protruding conductor 50.

  (2) In the wiring substrate 10 of the present embodiment, the ceramic capacitor 101 is housed in the resin core substrate 11 having the core main surface 12 and the core back surface 13. In the ceramic capacitor 101, since the resist residue on the side surface of the protruding conductor 50 is removed, the roughening process of the protruding conductor 50 can be reliably performed when the substrate is built-in. As a result, sufficient adhesion with the resin interlayer insulating layer 34 and the resin filler 92 constituting the wiring board 10 can be ensured. In addition, since the plating resist 181 having poor water resistance does not remain on the side surface of the protruding conductor 50, the intrusion of moisture from that portion is avoided, and the water resistance of the wiring board 10 can be ensured.

  (3) In the wiring substrate 10 of the present embodiment, a via array type ceramic capacitor 101 is incorporated as an electronic component. In this ceramic capacitor 101, the power supply capacitor internal via conductor 131 and the ground capacitor internal via conductor 132 are alternately arranged adjacent to each other, and flow through the power supply capacitor internal via conductor 131 and the ground capacitor internal via conductor 132. The current directions are set to be opposite to each other. In this way, the inductance component in the capacitor 101 can be reduced, and high-speed power supply for absorbing noise and smoothing power fluctuations can be achieved. In addition, it is easy to reduce the size of the entire capacitor. Furthermore, it is easy to achieve a high capacitance for a small amount, and more stable power supply is possible.

  (4) In the ceramic capacitor 101 of the present embodiment, in the plurality of internal electrode layers 141 and 142 in the electrode laminated portion 107, the clearance holes 133 and 134 are provided in every other region in the region through which the via conductors 131 and 132 pass through the capacitor. It has been. Therefore, around the via conductors 131 and 132 in the capacitor in the electrode laminated portion 107, the number of the internal electrode layers 141 and 142 is halved, and only that portion is formed thin. In the ceramic capacitor 101 of the present embodiment, a step correction insulating layer 151 having a diameter substantially equal to the clearance holes 133 and 134 is provided in the cover layer portion 108, and the step correction insulating layer 151 includes the clearance holes 133 and 133. It is disposed at a position overlapping with the stacking direction of the electrode stacking portion 107 with respect to 134. The step correction insulating layer 151 can reliably suppress a difference in thickness due to the provision of the clearance holes 133 and 134 in the electrode laminated portion 107.

  (5) In the wiring substrate 10 of the present embodiment, the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the IC chip mounting region 23, so that the wiring connecting the ceramic capacitor 101 and the IC chip 21 is short. Thus, an increase in the inductance component of the wiring is prevented. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  (6) In the wiring substrate 10 of the present embodiment, since the IC chip mounting area 23 is located in the area directly above the ceramic capacitor 101, the IC chip 21 mounted in the IC chip mounting area 23 is highly rigid. And supported by a ceramic capacitor 101 having a low coefficient of thermal expansion. Therefore, in the IC chip mounting area 23, the first buildup layer 31 is not easily deformed, so that the IC chip 21 mounted in the IC chip mounting area 23 can be supported more stably. Therefore, it is possible to prevent the IC chip 21 from cracking and poor connection due to large thermal stress. Therefore, the IC chip 21 is considered to be a large IC chip of 10 mm square or more, which has a large stress (strain) due to a difference in thermal expansion and is greatly affected by thermal stress, and has a large calorific value and severe thermal shock during use. A low-k (low dielectric constant) IC chip can be used.

  In addition, you may change embodiment of this invention as follows.

  In the ceramic capacitor 101 of the above embodiment, each surface layer electrode 111, 112, 121, 122 is a circular island electrode, but the shape of the surface layer electrode 111, 112, 121, 122 may be changed as appropriate. it can. For example, as in the ceramic capacitor 101A shown in FIG. 13, the power supply surface layer electrode 111 may be formed as a circular island electrode, and the ground surface layer electrode 112A may be formed as a plane electrode having a larger area than the island electrode. Good. The ground surface electrode 112A is formed so as to surround each surface layer electrode 111, and an annular clearance 116 having a predetermined width is provided between each surface layer electrode 111 and the surface layer electrode 112A. Yes. As shown in FIG. 14, also in this ceramic capacitor 101A, a plurality of power-source capacitor via conductors 131 and a plurality of ground-capacitor via conductors 132 are provided in an array. Then, the surface layer electrode 111 is connected to the end face of the power supply capacitor inner via conductor 131, and the surface layer electrode 112 </ b> A is connected to the end faces of the plurality of ground capacitor inner via conductors 132. In addition, protruding conductors 50 project from the surface electrode 111 and the surface electrode 112A, respectively. These protruding conductors 50 are provided at positions corresponding to the via conductors 131 and 132 in the capacitor.

  In the ceramic capacitor 101 of the above embodiment, the step correction insulating layers 151 provided in the cover layer portion 108 are all formed with the same number of layers (three layers). On the other hand, in the ceramic capacitor 101A of FIG. 14, the step correction insulating layer 151 corresponding to the surface electrode 112A (plane electrode) rather than the step correction insulating layer 151 corresponding to the surface electrode 111 (island electrode). The number is increasing. Specifically, the cover layer portion 108 is formed with two step correction insulating layers 151 corresponding to the surface electrode 111 and three step correction insulating layers 151 corresponding to the surface electrode 112A. Here, the surface layer electrode 111 of the island-shaped electrode is easily formed in a convex shape, and the surface layer electrode 112A of the plain electrode is more easily formed in a flat shape than the island-shaped electrode. The reason for this will be described below.

  That is, in the surface layer electrode forming step, a mesh mask is prepared in which the portions where the surface layer electrodes 111 and 112A are to be formed are mesh portions, and the mesh mask is placed on the upper surface of the green sheet laminate. Then, after the nickel mask is supplied to the upper surface of the mesh mask with the mesh mask disposed, the nickel paste is imprinted by moving the squeegee. As a result, the surface electrodes 111 and 112A are patterned on the upper surface of the green sheet laminate through the mesh portion of the mesh mask. When patterning the surface electrodes 111 and 112A in this way, the mesh portion in the mesh mask is softer than other portions, and therefore the mesh portion is recessed by a squeegee during paste printing. In particular, since the mesh portion of the surface layer electrode 112A has a larger area than the mesh portion of the surface layer electrode 111, the amount of depression is increased. Therefore, the surface layer electrode 112A of the plain electrode is printed relatively thin on the center side. On the other hand, the surface electrode 111 of the island-like electrode is printed with a relatively uniform thickness because the area of the mesh portion is small and the amount of dent is small. Furthermore, when the mesh mask is pulled away from the green sheet laminate after paste printing, the paste remains attached to the end of the mesh portion on the mesh mask side, and the amount of paste at the end of the surface layer electrodes 111 and 112A is reduced. . From the above, the surface electrode 111 of the island-shaped electrode is more easily formed in a convex shape than the surface electrode 112A of the plain electrode. Therefore, by increasing the number of step correction insulating layers 151 corresponding to the plane electrodes rather than the step correction insulating layer 151 corresponding to the island-shaped electrodes, the surface layer electrodes 111 and the surface layer electrodes 112A having different pattern shapes are projected. The electrode surface 115 having a shape can be reliably formed.

  In addition to changing the number of step correction insulating layers 151, the thickness of the step correction insulating layers 151 and 115A may be changed as in the ceramic capacitor 101B shown in FIG. Specifically, the step correction insulating layer 151A corresponding to the surface electrode 112A of the plane electrode is formed thicker than the step correction insulating layer 151 corresponding to the surface electrode 111 of the island electrode. For example, the step correction insulating layer 151A corresponding to the surface electrode 112A of the plane electrode may be formed larger than the step correction insulating layer 151 corresponding to the surface electrode 111 of the island electrode. Even in this case, the convex electrode surface 115 can be reliably formed in the surface layer electrode 111 and the surface layer electrode 112A having different pattern shapes. In this case, when the protruding conductor 50 is formed, the photoresist film 180 can be surely exposed so that the laser 202 reflects to the outer region R2 of the region R1 to be formed, and the protruding conductor has no unevenness on the side surface. 50 can be patterned.

  In the above embodiment, the step correction insulating layer 151 made of the same material as the ceramic insulating layer 150 is formed as the step correction layer. However, the present invention is not limited to this. For example, a step correction conductor layer made of the same metallized conductor (metal layer) as the internal electrode layers 141 and 142 may be used as the step correction layer. Further, the step-correcting insulating layer 151 in the cover layer portion 108 is connected to the outer periphery of the via conductors 131 and 132 in the capacitor, but may be provided around the via conductors 131 and 132. 131 and 132 may not be connected.

  In the wiring substrate 10 of the above embodiment, the ceramic capacitors 101, 101A, and 101B are accommodated in the resin core substrate 11, but the present invention is not limited to this. As in the wiring substrate 10A shown in FIG. 16, the ceramic capacitor 101C may be accommodated in the first buildup layer 310 (wiring laminated portion) formed on the core main surface 12 of the resin core substrate 11. The first buildup layer 310 in the wiring substrate 10A is formed by alternately laminating the resin interlayer insulating layer 30 and the conductor layer 42. The ceramic capacitor 101C is formed thinner than the ceramic capacitors 101, 101A, 101B, etc. of the above embodiment. Further, in the ceramic capacitor 101C, in addition to the surface layer electrodes 111 and 112 on the capacitor main surface 102 side, the protruding conductors 50 are also formed on the surface layer electrodes 121 and 122 on the capacitor back surface 103 side.

  In the above embodiment, the exposure process is performed by irradiating the blue-violet laser 202 having a wavelength of 405 nm. However, the present invention is not limited to this. Specifically, the exposure process may be performed using an ultraviolet laser having a wavelength of 355 nm or a mercury short arc lamp having a wavelength of 365 nm to 436 nm as a light source. Even when direct exposure is performed using such a light source, the incident light becomes relatively strong. However, by forming the electrode surface 115 of the surface layer electrodes 111 and 112 into a convex shape, the reflected light is reflected on the outer region R2 side (the film surface). Reflects reliably toward the photosensitive area. As a result, the same effect as that of the above embodiment can be obtained.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the respective embodiments described above are listed below.

  (1) The method for manufacturing an electronic component according to (1), wherein the step correction layer formed in the cover layer portion forming step is a ceramic insulating layer.

  (2) The method for manufacturing an electronic component according to (1), wherein the step correction layer formed in the cover layer portion forming step is the same metal layer as the internal electrode layer.

  (3) In the means 1, the surface layer electrode includes an island-shaped electrode and a plane electrode having a larger area than the island-shaped electrode, and the step corresponding to the island-shaped electrode is formed in the cover layer portion forming step. An electronic component manufacturing method, wherein an area of the step correction layer corresponding to the plane electrode is made larger than that of a correction layer.

  (4) In the means 1, a clearance hole is provided so as to surround the via electrode with a plurality of internal electrode layers in the electrode laminated portion, and the step correction layer has a diameter substantially equal to the clearance hole. A method for manufacturing an electronic component.

  (5) In the means 1, a clearance hole is provided so as to surround the via electrode with a plurality of internal electrode layers in the electrode stack portion, and the step correction layer is formed on the electrode stack portion with respect to the clearance hole. An electronic component manufacturing method, wherein the electronic component is arranged at a position overlapping in a stacking direction.

  (6) The method for manufacturing an electronic component according to the first aspect, wherein in the conductor forming step, the protruding conductor having a thickness of 100 μm or more is formed.

DESCRIPTION OF SYMBOLS 11 ... Resin core board | substrate 12 ... Core main surface 13 ... Core back surface 30 ... Resin interlayer insulation layer 42 ... Conductor layer 50 ... Protruding conductor 101, 101A, 101B, 101C ... Ceramic capacitor as electronic component 102 ... Capacitor as main surface Main surface 103: Capacitor back surface as main surface 105 ... Ceramic dielectric layer as ceramic insulating layer 107 ... Electrode laminated portion 108 ... Cover layer portion 111 ... Main surface side power source surface electrode as surface layer electrode 112, 112A ... Surface layer electrode Main surface side ground surface electrode 115 as electrode surface 121. Rear surface power surface layer electrode as surface layer electrode 122. Back surface side ground surface electrode as surface layer electrode 131. Via conductor in power supply capacitor as via electrode 132. ... via conductor in ground capacitor as via electrode 141 ... internal electrode layer Internal electrode layer for power supply 142... Internal electrode layer for ground as internal electrode layer 150... Ceramic insulating layer 151 and 151 A. Insulating layer for step correction as step correction layer 180... Photoresist film as a dry film for plating resist 181 ... Plating resist 182 ... Opening part 201 ... Direct drawing exposure machine 202 ... Laser 310 ... First buildup layer R1 ... Scheduled region R2 ... Outer region

Claims (6)

From at least one main surface, an electrode laminated portion formed by laminating a plurality of ceramic insulating layers and a plurality of internal electrode layers, and a plurality of ceramic insulating layers provided so as to cover the outer surface of the electrode laminated portion in the laminating direction A cover layer portion, a plurality of via electrodes extending in the stacking direction of the electrode stack portion and connected to the plurality of internal electrode layers, and provided on the surface of the cover layer portion on the main surface side, A method for producing an electronic component comprising a surface layer electrode connected to an end of a via electrode, and a protruding conductor projecting on the surface layer electrode,
A cover layer portion forming step of forming the cover layer portion with a step correction layer interposed between the ceramic insulating layers at positions around the via electrode;
On the surface of the cover layer portion, a surface electrode forming step for forming the surface electrode,
On the cover layer portion on which the surface layer electrode is formed, a film installation step of providing a photosensitive negative plating resist dry film;
Irradiating while scanning with a laser using a direct drawing exposure machine, when performing exposure of the dry film, the incident laser to expose the outer region of the formation planned region for forming the protruding conductor, An exposure step of performing exposure so as to change the direction of the surface layer electrode and reflect it to the outer region;
A development step of developing the exposed dry film to form a plating resist having an opening that exposes the region to be formed on the surface of the surface layer electrode;
Conductor forming step of forming the protruding conductor by plating the surface layer electrode exposed through the opening;
And a peeling step of removing the plating resist. In the surface electrode formation step, an island electrode and a plane electrode having a larger area than the island electrode are formed as the surface electrode.
2. The electronic component according to claim 1, wherein, in the cover layer portion forming step, the thickness of the step correction layer corresponding to the plane electrode is made thicker than the step correction layer corresponding to the island-shaped electrode. Manufacturing method. In the surface electrode formation step, an island electrode and a plane electrode having a larger area than the island electrode are formed as the surface electrode.
The number of layers of the step correction layer corresponding to the plane electrode is larger than that of the step correction layer corresponding to the island-shaped electrode in the cover layer portion forming step. Manufacturing method of electronic components.   In the surface layer electrode forming step, the surface layer electrode is formed such that an electrode surface corresponding to an outer region of the formation region is inclined toward an outer side of the formation region with respect to the main surface. The manufacturing method of the electronic component of any one of Claims 1 thru | or 3.   5. The method of manufacturing an electronic component according to claim 1, wherein the electronic component is a ceramic capacitor in which the ceramic insulating layer functions as a dielectric layer. 6.   The electronic component is a component with a built-in substrate accommodated in a resin core substrate having a core main surface and a core back surface, or in a wiring laminated portion having a structure in which a resin interlayer insulating layer and a conductor layer are laminated. The manufacturing method of the electronic component of any one of Claim 1 thru | or 5.

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