JP2013098514A - Semiconductor device manufacturing method, semiconductor device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method, a semiconductor device and an electronic apparatus, which can prevent a crash of a cavity and improve connection reliability between substrates.SOLUTION: A first substrate includes a first base material having a first surface and a second surface, a sacrificial layer provided on the first base material on the first surface side, through electrodes penetrating the first base material from the first surface to the second surface, and an insulation film provided between the through electrodes and the first base material. A second substrate includes a second base material having a third surface, bumps provided on the second base material on the third surface side, and an annular conductive part provided on the second base material on the third surface side and surrounding the bumps. A semiconductor device manufacturing method comprises: a mounting process of connecting the through electrodes and the bumps in a manner of opposing the second surface and the third surface and burying a peripheral edge of the first substrate in the annular conductive part; and an etching process of forming, after the mounting process, cavities on the first base material on the first surface side by etching the sacrificial layer.

Description

  The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and an electronic apparatus.

  As a prior art, there exist some which were disclosed by patent documents 1-3, for example. That is, Patent Document 1 discloses a pyroelectric detection element having a structure supported by a support portion above a cavity portion formed by removing a sacrificial layer. Patent Document 2 discloses a through electrode penetrating between a first surface (integrated circuit forming surface) and a second surface (back surface) of silicon. And in patent document 3, when mounting an electronic circuit element on a board | substrate, the outer periphery sealing electrode which an electronic circuit element has is joined to the sealing electrode which a board | substrate has, and the outer periphery sealing electrode of A technique for sealing a chip electrode disposed inside is disclosed.

JP 2011-153851 A JP 2010-177237 A JP 2004-214469 A

  By the way, when mounting a pyroelectric detection element having a structure supported above the cavity as disclosed in Patent Document 1 on another substrate, a load at the time of mounting is applied to this pyroelectric element. The cavity may be destroyed by the load. As a method for preventing such breakage of the cavity, a method in which the pyroelectric element is mounted on the substrate before the cavity is formed and the cavity is formed after mounting is conceivable. Further, in the above mounting, as disclosed in Patent Document 3, the outer peripheral sealing electrode and the sealing electrode are connected to hermetically seal the chip electrode located inside them. Can be considered.

Here, when the pyroelectric detection element has a through electrode as disclosed in Patent Document 2, the underlayer 141 (for example, silicon oxide (SiO ₂ ) described in FIG. 3 of Patent Document 2 is used. ) And silicon nitride (made of an insulating material such as Si ₃ N ₄ ) have a structure exposed to the outside of the outer peripheral sealing electrode. For this reason, when the sacrificial layer is etched to form the cavity, the underlying layer may also be etched. When the base layer is etched, a gap is generated between the outer periphery sealing electrode and the semiconductor substrate, and an etchant or the like enters. As a result, the hermetic sealing described above may be broken and the reliability of connection between the pyroelectric element and the substrate may be reduced.
Accordingly, the present invention has been made in view of such circumstances, and a semiconductor device manufacturing method, a semiconductor device, and an electronic device that can prevent the destruction of a cavity and improve the reliability of connection between substrates. One of the purposes is to provide equipment.

In order to solve the above problems, a method for manufacturing a semiconductor device according to one embodiment of the present invention is a method for manufacturing a semiconductor device in which at least one of a first substrate and a second substrate including a semiconductor element are connected to each other. The first substrate has a first base having a first face and a second face opposite to the first face, and a first face of the first base. Provided between the provided sacrificial layer, a through electrode penetrating between the first surface and the second surface of the first base material, and between the through electrode and the first base material And the second substrate has a second base material having a third surface, and a bump provided on the third surface side of the second base material, An annular conductive portion provided on the third surface side of the second base material and surrounding the bump, and in a state where the second surface and the third surface are opposed to each other, A mounting step of connecting the through electrode and the bump and embedding a peripheral portion of the first substrate in the annular conductive portion, and etching the sacrificial layer after the mounting step to etch the first And an etching step of forming a cavity on the first surface side of the substrate.
If it is such a manufacturing method, a mounting process is performed before an etching process. In the mounting process, the cavity is not formed, and the cavity is not broken by a load applied to the first substrate. For this reason, the first substrate can be mounted on the second substrate without damaging the cavity.

  In this mounting step, the insulating film is sealed in the region surrounded by the annular conductive portion by embedding the peripheral portion of the first substrate in the annular conductive portion. Since the insulating film can be prevented from being exposed to the outside of the annular conductive portion, it is possible to prevent the insulating film from being etched in the etching process, and there is a gap between the first substrate and the second substrate. It can be prevented from occurring. Accordingly, moisture and the like can be prevented from entering the semiconductor device through the gap, and corrosion of the through electrode can be prevented. Thereby, the reliability of the connection between the first substrate and the second substrate can be improved.

  The “first substrate” of the present invention corresponds to, for example, a semiconductor chip 10 or a semiconductor chip 110 described later. As the “second substrate”, for example, a base substrate 50 described later corresponds. The “first substrate” corresponds to, for example, the substrate 1 described later, the “first surface” corresponds to, for example, the surface 1a described later, and the “second surface” includes, for example, the back surface 1b described later. Applicable. The “second substrate” corresponds to, for example, a substrate 51 described later, and the “third surface” corresponds to, for example, a surface 51a described later. Furthermore, the “insulating film” corresponds to, for example, a TSV insulating film 27 described later. As the “annular conductive portion”, for example, an annular bump 70 described later corresponds.

  The semiconductor device manufacturing method may further include a recess forming step of forming a recess on a surface of the through electrode connected to the bump before the mounting step, and in the mounting step, The through electrode and the bump may be connected in a state where the tip of the bump is placed inside the recess. With such a manufacturing method, the crushing of the bump in the mounting process can be suppressed. Thereby, it is possible to reduce the possibility that the bumps are crushed and spread in the horizontal direction, and adjacent bumps contact each other unintentionally (that is, short-circuit).

  A semiconductor device according to another aspect of the present invention is a semiconductor device in which at least one of a first substrate including a semiconductor element and a second substrate are connected to each other, and the first substrate has a first surface. And a first substrate having a second surface opposite to the first surface and having a cavity on the first surface side, and the first surface of the first substrate. And a through electrode penetrating between the second surface and an insulating film provided between the through electrode and the first base material, and the second substrate includes the first substrate A second substrate having a third surface opposite to the second surface, a bump provided on the third surface side of the second substrate and connected to the through electrode, and the second substrate An annular conductive portion that is provided on the third surface side of the base material and surrounds the bump, and a peripheral portion of the first substrate is embedded in the annular conductive portion. To. If it is such a structure, a semiconductor device can be manufactured with said manufacturing method. Therefore, it is possible to provide a semiconductor device in which the cavity is not broken and the first substrate and the second substrate are connected with high reliability.

  In the above semiconductor device, the first substrate is between the first surface and the second surface of the first base material and is closer to the peripheral portion than the through electrode. A second through electrode penetrating the position, and an insulating film is provided between the second through electrode and the first base material, and the second through electrode and the annular conductive material It is good also as the feature that the part is connected. With such a configuration, the annular conductive portion of the second substrate can be used as a terminal connected to the first substrate. For example, when the annular conductive portion is connected to the ground potential (ground), the annular conductive portion can be used as a common ground terminal for the semiconductor element and the second substrate.

Further, in the above semiconductor device, the semiconductor device is provided in a region between the second surface of the first substrate and the third surface of the second substrate and surrounded by the annular conductive portion. A resin may be further included. With such a configuration, the resin can be adhered to the first substrate and the second substrate. The connection strength between the first substrate and the second substrate can be further increased by the adhesive force acting between the resin and the first substrate and the adhesive force acting between the resin and the second substrate. . Thereby, the reliability of connection between the first substrate and the second substrate can be further increased. The “resin” in the present invention corresponds to, for example, a sealing resin 81 described later.
An electronic apparatus according to still another aspect of the present invention includes the semiconductor device described above. With such a structure, an electronic device including a semiconductor device in which the cavity is not broken and the first substrate and the second substrate are connected with high reliability can be provided.

FIG. 6 is a view showing a method for manufacturing the semiconductor device 100 according to the first embodiment. The figure which shows an example of the shape etc. of the bump 60 and the annular bump 70. FIG. 4 is a diagram showing an example of a positional relationship between a semiconductor chip 10 and an annular bump 70. FIG. 10 is a diagram showing a first modification of the semiconductor device 100. FIG. 10 is a view showing a second modification of the semiconductor device 100. FIG. 10 is a view showing a third modification of the semiconductor device 100. The figure which shows the manufacturing method of the semiconductor device 200 concerning 2nd Embodiment. The figure which shows an example of the positional relationship of the 2nd penetration electrode 20b and the cyclic | annular bump 70. FIG. FIG. 6 is a diagram showing a first modification of the semiconductor device 200. FIG. 10 is a diagram showing a second modification of the semiconductor device 200. FIG. 10 is a view showing a third modification of the semiconductor device 200.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) First Embodiment (1.1) Manufacturing Method and Configuration FIGS. 1A to 1C are cross-sectional views showing a manufacturing method of a semiconductor device 100 according to the first embodiment of the present invention. As shown in FIG. 1A, first, a semiconductor chip 10 and a base substrate 50 are prepared.

The semiconductor chip 10 includes a base material 1 made of, for example, silicon, a first insulating layer 3 formed on the surface 1a side of the base material 1, and an electrode 5 formed on the first insulating layer 3. The second insulating layer 7 formed so as to cover the electrode 5, the third insulating layer 9 formed on the second insulating layer 7, and the sacrificial layer 11 embedded in the third insulating layer 9 And an element 13 provided on the third insulating layer 9 so as to cover a part of the sacrificial layer 11 and a plug electrode 15 connecting the element 13 and the electrode 5. The first insulating layer 3, the second insulating layer 7, and the third insulating layer 9 are made of, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ). The electrode 5 is made of, for example, titanium nitride (TiN). The sacrificial layer 11 is made of, for example, a silicon oxide film. The element 13 is a pyroelectric sensor capable of detecting infrared rays, for example. The plug electrode 15 is made of, for example, tungsten (W).

  Although not shown, etching prevention is provided between the surface of the third insulating layer 9, between the second insulating layer 7 and the sacrificial layer 11, and between the third insulating layer 9 and the sacrificial layer 11. A film may be provided. Further, an etching prevention film may be provided on the side surfaces of the first insulating layer 3, the second insulating layer 7, and the third insulating layer 9. This etching prevention film is a film for preventing the second insulating layer 7 and the third insulating layer 9 from being etched in the step of etching the sacrificial layer 11 to form a cavity to be described later. . As the etching preventive film, for example, a material having corrosion resistance to hydrogen fluoride (HF) used when etching the sacrificial layer 11 made of a silicon oxide film (for example, silicon nitride film, aluminum, tungsten, etc.) is used. It is a membrane.

  The semiconductor chip 10 includes a through electrode (TSV: Through Si Via) 20 and a TSV insulating film 27 provided between the through electrode 20 and the base material 1. As shown to Fig.1 (a), the base material 1 is provided with the through-hole 21 penetrated between the surface 1a and the back surface 1b. The through electrode 20 is provided in the through hole 21 via a TSV insulating film 27. That is, the TSV insulating film 27 is provided from the inner surface of the through hole 21 to the back surface 1 b of the substrate 1. The TSV insulating film 27 is, for example, a silicon oxide film.

  The through electrode 20 is provided on, for example, a seed layer 23 formed by sputtering, an electrode main body 24 formed by electrolytic plating, and a surface (for example, a lower surface) of the electrode main body 24 on the side connected to the base substrate 50. Brazing material 25. The seed layer 23 and the electrode body 24 are, for example, copper (Cu), and the brazing material 25 is, for example, an alloy of tin and silver (Sn—Ag). The through electrode 20 having such a configuration is connected to the electrode 5 through the first insulating layer 3.

  On the other hand, the base substrate 50 includes a base material 51 made of, for example, silicon, an insulating layer 53 formed on the surface 51a side of the base material 51, a first electrode 55 formed on the insulating layer 53, and A second electrode 57, a passivation film 59 formed on the insulating layer 53 so as to cover the first electrode 55 and the second electrode 57, and a bump 60 and an annular bump formed on the passivation film 59 70. As shown in FIG. 1A, the passivation film 59 is provided with an opening having the first electrode 55 or the second electrode 57 as a bottom surface. The bump 60 is connected to the electrode 55 and the annular bump 70 is connected to the electrode 57 through this opening.

  FIG. 2 is a plan view showing an example of each shape of the bump 60 and the annular bump 70 and their positional relationship. As shown in FIG. 2, the shape of the bump 60 in plan view (hereinafter referred to as a planar shape) is, for example, a circle. The planar shape of the annular bump 70 is, for example, a rectangular frame. The annular bump 70 is disposed so as to surround the bump 60 in plan view (that is, the bump 60 is disposed in a region surrounded by the annular bump 70).

  Returning to FIG. 1A, the insulating layer 53 is made of, for example, a silicon oxide film. The first electrode 55 and the second electrode 57 are made of, for example, aluminum (Al). The bump 60 and the annular bump 70 are made of, for example, gold (Au). The passivation film 59 is made of polyimide, for example. In FIG. 1A, when the height of the bump 60 and the annular bump 70 from the passivation film 59 is h, h is, for example, 10 to 25 μm. Although not shown, between the first electrode 55 and the bump 60 and between the second electrode 57 and the annular bump 70, titanium (Ti), tungsten (W), and platinum (Pt), respectively. An intermediate layer such as copper (Cu) or chromium (Cr) may be provided.

  Next, the prepared semiconductor chip 10 and the base substrate 50 are overlapped and bonded. That is, the semiconductor chip 10 is mounted on the base substrate 50 (mounting process). Here, as shown by the arrows in FIG. 1A, the back surface 1b side of the semiconductor chip 10 and the front surface 51a side of the base substrate 50 are opposed to each other. In this state, the semiconductor chip 10 is pressed relatively to the base substrate 50 to bond the semiconductor chip 10 to the base substrate 50.

Thereby, as shown in FIG. 1B, the through electrode 20 and the bump 60 are connected, and the peripheral portion (including the side surface) 1 c of the semiconductor chip 10 is embedded in the annular bump 70. In this mounting process, the bumps 60 are crushed by joining with the through electrodes 20. When h ′ is the height from the passivation film 59 of the bump 60 after being crushed, h> h ′. h ′ is, for example, 5 to 15 μm.
FIG. 3 is a plan view showing an example of the positional relationship between the semiconductor chip 10 and the annular bump 70 after the semiconductor chip 10 is mounted on the base substrate 50. As shown in FIG. 3, in the etching process of the sacrificial layer 11, the peripheral portion 1 c of the semiconductor chip 10 is embedded in the annular bump 70 over the entire circumference.

  Next, after the mounting process, the sacrificial layer 11 is removed by etching (etching process). In this etching step, a part of the sacrificial layer 11 is exposed from below the element 13 as shown in FIGS. For this reason, the sacrificial layer 11 made of the silicon oxide film can be etched and removed by immersing the semiconductor chip 10 in the HF solution together with the base substrate 50 (or exposing the semiconductor chip 10 to an HF vapor atmosphere). As a result, as shown in FIG. 1C, the cavity 31 is formed in the semiconductor chip 10. Through the above steps, the semiconductor chip 10 and the base substrate 50 are connected, and the semiconductor device 100 having a structure having the element 13 above the cavity 31 is completed.

  The completed semiconductor device 100 has the following configuration. That is, as shown in FIG. 1C, the semiconductor device 100 includes a semiconductor chip 10 and a base substrate 50. The semiconductor chip 10 includes a base material 1 provided with a cavity 31 on the front surface 1a side, a through electrode 20 penetrating between the front surface 1a and the back surface 1b of the base material 1, and the through electrode 20 and the base material 1. TSV insulating film 27 provided between the two. The base substrate 50 includes a base material 51, bumps 60 provided on the surface 51 a side of the base material 51, and annular bumps 70 provided on the surface 51 side and surrounding the bumps 60. The through electrode 20 and the bump 60 are connected in a state where the back surface 1b of the semiconductor chip 10 and the front surface 51a of the base substrate 50 face each other, and the peripheral portion 1c of the semiconductor chip 10 is embedded in the annular bump 70. ing. Here, “the peripheral edge portion 1c of the semiconductor chip 10 is embedded in the annular bump 70” means that the corner portion formed by the side surface connecting the front surface 1a and the back surface 1b of the semiconductor chip 10 and the back surface 1b. This is a state covered with the annular bump 70.

  Although not shown, the base substrate 50 may be formed with, for example, a control circuit for controlling the semiconductor chip 10 in addition to the wiring such as the first electrode 55 or the second electrode 57. This control circuit (not shown) can be formed on the base substrate 50 by a CMOS process before the mounting process. Thus, when the control circuit is formed on the base substrate 50, for example, between the control circuit and the element 13, the through electrode 20 (in the second embodiment, the first through electrode 20 a) is routed. The signal is transmitted and received.

(1.2) Effects of the First Embodiment According to the first embodiment of the present invention, the mounting process is performed before the etching process. In the mounting process, the cavity 31 is not formed, and the cavity 31 is not broken by a load applied to the semiconductor chip 10. For this reason, the semiconductor chip 10 can be mounted on the base substrate 50 without breaking the cavity 31 formed below the element 13.

  In this mounting process, the peripheral edge 1 c of the semiconductor chip 10 is embedded in the annular bump 70. Thereby, the TSV insulating film 27 is sealed in a region surrounded by the annular bumps 70. Since the TSV insulating film 27 can be prevented from being exposed to the outside of the annular bump 70, the TSV insulating film 27 can be prevented from being etched in the etching process, and between the semiconductor chip 10 and the base substrate 50. A gap can be prevented from being generated. Since moisture and the like can be prevented from entering the semiconductor device through this gap, corrosion of the through electrode 20 and the like can be prevented. Therefore, the connection reliability between the semiconductor chip 10 and the base substrate 50 can be improved. Next, a modification of the first embodiment is shown.

(1.3) First Modification FIG. 4 is a cross-sectional view showing a first modification of the semiconductor device 100. As shown in FIG. 4, the semiconductor device 100 may include a sealing resin 81 in a region between the semiconductor chip 10 and the base substrate 50 and surrounded by the annular bumps 70. Examples of the sealing resin 81 include a thermosetting epoxy resin, a polyimide resin, and an acrylic resin. With such a configuration, the sealing resin 81 can be adhered to the semiconductor chip 10 and the base substrate 50. The connection strength between the semiconductor chip 10 and the base substrate 50 is further increased by the adhesive force acting between the sealing resin 81 and the semiconductor chip 10 and the adhesive force acting between the sealing resin 81 and the base substrate 50. Can do. Thereby, the reliability of the connection between the semiconductor chip 10 and the base substrate 50 can be further enhanced.

  The sealing resin 81 is applied to a region surrounded by the annular bump 70 of the base substrate 50, for example, before the mounting process. Then, after applying the sealing resin 81, the semiconductor chip 10 is mounted on the base substrate 50. Thereby, the sealing resin 81 can be sealed in a region between the semiconductor chip 10 and the base substrate 50 and surrounded by the annular bumps 70. When the sealing resin 81 is thermosetting, for example, the sealing resin 81 can be cured by heat during mounting.

(1.4) Second Modification FIG. 5 is a cross-sectional view showing a second modification of the semiconductor device 100. As shown in FIG. 5, the semiconductor device 100 may have an insulating resin 83 that covers the side surface of the semiconductor chip 10 on the region 71 of the annular bump 70 exposed from the semiconductor chip 10. For example, the resin 83 is applied on the region 71 in the stage shown in FIG. That is, the resin 83 is applied after the peripheral portion 1 c of the semiconductor chip 10 is embedded in the annular bump 70. Then, after applying the resin 83, the sacrificial layer 11 is etched. Examples of the resin 83 include a thermosetting or ultraviolet curable epoxy resin, a polyimide resin, and an acrylic resin.

  With such a configuration, it is possible to prevent the etchant from directly contacting the contact interface between the semiconductor chip 10 and the annular bump 70 when the sacrificial layer 11 is etched. Since the possibility that the etchant reaches the TSV insulating film 27 along the contact interface can be further reduced, the reliability of the connection between the semiconductor chip 10 and the base substrate 50 can be further improved.

(1.5) Third Modification FIG. 6 is a cross-sectional view showing a third modification of the semiconductor device 100. As shown in FIG. 6, in the manufacturing process of the semiconductor device 100, the recess 29 may be formed on the surface of the through electrode 20 on the side connected to the bump 60 (recess formation process). The concave portion 29 can be formed by adjusting the plating processing time when forming the through electrode 20 to be shorter than when the concave portion 29 is not provided (for example, in the case of FIG. 1A). . The brazing material 25 is formed so as to cover the bottom surface and the inner surface of the recess 29 after the recess 29 is formed in the through electrode 20. In the mounting process, the tip portion 61 of the bump 60 is inserted into the recess 29 to connect the through electrode 20 and the bump 60. With such a manufacturing method, the collapse of the bumps 60 can be suppressed. Thereby, it is possible to reduce the possibility that the bumps 60 are crushed and spread in the horizontal direction, and the adjacent bumps 60 contact each other unintentionally (that is, short-circuit).

(2) Second Embodiment In the first embodiment described above, the case where the peripheral portion 1 c of the semiconductor chip 10 is embedded in the annular bump 70 and the region surrounded by the annular bump 70 is sealed has been described. That is, the case where the annular bump 70 is used as a sealing material has been described. However, in the present invention, an electrode function may be added to the annular bump 70. In the second embodiment, such a form will be described.

(2.1) Manufacturing Method and Configuration FIGS. 7A to 7C are cross-sectional views illustrating a manufacturing method of the semiconductor device 200 according to the second embodiment of the present invention. As shown in FIG. 2A, first, the semiconductor chip 110 and the base substrate 50 are prepared.
The semiconductor chip 110 includes, for example, a base material 1, a first insulating layer 3, a first electrode 5a and a second electrode 5b formed on the first insulating layer 3, a first electrode 5a, A second insulating layer 7 formed so as to cover the second electrode 5b, a third insulating layer 9, a sacrificial layer 11, and an element 13 are provided. The material of the first electrode 5a and the second electrode 5b is, for example, the same as that of the electrode 5 described in the first embodiment.

In addition, the semiconductor chip 110 includes a first through electrode 20a, a second through electrode 20b, a TSV insulating film 27, and a plug electrode 15. Here, between the front surface 1a and the back surface 1b of the base material 1, the 1st through-hole 21a and the 2nd through-hole 21b which penetrate the said part are provided. The second through hole 21b is provided at a position closer to the peripheral edge 1c than the first through hole 21a. The first through electrode 20a is provided in the first through hole 21a through the TSV insulating film 27, and the second through electrode 20b is provided in the second through hole 21b through the TSV insulating film 27. It has been. Each structure and each material of the 1st penetration electrode 20a and the 2nd penetration electrode 20b are the same as the penetration electrode 20 demonstrated in 1st Embodiment.
Note that the second electrode 5b connected to the second through electrode 20b is not an electrode for connecting to the element 13, but is used as, for example, a ground electrode (that is, an electrode having a ground potential).

  Next, the prepared semiconductor chip 110 is mounted on the base substrate 50 (mounting process). Here, as shown by an arrow in FIG. 7A, the back surface 1b side of the semiconductor chip 110 and the front surface 51a side of the base substrate 50 are opposed to each other. In this state, the semiconductor chip 110 is pressed relative to the base substrate 50 to bond the semiconductor chip 110 to the base substrate 50. Thereby, as shown in FIG. 1B, the through electrode 20 a and the bump 60 are connected, and the peripheral portion (including the side surface) 1 c of the semiconductor chip 110 is embedded in the annular bump 70. At the same time, the through electrode 20 b is connected to the annular bump 70.

  FIG. 8 is a plan view showing an example of the positional relationship between the second through electrode 20 b and the annular bump 70 after the semiconductor chip 110 is mounted on the base substrate 50. As shown in FIG. 8, at least a part of the second through electrode 20b is arranged so as to overlap the annular bump 70 in plan view. Thereby, the 2nd penetration electrode 20b and the annular bump 70 are connected. For this reason, the annular bump 70 can be a ground electrode common to the semiconductor chip 110 and the base substrate 50, for example.

  Next, the sacrificial layer 11 of the semiconductor chip 110 mounted on the base substrate 50 is removed by etching (etching process). The etching method is the same as in the first embodiment. As a result, as shown in FIG. 7C, the cavity 31 is formed on the surface 1 a side of the semiconductor chip 110. Through the above steps, the semiconductor chip 110 and the base substrate 50 are connected, and the semiconductor device 200 having a structure having the element 13 above the cavity 31 is completed.

  The completed semiconductor device 200 has the following configuration. That is, as shown in FIG. 7C, the semiconductor device 200 includes the semiconductor chip 110 and the base substrate 50. The semiconductor chip 1110 includes a first through electrode 20a that penetrates between the front surface 1a and the back surface 1b of the substrate 1, and a second through electrode that penetrates a position closer to the peripheral edge 1c than the first through electrode 20a. 20b. The TSV insulating film 27 is provided between the first through electrode 20a and the base material 1 and between the second through electrode 20b and the base material 1, respectively. The first through electrode 20 a is connected to the bump 60, and the second through electrode 20 b is connected to the annular bump 70.

(2.2) Effects of Second Embodiment According to the second embodiment of the present invention, the same effects as those of the first embodiment can be obtained.
Further, according to the second embodiment of the present invention, the annular bump 70 can be used as a terminal connected to the semiconductor chip 110. For example, when the annular bump 70 is connected to the ground potential (ground), the annular bump 70 can be used as a common ground terminal for the semiconductor chip 110 and the base substrate 50.

(2.3) Modifications In the second embodiment, the same aspects as the first to third modifications described in the first embodiment can be employed. That is, as shown in FIG. 9, the semiconductor device 200 may have a sealing resin 81 in a region between the semiconductor chip 110 and the base substrate 50 and surrounded by the annular bumps 70. Thereby, the reliability of the connection between the semiconductor chip 10 and the base substrate 50 can be further enhanced.

  As shown in FIG. 10, the semiconductor device 200 may have an insulating resin 83 that covers the side surface of the semiconductor chip 110 from the region 71 exposed from the semiconductor chip 110 of the annular bump 70. Thereby, when the sacrificial layer 11 is etched, it is possible to prevent the etchant from directly contacting the contact interface between the semiconductor chip 110 and the annular bump 70. Since the possibility that the etchant reaches the TSV insulating film 27 along the contact interface can be reduced, the reliability of the connection between the semiconductor chip 110 and the base substrate 50 can be further improved.

  Further, as shown in FIG. 11, in the process of manufacturing the semiconductor device 200, the first through electrode 20a is connected to the surface on the side connected to the bump 60 and the annular bump 70 of the second through electrode 20b. The concave portions 29 may be formed on the respective surfaces (recess forming step). These recesses 29 have a shorter plating treatment time when forming the first through electrode 20a and the second through electrode 20b at the same time than when there is no recess (for example, in the case of FIG. 7A). It can be formed by adjusting to. With such a manufacturing method, the collapse of the bumps 60 can be suppressed. Thereby, the bumps 60 are crushed and spread in the horizontal direction, and the possibility that the adjacent bumps 60 come into contact with each other unintentionally can be reduced.

(3) Electronic Device, Other An electronic device according to an embodiment of the present invention includes the semiconductor device 100 (or the semiconductor device 200). In the semiconductor device included in this electronic device, the cavity located below the element is not broken, and the semiconductor chip and the base substrate are connected with high reliability. Therefore, a highly reliable electronic device can be provided.

  The semiconductor device manufacturing method, the semiconductor device, and the electronic device according to each of the above embodiments detect, for example, a human sensor that detects the presence of a human body by receiving infrared light, a temperature distribution of the human body, and the like. The present invention can be applied to various devices such as temperature sensors and the like, and manufacturing methods thereof. The present invention can also be applied to a manufacturing method of a semiconductor device using a so-called MEMS (Micro Electro Mechanical Systems) process and a semiconductor device formed by this manufacturing method.

  DESCRIPTION OF SYMBOLS 1 (Semiconductor chip) base material, 1a, 51a surface, 1b back surface, 1c peripheral part (including side surface), 3 1st insulating layer, 5 electrode, 5a 1st electrode, 5b 2nd electrode, 7 1st 2 insulating layer, 9 third insulating layer, 10, 110 semiconductor chip, 11 sacrificial layer, 13 element, 15 plug electrode, 20, 20a, 20b through electrode, 21 through hole, 23 seed layer, 24 electrode body, 25 Brazing material, 27 TSV insulating film, 29 recess, 31 cavity, 50 base substrate, 51 (base substrate) base material, 51a surface, 53 insulating layer, 55 first electrode, 57 second electrode, 59 passivation film , 60 bump, 61 tip, 70 annular bump, 71 (exposed from semiconductor chip 11 of the annular bump), 81 sealing resin, 83 resin, 100, 200 semiconductor device

Claims (6)

A method for manufacturing a semiconductor device by connecting a first substrate and a second substrate, at least one of which includes a semiconductor element, to each other,
The first substrate is
A first substrate having a first surface and a second surface opposite the first surface;
A sacrificial layer provided on the first surface side of the first substrate;
A through electrode penetrating between the first surface and the second surface of the first substrate;
An insulating film provided between the through electrode and the first base material,
The second substrate is
A second substrate having a third surface;
A bump provided on the third surface side of the second substrate;
An annular conductive portion provided on the third surface side of the second base material and surrounding the bump,
A mounting step of connecting the through electrode and the bump in a state where the second surface and the third surface are opposed to each other and embedding a peripheral portion of the first substrate in the annular conductive portion. When,
And a step of etching the sacrificial layer after the mounting step to form a cavity on the first surface side of the first base material. Before the mounting step, further comprising a recess forming step of forming a recess on the surface of the through electrode connected to the bump,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the mounting step, the through electrode and the bump are connected in a state in which a tip of the bump is placed inside the recess. A semiconductor device in which at least one of the first substrate including the semiconductor element and the second substrate are connected to each other;
The first substrate is
A first substrate having a first surface and a second surface opposite to the first surface, wherein a cavity is provided on the first surface side;
A through electrode penetrating between the first surface and the second surface of the first substrate;
An insulating film provided between the through electrode and the first base material,
The second substrate is
A second substrate having a third surface facing the second surface;
A bump provided on the third surface side of the second base material and connected to the through electrode;
An annular conductive portion provided on the third surface side of the second base material and surrounding the bump,
A semiconductor device, wherein a peripheral portion of the first substrate is embedded in the annular conductive portion. The first substrate is
A second through electrode penetrating a position between the first surface and the second surface of the first base material and closer to the peripheral edge than the through electrode;
An insulating film is provided between the second through electrode and the first base material;
The semiconductor device according to claim 3, wherein the second through electrode is connected to the annular conductive portion.   And a resin provided between the second surface of the first substrate and the third surface of the second substrate and surrounded by the annular conductive portion. The semiconductor device according to claim 3 or 4. An electronic apparatus comprising the semiconductor device according to any one of claims 3 to 5.

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