JP2013085272A - Semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit having excellent radiation-resistant characteristics.SOLUTION: A semiconductor circuit includes a first circuit block 1 in which a plurality of pMOS transistors 11 and 12 are connected in series, and a second circuit block 2 in which a plurality of nMOS transistors 21 and 22 are connected in series. A gate of at least one pMOS transistor 12 and/or a gate of at least one nMOS transistor 21 are/is connected to an input terminal Vin, and an on-voltage is applied to a gate of at least one the other pMOS transistor 11 and/or a gate of at least one the other nMOS transistor 22.

Description

  The present invention relates to a semiconductor circuit such as a CMOS in which a pMOS transistor and an nMOS transistor are combined, and more particularly to a semiconductor circuit having excellent radiation resistance.

Conventionally, a semiconductor circuit combining a pMOS transistor and an nMOS transistor, for example, an inverter, a buffer, a NAND, a NOR, and the like is mounted on various electronic devices and widely used.
An example of such a semiconductor circuit is disclosed in Japanese Patent Laid-Open No. 2002-261597 (Patent Document 1).
Patent Document 1 discloses an inverter in which one pMOS transistor and one nMOS transistor are connected in series, the connection point is connected to an output terminal, and the gates of the two are connected to a common input terminal. Yes.

JP 2002-261597 A

By the way, when an electronic circuit incorporating a semiconductor circuit as disclosed in Patent Document 1 is operated in an environment that receives radiation stronger than natural radiation, such as in outer space, the off-state is caused by the incidence of radiation. This causes a problem that the MOS transistor is turned on transiently, the circuit is temporarily short-circuited, and the output voltage fluctuates.
This fluctuation of the output voltage causes a soft error in which data is inverted, which causes a malfunction of the electronic device.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor circuit having excellent radiation resistance.

In order to solve the above problems, the present invention employs the following means.
In the reference example of the present invention, at least one other pMOS transistor or a parallel circuit including at least one other pMOS transistor is connected in series to one pMOS transistor or a parallel circuit including one pMOS transistor. In the first circuit block in which a common signal is input to the gates of the pMOS transistor and the other pMOS transistor, and / or in the parallel circuit including one nMOS transistor or one nMOS transistor, at least one other A semiconductor circuit including a second circuit block in which a parallel circuit including an nMOS transistor or at least one other nMOS transistor is connected in series, and a common signal is input to the gates of the nMOS transistor and the other nMOS transistor .

As described above, in a normal circuit configuration, one pMOS transistor or a parallel circuit including one pMOS transistor, or one nMOS transistor or a parallel circuit including one nMOS transistor performs the same operation as those. By connecting another MOS transistor or a parallel circuit including another MOS transistor in series, even if one MOS transistor temporarily changes from an off state to an on state due to the influence of radiation, the operation of the other MOS transistor Thus, it is possible to prevent a short circuit of the circuit.
The signal input to the gate of the pMOS transistor and the signal input to the gate of the nMOS transistor may be a common signal or different signals. For example, a semiconductor circuit such as an inverter or a buffer may be a common signal, while a semiconductor circuit such as a NAND circuit or a NOR circuit may be a different signal.
As an example of the semiconductor circuit of the present invention, logic gates such as inverters, buffers, NAND, NOR, AND, OR, and EXOR (Exclusive OR) gates, sequential circuits such as flip-flops and latches, memories, etc. An example is a memory circuit.
Further, when a pMOS transistor and another pMOS transistor are connected in series, another element (for example, a MOS transistor or a resistor) may be interposed therebetween. The same applies to the nMOS transistor.
In the semiconductor circuit, the number of pMOS transistors and the number of nMOS transistors may be different. That is, the number of pMOS transistors may be larger or smaller than the number of nMOS transistors.

  In the reference example of the present invention, a first circuit block in which a plurality of pMOS transistors are connected in series or a parallel circuit having one pMOS transistor, and a plurality of nMOS transistors in a parallel circuit having a series or one nMOS transistor. A connection point between the first circuit block and the second circuit block is connected to an output terminal, and the gates of all the pMOS transistors and all the nMOS transistors are connected to each other. A semiconductor circuit for connecting a gate to a common input terminal is provided.

Since a plurality of pMOS transistors and a plurality of nMOS transistors are connected to a common input terminal, even if one MOS transistor, which is originally in an off state, is turned on by radiation incidence, The MOS transistor can avoid a short circuit.
Here, it is known that in space, the probability that two or more radiation particles are incident on a semiconductor device having a size such as a semiconductor circuit as in the present invention is extremely close to zero. Thus, at most one transistor is turned on by the incidence of radiation.
Therefore, in the semiconductor circuit according to the present invention, each of the first and second circuit blocks only needs to include at least two MOS transistors.

  According to the present invention, a plurality of pMOS transistors are connected in series, or a plurality of pMOS transistors are connected in series to a plurality of parallel circuits including one pMOS transistor, or a plurality of parallel circuits are provided with the one pMOS transistor. A plurality of nMOS transistors connected in series to a first circuit block having a circuit connected to each other in series and a plurality of nMOS transistors connected in series, or a plurality of parallel circuits having one nMOS transistor; A second circuit block in which a plurality of parallel circuits each having one nMOS transistor are connected in series with each other, and the gate of at least one of the pMOS transistors and / or the gate of at least one of the nMOS transistors is connected to an input terminal And at least one other pMOS transistor The gates of the gate and / or at least one other nMOS transistor, a semiconductor circuit for applying an on-voltage.

  The present invention provides a first circuit block in which at least one pMOS transistor and at least one parallel circuit including one pMOS transistor are connected in series, at least one nMOS transistor and at least one nMOS transistor. A second circuit block in which two parallel circuits are connected in series, the gate of at least one of the pMOS transistors and / or the gate of at least one of the nMOS transistors is connected to an input terminal, and at least one other A semiconductor circuit for applying an on-voltage to the gate of the pMOS transistor and / or the gate of at least one other nMOS transistor is provided.

According to the present invention, the MOS transistor whose gate is connected to the input terminal is driven according to the input signal applied to the input terminal.
On the other hand, the other MOS transistor acts as a resistance element having a certain resistance value when the ON voltage is applied.
As a result, even when the off-state MOS transistor is turned on due to the incidence of radiation, the current can be suppressed by the action of the resistance element, so that a decrease in output voltage can be suppressed. .
Furthermore, by using the on-resistance of the MOS transistor as the resistance element, it is sufficient to increase the number of MOS transistors formed on the substrate in the manufacturing process, and it can be easily manufactured without complicated design changes. Is possible.

As an example of the semiconductor circuit of the above invention, logic gates such as inverters, buffers, NAND, NOR, AND, OR, and EXOR (Exclusive OR) gates, sequential circuits such as flip-flops and latches, memories, etc. An example is a memory circuit.
Further, when a pMOS transistor and another pMOS transistor are connected in series, another element (for example, a MOS transistor or a resistor) may be interposed therebetween. The same applies to the nMOS transistor.
In the semiconductor circuit, the number of pMOS transistors and the number of nMOS transistors may be different. That is, the number of pMOS transistors may be larger or smaller than the number of nMOS transistors.

  According to the present invention, a plurality of pMOS transistors are connected in series, or a plurality of pMOS transistors are connected in series to a plurality of parallel circuits including one pMOS transistor, or a plurality of parallel circuits are provided with the one pMOS transistor. A plurality of nMOS transistors connected in series to a first circuit block having a circuit connected to each other in series and a plurality of nMOS transistors connected in series, or a plurality of parallel circuits having one nMOS transistor; And a second circuit block in which a plurality of parallel circuits each including one nMOS transistor are connected in series with each other, and a connection point between the first circuit block and the second circuit block is connected to an output terminal. , At least one gate of the pMOS transistor and at least one nMOS A gate connected to transistor to a common input terminal, the gates of the gate and other nMOS transistors other pMOS transistors, to provide a semiconductor circuit for applying an on-voltage.

In the semiconductor circuit of the present invention, it is preferable that the on-resistance of the pMOS transistor and the on-resistance of the nMOS transistor have substantially the same value.
Alternatively, in the semiconductor circuit of the present invention, it is preferable that the on-resistance of the MOS transistor in which the on-voltage is applied to the gate is higher than the on-resistance of the MOS transistor in which the gate is connected to the input terminal.

When all the MOS transistors have substantially the same on-resistance, the response speed of the first circuit block and the second circuit block, the value of the current flowing in the circuit, and the like can be kept in good balance. As a result, stable operation can be realized, and fluctuations in the output voltage can be kept uniform even when radiation is incident on any MOS transistor.
Here, “substantially the same value” means that, for example, when all the MOS transistors are uniformly formed in the manufacturing process, the on-resistance of each MOS transistor is within a range of variation due to manufacturing.

  In addition, when the on-resistance of the MOS transistor acting as a resistance element is made higher than the on-resistance of the MOS transistor driven by the input signal, it is possible to further reduce the current flowing due to the incidence of radiation, Output fluctuation can be further suppressed.

  In the semiconductor circuit of the present invention, the nMOS transistor and the pMOS transistor are formed on an insulating film formed on a semiconductor substrate, and each of the nMOS transistor and the pMOS transistor has a thickness reaching the insulating film. Are preferably separated from each other.

  In this way, the SOI (Silicon on Insulator) structure with excellent radiation resistance is adopted, and the MOS transistors are separated from each other by the insulating film, so that the charge generated by the incident radiation moves to the adjacent MOS transistor. Thus, adverse effects such as turning on the adjacent MOS transistor can be suppressed. Thereby, a radiation-resistant characteristic can be improved.

  In the semiconductor circuit of the present invention, the body region of the nMOS transistor and the body region of the pMOS transistor are preferably floating bodies.

For example, when the body region of the MOS transistor is not a floating body, there is a path for fixing the potential of the body region. In this case, when radiation enters, the output voltage fluctuates through this path.
Therefore, by making the body region of each MOS transistor a floating body and removing the path, it is possible to further reduce the output fluctuation due to the incidence of radiation, and to further improve the radiation resistance characteristics.

  The present invention provides an electronic device including any of the semiconductor circuits described above.

  According to the semiconductor circuit of the present invention, since a temporary circuit short circuit due to the incidence of radiation can be prevented, output fluctuations can be suppressed and the occurrence of soft errors can be prevented. As a result, it is possible to realize a semiconductor circuit having excellent radiation resistance characteristics, and it is possible to improve the reliability of an electronic device in which the semiconductor circuit is mounted.

1 is a circuit diagram of a CMOS inverter according to a first embodiment of the present invention. It is the figure which showed typically the cross section of the CMOS inverter shown in FIG. FIG. 3 is a diagram showing the state and operation of the CMOS inverter when radiation is incident on the CMOS inverter shown in FIG. 2. (A) is a configuration example of a known NAND circuit, and (b) and (c) are diagrams showing a configuration example of a NAND circuit according to the first embodiment of the present invention. (A) is a configuration example of a known NOR circuit, and (b) and (c) are diagrams showing a configuration example of a NOR circuit according to the first embodiment of the present invention. It is the figure which showed the other structural example of the semiconductor circuit which concerns on the 1st Embodiment of this invention. (A) is a structural example of a known transfer gate circuit, (b) is a diagram showing a structural example of a transfer gate circuit according to the first embodiment of the present invention. It is a circuit diagram of the CMOS inverter which concerns on the 2nd Embodiment of this invention. It is the figure which showed typically the cross section of the CMOS inverter shown in FIG. FIG. 10 is a diagram showing the state and operation of the CMOS inverter when radiation is incident on the CMOS inverter shown in FIG. 9. It is the figure which showed the example of 1 structure of the NAND circuit based on the 2nd Embodiment of this invention. It is the figure which showed the example of 1 structure of the NOR circuit which concerns on the 2nd Embodiment of this invention.

  Hereinafter, embodiments of a semiconductor circuit of the present invention will be described in detail in the order of [First Embodiment] and [Second Embodiment] with reference to the drawings.

[First Embodiment]
In the present embodiment, a CMOS inverter will be described as an example of the semiconductor circuit according to the present invention. FIG. 1 is a circuit diagram of a CMOS inverter according to the present embodiment.
In this figure, the CMOS inverter includes a first circuit block 1 in which pMOS transistors 11 and 12 are connected in series, and a second circuit block 2 in which nMOS transistors 21 and 22 are connected in series.
A connection point S between the first circuit block 1 and the second circuit block 2 is connected to the output terminal Vout. The gates of all the pMOS transistors 11 and 12 and the gates of all the nMOS transistors 21 and 22 are connected to a common input terminal Vin.
Thus, in the case of a normal CMOS inverter, it is composed of one pMOS transistor and one nMOS transistor. In this embodiment, a spare pMOS transistor and an nMOS transistor are provided, and each circuit block includes a plurality of circuit blocks. By using MOS transistors, the circuit configuration has excellent radiation resistance.

FIG. 2 is a diagram schematically showing a cross section of the CMOS inverter shown in FIG. In this figure, the same reference numerals as those in FIG. 1 denote the same elements.
As shown in FIG. 2, in the CMOS inverter according to the present embodiment, a buried oxide film 40 that is an insulating film is buried in a p-type silicon substrate 30. The buried oxide film 40 is made of, for example, silicon oxide. The p-type silicon substrate 30 is separated into the SOI layer 50 and the silicon substrate body 60 by the buried oxide film 40.
In the SOI layer 50, pMOS transistors 11 and 12 and nMOS transistors 21 and 22 are formed, respectively. The MOS transistors 11, 12, 21, and 22 are separated from each other by an insulating film 70 having a thickness that reaches the buried oxide film 40.
Thus, by forming the MOS transistors 11, 12, 21, 22 apart from each other, the charge generated by the incidence of radiation moves to the adjacent MOS transistor and turns on the adjacent transistor. It is possible to suppress adverse effects.

The pMOS transistors 11 and 12 include a P-type drain region 81, an N-type body region 82, and a P-type source region 83 formed in the SOI layer 50, respectively. The nMOS transistors 21 and 22 include SOI layers 50, an N-type drain region 81, a P-type body region 82, and an N-type source region 83, respectively.
A drain electrode 91 is formed on the drain region 81 of each MOS transistor 11, 12, 21, 22, and a source electrode 93 is formed on the source region 83.
On the body region 82, a gate insulating film 94 and a gate electrode 92 are stacked in this order. The gate insulating film 94 is made of silicon oxide, and the gate electrode 92 is made of highly doped polysilicon.

The source electrode 93 of the pMOS transistor 11 is connected to the + terminal Vdd.
The source electrode 93 of the nMOS transistor 22 is connected to the ground terminal Vss.
The gate electrodes 92 of the pMOS transistors 11 and 12 and the gate electrodes 92 of the nMOS transistors 21 and 22 are connected to a common input terminal Vin.
The drain electrode 91 of the pMOS transistor 12 is connected to the drain electrode 91 of the nMOS transistor 21, and this connection point is connected to the output terminal Vout.
The drain electrode 91 of the pMOS transistor 11 is connected to the source electrode 93 of the pMOS transistor 12, and the source electrode 93 of the nMOS transistor 21 is connected to the drain electrode 91 of the nMOS transistor 22.

In the CMOS inverter having the above-described configuration, when “1” is applied to the input terminal Vin, the pMOS transistors 11 and 12 are turned off and the nMOS transistors 21 and 22 are turned on. “0 (Vss)” is output to Vout.
On the other hand, when “0” is applied to the input terminal Vin, the pMOS transistors 11 and 12 are turned on and the nMOS transistors 21 and 22 are turned off, so that “1 (Vdd)” is applied to the output terminal Vout. Is output.

Next, a case where radiation is incident on the CMOS inverter according to the present embodiment will be described with reference to FIG.
As shown in FIG. 3, when “0” is applied to the input terminal Vin, radiation is incident on the nMOS transistor 22 when the pMOS transistors 11 and 12 are on and the nMOS transistors 21 and 22 are off. In this case, the nMOS transistor 22 is transiently turned on due to the influence of radiation.
However, even in such a case, since one of the nMOS transistors 21 maintains the OFF state, it is possible to prevent a current from flowing in the circuit and to prevent an output fluctuation.
In addition, when two or more radiation particles enter the circuit at the same time, it is considered that the circuit is short-circuited because the two MOS transistors are turned on.
However, the probability that two or more radiation particles are incident on a semiconductor circuit like the present invention is extremely low even in an environment where there is much radiation compared to the natural world on the ground, such as outer space. close.
Therefore, it can be said that if each circuit block includes at least two MOS transistors as in the CMOS inverter shown in this embodiment, it is sufficient to prevent malfunction of the CMOS inverter due to the influence of radiation.
Similarly, when “1” is input to the input terminal Vin, even if one of the pMOS transistors 11 and 12 is turned on due to radiation, the other pMOS transistors prevent the circuit from being short-circuited. Thus, output fluctuation can be avoided.

As described above, according to the CMOS inverter according to the present embodiment, the pMOS transistors 11 and 12 and the nMOS transistors 21 and 22 are connected to the common input terminal Vin. Even if one MOS transistor (for example, nMOS transistor 22) which is in a state is turned on, it is possible to avoid a short circuit by another MOS transistor (for example, nMOS transistor 21) which is in an off state. Become.
In other words, normally, in a CMOS inverter composed of one pMOS transistor and one nMOS transistor, at least one other pMOS transistor is connected in series to the pMOS transistor, and the pMOS transistor and the other pMOS transistor Are connected to a common input terminal to form a first circuit block, and nMOS transistors are similarly connected to other MOS transistors to form a second circuit block. Even if the MOS transistor is turned on, a short circuit can be avoided by the action of the other MOS transistors.
As a result, it is possible to suppress voltage fluctuation of the output terminal Vout, and there is an effect that a semiconductor circuit having excellent radiation resistance characteristics can be realized.

Further, the pMOS transistors 11 and 12 and the nMOS transistors 21 and 22 are formed on the buried oxide film 40 embedded in the p-type silicon substrate 30, and each of the pMOS transistors 11 and 12 and the nMOS transistors 21 and 22 is formed. Since the insulating films 70 having a thickness reaching the buried oxide film 40 are separated from each other, the charge generated by the incident radiation moves to the adjacent MOS transistor and turns on the adjacent MOS transistor. Can be suppressed. Thereby, the radiation resistance can be further improved.
In this embodiment, the number of MOS transistors constituting the first circuit block and the second circuit block is made equal. However, the present invention is not limited to this, and the pMOS transistor constituting the first circuit block 1 is used. And the number of nMOS transistors constituting the second circuit block 2 may be different.

Further, the semiconductor circuit according to the present embodiment is not limited to the CMOS inverter having the above-described configuration, but includes a logic gate such as a buffer, NAND, NOR, AND, OR circuit and ExOR (Exclusive OR), and a flip-flop. Further, it may be a sequential circuit such as a latch or a storage circuit such as a memory.
In other words, in general circuit configurations such as logic circuits, sequential circuits, and memory circuits, at least one other MOS transistor that performs the same operation is redundantly connected to the pMOS transistor and nMOS transistor connected to the input terminal. By doing so, it is possible to prevent the influence of radiation, and it is possible to obtain the same operation and effect as the above-described CMOS inverter.

For example, a NAND circuit can be configured as shown in FIGS. 4B and 4C.
4A shows a circuit configuration of a NAND circuit that is generally known at present, and FIGS. 4B and 4C show a circuit configuration of a NAND circuit having excellent radiation resistance according to the present invention. An example is shown.
As shown in FIG. 4B, at least one other pMOS transistor 202 is connected in series to the pMOS transistor 201 which is one semiconductor element constituting the NAND circuit, and the gate of the pMOS transistor 202 is connected to the pMOS. By connecting to the same input terminal Vin (A) as the transistor 201, the same signal is input to configure the circuit block (first circuit block) 301.
Similarly, the pMOS transistor 203 connected to the input terminal Vin (B) and the nMOS transistors 205 and 207 connected to the input terminals Vin (A) and (B) are also connected to the other pMOS transistors 204 and nMOS. Transistors 206 and 208 are connected in series to constitute circuit blocks 302, 303, and 304, respectively.
As a result, even if any one of the MOS transistors is turned on, it is possible to avoid a short circuit due to the action of the other MOS transistors, and to realize a semiconductor circuit having excellent radiation resistance characteristics. Can do.

In addition to the circuit configuration shown in FIG. 4B, the same effect can be obtained by using a circuit configuration as shown in FIG.
In the NAND circuit shown in FIG. 4C, for example, a parallel circuit 306 including at least one other pMOS transistor 202 is connected in series to the pMOS transistor 201 connected to the input terminal Vin (A). A circuit block 307 is configured by connecting the gates of the pMOS transistors to a common input terminal Vin (A).
The same applies to the pMOS transistor 203 connected to the input terminal Vin (B).

As for the NOR circuit, it is possible to configure the circuit as shown in FIGS. 5B and 5C by the same technique as the NAND circuit described above.
As shown in FIG. 6A, another nMOS transistor 402 connected in series to one nMOS transistor 401 may be connected via another MOS transistor or a resistor.
In addition, radiation resistance can be further improved by connecting a parallel circuit 501 including another pMOS transistor 403 to a circuit block in which two or more pMOS transistors 401 and 402 are connected in series.
Further, the semiconductor circuit according to the present invention does not necessarily include a pMOS transistor and an nMOS transistor. As shown in FIG. 6B, at least one other MOS transistor or one of the MOS transistors or Any parallel circuit including at least one other MOS transistor connected in series and a circuit block configured to input a common signal to the gates of these MOS transistors may be used.
Further, as shown in FIGS. 7B and 7C, the present invention can be similarly applied to a semiconductor circuit such as a transfer gate circuit.

[Second Embodiment]
Next, a semiconductor circuit according to a second embodiment of the present invention will be described using a CMOS inverter as an example with reference to FIG.
FIG. 8 is a circuit diagram of the CMOS inverter according to the present embodiment, and FIG. 9 is a diagram schematically showing a cross section of the CMOS inverter shown in FIG.
As shown in FIGS. 8 and 9, the CMOS inverter according to this embodiment has the same components as those of the CMOS inverter according to the first embodiment described above, but the gate wiring of some MOS transistors is not identical. Is different.
That is, in the CMOS inverter according to the present embodiment, as shown in FIG. 8, the gate of the pMOS transistor 12 constituting the first circuit block 1 and the gate of the nMOS transistor 21 constituting the second circuit block 2 are provided. Connect to a common input terminal Vin.
On the other hand, the on-voltage is applied by connecting the gate of the pMOS transistor 11 to the ground terminal VSS and connecting the gate of the nMOS transistor 22 to the + terminal Vdd.
With such a configuration, the pMOS transistor 12 and the nMOS transistor 21 connected to the input terminal Vin operate in response to the input signal, while the pMOS transistor 11 and the nMOS transistor 22 are always in an on state and have a constant resistance value. Acts as a resistance element having (ON resistance).

As shown in FIG. 9, also in the semiconductor circuit of this embodiment, the p-type silicon substrate 30 is made of SOI by the buried oxide film 40 as in the semiconductor circuit according to the first embodiment shown in FIG. 2. Separated from layer 50. Further, the pMOS transistors 11 and 12 and the nMOS transistors 21 and 22 formed in the SOI layer 50 are separated from each other by an insulating film 70 having a thickness reaching the buried oxide film 40. As a result, it is possible to suppress the adverse effect that the charge generated by the incidence of radiation moves to the adjacent MOS transistor and turns on the adjacent transistor.
Further, by making the body region of each MOS transistor a floating body, a path for fixing the potential of the body region can be removed, and output fluctuation due to radiation incidence can be reduced.

Here, the pMOS transistors 11 and 12 and the nMOS transistors 21 and 22 are uniformly formed on the buried oxide film 40 in the manufacturing process. Accordingly, these on-resistances have substantially the same value although there are variations due to manufacturing.
As a result, it is possible to maintain a balance between the response speed and the output voltage between the first circuit block 1 and the second circuit block 2, and a stable operation can be realized.

Next, a case where radiation is incident on the semiconductor circuit according to the present embodiment will be described with reference to FIG.
For example, as shown in FIG. 10, when “0” is applied to the input terminal Vin, the pMOS transistor 12 is turned on and the nMOS transistor 21 is turned off in normal operation. As a result, “1 (Vdd)” is output to the output terminal Vout.
Further, the pMOS transistor 11 and the nMOS transistor 22 always act as resistance elements because they are on.
In this state, when radiation is incident on the nMOS transistor 21 in the off state, the nMOS transistor 21 is transiently turned on, and a current temporarily flows from the + terminal Vdd to the ground terminal Vss.
As a result, for example, when the on-resistance of each of the MOS transistors 11, 12, and 22 is set to “rΩ”, and the nMOS transistor that is turned on due to the incidence of radiation is set to resistance = 0Ω, the output terminal Vout The output voltage is a value represented by the following equation (1).

Vout≈ (r / 3r) * Vdd = (1/3) * Vdd (1)
As described above, even if the MOS transistor that is originally in the off state is completely turned on due to the incidence of radiation, it is possible to secure an output voltage of (1/3) * Vdd. That is, an output voltage of (1/3) * Vdd can be secured even in the worst case.
As described above, according to the CMOS inverter according to the second embodiment, even when the MOS transistor which is in the off state is transiently turned on due to the incidence of radiation, 1 It becomes possible to compensate the output voltage of / 3Vdd. As a result, it is possible to prevent the occurrence of soft errors due to output fluctuations.

In addition, it is possible to further suppress fluctuations in the output voltage by setting the on-resistances of the MOS transistors 11, 12, 21, and 22 as follows.
For example, in the CMOS inverters shown in FIGS. 8 and 9, the on-resistances of the pMOS transistor 11 and the nMOS transistor 22 to which the on-voltage is applied to the gate are connected to the pMOS transistor 12 and the nMOS transistor 21 to which the gate is connected to the input terminal Vin. Higher than the on-resistance. As a result, it is possible to further reduce the current that flows due to the incidence of radiation, thereby further suppressing output fluctuation.

In each of the circuit blocks 1 and 2, the number of MOS transistors driven by the input signal is one, so that the increase in input capacitance can be suppressed, and the first MOS transistor is connected to the input terminals. Compared with the CMOS inverter according to the embodiment, the response speed can be increased.
That is, according to the CMOS inverter according to the second embodiment, there is an effect that high-speed operation can be realized while maintaining the radiation resistance characteristics to such an extent that no malfunction occurs.

Further, the semiconductor circuit according to the present embodiment is not limited to the CMOS inverter having the above-described configuration, but includes a logic gate such as a buffer, NAND, NOR, AND, OR circuit and ExOR (Exclusive OR), Further, it may be a sequential circuit such as a latch or a storage circuit such as a memory.
That is, in a circuit configuration such as a general logic circuit, sequential circuit, and memory circuit, at least one other MOS transistor or the like is redundantly connected to the pMOS transistor or nMOS transistor connected to the input terminal, By applying an on-voltage to these connected MOS transistors and acting as a resistance element, the influence of radiation can be prevented, and the same operation and effect as the above-described CMOS inverter can be obtained.

For example, a NAND circuit can be configured as shown in FIG.
As shown in FIG. 11, a circuit block (first circuit block) 301 is configured by connecting at least one other pMOS transistor 202 in series to a pMOS transistor 201 which is one semiconductor element constituting a NAND circuit. To do. In this case, the gate of the redundantly arranged pMOS transistor 202 is connected to the ground, so that it is always turned on to act as a resistance element.
Similarly, the pMOS transistor 203 connected to the input terminal Vin (B) and the nMOS transistors 205 and 207 connected to the input terminals Vin (A) and (B) are also connected to the other pMOS transistors 204 and nMOS. The transistors 206 and 208 are connected in series to constitute the respective circuit blocks 302, 303, and 304, and the on-voltage is applied to the redundantly arranged pMOS transistor 204 and nMOS transistors 206 and 208, whereby the resistance element To act as.
As a result, even if any one of the MOS transistors is turned on, the MOS transistor acting as a resistance element can avoid a short circuit and realize a semiconductor circuit having excellent radiation resistance characteristics. can do.
In the NAND circuit shown in FIG. 11, in the nMOS transistors 205 to 208, the nMOS transistors 205 and 207 whose gates are connected to the input terminals are directly connected in series, and further, the resistance elements are connected to the nMOS transistor 207. NMOS transistors 206 and 208 acting as the above are connected in series.
However, the present invention is not limited to this example. For example, the same effect can be obtained by arranging an nMOS transistor 206 acting as a resistance element between the nMOS transistor 205 and the nMOS transistor 207.
It is also possible to change the order of connection between these redundantly arranged MOS transistors and the MOS transistor whose input signal is input to the gate.

As for the NOR circuit, it is possible to configure the circuit as shown in FIG. 12 by the same technique as the NAND circuit described above.
The semiconductor circuit according to the present invention does not necessarily include a pMOS transistor and an nMOS transistor, and any one MOS transistor includes at least one other MOS transistor or at least one other MOS transistor in parallel. Any circuit may be used as long as the circuit is connected in series and the circuit block is configured such that the ON voltage is input to the gates of the redundantly arranged MOS transistors.

The second embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and design changes and the like within the scope of the present invention are also possible. included.
First, although the number of MOS transistors constituting the first circuit block and the second circuit block is made equal, the present invention is not limited to this, and the number of pMOS transistors constituting the first circuit block, The number of nMOS transistors constituting the two circuit blocks may be different.
Second, the number of pMOS transistors and nMOS transistors connected to the input terminal Vin may be different.
Thirdly, the number of MOS transistors that act as resistance elements can be made different between the first circuit block and the second circuit block by always turning on.
As described above, even when the number of MOS transistors is different between the first and second circuit blocks, the sum of the on-resistances of the MOS transistors that are always in the ON state is the same as the first circuit block. It is preferable that the second circuit block is designed and manufactured to have substantially the same value.

Similarly, the on-resistance of the MOS transistor driven by the input voltage Vin is designed and manufactured so that the sum thereof is substantially the same in the first circuit block and the second circuit block. Is preferred.
In this way, balanced and stable driving can be realized by matching the on-resistance in the first circuit block and the second circuit block.
Fourth, the resistance element is configured by always turning on the MOS transistor. However, the present invention is not limited to this, and the resistance element may be formed by another structure.

Fifth, the semiconductor circuit according to the present invention can be generally used not only in outer space but also naturally mounted on an electronic device on the ground.
For example, in recent years, it has been reported that integrated circuits have been miniaturized, and along with this, soft errors are also caused by a small amount of α-rays emitted from cases and solder. Even on the ground, a semiconductor circuit having excellent radiation resistance is indispensable for an electronic device used in a place with a lot of radiation. Thus, radiation resistance is now a very important factor even on the ground.
Sixth, it is also possible to realize a semiconductor circuit configured by combining the semiconductor circuit according to the first embodiment of the present invention and the semiconductor circuit according to the second embodiment.
For example, when three MOS transistors that perform the same operation are connected redundantly, a common input signal is input to the gates of the two MOS transistors, and an ON voltage is applied to the gates of the other MOS transistors. Even with such a configuration, it is possible to realize a semiconductor circuit having excellent radiation resistance.

1, 301, 302, 307 First circuit block 2, 303, 304 Second circuit block 11, 12 pMOS transistor 21, 22 nMOS transistor 40 buried oxide film 70 insulating film S connection point Vin input terminal Vout output terminal Vdd + Terminal Vss Ground terminal

Claims (8)

A plurality of pMOS transistors connected in series, a plurality of pMOS transistors connected in series to a plurality of parallel circuits including one pMOS transistor, or a plurality of parallel circuits including the one pMOS transistor in series A first circuit block connected to
A plurality of nMOS transistors are connected in series, a plurality of nMOS transistors are connected in series to a plurality of parallel circuits including one nMOS transistor, or a plurality of parallel circuits including the one nMOS transistor are connected in series to each other. And a second circuit block connected to
Connecting at least one gate of the pMOS transistor and / or at least one gate of the nMOS transistor to an input terminal;
A semiconductor circuit that applies an ON voltage to the gate of at least one other pMOS transistor and / or to the gate of at least one other nMOS transistor. A first circuit block in which at least one pMOS transistor and at least one parallel circuit including one pMOS transistor are connected in series;
A second circuit block in which at least one nMOS transistor and at least one parallel circuit including one nMOS transistor are connected in series;
Connecting at least one gate of the pMOS transistor and / or at least one gate of the nMOS transistor to an input terminal;
A semiconductor circuit that applies an ON voltage to the gate of at least one other pMOS transistor and / or to the gate of at least one other nMOS transistor. A plurality of pMOS transistors are connected in series, or a plurality of pMOS transistors are connected in series to a plurality of parallel circuits including one pMOS transistor, or a plurality of parallel circuits including the one pMOS transistor are connected to each other. A first circuit block connected in series;
A plurality of nMOS transistors are connected in series, a plurality of nMOS transistors are connected in series to a plurality of parallel circuits including one nMOS transistor, or a plurality of parallel circuits including the one nMOS transistor are connected in series to each other. And a second circuit block connected to
A connection point between the first circuit block and the second circuit block is connected to an output terminal, and a gate of at least one pMOS transistor and a gate of at least one nMOS transistor are connected to a common input terminal. ,
A semiconductor circuit that applies an on-voltage to the gates of other pMOS transistors and the gates of other nMOS transistors.   4. The semiconductor circuit according to claim 1, wherein the on-resistance of the pMOS transistor and the on-resistance of the nMOS transistor have substantially the same value. 5.   4. The semiconductor according to claim 1, wherein an on-resistance of the MOS transistor to which an on-voltage is applied to a gate is higher than an on-resistance of the MOS transistor in which the gate is connected to an input terminal. circuit. The nMOS transistor and the pMOS transistor are formed on an insulating film formed on a semiconductor substrate,
6. The semiconductor circuit according to claim 1, wherein each of the nMOS transistor and the pMOS transistor is separated from each other by an insulating film having a thickness reaching the insulating film.   The semiconductor circuit according to claim 1, wherein the gate of the nMOS transistor and the body region of the pMOS transistor are floating bodies. The electronic device provided with the semiconductor circuit of any one of Claims 1-7.

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