JP2013062728A - Rf power amplifier and method of operating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a degradation of a ramp-up or ramp-down switching spectrum.SOLUTION: Initial and final stage bias circuits 81, 83 determine idling currents of initial and final stage amplification circuits 41, 43. A power detection circuit 5, 6 generates a power detection signal Vresponsive to a signal level of a final stage output signal Pout. The detection signal Vand a target power signal Vare supplied to an error amplifier 7, and a power control voltage Vis supplied to an input of a control signal enhancement circuit 9, whose output generates an enhanced control signal V. The control signal enhancement circuit 9 has a predetermined nonlinear input/output characteristic. The enhanced control signal Vis supplied to the initial and final stage bias circuits 81, 83, so that the enhanced control signal Vcontrols the idling currents of the initial and final stage amplification circuits 41, 43 to compensate for a reduced control gain of an RF power amplifier.

Description

  The present invention relates to an RF power amplifier and an operation method thereof, and more particularly, to a technique effective in reducing deterioration of a switching spectrum and reducing reduction in power efficiency during ramp-up or ramp-down.

  Mobile communication systems such as GSM (Global System for Mobile Communications) and GPRS (General Packet Radio Service) are used almost all over the world, and are expected to continue to be used in the future. In mobile communication systems such as GSM and GPRS, it is required to control the transmission output power of a mobile terminal device according to the communication distance between the base station and the mobile terminal device. The power control of the transmission output is realized by controlling the power gain of the RF power amplifier mounted on the portable terminal device with the control voltage. This control is called APC (Automatic Power Control).

  In the following Patent Document 1, the output power Pout with respect to the change of the output power control voltage Vapc when the output power Pout of the conventional RF power amplifier used for the mobile phone is around 0 dBm is steep, and the output by the output power control voltage Vapc is described. It is described that the problem that the controllability of the power Pout is not good is solved. In Patent Document 1 below, a bias voltage or a bias current is set near the threshold voltage of the amplifying element of each stage of the multistage amplifier circuit of the RF power amplifier so that the fluctuation of the output power Pout with respect to the output power control voltage Vapc is reduced. It is described that a bias control circuit for controlling the above is connected to an amplification element at each stage of a multistage amplifier circuit. Specifically, the multistage amplifier circuit includes a first stage amplifier circuit, an intermediate stage amplifier circuit, and a final stage amplifier circuit. The bias control circuit generates an initial stage bias voltage, an intermediate stage bias voltage, and a final stage bias voltage and supplies them to the initial stage amplifier circuit, the intermediate stage amplifier circuit, and the final stage amplifier circuit, respectively.

  When the output power control voltage Vapc is a predetermined voltage, for example, 1.7 volts or less, the rate of change of the initial stage bias voltage, the rate of change of the intermediate stage bias voltage, and the rate of change of the final stage bias voltage with respect to the change of the output power control voltage Vapc Is set to a relatively small value. However, when the output power control voltage Vapc is a predetermined voltage, for example, 1.7 volts or more, the change rate of the initial stage bias voltage, the change rate of the intermediate stage bias voltage, and the change of the final stage bias voltage with respect to the change of the output power control voltage Vapc. The rate is set to a relatively large value. In particular, the change rate of the intermediate stage bias voltage is set to a change rate larger than the change rate of the first stage bias voltage, and the change rate of the final stage bias voltage is set to a change rate larger than the change rate of the intermediate stage bias voltage. .

  In order to set each change rate of the initial stage bias voltage, the intermediate stage bias voltage, and the final stage bias voltage to a relatively large value when the output power control voltage Vapc is a predetermined voltage, for example, 1.7 volts or more, a bias control circuit Includes a voltage-current conversion transistor. When the voltage-current conversion transistor converts a gate voltage proportional to the output power control voltage Vapc into a drain current, a drain current proportional to the square of the output power control voltage Vapc is generated. Since a constant current source is connected between the gate of the voltage-current conversion transistor and the ground voltage, when the current proportional to the output power control voltage Vapc increases beyond the constant current of the constant current source, the voltage − The current conversion transistor generates a drain current proportional to the square of the output power control voltage Vapc.

  Specifically, the bias control circuit includes a bias control circuit that generates an initial stage bias voltage, a bias control circuit that generates an intermediate stage bias voltage, and a bias control circuit that generates a final stage bias voltage. Since the magnitudes of the constant currents of the constant current sources of the three bias control circuits are different, the starting point at which the voltage-current conversion transistors of the three bias control circuits start to flow the drain current is shifted.

  Patent Document 2 listed below describes a technique for reducing a decrease in power added efficiency (PAE) at the time of low power and intermediate power of an RF power amplifier including a multistage amplifier stage. Specifically, the idling current of the first stage amplification transistor is controlled by a linear characteristic in response to the output power control voltage Vapc, and the idling current of the second stage amplification transistor is squared in response to the output power control voltage Vapc. Controlled by the characteristics, the idling current of the third stage amplification transistor is controlled by the cube characteristics in response to the output power control voltage Vapc. Patent Document 2 listed below further describes a current square circuit for realizing the square characteristic and a current square circuit for realizing the cube characteristic.

  In Patent Document 3 below, a plurality of current-square conversion circuits for making an idling current flowing through a transistor of a final-stage amplifier of an RF power amplifier constituted by a multistage amplifier proportional to the square of the output power control voltage Vapc are disclosed. It is described that the current square conversion circuit can be operated even at a low power supply voltage by operating the MOS transistor in the subthreshold region.

  Non-Patent Document 1 below has a trade-off that the efficiency of the RF power amplifier increases as the output approaches saturation, whereas the output power is not proportional to the input power and the signal distortion increases. A back-off technique for solving is described. This approach limits the linear output peak output power to below the maximum saturation output power obtainable from the RF power amplifier. As a result, the RF power amplifier is designed and operated as either a fixed gain linear amplifier or a variable gain saturation amplifier.

JP 2003-37454 A JP 2010-183135 A JP 2010-200078 JP

Earl McCune, “High-Efficiency, Multi-Mode, Multi-Band Terminal Power Amplifiers”, IEEE microwave magazine, March 2005, PP. 44-55.

  Prior to the present invention, the inventors engaged in the development of an RF power amplifier that can be mounted on a mobile phone terminal capable of GSM communication.

  As is well known, in a mobile phone terminal capable of GSM communication, a plurality of time slots for communication are selected from an idle state, a reception operation from the base station, and a transmission operation to the base station. A time division multiple access (TDMA) method that can be set to be used is used. In the TDMA system, when switching from another time slot to a transmission operation time slot, the signal strength of the RF transmission signal must be increased at an increase rate defined by the GMSK standard. Note that GMSK is an abbreviation for Gaussian Minimum Shift Keying. The increase in signal strength of the RF transmission signal at this time is called ramp-up. On the other hand, when switching from a transmission operation time slot to another time slot, the signal strength of the RF transmission signal must be reduced at a reduction rate defined in the GMSK standard. The decrease in signal strength of the RF transmission signal at this time is called ramp-down. The maximum value and the minimum value of the increase in the time change of the ramp-up signal strength, and the maximum value and the minimum value of the decrease in the time change of the signal strength of the ramp-down are called a time mask.

  FIG. 22 is a diagram illustrating the relationship between the time mask defined by the GMSK standard and the signal strength of the RF transmission signal.

  As shown in the time mask of FIG. 22, the signal strength of the RF transmission signal Tx_sig must increase between the maximum value L1 and the minimum value L2 at the time of ramp-up, and the maximum value L3 and the minimum value of the decrease at the time of ramp-down. Between the values L4, the signal strength of the RF transmission signal Tx_sig must decrease.

  Further, the maximum allowable power Al_Pout of the spurious component Spur having a predetermined offset frequency of 400 kHz, 600 kHz, 1.2 MHz, and 1.8 MHz from the transmission frequency of the RF transmission signal Tx_sig is −23 dBm and −26 dBm per 30 kHz, respectively. , -32 dBm, -33 dBm, which are defined by the standard. The spurious component Spur having a large interference signal component is also called a switching spectrum, and is generated at the time of ramp-up and ramp-down.

  Therefore, prior to the present invention, the present inventors have studied in detail the mechanism by which spurious components Spur having a large disturbing signal component are generated during ramp-up and ramp-down.

  FIG. 23 is a diagram showing a configuration of an RF power amplifier studied by the present inventors prior to the present invention.

  The RF power amplifier examined by the present inventors prior to the present invention shown in FIG. 23 includes an RF signal input terminal 1, an RF signal output terminal 2, a lamp control terminal 3, a multistage amplifier circuit 4, a power combiner 5, and an electric power. A detector 6, an error amplifier 7, and a bias circuit 8 are included.

  The RF signal input terminal 1 is supplied with an RF input signal Pin generated by a transmission signal processing unit of an RF signal processing semiconductor integrated circuit (RFIC) mounted on a mobile phone terminal. The RF input signal Pin is sequentially amplified by the first stage amplifier circuit 41, the intermediate stage amplifier circuit 42, and the final stage amplifier circuit 43 of the multistage amplifier circuit 4, and the amplified output signal of the final stage amplifier circuit 43 passes through the main line of the power combiner 5. Via the RF signal output terminal 2 as an RF output signal Pout.

A part of the RF output signal Pout is transmitted to the subline of the power coupler 5 that is electromagnetically and electrostatically coupled to the main line of the power coupler 5. As a result, the power detector 6 whose input terminal is connected to the sub line of the power combiner 5 generates a power detection voltage V _DET proportional to the signal level of the RF output signal Pout, and one input terminal of the error amplifier 7. To supply. The ramp voltage V _RAMP supplied to the other input terminal of the error amplifier 7 via the ramp control terminal 3 for ramp-up and ramp-down is a lamp D / A conversion built in the RF signal processing semiconductor integrated circuit (RFIC). Generated from the analog output terminal of the instrument. Digital ramp data for ramp-up and ramp-down is generated inside the baseband signal processing LSI, and the digital ramp data is built into the RF signal processing semiconductor integrated circuit (RFIC) via the digital interface from the baseband signal processing LSI. Are supplied to the digital input terminal of the lamp D / A converter.

The error amplifier 7 detects a difference between the power detection voltage V _DET at one input terminal and the ramp voltage V _RAMP at the other input terminal, generates an output power control voltage V _APC proportional to the difference, and generates a bias circuit. 8 input terminals. The bias circuit 8 includes a first bias circuit 81, a second bias circuit 82, and a third bias circuit 83, and in response to the output power control voltage VA _APC , the first bias circuit 81, the second bias circuit 82, and the third bias circuit. 83 generates a first bias voltage V _GB1 , a second bias voltage V _GB2, and a third bias voltage V _GB3 , respectively. The first bias voltage V _GB1 is supplied to the gate of the MOS transistor as the first stage amplifier element of the first stage amplifier circuit 41 of the multistage amplifier circuit 4, and the second bias voltage V _GB2 is intermediate between the intermediate stage amplifier circuit 42 of the multistage amplifier circuit 4. The third bias voltage V _GB3 is supplied to the gate of the MOS transistor as the final stage amplification element of the final stage amplification circuit 43 of the multistage amplification circuit 4.

24 is generated from the first bias circuit 81, the second bias circuit 82, and the third bias circuit 83 of the bias circuit 8 of the RF power amplifier examined by the present inventors prior to the present invention shown in FIG. it is a diagram showing the dependence of the first bias voltage _{V GB1} and second bias voltage _{V GB2} to the change in the output power control voltage _{V APC} of the third bias voltage _{V GB3} being.

The bias voltage dependency shown in FIG. 24 has three bias voltages before the output power control voltage V _APC reaches a predetermined voltage of approximately 1.7 volts, as described in Patent Document 1 described at the beginning. While the rate of change of V _GB1 , V _GB2 , and V _GB3 is set to a relatively small value, after the output power control voltage V _APC reaches a predetermined voltage of approximately 1.7 volts, three bias voltages V _{GB1 are set.} , V _GB2 and V _GB3 are set to relatively large values. Further, after this arrival, the change rate of the second bias voltage V _GB2 is set to be larger than the change rate of the first bias voltage V _GB1 , and the third bias voltage is set to be higher than the change rate of the second bias voltage V _GB2. The change rate of V _GB3 is set to a large change rate.

FIG. 25 is a diagram showing the dependence of the RF output power Pout of the RF power amplifier examined by the inventors prior to the present invention shown in FIG. 23 on the change in the output power control voltage V _APC .

As shown in FIG. 25, in the operation region where the voltage level of the output power control voltage V _APC is relatively low, the RF output power Pout of the RF power amplifier is substantially proportional to the increase of the output power control voltage V _APC along the linear characteristic L. As a result, the RF output power Pout of the RF power amplifier increases. However, the increase rate of the RF output power Pout gradually decreases, and the RF output power Pout reaches saturation.

The reason why the RF output power Pout of the RF power amplifier reaches saturation is, as is well known, that an RF choke (RFC) is connected between the drain (collector) output of the source (emitter) grounded RF power amplifier and the power supply voltage V _DD. This is because the drain (collector) output voltage can be output only from the ground voltage of zero volts to 2V _DD, which is approximately twice the power supply voltage, by connecting a large coil called).

Therefore, as shown in FIG. 25, when the RF output power Pout of the RF power amplifier approaches the maximum output (saturation), the control gain (= ΔPout / ΔV _APC ) decreases, so that the automatic power control (APC) loop The loop bandwidth is also reduced. As a result, when the RF output power Pout is changed in the vicinity of the maximum output power (saturation) during ramp-up and ramp-down as shown in FIG. 22, a response delay occurs and the switching spectrum deteriorates. Guessed.

Note that the automatic power control (APC) loop operation is greatly affected by the loop band of the automatic power control (APC) loop. The elements that determine the loop band are the gain of the error amplifier 7, the degree of coupling between the main line and the subline of the power combiner 5, the detection sensitivity of the power detector 6, the bias circuit 8, and the RF power amplifier shown in FIG. This is the control gain (= ΔPout / ΔV _APC ) of the multistage amplifier circuit 4.

In order to reduce the deterioration of the switching spectrum during ramp-up and ramp-down, the present inventors also examined the use of the back-off method described in Non-Patent Document 1 prior to the present invention. That is, a linear characteristic in which the control gain (= ΔPout / ΔV _APC ) does not decrease below the maximum output (saturation) power in the control region of the RF output power Pout by the output power control voltage V _APC at the time of ramp-up and ramp-down. It is limited to a range close to L. However, in this back-off method, when the power efficiency in the control region of the RF output power Pout by the output power control voltage V _APC at the time of ramp-up and ramp-down is significantly lower than the good power efficiency at the maximum output (saturation). This problem has been clarified by the study by the present inventors prior to the present invention.

On the other hand, according to the technique described in Patent Document 1, after the output power control voltage Vapc reaches a predetermined voltage of approximately 1.7 volts, the first-stage amplification of the first-stage amplifier circuit responding to the change in the control voltage Vapc. The rate of change of the idling current of the intermediate stage amplifier transistor of the intermediate stage amplifier circuit is larger than the rate of change of the idling current of the transistor, and further, the idling current of the final stage amplifier transistor of the final stage amplifier circuit is higher than the idling current of the intermediate stage amplifier transistor. The rate of change increases. As a result, the output impedance of the first stage amplifier circuit and the input impedance of the intermediate stage amplifier circuit in response to changes in the control voltage Vapc change in a complicated manner, and the output impedance of the intermediate stage amplifier circuit and the input impedance of the final stage amplifier circuit become more complex. To change. Therefore, if the balance of the idling current between the stage amplifier circuits is changed in order to prevent the control gain (= ΔPout / ΔV _APC ) from decreasing, the first stage between the output of the first stage amplifier circuit and the input of the intermediate stage amplifier circuit is changed. RF signal reflection occurs due to impedance mismatch between the impedance matching circuit, the output of the intermediate amplifier circuit, and the second impedance matching circuit between the output of the final amplifier circuit and the input of the final amplifier circuit, thereby maintaining high power efficiency. The problem that it becomes difficult is also clarified by the study by the present inventors prior to the present invention.

Furthermore, also in the technique described in Patent Document 2, the idling current of the first stage amplifying transistor is controlled by a linear characteristic in response to the change of the control voltage Vapc, and the idling current of the second stage amplifying transistor is squared. Since the idling current of the third stage amplification transistor is controlled by the third power characteristic, the balance of the idling current between the stage amplification circuits is changed in order to prevent a decrease in control gain (= ΔPout / ΔV _APC ). Then, the same problem as the method described in Patent Document 1 occurs.

Further, also in the technique described in Patent Document 3, the idling current of the first stage amplifier transistor of the first stage amplifier circuit and the idling current of the intermediate stage amplifier transistor of the intermediate stage amplifier circuit are controlled by a linear function of the control voltage Vapc, Since the idling current of the final stage amplification transistor of the final stage amplifier circuit is controlled in proportion to the square of the control voltage Vapc, in order to prevent a decrease in control gain (= ΔPout / ΔV _APC ), idling between the respective stage amplifier circuits is performed. When the current balance is changed, RF signal reflection occurs due to impedance mismatch in the second-stage impedance matching circuit between the output of the intermediate amplifier circuit and the input of the final amplifier circuit, and high power efficiency is maintained. The problem that it becomes difficult is also clarified by the study by the present inventors prior to the present invention.

In conclusion, according to the methods described in Patent Document 1, Patent Document 2, and Patent Document 3, in order to prevent a decrease in control gain (= ΔPout / ΔV _APC ), an idling current between each stage amplifier circuit is determined. If the balance is changed, RF signal reflection occurs due to impedance mismatching, and it becomes difficult to maintain high power efficiency.

  Further, in the methods described in Patent Document 1, Patent Document 2, and Patent Document 3, in order to make the change rate of the idling current of at least two amplification elements of the multistage amplifier circuit constituting the RF power amplifier different. The problem that the addition of two types of bias control circuits is necessary and the semiconductor chip area and the manufacturing cost of the semiconductor integrated circuit increase has also been clarified by the study by the present inventors prior to the present invention.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to reduce the deterioration of the switching spectrum and reduce the power efficiency in the ramp-up or ramp-down.

  Another object of the present invention is to determine the semiconductor chip area and the manufacturing process when determining the idling current of the multistage amplifying element of the multistage amplifying circuit constituting the RF power amplifier in order to reduce the deterioration of the switching spectrum. It is to reduce the increase in cost.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, the RF power amplifier according to the representative embodiment of the present invention includes a multistage amplifier circuit (4) having at least a first stage amplifier circuit (41) and a final stage amplifier circuit (43), and a power detection circuit (5, 6). And an error amplifier (7), a bias circuit (8) having at least a first stage bias circuit (81) and a last stage bias circuit (83), and a control signal enhancement circuit (9).

The first stage bias voltage (V _GB1 ) of the first stage bias circuit (81) is supplied to the first stage amplifier circuit (41), and the first stage idling current of the first stage amplifier circuit (41) is determined.

The final stage bias voltage (V _GB3 ) of the final stage bias circuit (83) is supplied to the final stage amplifier circuit (43), and the final stage idling current of the final stage amplifier circuit (43) is determined.

  The first stage amplifier circuit (41) amplifies the RF input signal (Pin) supplied to the input terminal (1), and the last stage amplifier circuit (43) becomes the first stage amplified output signal of the first stage amplifier circuit (41). In response, the final stage amplified output signal (Pout) is generated.

The power detection circuit (5, 6) is a power detection signal (V _DET ) responsive to the signal level of the final stage amplified output signal (Pout) of the final stage amplifier circuit (43) of the multistage amplifier circuit (4). Is generated.

By supplying the power detection signal (V _DET ) to one input terminal of the error amplifier (7) and supplying the target power signal (V _RAMP ) to the other input terminal of the error amplifier (7), The output terminal of the error amplifier (7) generates a power control voltage (V _APC ).

The power control voltage (V _APC ) is supplied to an input terminal of the control signal enhancement circuit (9), and an output terminal of the control signal enhancement circuit (9) generates an enhancement control signal (V _EN ).

Said control signal enhancement circuit (9) has an input-output characteristic of the predetermined non-linear response to an increase in the previous said power control voltage the power control voltage (V _APC) reaches a predetermined voltage (V _APC) the enhancement control signal in response to an increase in the enhancement control signal (V _EN) the power control voltage than the rate of increase (V _APC) is the power control voltage after reaching the predetermined voltage (V _APC) to ( The increase rate of V _EN ) is set large.

The enhancement control signal (V _EN ) is supplied to the first stage bias circuit (81) and the last stage bias circuit (83), and the first stage idling current and the last stage idling current are the same as the enhancement control signal (V _EN). ) (See FIG. 1).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to reduce deterioration of the switching spectrum during ramp-up or ramp-down and reduce power efficiency.

FIG. 1 is a diagram showing a configuration of an RF power amplifier according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing the characteristics of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 3 is a diagram showing the characteristics of the RF power amplifier according to the first embodiment of the present invention having the control signal enhancement circuit (EN) 9. FIG. 4 is a diagram showing a specific example of the nonlinear characteristic of the enhancement control signal V _EN of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention of FIG. 1 shown in FIG. . FIG. 5 is a diagram showing an example of input / output characteristics of the power detector 6 included in the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 6 is a diagram showing another example of input / output characteristics of the power detector 6 included in the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 7 is a diagram showing a specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 8 shows the change of the output power control voltage V _APC of the output power control current I _APC of the control signal enhancement circuit (EN) 9 including the voltage / current conversion circuit VIC and the current squaring circuit CS1 as shown in FIG. It is a figure which shows the change characteristic which responds to. FIG. 9 is a diagram showing another specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 10 is a diagram showing in more detail the configuration of multistage amplifier circuit 4, bias circuit 8 and control signal enhancement circuit (EN) 9 of the RF power amplifier according to Embodiment 1 of the present invention shown in FIG. FIG. 11 is a diagram showing in more detail the other configurations of the multistage amplifier circuit 4, the bias circuit 8, and the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. . FIG. 12 is a diagram showing another specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 13 is a diagram showing another specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. FIG. 14 is a diagram showing another configuration of the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention. FIG. 15 is a diagram for explaining the operation of the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. FIG. 16 is a diagram for explaining the characteristics of the output power control current I _APC generated from the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. FIG. 17 is a diagram showing another configuration of the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention. FIG. 18 is a diagram for explaining the characteristics of the output power control current I _APC generated from the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention shown in FIG. FIG. 19 is a diagram showing a specific configuration of the RF power amplifier according to the fourth embodiment of the present invention. FIG. 20 is a diagram showing a configuration of a transmission system using the RF power amplifier according to the fifth embodiment of the present invention. FIG. 21 is a diagram showing a configuration of a variable gain amplifier (VGA) 19 of the RF signal processing semiconductor integrated circuit (RFIC) of the transmission system according to the fifth embodiment of the present invention shown in FIG. FIG. 22 is a diagram illustrating the relationship between the time mask defined by the GMSK standard and the signal strength of the RF transmission signal. FIG. 23 is a diagram showing a configuration of an RF power amplifier studied by the present inventors prior to the present invention. 24 is generated from the first bias circuit 81, the second bias circuit 82, and the third bias circuit 83 of the bias circuit 8 of the RF power amplifier examined by the present inventors prior to the present invention shown in FIG. it is a diagram showing the dependence of the first bias voltage _{V GB1} and second bias voltage _{V GB2} to the change in the output power control voltage _{V APC} of the third bias voltage _{V GB3} being. FIG. 25 is a diagram showing the dependence of the RF output power Pout of the RF power amplifier examined by the inventors prior to the present invention shown in FIG. 23 on the change in the output power control voltage V _APC .

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] An RF power amplifier according to a typical embodiment of the present invention includes a multistage amplifier circuit (4) having at least a first stage amplifier circuit (41) and a final stage amplifier circuit (43), and power detection circuits (5, 6). ), An error amplifier (7), a bias circuit (8) having at least a first stage bias circuit (81) and a last stage bias circuit (83), and a control signal enhancement circuit (9).

The first stage bias voltage (V _GB1 ) of the first stage bias circuit (81) is supplied to the first stage amplifier circuit (41), and the first stage idling current of the first stage amplifier circuit (41) is determined.

The final stage bias voltage (V _GB3 ) of the final stage bias circuit (83) is supplied to the final stage amplifier circuit (43), and the final stage idling current of the final stage amplifier circuit (43) is determined.

  The first stage amplifier circuit (41) is capable of amplifying the RF input signal (Pin) supplied to the input terminal (1), and the last stage amplifier circuit (43) is a first stage amplified output signal of the first stage amplifier circuit (41). In response to this, the final stage amplified output signal (Pout) can be generated.

The power detection circuit (5, 6) is a power detection signal (V _DET ) responsive to the signal level of the final stage amplified output signal (Pout) of the final stage amplifier circuit (43) of the multistage amplifier circuit (4). Can be generated.

By supplying the power detection signal (V _DET ) to one input terminal of the error amplifier (7) and supplying the target power signal (V _RAMP ) to the other input terminal of the error amplifier (7), A power control voltage (V _APC ) can be generated from the output terminal of the error amplifier (7).

When the power control voltage (V _APC ) is supplied to the input terminal of the control signal enhancement circuit (9), the enhancement control signal (V _EN ) can be generated from the output terminal of the control signal enhancement circuit (9). Is done.

Said control signal enhancement circuit (9) are those having the input-output characteristics of a given non-linear, increases in previous the power control voltage the power control voltage (V _APC) reaches a predetermined voltage (V _APC) The enhancement control responding to an increase in the power control voltage (V _APC ) after the power control voltage (V _APC ) reaches the predetermined voltage rather than an increase rate of the enhancement control signal (V _EN ) responding to The increase rate of the signal (V _EN ) is set large.

The enhancement control signal (V _EN ) is supplied to the first stage bias circuit (81) and the last stage bias circuit (83), and the first stage idling current and the last stage idling current are the same as the enhancement control signal (V _EN). ) (See FIG. 1).

  According to the embodiment, it is possible to reduce deterioration of the switching spectrum during ramp-up or ramp-down and reduce power efficiency. Furthermore, according to the above embodiment, when determining the idling current of the multistage amplifying element of the multistage amplifying circuit constituting the RF power amplifier in order to reduce the deterioration of the switching spectrum described above, the semiconductor chip area and the manufacturing cost are increased. Can be reduced.

  In a preferred embodiment, the multistage amplifier circuit (4) further includes an intermediate stage amplifier circuit (42) connected between the first stage amplifier circuit (41) and the final stage amplifier circuit (43).

  The bias circuit (8) further includes an intermediate stage bias circuit (82) connected to the intermediate stage amplifier circuit (42).

The intermediate stage bias voltage (V _GB2 ) of the intermediate stage bias circuit (82) is supplied to the intermediate stage amplifier circuit (42), and the intermediate stage idling current of the intermediate stage amplifier circuit (42) is determined.

The enhancement control signal (V _EN ) is supplied to the intermediate stage bias circuit (82), and the intermediate stage idling current is controlled by the enhancement control signal (V _EN ) (FIG. 1).

In another preferred embodiment, the first stage bias circuit (81) includes a first stage bias transistor (Q _B1 ) connected in a current mirror manner to the first stage amplifier transistor (Q _A1 ) of the first stage amplifier circuit (41).

The final stage bias circuit (83) includes a final stage bias transistor (Q _B3 ) connected in a current mirror manner with the final stage amplification transistor (Q _A3 ) of the final stage amplification circuit (43).

The first stage bias current (I _APC1 ) and the last stage bias current (I _APC3 ) as the enhancement control signal (V _EN ) are supplied to the first stage bias transistor (Q _B1 ) and the last stage bias transistor (Q _B3 ), respectively. The first stage idling current and the last stage idling current are determined by the first stage bias current (I _APC1 ) and the last stage bias current (I _APC3 ), respectively (see FIG. 10). ).

In still another preferred embodiment, the intermediate-stage bias circuit (82) includes an intermediate-stage bias transistor (Q _B2 ) that is current-mirror connected to the intermediate-stage amplifier transistor (Q _A2 ) of the intermediate-stage amplifier circuit (42). )including.

An intermediate stage bias current (I _APC2 ) as the enhancement control signal (V _EN ) is supplied to the intermediate stage bias transistor (Q _B2 ), and the intermediate stage idling current is determined by the intermediate stage bias current (I _APC2 ), respectively. (See FIG. 10).

  In a more preferred embodiment, the control signal enhancement circuit (9) includes a voltage / current conversion circuit (VIC) and a current square circuit (CS1).

The voltage / current conversion circuit (VIC) can generate a conversion current (I _{APC_LIN} ) that is substantially proportional to the change in response to the change in the power control voltage (V _APC ).

The current square circuit (CS1) can generate a square output current (I _{APC_SQ} ) that is substantially proportional to the square of the power control voltage (V _APC ).

The control signal enhancement circuit (9) generates an output power control current (I _APC ) by adding the conversion current (I _{APC_LIN} ) and the square output current (I _{APC_SQ} ) as the enhancement control signal (V _EN ). This is characterized in that it is possible (see FIG. 7).

  In another more preferred embodiment, the control signal enhancement circuit (9) includes a voltage / current conversion circuit (VIC) and a current cube circuit (CB).

The voltage / current conversion circuit (VIC) can generate a conversion current (I _{APC_LIN} ) that is substantially proportional to the change in response to the change in the power control voltage (V _APC ).

The current cube circuit (CB) can generate a cubed output current (I _{APC_CB} ) that is substantially proportional to the cube of the power control voltage (V _APC ).

The control signal enhancement circuit (9) generates an output power control current (I _APC ) by adding the conversion current (I _{APC_LIN} ) and the cubed output current (I _{APC_CB} ) as the enhancement control signal (V _EN ). This is characterized in that it is possible (see FIG. 13).

In yet another more preferred embodiment, the control signal enhancement circuit (9) has a plurality of operational amplifiers (OP2, OP3, OP4), thereby providing non-linear characteristics with respect to a plurality of reference voltages (Vref1, Vref2). The output power control current (I _APC ) having the following can be generated as the enhancement control signal (V _EN ) (see FIG. 14).

In another more preferred embodiment, the control signal enhancement circuit (9) comprises an analog-to-digital converter (10), a look-up table (11), and digital-to-analog converters (12, 13, OP1, R ₂ , MP01, MP02).

The analog / digital converter (10) can convert the power control voltage (V _APC ) supplied from the error amplifier (7) into a first digital signal.

  The look-up table (11) has the predetermined non-linear input / output characteristic, and can convert the first digital signal into a second digital signal according to the predetermined non-linear input / output characteristic.

The digital / analog converters (12, 13, OP1, R ₂ , MP01, MP02) generate an output power control current (I _APC ) obtained by analog conversion of the second digital signal as the enhancement control signal (V _EN ). This is characterized in that it is possible (see FIG. 17).

In still another more preferred embodiment, the target power signal (V _RAMP ) supplied to the other input terminal of the error amplifier (7) is ramped up in a transmission operation time slot of the time division multiple access method. And ramp-down can be controlled.

In a specific embodiment, each of the first stage amplification transistor (Q _A1 ), the last stage amplification transistor (Q _A3 ), the first stage bias transistor (Q _B1 ), and the last stage bias transistor (Q _B3 ) is: It is a MOS transistor or a bipolar transistor.

  [2] A typical embodiment of another aspect of the present invention includes a multistage amplifier circuit (4) having at least an initial stage amplifier circuit (41) and a final stage amplifier circuit (43), and power detection circuits (5, 6). ), An error amplifier (7), a bias circuit (8) having at least a first stage bias circuit (81) and a last stage bias circuit (83), and a control signal enhancement circuit (9). Is the method.

The first stage bias voltage (V _GB1 ) of the first stage bias circuit (81) is supplied to the first stage amplifier circuit (41), and the first stage idling current of the first stage amplifier circuit (41) is determined.

The final stage bias voltage (V _GB3 ) of the final stage bias circuit (83) is supplied to the final stage amplifier circuit (43), and the final stage idling current of the final stage amplifier circuit (43) is determined.

  The first stage amplifier circuit (41) is capable of amplifying the RF input signal (Pin) supplied to the input terminal (1), and the last stage amplifier circuit (43) is a first stage amplified output signal of the first stage amplifier circuit (41). In response to this, the final stage amplified output signal (Pout) can be generated.

The power detection circuit (5, 6) is a power detection signal (V _DET ) responsive to the signal level of the final stage amplified output signal (Pout) of the final stage amplifier circuit (43) of the multistage amplifier circuit (4). Can be generated.

By supplying the power detection signal (V _DET ) to one input terminal of the error amplifier (7) and supplying the target power signal (V _RAMP ) to the other input terminal of the error amplifier (7), A power control voltage (V _APC ) can be generated from the output terminal of the error amplifier (7).

When the power control voltage (V _APC ) is supplied to the input terminal of the control signal enhancement circuit (9), the enhancement control signal (V _EN ) can be generated from the output terminal of the control signal enhancement circuit (9). Is done.

Said control signal enhancement circuit (9) are those having the input-output characteristics of a given non-linear, increases in previous the power control voltage the power control voltage (V _APC) reaches a predetermined voltage (V _APC) The enhancement control responding to an increase in the power control voltage (V _APC ) after the power control voltage (V _APC ) reaches the predetermined voltage rather than an increase rate of the enhancement control signal (V _EN ) responding to The increase rate of the signal (V _EN ) is set large.

The enhancement control signal (V _EN ) is supplied to the first stage bias circuit (81) and the last stage bias circuit (83), and the first stage idling current and the last stage idling current are the same as the enhancement control signal (V _EN). ) (See FIG. 1).

  According to the embodiment, it is possible to reduce deterioration of the switching spectrum during ramp-up or ramp-down and reduce power efficiency. Furthermore, according to the above embodiment, when determining the idling current of the multistage amplifying element of the multistage amplifying circuit constituting the RF power amplifier in order to reduce the deterioration of the switching spectrum described above, the semiconductor chip area and the manufacturing cost are increased. Can be reduced.

  [3] A representative embodiment of another aspect of the present invention is that a multistage amplifier circuit (4) having at least a first stage amplifier circuit (41) and a final stage amplifier circuit (43), a first stage bias circuit (81), This is an operation method of an RF power amplifier including a bias circuit (8) having at least a final stage bias circuit (83) and a power detection circuit (5, 6).

The first stage bias voltage (V _GB1 ) of the first stage bias circuit (81) is supplied to the first stage amplifier circuit (41), and the first stage idling current of the first stage amplifier circuit (41) is determined.

The final stage bias voltage (V _GB3 ) of the final stage bias circuit (83) is supplied to the final stage amplifier circuit (43), and the final stage idling current of the final stage amplifier circuit (43) is determined.

  The first stage amplifier circuit (41) can amplify an RF input signal (Pin) supplied to the input terminal (1) of the RF power amplifier, and the last stage amplifier circuit (43) is capable of amplifying the first stage amplifier circuit (41). In response to the first stage amplified output signal, the last stage amplified output signal (Pout) can be generated.

The power detection circuit (5, 6) is a power detection signal (V _DET ) responsive to the signal level of the final stage amplified output signal (Pout) of the final stage amplifier circuit (43) of the multistage amplifier circuit (4). Can be generated.

  A semiconductor integrated circuit (RFIC) including an error amplifier (7), a control signal enhancement circuit (9), and a variable gain amplifier (19) is connected in advance to the RF power amplifier.

  When an RF transmission input signal (RFin) is supplied to an input terminal of the variable gain amplifier (19) of the semiconductor integrated circuit (RFIC), an output signal of the variable gain amplifier (19) is converted to the RF input signal (Pin). ) Can be supplied to the input terminal (1) of the RF power amplifier.

The power detection signal (V _DET ) generated from the power detection circuit (5, 6) of the RF power amplifier is supplied to one input terminal of the error amplifier (7) of the semiconductor integrated circuit (RFIC). On the other hand, by supplying the target power signal (V _RAMP ) to the other input terminal of the error amplifier (7), a power control voltage (V _APC ) can be generated from the output terminal of the error amplifier (7). The

When the power control voltage (V _APC ) is supplied to the input terminal of the control signal enhancement circuit (9), the enhancement control signal (V _EN ) can be generated from the output terminal of the control signal enhancement circuit (9). Is done.

Said control signal enhancement circuit (9) are those having the input-output characteristics of a given non-linear, increases in previous the power control voltage the power control voltage (V _APC) reaches a predetermined voltage (V _APC) The enhancement control responding to an increase in the power control voltage (V _APC ) after the power control voltage (V _APC ) reaches the predetermined voltage rather than an increase rate of the enhancement control signal (V _EN ) responding to The increase rate of the signal (V _EN ) is set large.

By supplying the enhancement control signal (V _EN ) to the gain control terminal of the variable gain amplifier (19), the variable gain of the variable gain amplifier (19) is controlled by the enhancement control signal (V _EN ). (See FIG. 20).

  In a preferred embodiment, the RF transmission input signal (RFin) supplied to the input terminal of the variable gain amplifier (19) is at least one of WCDMA, EDGE, LTE, and HSUPA. The RF transmission signal conforms to the above (see FIG. 20).

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<< Configuration of RF power amplifier >>
FIG. 1 is a diagram showing a configuration of an RF power amplifier according to Embodiment 1 of the present invention.

  The RF power amplifier according to the first embodiment of the present invention shown in FIG. 1 is different from the RF power amplifier examined by the present inventors prior to the present invention shown in FIG. 23 in the following points.

That is, a control signal enhancement circuit (EN) 9 that is not included in the RF power amplifier of FIG. 23 is added to the RF power amplifier according to the first embodiment of the present invention shown in FIG. The control signal enhancement circuit (EN) 9 generates the enhancement control signal V _EN in response to the output power control voltage V _APC generated from the error amplifier 7 to generate the first bias circuit 81 and the second bias circuit of the bias circuit 8. 82 and the third bias circuit 83.

  FIG. 2 is a diagram showing the characteristics of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG.

As shown in FIG. 2, the RF output power Pout of the RF power amplifier not provided with the control signal enhancement circuit (EN) 9 approaches the maximum output (saturation), and compared with the linear characteristic L, the control gain (= ΔPout / ΔV _APC On the contrary, the increase rate of the value of the enhancement control signal V _EN increases from the operation region where the decrease starts. That is, the control gain (= ΔPout / ΔV _APC) than the increase rate of the enhanced control signal _{V EN} starting a previous reduction in the control gain (= ΔPout / ΔV _APC) after the start in the enhanced control signal _{V EN} of the decrease in the Increase rate is set large.

  FIG. 3 is a diagram showing the characteristics of the RF power amplifier according to the first embodiment of the present invention having the control signal enhancement circuit (EN) 9.

  That is, in FIG. 3, the characteristic Pout indicates the RF output power of the RF power amplifier shown in FIG. 23 that does not include the control signal enhancement circuit (EN) 9, while the characteristic Pout_EN includes the control signal enhancement circuit (EN) 9. FIG. 2 shows RF output power of the RF power amplifier according to Embodiment 1 of the present invention shown in FIG. 1. FIG.

Since the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1 includes the control signal enhancement circuit (EN) 9 having the control characteristics shown in FIG. 2, the control gain of the characteristic Pout as shown in FIG. A decrease in (= ΔPout_EN / ΔV _APC ) is compensated by an increase in the enhancement control signal V _EN of the control signal enhancement circuit (EN) 9.

That is, the RF output power characteristic Pout_EN of the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1 having the control signal enhancement circuit (EN) 9 having the control characteristics shown in FIG. In response to V _APC , the maximum output power (saturation) is reached relatively early while maintaining the substantially linear characteristic L. As a result, in the linear characteristic L until the maximum output power (saturation) is reached, the decrease in the control gain (= ΔPout_EN / ΔV _APC ) can be reduced to a negligible level.

  Accordingly, when the maximum output power (saturation) is approached, the reduction of the loop band of the automatic power control (APC) loop can be similarly reduced.

  Thus, according to the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1 having the control signal enhancement circuit (EN) 9 having the control characteristics shown in FIG. ), The response delay can be reduced when the RF output power Pout_EN is changed, so that it is possible to reduce the deterioration of the switching spectrum during ramp-up and ramp-down.

Further, according to the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1, the first stage amplifier circuit 41 and the intermediate stage amplifier circuit 42 of the multistage amplifier circuit 4 regardless of the presence or absence of the control signal enhancement circuit (EN) 9. The bias balance of the final stage amplifier circuit 43 does not change, and the control region of the RF output power Pout_EN that responds to the output power control voltage V _APC at the time of ramp-up and ramp-down is set to approximately the maximum output power (saturation). Therefore, it is possible to realize a power efficiency substantially equal to a good power efficiency of the maximum output power (saturation).

<< Specific configuration of RF power amplifier >>
Therefore, the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1 includes an RF signal input terminal 1, an RF signal output terminal 2, a lamp control terminal 3, a multistage amplifier circuit 4, a power combiner 5, and a power detector 6. , An error amplifier 7, a bias circuit 8, and a control signal enhancement circuit (EN) 9.

  The RF signal input terminal 1 is supplied with an RF input signal Pin generated by a transmission signal processing unit of an RF signal processing semiconductor integrated circuit (RFIC) mounted on a mobile phone terminal. The RF input signal Pin is sequentially amplified by the first stage amplifier circuit 41, the intermediate stage amplifier circuit 42, and the final stage amplifier circuit 43 of the multistage amplifier circuit 4, and the amplified output signal of the final stage amplifier circuit 43 passes through the main line of the power combiner 5. Via the RF signal output terminal 2 as an RF output signal Pout.

A part of the RF output signal Pout is transmitted to the subline of the power coupler 5 that is electromagnetically and electrostatically coupled to the main line of the power coupler 5. As a result, the power detector 6 whose input terminal is connected to the sub line of the power combiner 5 generates a power detection voltage V _DET proportional to the signal level of the RF output signal Pout, and one input terminal of the error amplifier 7. To supply. The ramp voltage V _RAMP supplied to the other input terminal of the error amplifier 7 via the ramp control terminal 3 for ramp-up and ramp-down is a lamp D / A conversion built in the RF signal processing semiconductor integrated circuit (RFIC). Generated from the analog output terminal of the instrument. Digital ramp data for ramp-up and ramp-down is generated inside the baseband signal processing LSI, and the digital ramp data is built into the RF signal processing semiconductor integrated circuit (RFIC) via the digital interface from the baseband signal processing LSI. Are supplied to the digital input terminal of the lamp D / A converter.

The error amplifier (EA) 7 detects the difference between the power detection voltage V _DET at one input terminal and the ramp voltage V _RAMP at the other input terminal, and generates an output power control voltage V _APC proportional to the difference. The signal is supplied to the input terminal of the control signal enhancement circuit (EN) 9.

The control signal enhancement circuit (EN) 9 generates an enhancement control signal V _EN in response to the output power control voltage V _APC generated from the error amplifier (EA) 7 and the first bias circuit 81 and the first bias circuit 81 of the bias circuit 8. The second bias circuit 82 and the third bias circuit 83 are supplied.

  Although not shown in FIG. 1, the first bias circuit 81, the second bias circuit 82, and the third bias circuit 83 include a first bias transistor, a second bias transistor, and a third bias transistor, respectively. The first bias transistor of the first bias circuit 81 is current mirror connected to the first stage amplifier transistor of the first stage amplifier circuit 41, and the second bias transistor of the second bias circuit 82 is the current stage mirror and the intermediate stage amplifier transistor of the intermediate stage amplifier circuit 42. The third bias transistor of the third bias circuit 83 is connected to the final stage amplifier transistor of the final stage amplifier circuit 43 in a current mirror connection.

Although not shown in FIG. 1, the enhancement control signal V _EN supplied from the control signal enhancement circuit (EN) 9 to the bias circuit 8 is actually a first bias current, a second bias current, and a third bias. It is a current. That is, the first bias current and the second bias current and third bias current as potentiators control signal V _EN is responsive to the output power control voltage V _APC in a non-linear increase rate of the enhanced control signal V _EN shown in FIG. 2 And change.

When the first bias current flows into the first bias transistor of the first bias circuit 81, the first bias voltage V _GB1 is generated from the first bias transistor. Further, when the second bias current flows into the second bias transistor of the second bias circuit 82, the second bias voltage V _GB2 is generated from the second bias transistor. Similarly, when the third bias current flows into the third bias transistor of the third bias circuit 83, the third bias voltage V _GB3 is generated from the third bias transistor.

The first bias voltage V _GB1 is supplied to the gate of the first stage amplification MOS transistor of the first stage amplification circuit 41, and the idling current of the first stage amplification transistor is determined. Further, the second bias voltage V _GB2 is supplied to the gate of the intermediate stage amplification MOS transistor of the intermediate stage amplification circuit 42, and the idling current of the intermediate stage amplification transistor is determined. Similarly, the third bias voltage V _GB3 is supplied to the gate of the final stage amplification MOS transistor of the final stage amplification circuit 43, and the idling current of the final stage amplification transistor is determined.

As a result, the idling current of the first stage amplifying transistor of the first stage amplifying circuit 41, the idling current of the middle stage amplifying transistor of the intermediate stage amplifying circuit 42, and the idling current of the last stage amplifying transistor of the last stage amplifying circuit 43 are shown in FIG. The increase control signal V _EN changes in response to the output power control voltage V _APC at a non-linear increase rate.

As described above, according to the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1, the first stage amplifier circuit 41 of the multistage amplifier circuit 4 for compensating for the decrease in the control gain (= ΔPout_EN / ΔV _APC ) and the intermediate Since the change rate of the idling current of each amplification element of the stage amplification circuit 42 and the final stage amplification circuit 43 is determined in common by the control signal enhancement circuit (EN) 9 that outputs the enhancement control signal _VEN , the semiconductor chip area and An increase in manufacturing cost can be reduced.

《Specific example of nonlinear characteristics of enhancement control signal》
FIG. 4 is a diagram showing a specific example of the nonlinear characteristic of the enhancement control signal V _EN of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention of FIG. 1 shown in FIG. .

In the specific example shown in FIG. 4, before the output power control voltage V _APC reaches a predetermined value, the value of the boost control signal V _EN changes according to the linear characteristic L, while the output power control voltage V _APC has a predetermined value. After reaching the value, the value of the enhancement control signal V _EN is set so as to change according to the characteristic L _{EN obtained} by adding the square characteristic to the linear characteristic L.

<Input / output characteristics of power detector>
FIG. 5 is a diagram showing an example of input / output characteristics of the power detector 6 included in the RF power amplifier according to the first embodiment of the present invention shown in FIG.

As shown in the characteristic L _DET in FIG. 5, the power detection voltage V _{DET at} the output terminal of the power detector 6 changes in proportion to the change in the logarithmic value of the input power _{PIN_DET} at the input terminal of the power detector 6. It is.

  FIG. 6 is a diagram showing another example of input / output characteristics of the power detector 6 included in the RF power amplifier according to the first embodiment of the present invention shown in FIG.

As shown by the characteristic L _DET in FIG. 6, before the input power P _{IN_DET at} the input terminal of the power detector 6 reaches a predetermined value, it is proportional to the change in the logarithmic value of the input power P _{IN_DET} of the power detector 6. Thus, the power detection voltage V _{DET at} the output terminal of the power detector 6 changes. On the other hand, as indicated by the characteristic L _{DET_EN} in FIG. 6, the value of the power detection voltage V _DET changes according to the linear characteristic L after the input power P _{IN_DET} reaches a predetermined value.

  As a result, when the power detector 6 having the input / output characteristics shown in FIG. 6 is used, the RF power amplifier according to the first embodiment of the present invention shown in FIG. 1 outputs the RF output signal Pout having a high output level. It becomes possible to improve the controllability.

《Specific example of control signal enhancement circuit》
FIG. 7 is a diagram showing a specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG.

  As shown in FIG. 7, the control signal enhancement circuit (EN) 9 includes a voltage / current conversion circuit VIC and a current squaring circuit CS1.

Voltage-to-current converter circuit VIC includes resistors R1, R2, R3 and an operational amplifier OP1 and a reference voltage _{V REF} and P-channel MOS transistors MP01, MP02, MP03, and N-channel MOS transistors MN11, MN12, and the offset current _{I OFFSET,} And an initial current I _INT .

Current squaring circuit CS1 includes a P-channel MOS transistors MP21, MP22, MP23, MP24 and the reference current _{I REF.}

Output power control voltage _{V APC} by resistors R1, R2, R3 and an operational amplifier OP1 and a reference voltage _{V REF} and P-channel MOS transistor MP01 of the voltage-current conversion circuit VIC, is converted into conversion current _{I APC0.} Since the potentials of the non-inverting input terminal and the inverting output terminal of the operational amplifier OP1 are equal, the following equation (1) is established.

By converting the above equation (1), the conversion current I _APC0 flowing through the P-channel MOS transistor MP01 is calculated by the following equation (2).

  Since the source / gate voltages of the three P-channel MOS transistors MP01, MP02, and MP03 are the same, assuming that the transistor sizes of the P-channel MOS transistors MP01, MP02, and MP03 are n01, n02, and n03, three P-channel MOS transistors The drain current of the MOS transistor is proportional to the transistor size.

Therefore, the current I _{APC_LIN} flowing through the P-channel MOS transistor MP03 is calculated by the following equation (3).

On the other hand, the difference between the current flowing through the P-channel MOS transistor MP02 and the offset current I _OFFSET becomes the input current I _{SQ_IN of the} current square circuit CS1 via the N-channel MOS transistors MN11 and MN12 of the current mirror, and this input current I _{SQ_IN} Is calculated by the following equation (4). Here, the transistor sizes of the N-channel MOS transistors MN11 and MN12 of the current mirror are n11 and n12.

The four P-channel MOS transistors MP21, MP22, MP23, and MP24 included in the current square circuit CS1 are connected to the voltage / current conversion circuit VIC supplied to the current square circuit CS1 so as to operate in the subthreshold region. The maximum output current value of the input current I _{SQ_IN} supplied from the N-channel MOS transistors MN11 and MN12 of the current mirror is set.

On the other hand, as is well known, the drain current _ID due to the weak inversion layer does not become zero under the condition that the gate-source voltage V _GS of the MOS transistor is lower than the threshold voltage Vth. drain current I _D to decrease the wake of the V _GS decreases exponentially.

  This is called a subthreshold leakage current and is calculated by the following equation (5).

Here, _ISO and ζ are constants determined by the manufacturing process of the MOS transistor, and ζ> 1 is an error coefficient representing an error from the ideal. The thermal voltage V _T is V _T = kT / q, k is the Boltzmann constant, T is the absolute temperature, and q is the charge amount of electrons. It will be referred to herein as the saturation current I _SO.

  The following equation (6) is calculated by modifying the above equation (5).

From this equation (6), it can be understood that the gate-source voltage V _GS of the sub-threshold MOS transistor is determined by the ratio of the saturation current _ISO to the drain current _ID .

That is, the value of the maximum output current of the input current I _{SQ_IN} from the voltage / current conversion circuit VIC and the N-channel MOS transistors MN11 and MN12 of the current mirror to the current squaring circuit CS1 in response to the maximum value of the output power control voltage V _APC Is maintained, the gate-source voltage V _GS is kept lower than the threshold voltage Vth by setting the upper limit value of the ratio of the saturation current _ISO to the drain current _ID in equation (6) It is important to.

  Here, in order to simplify the calculation, the following equation (7) is calculated by modifying the above equation (6).

That is, the constant C ₀ and a constant C ₁ of the formula (7), and corresponds to a product ZetaV _T between the saturation current I _SO and the error coefficient and thermal voltage of the above formula (6).

The gate-source voltages V _GS of the four P-channel MOS transistors MP21, MP22, MP23, and MP24 of the current squaring circuit CS1 are V _GS21 , V _GS22 , V _GS23 , and V _GS24 , respectively. Let n21, n22, n23, and n24. The drain currents of the transistors MP21 and MP22 connected in series are the input current I _{SQ_IN} of the current square circuit CS1, the drain current of the transistor MP23 is the reference current I _REF , and the drain current of the transistor MP24 is the output of the current square circuit CS1 Since it is the current I _{APC_SQ} , the following equation (8) is calculated.

Since the sum of the gate-source voltages V _GS of the transistors MP21 and MP22 connected in series is equal to the sum of the gate-source voltages V _GS of the transistors MP23 and MP24, the following equation (9) is calculated.

  When the above equation (8) is substituted into the above equation (9), the relationship of the following equation (10) is calculated.

From the above equation (10), it is understood that the output current I _{APC_SQ} of the current squaring circuit CS1 is proportional to the square of the input current I _{SQ_IN} .

When the input current I _{SQ_IN of the} current squaring circuit CS1 is zero, the drain current does not flow through the serially connected transistors MP21 and _MP22 . Therefore, the gate voltage of the transistor MP23 becomes substantially the power supply voltage V _DD and the transistor MP23 has a reference current. I _REF does not flow. Since the reference current I _REF starts to flow through the transistor MP23 from the time when the input current I _{SQ_IN} is supplied to the current square circuit CS1 from this state, a response delay may occur in the current square conversion operation of the current square circuit CS1. There is sex.

In order to reduce this response delay, the initial current I _INT is connected between the source / drain current path of the transistors MP21 and MP22 connected in series in the current square circuit CS1 and the ground voltage GND. Therefore, since the initial current I _INT set to a current of about several μA together with the input current I _{SQ_IN} flows to the input terminal of the current squaring circuit CS1, the above equation (10) becomes the following equation (11): .

As shown in FIG. 7, in the circuit node CN of the control signal enhancement circuit (EN) 9 including the voltage / current conversion circuit VIC and the current square circuit CS1, the current flows to the P-channel MOS transistor MP03 of the above equation (3). The current I _{APC_LIN} and the output current I _{APC_SQ of the} current squaring circuit CS1 of the above equation (11) are added to generate the output power control current I _APC . This output power control current I _APC is expressed by the following equation (12).

From the above equation (12), it is understood that the output power control current I _APC is proportional to the first power and the second power of the output power control voltage V _APC .

FIG. 8 shows changes in the output power control voltage V _APC of the output power control current I _APC of the control signal enhancement circuit (EN) 9 including the voltage / current conversion circuit VIC and the current squaring circuit CS1 as shown in FIG. It is a figure which shows the change characteristic which responds to.

In FIG. 8, the characteristic L1 represents a linear characteristic (the first power characteristic of the output power control voltage V _APC ), while the characteristic L2 represents the characteristic according to the above equation (12).

As can be understood from FIG. 8, before the output power control voltage V _APC reaches the first predetermined voltage V ₀ (= 0.384 volts), the output power control current I _APC becomes zero, and the output power control voltage When V _APC is between the first predetermined voltage V ₀ and the second predetermined voltage V ₁ (= 0.997 volts), the output power control current I _APC varies according to the linear characteristic L1, and the output power control voltage V _APC is 2 after having reached the predetermined voltages V ₁ is to vary according to the synthetic characteristic L2 of the first power property and the square-law characteristic according to the aforementioned equation (12).

  FIG. 9 is a diagram showing another specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG.

  The control signal enhancement circuit (EN) 9 shown in FIG. 9 is different from the control signal enhancement circuit (EN) 9 shown in FIG. 7 in that the four P-channel MOS transistors MP21, MP22, MP23, and MP24 in FIG. It is replaced with four PNP bipolar transistors QP21, QP22, QP23, QP24.

On the other hand, as is well known, the collector current I _C of the bipolar transistor, the saturation current I _SO and electron charge amount q and the Boltzmann constant k and absolute temperature T and the thermal voltage V _T and the base-emitter voltage V _BE Is calculated by the following equation (13).

  By transforming the above equation (13), the following equation (14) is calculated.

From this equation (14), the base-emitter voltage V _BE of the bipolar transistor can be understood to be determined by the ratio of the saturation current I _SO versus collector current I _C.

The base-emitter voltages V _BE of the four bipolar transistors QP21, QP22, QP23, and QP24 of the current squaring circuit CS1 are respectively V _BE21 , V _BE22 , V _BE23 , and V _BE24, and the transistor sizes of the transistors are n21 and n22 , N23, and n24. The collector currents of the transistors QP21 and QP22 connected in series are the input current I _{SQ_IN} of the current square circuit CS1, the collector current of the transistor QP23 is the reference current I _REF , and the collector current of the transistor QP24 is the output of the current square circuit CS1 Since it is the current I _{APC_SQ} , the following equation (15) is calculated.

Since the sum of the base-emitter voltages V _BE of the transistors QP21 and QP22 connected in series is equal to the sum of the base-emitter voltages V _BE of the transistors QP23 and QP24, the following equation (16) is calculated.

  When the above equation (15) is substituted into the above equation (16), the relationship of the following equation (17) is calculated.

From the above equation (17), it is understood that the output current I _{APC_SQ} of the current square circuit CS1 of the control signal enhancement circuit (EN) 9 shown in FIG. 9 is proportional to the square of the input current I _{SQ_IN} .

  It is understood that the operation function of the control signal enhancement circuit (EN) 9 shown in FIG. 9 is completely equivalent to that of the control signal enhancement circuit (EN) 9 shown in FIG. Note that the current squaring circuit CS1 included in the control signal enhancement circuit (EN) 9 shown in FIG. 7 and FIG. 9 is called translinear, and is increased to the third power by increasing the number of transistors connected in series to three. A proportional output current can be obtained, and an output current proportional to the fourth power can be obtained by increasing the series connection of the transistors to four.

  FIG. 10 is a diagram showing in more detail the configuration of multistage amplifier circuit 4, bias circuit 8 and control signal enhancement circuit (EN) 9 of the RF power amplifier according to Embodiment 1 of the present invention shown in FIG.

Although not shown in FIG. 10, in order to reduce the response delay, the initial current I _INT is between the source / drain current paths of the series-connected transistors MP21 and MP22 of the current square circuit CS1 and the ground voltage GND. Connected to.

  As shown in FIG. 10, the RF input signal Pin is supplied to the input terminal of the first stage amplifier circuit 41 of the multistage amplifier circuit 4 via the input impedance matching circuit 91.

Drain of the source grounded N-channel MOS transistor Q _A1 is the first stage amplifier transistor of the first-stage amplifier circuit 41 via an inductor as a load is connected to the power supply voltage V _DD. The drain and gate of the common-source N-channel MOS transistor Q _B1 which is the first bias transistor of the first bias circuit 81 are connected to the gate of the N-channel MOS transistor Q _A1 through a resistor R _B1 in a current mirror connection. The RF first stage amplified signal generated at the drain of the N channel MOS transistor Q _A1 is supplied to the input terminal of the intermediate stage amplifier circuit 42 via the first interstage impedance matching circuit 92.

Drain of the source grounded N-channel MOS transistor Q _A2 is an intermediate stage amplifying transistor of the intermediate-stage amplifier 42, via an inductor as a load is connected to the power supply voltage V _DD. The drain and gate of the common-source N-channel MOS transistor Q _B2 which is the second bias transistor of the second bias circuit 82 are connected to the gate of the N-channel MOS transistor Q _A2 through a resistor R _B2 in a current mirror connection. The RF intermediate stage amplified signal generated at the drain of the N-channel MOS transistor Q _A2 is supplied to the input terminal of the final stage amplifier circuit 43 via the second interstage impedance matching circuit 93.

The drain of the common-source N-channel MOS transistor _QA3 , which is the final stage amplification transistor of the final stage amplification circuit 43, is connected to the power supply voltage V _DD via an inductor as a load. The third drain source grounded a third bias transistor in the bias circuit 83 N-channel MOS transistor _{Q B3} and the gate is a gate and a current mirror connection of the N-channel MOS transistor _{Q A3} through a resistor _{R B3.} An RF final stage amplification signal Pout is output from the drain of the N-channel MOS transistor Q _A3 via the output impedance matching circuit 94.

As shown in FIG. 10, at the first circuit node CN1 of the control signal enhancement circuit (EN) 9, the current I _{APC_LIN1} flowing through the P channel MOS transistor MP031 and the output current flowing through the P channel MOS transistor MP241 of the current squaring circuit CS1 I _{APC_SQ1} is added to generate the first output power control current I _APC1 . The first output power control current _{I APC 1} as a first bias current supplied to the drain-source current path of the source-grounded N-channel MOS transistor _{Q B1} is first bias transistor of the first bias circuit 81.

At the second circuit node CN2 of the control signal enhancement circuit (EN) 9, the current I _{APC_LIN2} flowing through the P channel MOS transistor MP032 and the output current I _{APC_SQ2} flowing through the P channel MOS transistor MP242 of the current squaring circuit CS1 are added. Two output power control current I _APC2 is generated. The second output power control current _{I APC 2} as the second bias current is supplied to the drain-source current path of the source-grounded N-channel MOS transistor _{Q B2} is a second bias transistor of the second bias circuit 82.

At the third circuit node CN3 of the control signal enhancement circuit (EN) 9, the current I _{APC_LIN3} flowing through the P channel MOS transistor MP033 and the output current I _{APC_SQ3} flowing through the P channel MOS transistor MP243 of the current squaring circuit CS1 are added. Three output power control current I _APC3 is generated. The third output power control current _{I APC3} a third bias current is supplied to the drain-source current path of the source-grounded N-channel MOS transistor _{Q B3} is a third bias transistor of the third bias circuit 83.

Further, the first, second and third output power control currents I _APC1 , I _APC2 and I _APC3 generated from the control signal enhancement circuit (EN) 9 are output power as _shown in the above equation (12) and FIG. It changes in response to the control voltage V _APC .

  As a result, in the RF power amplifier according to the first embodiment of the present invention shown in FIG. 10, the idling currents of the first stage amplifier circuit 41, the intermediate stage amplifier circuit 42, and the final stage amplifier circuit 43 of the multistage amplifier circuit 4 are the first bias. The bias currents of the circuit 81, the second bias circuit 82, and the third bias circuit 83 are determined.

As described above, according to the RF power amplifier according to the first embodiment of the present invention shown in FIG. 10, the first stage amplifier circuit 41 of the multistage amplifier circuit 4 for compensating for the decrease in the control gain (= ΔPout_EN / ΔV _APC ) and the intermediate Since the change rate of the idling current of each amplifier element in the stage amplifier circuit 42 and the final stage amplifier circuit 43 is determined in common by the control signal enhancement circuit (EN) 9, the increase in the semiconductor chip area and the manufacturing cost can be reduced. Is possible.

  FIG. 11 is a diagram showing in more detail the other configurations of the multistage amplifier circuit 4, the bias circuit 8, and the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. .

Although not shown in FIG. 11, in order to reduce the response delay, the initial current I _INT is between the source / drain current paths of the series-connected transistors MP21 and MP22 of the current square circuit CS1 and the ground voltage GND. Connected to.

  The RF power amplifier shown in FIG. 11 is different from the RF power amplifier shown in FIG. 10 in the configuration of the third bias circuit 83.

That is, two source grounded N-channel MOS transistors Q _B32 and Q _B33 and a second current squaring circuit CS2 are added to the third bias circuit 83 of the RF power amplifier shown in FIG. The transistor Q _B32 is current mirror connected to a source-grounded N-channel MOS transistor Q _B3 which is a third bias transistor, and the drain / source current path of the transistor Q _B32 is connected to the input terminal of the second current squaring circuit CS2. The output terminal of the second current squaring circuit CS2 drain-source current path of the transistor Q _B33 is connected, the drain and gate of the transistor Q _B33 via the resistor R _B3 at the final stage amplifying transistor of the final stage amplifier circuit 43 A current-mirror connection is made to the gate of a certain source-grounded N-channel MOS transistor _QA3 .

Therefore, since the square characteristic of the second current squaring circuit CS2 further converts the third output power control current I _APC3 to a square, the bias current of the transistor Q _B33 connected to the output terminal of the second current squaring circuit CS2 And the adding current of the final stage amplifier transistor Q _A3 of the final stage amplifier circuit 43 changes rapidly in response to the change of the output power control voltage V _APC . As a result, according to the multistage amplifier circuit 4 of the RF power amplifier according to the first embodiment of the present invention shown in FIG. 11, the control gain (=) in the final stage amplifier circuit 43 rather than the first stage amplifier circuit 41 and the intermediate stage amplifier circuit 42. It is possible to further enhance the compensation operation for the decrease in ΔPout_EN / ΔV _APC ).

  FIG. 12 is a diagram showing another specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG.

  The control signal enhancement circuit (EN) 9 shown in FIG. 12 is different from the control signal enhancement circuit (EN) 9 shown in FIG. 7 in that there are two N-channel MOS transistors MN21 and MN22 and two P-channel MOS transistors. MP31 and MP32 are added.

  That is, the drain / source current path of the N-channel MOS transistor MN21 of the input transistor of the first current mirror is connected to the circuit node CN of the control signal enhancement circuit (EN) 9, and the output transistor of the first current mirror is connected to the gate of the transistor MN21. The gates of the N-channel MOS transistors MN22 are connected. Further, the source / drain current path of the input transistor MP31 of the second current mirror is connected to the drain / source current path of the N-channel MOS transistor MN22 of the output transistor of the first current mirror, and the gate of the second current mirror is connected to the gate of the transistor MP31. The gate of the output MOS transistor MP32 is connected.

Therefore, the output power control current NM · I _APC adjusted by the transistor size ratio N of the N-channel MOS transistors MN21 and MN22 of the first current mirror and the transistor size ratio M of the P-channel MOS transistors MP31 and MP32 of the second current mirror. Is generated from the control signal enhancement circuit (EN) 9 shown in FIG.

  FIG. 13 is a diagram showing another specific example of the control signal enhancement circuit (EN) 9 of the RF power amplifier according to the first embodiment of the present invention shown in FIG.

  The control signal enhancement circuit (EN) 9 shown in FIG. 13 is different from the control signal enhancement circuit (EN) 9 shown in FIG. 7 in that the current squaring circuit CS1 in FIG. 7 is changed to the current squaring circuit CB in FIG. It is replaced.

  That is, in the current cube circuit CB as a translinear shown in FIG. 13, three P-channel MOS transistors MP21, MP22, MP23 are connected in series on the input side, while three P-channel MOS transistors MP24, MP25 are connected. , MP26 are cascade-connected on the output side.

Therefore, at the circuit node CN of the control signal enhancement circuit (EN) 9 shown in FIG. 13, the current I _{APC_LIN} having the first power characteristic of the output power control voltage V _APC that flows through the P-channel MOS transistor MP03 and the current flows through the P-channel MOS transistor MP26. The output power control voltage V _APC is added to the cube of the output current I _{APC_CB} to generate the output power control current I _APC .

[Embodiment 2]
<< Other configuration of control signal enhancement circuit >>
FIG. 14 is a diagram showing another configuration of the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention.

  The control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. 14 is different from the control signal enhancement circuit (EN) 9 according to the first embodiment of the present invention described above in the following points. is there.

That is, in the control signal enhancement circuit (EN) 9 according to the first embodiment of the present invention described above, a current squaring circuit configured as a translinear in order to perform a compensation operation for a decrease in control gain (= ΔPout_EN / ΔV _APC ). CS1 or current cube circuit CB was included.

On the other hand, the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. 14 includes a polygonal line circuit for performing a compensation operation for a decrease in control gain (= ΔPout_EN / ΔV _APC ). It is a waste.

As shown in FIG. 14, the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention includes resistors R _11A , R _11B , R _11C , R _11D , R ₁₂ , R ₁₃ , R _14A , R _14B , R _14C , operational amplifiers OP2, OP3, OP4, and diodes D1, D2, D3, D4.

The negative first reference voltage −Vref1 is supplied to one end of the resistor R _11A, the output power control voltage V _APC is supplied from the error amplifier 7 to the common node of the resistors R _11B and R _11C , and the negative voltage is supplied to one end of the resistor R _11D. A second reference voltage -Vref2 is supplied. The common node of the resistors R _11A and R _11B is connected to the inverting input terminal of the operational amplifier OP2, the common node of the resistors R _11C and R _11D is connected to the inverting input terminal of the operational amplifier OP3, and the non-inverting input terminal of the operational amplifier OP2 And the non-inverting input terminal of the operational amplifier OP3 are connected to the ground voltage GND.

Cathode and one end of the resistor R ₁₂ of the diode D1 is connected to the inverting input terminal of the operational amplifier OP2, the anode of the diode D1 is connected to the cathode of the output terminal and the diode D2 of the operational amplifier OP2, the other end of the resistor R ₁₂ is diode The first voltage V1 is generated by being connected to the anode of D2.

Cathode and one end of the resistor R ₁₃ of diode D3 is connected to the inverting input terminal of the operational amplifier OP3, the anode of the diode D3 is connected to the cathode of the output terminal and the diode D4 of the operational amplifier OP3, the other end of the resistor R ₁₃ is diode The second voltage V2 is generated by being connected to the anode of D4.

The first voltage V1 is supplied to one end of resistor _{R 14A,} the second voltage V2 is supplied to one end of the resistor _{R 14B,} the other ends of the resistor _{R 14B} of the resistor _{R 14A} to the inverting input terminal of the operational amplifier OP4 The non-inverting input terminal of the operational amplifier OP4 is connected to the ground voltage GND. The resistor R _14C is connected between the inverting input terminal and the output terminal of the operational amplifier OP4, the third voltage V3 is generated from the output terminal of the operational amplifier OP4, and the third voltage V3 is supplied to the inverting input terminal of the operational amplifier OP1. The

The third voltage V3 by the operational amplifier OP1 and the resistor _{R 2} and P-channel MOS transistor MP01, is converted into conversion current _{I APC0.} Therefore, the output power control current I _APC adjusted by the transistor size ratio of the P-channel MOS transistors MP01 and MP02 is generated from the control signal enhancement circuit (EN) 9 shown in FIG.

Although not shown in FIG. 14, three operational amplifiers OP2, OP3, by a positive power supply voltage _{V DD} and the negative supply voltage _{V EE} is supplied to OP4, three operational amplifiers OP2, OP3 , OP4 can process an input signal that changes from a positive voltage to a negative voltage.

Assuming that the resistance values of the resistors R _11A and R _11B are both R ₁₁ , the current I ₁ flowing through the resistor R _11A and the current I ₂ flowing through the resistor R _11B are expressed by the following formula (18) and the following formula: And (19).

When the relationship of V _APC <Vref1 is established between the output power control voltage V _APC and the positive first reference voltage Vref1, the current I ₃ calculated by the following equation (20) is obtained from the operational amplifier OP2. The current flows from the output terminal to the inverting input terminal via the diode D1.

In this case, since no current flows through the resistor R _12, a first voltage V1 and the anode of the other end and the diode D2 of the resistor R ₁₂ is a zero volt of the ground voltage GND of the inverting input terminal of the operational amplifier OP2 .

When the relationship of V _APC > Vref1 is established between the output power control voltage V _APC and the positive first reference voltage Vref1, the current I ₁ flowing through the resistor R _11A and the current I ₂ flowing through the resistor R _11B are since equal currents I ₄ to the current of the sum of flows to the resistor R _12, each de the following equation (21) and (22) below is calculated from the current I ₄ and the first voltage V1.

  FIG. 15 is a diagram for explaining the operation of the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG.

As shown in FIG. 15, when the relationship of V _APC <Vref1 is satisfied, the first voltage V1 is zero volts, and when the relationship of V _APC > Vref1 is satisfied, the first voltage V1 is the output power control voltage V _APC. Decreases in proportion to the increase in.

Assuming that the resistance values of the resistor R _11C and the resistor R _11D are both R ₁₁ , the current I ₅ flowing through the resistor R _11D and the current I ₆ flowing through the resistor R _11C are expressed by the following equation (23) and the following equation: And (24).

When the relationship of V _APC <Vref2 is established between the output power control voltage V _APC and the positive second reference voltage Vref2, the current I ₇ calculated by the following equation (25) is obtained from the operational amplifier OP3. The current flows from the output terminal to the inverting input terminal via the diode D3.

In this case, since no current flows in the resistor R _13, the second voltage V2 of the anode of the other end and the diode D4 of the resistor R _13, a zero volt of the ground voltage GND of the inverting input terminal of the operational amplifier OP3 .

When the relationship of V _APC > Vref2 is established between the output power control voltage V _APC and the positive second reference voltage Vref2, the current I ₅ flowing through the resistor R _11D and the current I ₆ flowing through the resistor R _11C Since the current I ₈ equal to the sum current flows into the resistor R ₁₃ , the current I ₈ and the second voltage V 2 are calculated by the following formula (26) and the following formula (27), respectively.

As shown in FIG. 15, when the relationship of V _APC <Vref2 is satisfied, the second voltage V2 is zero volts, and when the relationship of V _APC > Vref2 is satisfied, the second voltage V2 is the output power control voltage V _APC. Decreases in proportion to the increase in.

In the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. 14, the resistors R _14A , R _14B and R _14C and the operational amplifier OP4 constitute an inverting adder, so that the resistor R _14A Assuming that both R _14B and R _14C have the same resistance value, a third voltage V3 having a relationship of V3 = − (V1 + V2) is generated at the output terminal of the operational amplifier OP4 of the inverting adder.

FIG. 15 also shows changes in the third voltage V3 at the output terminal of the operational amplifier OP4 of the inverting adder in response to changes in the output power control voltage V _APC .

The third voltage V3 is converted into an output power control current I _APC by the operational amplifier OP1, the resistor R2, and the P-channel MOS transistors MP01 and MP02.

FIG. 16 is a diagram for explaining the characteristics of the output power control current I _APC generated from the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG.

As shown in FIG. 16, when the relationship of V _APC > Vref1 is established, the output power control current I _APC increases in response to the increase of the output power control voltage V _APC at the first rate of change, and V _APC > Vref2 When the relationship is established, the output power control current I _APC increases in response to the increase in the output power control voltage V _{APC at} a second rate of change that is greater than the first rate of change.

  Actually, the first bias current, the second bias current, and the third bias current similar to the change characteristics shown in FIG. And the third bias transistor of the third bias circuit. The first bias transistor is current-mirror connected to the first-stage amplifier transistor of the first-stage amplifier circuit 41, the second bias transistor is current-mirror connected to the intermediate-stage amplifier transistor of the intermediate-stage amplifier circuit 42, and the third bias transistor is the last-stage amplifier. The final stage amplification transistor of the circuit 43 is current mirror connected.

As described above, the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. 14 performs the first stage of the multistage amplifier circuit 4 in order to compensate for the decrease in the control gain (= ΔPout_EN / ΔV _APC ). Since the change rate of the idling current of each amplifier element in the amplifier circuit 41, the intermediate amplifier circuit 42, and the final amplifier circuit 43 is determined in common, it is possible to reduce the increase in the semiconductor chip area and the manufacturing cost.

[Embodiment 3]
<< Other configuration of control signal enhancement circuit >>
FIG. 17 is a diagram showing another configuration of the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention.

  The control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention shown in FIG. 17 is different from the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. This is the point.

That is, the control signal enhancement circuit (EN) 9 according to the second embodiment of the present invention shown in FIG. 14 described above includes a broken line circuit for performing a compensation operation for a decrease in control gain (= ΔPout_EN / ΔV _APC ). It was out.

On the other hand, the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention shown in FIG. 17 performs a look-up table (EN) to perform a compensation operation for a decrease in control gain (= ΔPout_EN / ΔV _APC ). LUT) 11.

As shown in FIG. 17, the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention includes an analog / digital converter (ADC) 10, a look-up table (LUT) 11, and a digital / analog converter ( a DAC) 12, a low pass filter (LPF) 13, a clock pulse generator and (CPG) 13, an operational amplifier OP1, a resistor _{R 2,} is constituted by a P-channel MOS transistors MP01, MP02.

  The analog-to-digital converter (ADC) 10 and the digital-to-analog converter (DAC) 12 operate in response to clock pulses generated from a clock pulse generator (CPG) 13.

The analog-to-digital converter (ADC) 10 converts the analog output power control voltage V _APC supplied from the error amplifier 7 into a first digital signal in response to the clock pulse. The look-up table (LUT) 11 has an appropriate input / output nonlinear characteristic, and converts the first digital signal into the second digital signal according to the input / output nonlinear characteristic (compensation operation for lowering the control gain). The digital / analog converter (DAC) 12 is supplied.

The digital-to-analog converter (DAC) 12 converts the second digital signal supplied from the look-up table (LUT) 11 into an analog output signal in response to the clock pulse. The low pass filter (LPF) 13 reduces clock noise and the like contained in the analog output signal of the digital / analog converter (DAC) 12. The analog output signals of such low-pass filter (LPF) digital-to-analog converter noise or the like is reduced by 13 (DAC) 12, due the operational amplifier OP1 resistor _{R 2} and P-channel MOS transistors MP01, MP02, the output power It is converted into a control current I _APC .

FIG. 18 is a diagram for explaining the characteristics of the output power control current I _APC generated from the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention shown in FIG.

As shown in FIG. 18, according to the appropriate input / output nonlinear characteristics of the look-up table (LUT) 11, the output power control current I _APC initially responds to an increase in the output power control voltage V _{APC at} a first rate of change. The output power control current I _APC then increases in response to the increase in the output power control voltage V _{APC at} a second rate of change that is greater than the first rate of change.

  Actually, the first bias current, the second bias current, and the third bias current similar to the change characteristics shown in FIG. 18 are the first bias transistor of the first bias circuit and the second bias transistor of the second bias circuit. And the third bias transistor of the third bias circuit. The first bias transistor is current-mirror connected to the first-stage amplifier transistor of the first-stage amplifier circuit 41, the second bias transistor is current-mirror connected to the intermediate-stage amplifier transistor of the intermediate-stage amplifier circuit 42, and the third bias transistor is the last-stage amplifier. The final stage amplification transistor of the circuit 43 is current mirror connected.

As described above, the control signal enhancement circuit (EN) 9 according to the third embodiment of the present invention shown in FIG. 17 performs the first stage of the multistage amplifier circuit 4 in order to compensate for the decrease in the control gain (= ΔPout_EN / ΔV _APC ). Since the change rate of the idling current of each amplifier element in the amplifier circuit 41, the intermediate amplifier circuit 42, and the final amplifier circuit 43 is determined in common, it is possible to reduce the increase in the semiconductor chip area and the manufacturing cost.

[Embodiment 4]
<< Specific configuration of RF power amplifier >>
FIG. 19 is a diagram showing a specific configuration of the RF power amplifier according to the fourth embodiment of the present invention.

  The RF power amplifier according to the fourth embodiment of the present invention shown in FIG. 19 is configured as a multiband high frequency power module (RF power module) mounted on a mobile phone terminal capable of GSM communication.

  That is, the multiband RF power module shown in FIG. 19 is capable of outputting RF transmission signals having a plurality of transmission frequencies of a high band (high frequency band) and a low band (low frequency band).

  Accordingly, the multiband RF power module according to the fourth embodiment of the present invention shown in FIG. 19 includes a highband RF signal input terminal 1H, a highband RF signal output terminal 2H, a highband multistage amplifier circuit 4H, and a highband power coupler. 5H, a high-band RF power amplifier including a high-band power detector 6H, a high-band bias circuit 8H, and a high-band low-pass filter 16H. Further, this multi-band RF power module includes a low-band RF signal input terminal 1L, a low-band RF signal output terminal 2L, a low-band multistage amplifier circuit 4L, a low-band power combiner 5L, a low-band power detector 6L, a low-band bias circuit 8L, and a low-band low-pass filter. A low-band RF power amplifier composed of 16L is included.

  Furthermore, the multiband RF power module according to the fourth embodiment of the present invention shown in FIG. 19 includes a ramp control terminal 3, an error amplifier 7, a control signal shared by the high-band RF power amplifier and the low-band RF power amplifier described above. An enhancement circuit (EN) 9, a control circuit 15, an antenna switch 17, and an antenna filter 18 are included. The antenna switch 17 can be connected to an antenna ANT mounted on a mobile phone terminal via an antenna filter 18. Although not shown, impedance matching circuits are respectively provided between the high-band multistage amplifier circuit 4H and the highband power coupler 5H and between the lowband multistage amplifier circuit 4L and the lowband power coupler 5L. Also good.

In particular, in the multiband RF power module according to the fourth embodiment of the present invention shown in FIG. 19, an error amplifier 7 and a control signal enhancement circuit (EN) 9 shared by the high band RF power amplifier and the low band RF power amplifier are provided. In addition, the non-linear characteristic of the enhancement control signal V _EN of the control signal enhancement circuit (EN) 9 according to any one of the above-described first to third embodiments of the present invention is used. As a result, according to the multiband RF power module according to the fourth embodiment of the present invention shown in FIG. 19, the control signal enhancement circuit (EN) 9 having a suitable non-linear characteristic has a control gain (= ΔPout_EN / ΔV _APC ). It is possible to compensate for the decrease in the.

  The high band RF signal input terminal 1H of the high band RF power amplifier has a high band of GSM DCS1800 and PCS1900 generated by a transmission signal processing unit of an RF signal processing semiconductor integrated circuit (RFIC) mounted on a mobile phone terminal. An RF transmission input signal Pin_HB is supplied. DCS is an abbreviation for Digital Cellar System, and PCS is an abbreviation for Personal Communication System. The transmission frequency of DCS 1800 is 1710 MHz to 1785 MHz, and the transmission frequency of PCS 1900 is 1850 MHz to 1910 MHz.

  The high-band RF transmission input signal Pin_HB is sequentially amplified by the first-stage amplifier circuit 41H, the intermediate-stage amplifier circuit 42H, and the final-stage amplifier circuit 43H of the high-band multistage amplifier circuit 4H, and the amplified output signal of the final-stage amplifier circuit 43H is high-band power. A high band RF output signal Pout_HB is output from the high band RF signal output terminal 2H via the main line of the coupler 5H and the high band low pass filter 16H.

A part of the high-band RF output signal Pout_HB is transmitted to the sub-line of the high-band power coupler 5H that is electromagnetically and capacitively coupled to the main line of the high-band power coupler 5H. As a result, the high band power detector 6H whose input terminal is connected to the sub-line of the high band power coupler 5H generates a high band power detection voltage V _{DET_HB} that is proportional to the signal level of the high band RF output signal Pout_HB. This is supplied to the first input terminal of the error amplifier 7.

The ramp voltage V _RAMP supplied to the third input terminal of the error amplifier 7 via the ramp control terminal 3 for ramp-up and ramp-down is a lamp D / B built in the RF signal processing semiconductor integrated circuit (RFIC). It is generated from the analog output terminal of the A converter. Digital ramp data for ramp-up and ramp-down is generated inside the baseband signal processing LSI, and the digital ramp data is built into the RF signal processing semiconductor integrated circuit (RFIC) via the digital interface from the baseband signal processing LSI. Are supplied to the digital input terminal of the lamp D / A converter.

The error amplifier (EA) 7 detects a difference between the high-band power detection voltage V _{DET_HB} at the first input terminal and the ramp voltage V _RAMP at the third input terminal, and outputs an output power control voltage V _APC proportional to the difference. It is generated and supplied to the input terminal of the control signal enhancement circuit (EN) 9.

The control signal enhancement circuit (EN) 9 generates the enhancement control signal V _EN in response to the output power control voltage V _APC generated from the error amplifier (EA) 7 to generate the first bias circuit 81H of the high band bias circuit 8H. And supplied to the second bias circuit 82H and the third bias circuit 83H.

  The low-band RF signal input terminal 1L of the low-band RF power amplifier has a low-band RF transmission between GSM GSM850 and GSM900 generated by a transmission signal processing unit of an RF signal processing semiconductor integrated circuit (RFIC) mounted on a mobile phone terminal. An input signal Pin_LB is supplied. The transmission frequency of GSM850 is 824 MHz to 849 MHz, and the transmission frequency of GSM900 is 880 MHz to 915 MHz.

  The low-band RF transmission input signal Pin_LB is sequentially amplified by the first-stage amplifier circuit 41L, the intermediate-stage amplifier circuit 42L, and the final-stage amplifier circuit 43L of the low-band multistage amplifier circuit 4L, and the amplified output signal of the final-stage amplifier circuit 43L is the low-band power coupler 5L. Are output as a low-band RF output signal Pout_LB from the low-band RF signal output terminal 2L through the main line and the low-band low-pass filter 16L.

A part of the low-band RF output signal Pout_LB is transmitted to the sub-line of the low-band power coupler 5L that is electromagnetically and capacitively coupled to the main line of the low-band power coupler 5L. As a result, the low-band power detector 6L whose input terminal is connected to the sub-line of the low-band power coupler 5L generates a low-band power detection voltage V _{DET_LB} that is proportional to the signal level of the low-band RF output signal Pout_LB. Supply to the second input terminal.

The ramp voltage V _RAMP supplied to the third input terminal of the error amplifier 7 via the ramp control terminal 3 for ramp-up and ramp-down is a lamp D / B built in the RF signal processing semiconductor integrated circuit (RFIC). It is generated from the analog output terminal of the A converter. Digital ramp data for ramp-up and ramp-down is generated inside the baseband signal processing LSI, and the digital ramp data is built into the RF signal processing semiconductor integrated circuit (RFIC) via the digital interface from the baseband signal processing LSI. Are supplied to the digital input terminal of the lamp D / A converter.

The error amplifier (EA) 7 detects the difference between the low-band power detection voltage V _{DET_LB} at the second input terminal and the ramp voltage V _RAMP at the third input terminal, and generates an output power control voltage V _APC proportional to the difference. And supplied to the input terminal of the control signal enhancement circuit (EN) 9.

The control signal enhancement circuit (EN) 9 generates an enhancement control signal V _EN in response to the output power control voltage V _APC generated from the error amplifier (EA) 7 and the first bias circuit 81L of the low-band bias circuit 8L. This is supplied to the second bias circuit 82L and the third bias circuit 83L.

  Further, the control circuit 15 shared by the high-band RF power amplifier and the low-band RF power amplifier responds to the reception / transmission switch signal Rx / Tx_SW and the high-band / low-band switch signal HB / LB_SW. As a result, the shared control circuit 15 operates with the operation switches of the high-band multistage amplifier circuit 4H and the low-band multistage amplifier circuit 4L, and the operations of the high-band power detector 6H, the low-band power detector 6L, and the error amplifier (EA) 7. It is also possible to adjust the characteristics of the error amplifier (EA) 7 and the control signal enhancement circuit (EN) 9 in the high band and the low band while executing the switch.

[Embodiment 5]
<Configuration of transmission system>
FIG. 20 is a diagram showing a configuration of a transmission system using the RF power amplifier according to the fifth embodiment of the present invention.

  The transmission system according to the fifth embodiment of the present invention shown in FIG. 20 is different from the above-described first to third embodiments of the present invention in that an error amplifier (EA) 7 and a control signal enhancement circuit are provided. (EN) 9 is configured as an RF power module HPA and not disposed in the RF power amplifier, but disposed in the RF signal processing semiconductor integrated circuit (RFIC).

  The transmission system according to the fifth embodiment of the present invention shown in FIG. 20 enables a WCDMA, EDGE, LTE, and HSUPA communication system.

  Note that the WCDMA system employs a frequency division duplex (FDD) radio interface for code division multiple access (CDMA) using a wide frequency band of 1.25 MHz or 5 MHz. The EDGE method is an abbreviation for Enhanced Data Rates for GSM Evolution, and is a packet communication standard that extends GPRS (General Packet Radio Service). Furthermore, the LTE scheme is an abbreviation for Long Term Evolution, and the HSUPA scheme is an abbreviation for High-Speed Uplink Packet Access, also called EUL (Enhanced Uplink).

  The transmission system according to the fifth embodiment of the present invention shown in FIG. 20 supports the RF input signal Pin supplied to the RF signal input terminal 1 of the multistage amplifier circuit 4 of the RF power amplifier in order to support these communication methods. A variable gain amplifier (VGA) 19 for controlling the signal amplitude is provided inside the RF signal processing semiconductor integrated circuit (RFIC). Accordingly, the RF signal processing semiconductor integrated circuit (RFIC) of the transmission system of FIG. 20 includes an error amplifier (EA) 7, a control signal enhancement circuit (EN) 9, and a variable gain amplifier (VGA) 19. An RF transmission input signal RFin generated by a transmission signal processing unit of an RF signal processing semiconductor integrated circuit (RFIC) is supplied to an input terminal of the variable gain amplifier (VGA) 19.

Therefore, in the transmission system of FIG. 20, the control signal enhancement circuit (EN) 9 generates the enhancement control signal V _EN generated in response to the output power control voltage V _APC generated from the error amplifier 7 according to the above-described implementation of the present invention. Instead of being supplied to the first bias circuit 81, the second bias circuit 82, and the third bias circuit 83 of the bias circuit 8 as in the first to third embodiments of the present invention, the variable gain amplifier (VGA) 19 is supplied. By supplying, the variable gain of the variable gain amplifier (VGA) 19 is controlled. As a result, the first bias voltage V _GB1 supplied from the first bias circuit 81 to the first stage amplifier circuit 41 of the multistage amplifier circuit 4 of the RF power amplifier and the second bias circuit 82 supplied from the second bias circuit 82 to the intermediate stage amplifier circuit 42. The bias voltage V _GB2 and the third bias voltage V _GB3 supplied from the third bias circuit 83 to the final stage amplifier circuit 43 are fixed bias voltages, respectively. Therefore, the multistage amplifier circuit 4 of the RF power amplifier including the first stage amplifier circuit 41, the intermediate stage amplifier circuit 42, and the final stage amplifier circuit 43 operates as a linear amplifier with a fixed gain.

<Configuration of variable gain amplifier>
FIG. 21 is a diagram showing a configuration of a variable gain amplifier (VGA) 19 of the RF signal processing semiconductor integrated circuit (RFIC) of the transmission system according to the fifth embodiment of the present invention shown in FIG.

  The core of the variable gain amplifier (VGA) 19 shown in FIG. 21 is configured by a gain cell GC including six N-channel MOS transistors MN1931 to MN1936.

The sources of the transistor MN1932 transistor MN1931 is differentially connected via a resistor _{R 1925, R 1926,} a common connection node of the resistors _{R 1925, R 1926} is connected through a resistor _{R 1924} to the ground voltage GND. The bias voltage V _BIAS is supplied to the gate of the transistor MN1931 and the gate of the transistor MN1932, and the RF transmission input signal RFin is supplied to the gate of the transistor MN1931 through the capacitor Cin.

The source of the transistor MN1933 and the source of the transistor MN1934 are differentially connected to the drain of the transistor MN1931, and the source of the transistor MN1935 and the source of the transistor MN1936 are differentially connected to the drain of the transistor MN1932. Gate voltage _{V G} to the gate of the gate and the transistor MN1935 transistor MN1934 is supplied, the gain control voltage _{V CNTL} is supplied to the gates of the transistor MN1936 transistor MN1933. Drains of transistor MN1935 transistor MN1934 is connected directly to the power supply voltage _{V DD,} the drain of the transistor MN1933 is connected to the power supply voltage _{V DD} via a resistor _{R 1928,} the drain of the transistor MN1936 is through a resistor _{R 1929} Power Connected to voltage V _DD . A differential output signal of the gain cell GC of the resistors R ₁₉₂₈ and R ₁₉₂₉ is output as an RF input signal Pin via a differential amplifier DA configured by P-channel MOS transistors MP1930 and MP1931 and resistors R ₁₉₃₀ and R ₁₉₃₁ . .

The gain control voltage V _CNTL is generated from the control circuit CC to which the enhancement control signal V _EN generated from the control signal enhancement circuit (EN) 9 is supplied. The enhancement control signal V _EN is supplied to the gate of the source follower-connected (drain grounded) P-channel MOS transistor MP1900 via resistors R ₁₉₂₁ and R ₁₉₂₂ , and the source of the MOS transistor MP1900 is supplied to the power supply voltage V _DD via the resistor R _1923. And gain control voltage V _CNTL is generated.

When the enhancement control signal V _EN is at a low voltage level, in the control circuit CC, the gain control voltage V _{CNTL at} the source of the transistor MP1900 is at a low voltage level, and the differential output signal of the gain cell GC of the resistors R ₁₉₂₈ and R ₁₉₂₉ The signal amplitude is minimum.

On the other hand, when the enhancement control signal V _EN is at a high voltage level, in the control circuit CC, the gain control voltage V _{CNTL at} the source of the transistor MP1900 is at a high voltage level, and the gain cells GC of the resistors R ₁₉₂₈ and R ₁₉₂₉ The signal amplitude of the differential output signal becomes maximum.

On the other hand, in the transmission system of FIG. 20, the output power control voltage V _APC generated from the error amplifier 7 is directly supplied to the gain control terminal of the variable gain amplifier (VGA) 19 without passing through the control signal enhancement circuit (EN) 9. Assuming that In this case, in the variable gain amplifier (VGA) 19 shown in FIG. 21, the input terminal of the control circuit CC is not the enhancement control signal V _EN generated from the control signal enhancement circuit (EN) 9 but the error amplifier 7. Is supplied with an output power control voltage V _APC generated from When the output power control voltage V _APC becomes a high voltage level, the gain control voltage V _CNTL of the source of the transistor MP1900 becomes a high voltage level in the control circuit CC, and the differential output signal of the gain cell GC of the resistors R ₁₉₂₈ and R ₁₉₂₉ The signal amplitude is maximized. As a result, the RF input signal Pin as the output signal of the variable gain amplifier (VGA) 19 is in a maximum output (saturated) state.

Therefore, when the output power control voltage V _APC is directly supplied to the gain control terminal of the variable gain amplifier (VGA) 19, when the variable gain amplifier (VGA) 19 approaches the maximum output (saturated) state, the control gain ( = ΔPin / ΔV _APC ) is lowered.

In order to compensate for the decrease in the control gain (= ΔPin / ΔV _APC ), a control signal enhancement circuit (EN) 9 that generates an enhancement control signal V _EN having nonlinear characteristics with respect to a change in the output power control voltage V _APC. Are connected between the output terminal of the error amplifier 7 and the gain control terminal of the variable gain amplifier (VGA) 19 in the transmission system of FIG. Accordingly, as shown in FIG. 21, the control signal CC of the variable gain amplifier (VGA) 19 is supplied with the boost control signal V _EN generated from the control signal boost circuit (EN) 9. is there. As a result, the decrease in the control gain (= ΔPin / ΔV _APC ) of the variable gain amplifier (VGA) 19 in the vicinity of the maximum output (saturation) state is an enhancement control signal generated from the control signal enhancement circuit (EN) 9. it is intended to be compensated by a suitable non-linear characteristics of the V _EN. In the transmission system of FIG. 20, the control signal enhancement circuit (EN) 9 includes a control signal enhancement circuit (EN) 9 according to any one of the above-described first to third embodiments of the present invention. And the non-linear characteristics of the enhancement control signal V _EN can be used.

  Although not described at the beginning, the first stage amplification MOS transistor of the first stage amplification circuit 41 of the multistage amplification circuit 4 of the RF power amplifier, the intermediate stage amplification MOS transistor of the intermediate stage amplification circuit 42, and the final stage amplification of the final stage amplification circuit 43. As the MOS transistor, a MOS transistor suitable for high-frequency amplification and high-power amplification called an LD type is used. Note that LD is an abbreviation for Laterally Diffused.

  As mentioned above, the invention made by the present inventor has been specifically described based on various embodiments. However, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the RF power module according to Embodiment 4 of the present invention shown in FIG. 19, the high-band power coupler 5H and the low-band power coupler 5L use directional couplers. . As another power detection method, a current sense type power detection method may be employed. In the current sense type power detection method, a detection transistor having a small element size is connected in parallel with the output transistor of the power amplifier, and a small detection AC / DC operation current proportional to the AC / DC operation current of the output transistor is used as the detection transistor. The power is detected by flowing it.

  Further, the first-stage amplifier 41 of the first-stage amplifier 41 of the multi-stage amplifier circuit 4 of the RF power amplifier, the intermediate-stage amplifier of the intermediate-stage amplifier 42 and the final-stage amplifier of the final-stage amplifier 43 include LD type N-channel MOS transistors. In addition, it is also possible to use a heterojunction bipolar transistor (HBT), a MESFET using a compound semiconductor such as GaAs or InP, or a HEMT N-channel field effect transistor.

DESCRIPTION OF SYMBOLS 1 ... RF signal input terminal 2 ... RF signal output terminal 3 ... Lamp control terminal 4 ... Multistage amplifier circuit 41 ... First stage amplifier circuit 42 ... Intermediate stage amplifier circuit 43 ... Final stage amplifier circuit 5 ... Power combiner 6 ... Power detector 7 ... Error amplifier 8 ... Bias circuit 81 ... First bias circuit 82 ... Second bias circuit 83 ... Third bias circuit 9 ... Control signal enhancement circuit Pin ... RF input signal Pout ... RF output signal V _RAMP ... Lamp voltage P _{IN_DET} ... Power Input power of detector 6 V _DET ... Power detection voltage V _APC ... Output power control voltage V _EN ... Boost control signal

Claims (20)

A multi-stage amplifier circuit having at least a first stage amplifier circuit and a final stage amplifier circuit, a power detection circuit, an error amplifier, a bias circuit having at least a first stage bias circuit and a final stage bias circuit, and a control signal enhancement circuit,
The first stage bias voltage of the first stage bias circuit is supplied to the first stage amplifier circuit, the first stage idling current of the first stage amplifier circuit is determined,
The final stage bias voltage of the final stage bias circuit is supplied to the final stage amplifier circuit, the final stage idling current of the final stage amplifier circuit is determined,
The first stage amplifier circuit can amplify an RF input signal supplied to an input terminal, and the last stage amplifier circuit can generate a final stage amplified output signal in response to the first stage amplified output signal of the first stage amplifier circuit,
The power detection circuit is capable of generating a power detection signal responsive to a signal level of the final stage amplified output signal of the final stage amplifier circuit of the multistage amplifier circuit;
When the power detection signal is supplied to one input terminal of the error amplifier and the target power signal is supplied to the other input terminal of the error amplifier, a power control voltage can be generated from the output terminal of the error amplifier. And
By supplying the power control voltage to the input terminal of the control signal enhancement circuit, an enhancement control signal can be generated from the output terminal of the control signal enhancement circuit,
The control signal enhancement circuit has a predetermined non-linear input / output characteristic, and is based on an increase rate of the enhancement control signal in response to an increase in the power control voltage before the power control voltage reaches a predetermined voltage. Also, the increase rate of the enhancement control signal in response to the increase in the power control voltage after the power control voltage reaches the predetermined voltage is set large,
The RF power amplifier, wherein the boost control signal is supplied to the first stage bias circuit and the last stage bias circuit, and the first stage idling current and the last stage idling current are controlled by the boost control signal. In claim 1,
The multistage amplifier circuit further includes an intermediate stage amplifier circuit connected between the first stage amplifier circuit and the final stage amplifier circuit,
The bias circuit further includes an intermediate stage bias circuit connected to the intermediate stage amplifier circuit,
An intermediate stage bias voltage of the intermediate stage bias circuit is supplied to the intermediate stage amplifier circuit, an intermediate stage idling current of the intermediate stage amplifier circuit is determined,
The RF power amplifier, wherein the boost control signal is supplied to the intermediate stage bias circuit, and the intermediate stage idling current is controlled by the boost control signal. In claim 1,
The first stage bias circuit includes a first stage bias transistor connected in a current mirror with a first stage amplification transistor of the first stage amplifier circuit,
The final stage bias circuit includes a final stage bias transistor connected in a current mirror with a final stage amplification transistor of the final stage amplification circuit,
The first stage bias current and the last stage bias current as the enhancement control signal are respectively supplied to the first stage bias transistor and the last stage bias transistor, and the first stage idling current and the last stage idling current are the first stage bias current and the last stage bias current, respectively. An RF power amplifier characterized by being determined by a final stage bias current. In claim 2,
The intermediate stage bias circuit includes an intermediate stage bias transistor connected in current mirror with the intermediate stage amplifier transistor of the intermediate stage amplifier circuit,
An RF power amplifier, wherein an intermediate stage bias current as the enhancement control signal is supplied to the intermediate stage bias transistor, and the intermediate stage idling current is determined by the intermediate stage bias current. In claim 3,
The control signal enhancement circuit includes a voltage / current conversion circuit and a current square circuit,
The voltage-current conversion circuit is capable of generating a conversion current that is substantially proportional to the change in response to a change in the power control voltage,
The current squaring circuit is capable of generating a squared output current substantially proportional to the square of the power control voltage;
The RF power amplifier, wherein the control signal enhancement circuit can generate an output power control current obtained by adding the conversion current and the square output current as the enhancement control signal. In claim 3,
The control signal enhancement circuit includes a voltage / current conversion circuit and a current cube circuit.
The voltage-current conversion circuit is capable of generating a conversion current that is substantially proportional to the change in response to a change in the power control voltage,
The current cube circuit is capable of generating a cubed output current substantially proportional to the cube of the power control voltage;
The RF power amplifier, wherein the control signal enhancement circuit can generate an output power control current obtained by adding the conversion current and the cubed output current as the enhancement control signal. In claim 3,
The RF power amplifier according to claim 1, wherein the control signal enhancement circuit includes a plurality of operational amplifiers so that an output power control current having a non-linear characteristic with respect to a plurality of reference voltages can be generated as the enhancement control signal. In claim 3,
The control signal enhancement circuit includes an analog-to-digital converter, a look-up table, and a digital-to-analog converter.
The analog-to-digital converter can convert the power control voltage supplied from the error amplifier into a first digital signal;
The look-up table has the predetermined nonlinear input / output characteristic, and can convert the first digital signal into a second digital signal according to the predetermined nonlinear input / output characteristic.
The RF power amplifier, wherein the digital / analog converter is capable of generating an output power control current obtained by analog conversion of the second digital signal as the enhancement control signal. In claim 3,
An RF power amplifier characterized in that the target power signal supplied to the other input terminal of the error amplifier can control ramp-up and ramp-down in a transmission operation time slot of a time division multiple access method. . In claim 3,
Each of the first stage amplification transistor, the last stage amplification transistor, the first stage bias transistor, and the last stage bias transistor is a MOS transistor or a bipolar transistor. RF power comprising a multistage amplifier circuit having at least a first stage amplifier circuit and a final stage amplifier circuit, a power detection circuit, an error amplifier, a bias circuit having at least a first stage bias circuit and a final stage bias circuit, and a control signal enhancement circuit A method of operating an amplifier, comprising:
The first stage bias voltage of the first stage bias circuit is supplied to the first stage amplifier circuit, the first stage idling current of the first stage amplifier circuit is determined,
The final stage bias voltage of the final stage bias circuit is supplied to the final stage amplifier circuit, the final stage idling current of the final stage amplifier circuit is determined,
The first stage amplifier circuit can amplify an RF input signal supplied to an input terminal, and the last stage amplifier circuit can generate a final stage amplified output signal in response to the first stage amplified output signal of the first stage amplifier circuit,
The power detection circuit is capable of generating a power detection signal responsive to a signal level of the final stage amplified output signal of the final stage amplifier circuit of the multistage amplifier circuit;
When the power detection signal is supplied to one input terminal of the error amplifier and the target power signal is supplied to the other input terminal of the error amplifier, a power control voltage can be generated from the output terminal of the error amplifier. And
By supplying the power control voltage to the input terminal of the control signal enhancement circuit, an enhancement control signal can be generated from the output terminal of the control signal enhancement circuit,
The control signal enhancement circuit has a predetermined non-linear input / output characteristic, and is based on an increase rate of the enhancement control signal in response to an increase in the power control voltage before the power control voltage reaches a predetermined voltage. Also, the increase rate of the enhancement control signal in response to the increase in the power control voltage after the power control voltage reaches the predetermined voltage is set large,
The enhancement control signal is supplied to the first stage bias circuit and the last stage bias circuit, and the first stage idling current and the last stage idling current are controlled by the enhancement control signal. How it works. In claim 11,
The first stage bias circuit includes a first stage bias transistor connected in a current mirror with a first stage amplification transistor of the first stage amplifier circuit,
The final stage bias circuit includes a final stage bias transistor connected in a current mirror with a final stage amplification transistor of the final stage amplification circuit,
The first stage bias current and the last stage bias current as the enhancement control signal are respectively supplied to the first stage bias transistor and the last stage bias transistor, and the first stage idling current and the last stage idling current are the first stage bias current and the last stage bias current, respectively. A method of operating an RF power amplifier, wherein the method is determined by a final stage bias current. In claim 12,
The control signal enhancement circuit includes a voltage / current conversion circuit and a current square circuit,
The voltage-current conversion circuit is capable of generating a conversion current that is substantially proportional to the change in response to a change in the power control voltage,
The current squaring circuit is capable of generating a squared output current substantially proportional to the square of the power control voltage;
The method for operating an RF power amplifier, wherein the control signal enhancement circuit is capable of generating an output power control current obtained by adding the conversion current and the square output current as the enhancement control signal. In claim 12,
The control signal enhancement circuit includes a voltage / current conversion circuit and a current cube circuit.
The voltage-current conversion circuit is capable of generating a conversion current that is substantially proportional to the change in response to a change in the power control voltage,
The current cube circuit is capable of generating a cubed output current substantially proportional to the cube of the power control voltage;
The method for operating an RF power amplifier, wherein the control signal enhancement circuit is capable of generating an output power control current obtained by adding the conversion current and the cubed output current as the enhancement control signal. In claim 12,
The control signal enhancement circuit includes a plurality of operational amplifiers, so that an output power control current having nonlinear characteristics with respect to a plurality of reference voltages can be generated as the enhancement control signal. How it works. In claim 12,
The control signal enhancement circuit includes an analog-to-digital converter, a look-up table, and a digital-to-analog converter.
The analog-to-digital converter can convert the power control voltage supplied from the error amplifier into a first digital signal;
The look-up table has the predetermined nonlinear input / output characteristic, and can convert the first digital signal into a second digital signal according to the predetermined nonlinear input / output characteristic.
The method of operating an RF power amplifier, wherein the digital / analog converter is capable of generating an output power control current obtained by analog conversion of the second digital signal as the enhancement control signal. In claim 12,
An RF power amplifier characterized in that the target power signal supplied to the other input terminal of the error amplifier can control ramp-up and ramp-down in a transmission operation time slot of a time division multiple access method. How it works. In claim 12,
A method of operating an RF power amplifier, wherein each of the first stage amplification transistor, the last stage amplification transistor, the first stage bias transistor, and the last stage bias transistor is a MOS transistor or a bipolar transistor. An operation method of an RF power amplifier comprising a multistage amplifier circuit having at least a first stage amplifier circuit and a final stage amplifier circuit, a bias circuit having at least a first stage bias circuit and a final stage bias circuit, and a power detection circuit,
The first stage bias voltage of the first stage bias circuit is supplied to the first stage amplifier circuit, the first stage idling current of the first stage amplifier circuit is determined,
The final stage bias voltage of the final stage bias circuit is supplied to the final stage amplifier circuit, the final stage idling current of the final stage amplifier circuit is determined,
The first stage amplifier circuit can amplify an RF input signal supplied to an input terminal of the RF power amplifier, and the final stage amplifier circuit outputs a final stage amplified output signal in response to the first stage amplified output signal of the first stage amplifier circuit. Can be generated,
The power detection circuit is capable of generating a power detection signal responsive to a signal level of the final stage amplified output signal of the final stage amplifier circuit of the multistage amplifier circuit;
A semiconductor integrated circuit comprising an error amplifier, a control signal enhancement circuit, and a variable gain amplifier is connected in advance to the RF power amplifier,
By supplying an RF transmission input signal to the input terminal of the variable gain amplifier of the semiconductor integrated circuit, the output signal of the variable gain amplifier can be supplied to the input terminal of the RF power amplifier as the RF input signal. ,
The power detection signal generated from the power detection circuit of the RF power amplifier is supplied to one input terminal of the error amplifier of the semiconductor integrated circuit, while a target power signal is supplied to the other input terminal of the error amplifier. By being supplied, a power control voltage can be generated from the output terminal of the error amplifier,
By supplying the power control voltage to the input terminal of the control signal enhancement circuit, an enhancement control signal can be generated from the output terminal of the control signal enhancement circuit,
The control signal enhancement circuit has a predetermined non-linear input / output characteristic, and is based on an increase rate of the enhancement control signal in response to an increase in the power control voltage before the power control voltage reaches a predetermined voltage. Also, the increase rate of the enhancement control signal in response to the increase in the power control voltage after the power control voltage reaches the predetermined voltage is set large,
A method of operating an RF power amplifier, wherein a variable gain of the variable gain amplifier is controlled by the enhancement control signal by supplying the enhancement control signal to a gain control terminal of the variable gain amplifier. In claim 19,
The RF transmission input signal supplied to the input terminal of the variable gain amplifier is an RF transmission signal according to at least one of a WCDMA system, an EDGE system, an LTE system, and an HSUPA system. Power amplifier operation method.

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