JP2012233965A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device capable of suppressing disturbance of a display image to prevent malfunction or hang-up even when a bit error occurs on a display list stored in a video memory 8.SOLUTION: The image display device includes a video memory 8 that holds a display list for each frame; image processing means 5 that generates a piece of drawing data from the display list for one frame held by the video memory 8; display control means 6 that outputs the drawing data generated by the image processing means 5 as a display image; and error detection means 4 that detects a bit error when the image processing means 5 inputs the display list for one frame. When the error detection means 4 detects a bit error, the image processing means 5 generates a piece of drawing data of a frame next to the frame relevant to the display list in which the bit error is detected, the display control means 6 continues the output of the display image relevant to the drawing data of the frame prior to the frame by one.

Description

  The present invention relates to an image display device.

  In recent years, as means for displaying information to users, such as home appliances, car navigation systems, portable terminals, on-board meters, etc. (Graphical User Interface), digital bulletin boards, electronic posters, and digital signage (electronic signage) such as operation displays and departure tickets, An image display device equipped with a graphics function is widely used. In these image display apparatuses, graphics drawing by a hardware (graphics engine) dedicated to graphics drawing is performed separately from the CPU, not graphics drawing by a conventional CPU. The graphics engine aims to reduce the CPU load and improve the drawing performance by performing graphics drawing such as point / line / polygon drawing, painting, BitBLT, font drawing and animation drawing instead of the CPU.

In graphics drawing processing by the graphics engine, a method called a display list method is used. In the display list method, graphics to be drawn and parts constituting the graphics are collected into a command format list (display list) and stored in a memory connected to the graphics engine. The graphics engine directly reads out the command in the display list (without CPU intervention) and executes the command (drawing process). This aims to reduce graphics rendering control and data transfer between the CPU and the graphics engine (for example, Patent Document 1).
An image display device equipped with a graphics function is equipped with a memory (graphics memory, video memory, or the like) necessary for processing such as drawing and display. As the memory, high-speed memory dedicated to graphics (GDDR, etc.), DRAM (SDR / DDR / DDR2 / DDR3-SDRAM, etc.) and SRAM used for main memory, and non-volatile flash memory are used. Yes.

JP 2009-294991 A

  However, when these memories (video memories) are used, memory errors (memory bit errors, bit errors) due to structural factors of the memory cells themselves and external factors around the memory (video memory) occur. There is a case. In an image display device using the display list method, when the bit error occurs in the display list stored in the memory (video memory), the command and parameters in the display list change from the values specified by the user, and the graphic is displayed. As a result of an unexpected graphics drawing (drawing process) caused by a malfunction in the image engine (image display device), the display image is disturbed, and the graphics engine or image display device malfunctions or hangs up. There was a problem of doing it.

  The present invention has been made to solve the above-described problems. Even when a bit error occurs in the display list stored in the video memory, the display image is prevented from being disturbed to prevent malfunction and hang-up. An object of the present invention is to provide an image display device.

  The image display apparatus according to the present invention includes a holding unit that holds a display list including commands for generating drawing data for each frame, and a drawing that generates drawing data from the display list for one frame held by the holding unit. A processing means, a display control means for outputting drawing data generated by the drawing processing means as a display image, and when the drawing processing means inputs a display list for one frame, the holding means holds the display list Error detection means for detecting a bit error occurring in the display list, and when the error detection means detects a bit error, the drawing processing means is a frame next to the frame related to the display list in which the bit error is detected. The display control means generates the drawing data of the previous frame. It is characterized in that to continue output of the display image according.

  According to the present invention, the bit error is detected, and the processing is stopped for the frame in which the bit error is detected. Even when a bit error occurs in the display list stored in the video memory, the display image is disturbed. It is possible to provide an image display device that suppresses and prevents malfunction and hang-up.

It is a functional block diagram of the image display apparatus which concerns on this invention. It is a figure which shows the memory map in the image display apparatus of FIG. It is a figure which shows the video memory mapping and display list structure in the image display apparatus of FIG. 2 is a flowchart showing a flow of processing executed first in the image display device shown in FIG. 1. 2 is a flowchart showing a flow of processing for one frame when an error is not detected in the image display device shown in FIG. 1. 3 is a flowchart showing a flow of processing in the image display device shown in FIG. 1. 3 is a flowchart showing a flow of processing in the image display device shown in FIG. 1. 3 is a flowchart showing a flow of processing in the image display device shown in FIG. 1. It is a figure for demonstrating the operation | movement in the image display apparatus of FIG. It is a figure which shows the example of the image display operation | movement in the image display apparatus of FIG. It is a figure which shows the example of the image display operation | movement in the image display apparatus of FIG. It is a figure which shows the example of the image display operation | movement in the image display apparatus of FIG. It is a figure which shows the example of the image display operation | movement in the image display apparatus concerning Embodiment 2 of this invention. It is a figure for demonstrating operation | movement in the image display apparatus which concerns on Embodiment 2 of this invention. It is a figure for demonstrating operation | movement in the image display apparatus which concerns on Embodiment 2 of this invention.

Embodiment 1 FIG.
FIG. 1 is a functional configuration diagram of an image display apparatus 10 according to the present invention. As shown in FIG. 1, an image display apparatus 10 according to the present invention is an image display apparatus having graphics display and display functions by a display list method. The image display device 10 is connected to an external host (for example, a CPU. In the following description, a case where a CPU is used as an example of the host will be described) as a host device, and connected to an external display means (not shown). Output the display image.

  Specifically, the image display device 10 includes a host interface unit 1, a display list control unit 2, a display list analysis unit 3, an error detection unit 4, a drawing processing unit 5, a display control unit 6, a memory control unit 7, and a video memory. (VRAM) 8 is provided.

  The host interface unit 1 is a bus interface with a CPU (host), and inputs and outputs control parameters and a display list from the outside of the image display device 10.

  A register space and a video memory space (VRAM space) in the image display device 10 are mapped on the memory map of the CPU. The CPU controls the image display device 10 by accessing the register space and video memory space inside the image display device 10 via the host interface means 1.

  The host interface means 1 decodes the address input via the CPU bus 100, and if it is an access to the internal register space, it writes or reads data from / into the registers in each means via the internal register bus 101-1. Do. If the video memory space is to be accessed, a memory access request is made to the memory control means 7 via the video memory bus 101-2, and the video memory 8 is written or read.

  Here, the structure of the display list will be described with reference to FIG. The display list is composed of a command group that generates drawing data for each of a plurality of frames (L in the example of FIG. 3). The command group of each frame is composed of a plurality of commands (0 to M in the example of FIG. 3). Of the plurality of commands, command 0 is a frame header of each frame. Command 1 to command M, excluding command 0 (frame header), are composed of a command header of each command and a plurality of parameters (N in the example of FIG. 3).

  The command header includes information on the type of command and the number of parameters. For example, when performing fixed color filling of a rectangular area, the command type is “painting”, the number of parameters is “3”, parameter 1 is the upper left coordinates (X1, Y1) of the rectangular area, and parameter 2 is the lower right coordinates (X2). , Y2), parameter 3 is the color to be filled. The number of parameters and the contents of the parameters vary depending on the command to be executed.

Commands include drawing of points, lines, circles, polygons, BitBLT transfer (bit block transfer), fill (filling), texture map, vector graphics drawing, font drawing, bitmap drawing, animation drawing, etc. Including commands used in simple graphics drawing and those uniquely defined as a display list (for example, an end command and a jump command).
The numbers L, M, and N are used only for convenience of explanation, and do not limit the scope of the present invention.

  Returning to FIG. 1, the display list is first input to the host interface means 1 from the outside via the CPU bus 100. In the following description, an example will be described in which the host interface unit 1 inputs display lists for frames 1 to L from the outside. The host interface unit 1 outputs to the memory control unit 7 a request to write the input display list for the frames 1 to L in a display list area of the video memory 8 described later.

  The display list control means 2 sends a display list read request 102 to the memory control means 7 based on parameters set via the internal register bus 101-1 and display list analysis information 103-1 from the display list analysis means 3 described later. -1 is output. Specifically, when a bit error is detected in the frame header (command 0) or command header portion of each frame, the display list read request 102-1 is a request to read again from the head of the same frame header or command header. . When a bit error is detected in the parameter group of each command, the display list read request 102-1 is a request for reading from the head of the frame next to the frame in which the error is detected.

  When the display list control means 2 receives from the error detection means 4 an error notification 104-2 indicating that a bit error has been detected in the parameter group of each command, the command invalid signal 102-2 is sent to the display list analysis means 3. Is output to the drawing processing means 5 and the display control means 6 is notified of non-update of the display image.

  The drawing control bus 102-3 is a drawing processing control bus connected to the drawing processing means 5, and the display list control means 2 receives a drawing completion signal from the drawing processing means 5 via the drawing control bus 102-3. Receive. Further, the display list control unit 2 notifies the drawing processing unit 5 of a drawing buffer switching signal, command invalidity, and the like via the drawing control bus 102-3.

  The display control bus 102-4 is a display control bus connected to the display control means 6, and the display list control means 2 obtains display timing from the display control means 6 via the display control bus 102-4. . The display list control means 2 also sends a display control signal (display image switching signal, head address in the video memory 8 storing drawing data and screen to the display control means 6 via the display control bus 102-4. Size (width, height, etc.).

  The display list analysis means 3 inputs the display list 104-1 from the error detection means 4 described later, analyzes the input display list 104-1 according to the parameters set via the internal register bus 101-1, and analyzes the analysis results. The drawing parameters and drawing commands 103-2 are output to the drawing processing means 5.

The display list analysis unit 3 outputs the display list analysis information 103-1 to the display list control unit 2. The display list analysis information 103-1 is a display list analysis result, and includes a frame header, a command header, a command type, a command parameter, and the like.
When receiving the command invalid signal 102-2 from the display list control means 2, the display list analysis means 3 returns (initializes) the state being analyzed to the initial state.

The error detection unit 4 detects a bit error in the display list read from the video memory 8 via the memory control unit 7 using the error check bit and the read data 107-2 input from the memory control unit 7.
Here, the bit error refers to an error that occurs in the display list while the video memory 8 described later holds the display list.

When a bit error is detected in the display list, the error detection unit 4 outputs an error notification 104-2 to the display list control unit 2.
The error detection unit 4 outputs the display list 104-1 to the display list analysis unit 3.

  The drawing processing means 5 includes parameters set via the internal register bus 101-1, drawing control signals from the display list control means 2 (drawing control bus 102-3), drawing parameters from the display list analysis means 3, and In response to the drawing command 103-2, an output of an access request to the video memory 8 to the memory control means 7 via the drawing bus 105-2, generation of drawing data, and the drawing data to the memory control means 7 are output. I / O is performed.

  Specifically, the drawing processing unit 5 generates drawing data by processing the drawing parameters and the drawing command 103-2 input from the display list analyzing unit 3 according to the parameters set via the internal register bus 101-1. . The drawing processing means 5 alternately writes the generated drawing data into the first or second drawing area provided in the video memory 8 described later. The switching between the first and second drawing areas is performed based on information relating to the drawing buffer switching included in the drawing control signal input via the drawing control bus 102-3.

  When the drawing processing means 5 receives the command invalidity notification from the display list control means 2, the drawing processing means 5 stops the writing process to the first or second drawing area at that time, and then draws the drawing data of the next frame. The generated drawing data is written into the first or second drawing area which has been written when the command invalidation notification is received.

  The display control means 6 receives the parameters set via the internal register bus 101-1 and the display control signal from the display list control means 2 (display control bus 102-4), and via the display bus 106-2, A read request is output to the memory control means 7, and drawing data is read from the video memory 8. The display control means 6 outputs the read drawing data as the display image 106-1 in accordance with the display timing.

  Specifically, the display control means 6 reads the drawing data written in the second drawing area while the drawing processing means 5 writes the drawing data to the first drawing area. While the drawing processing means 5 is writing drawing data to the second drawing area, the drawing data written in the first drawing area is read.

  When the display control means 6 receives a notification of non-update of the display image from the display list control means 2, it does not switch the display area at the next display timing.

  The memory control means 7 performs writing to the video memory 8 and reading from the video memory 8 based on a memory access request from each means. During the writing of the display list, the memory control means 7 stores the error check bit calculated from the display list in the video memory 8 together with the display list. During the reading of the display list, the memory control means 7 reads the error check bit together with the display list and outputs both to the error detection means 4.

  The video memory 8 is a memory that stores drawing data and a display list. It is also used as a temporary memory for drawing processing. The video memory 8 is controlled by the memory control means 7 for write access and read access.

  FIG. 3 shows the mapping in the video memory 8. As shown in FIG. 3, on the video memory 8, a display list area for holding a display list, an area for storing font data, vector data, bitmap data, and the like, which are data necessary for drawing processing, First and second drawing areas in which drawing data are stored are provided.

Next, the process flow of the image display apparatus 10 according to the first embodiment will be described.
FIG. 4 is a flowchart showing a flow of processing executed first in the image display apparatus 10 according to this embodiment.

  An external host device or host (CPU) is connected to the CPU bus 100 to control drawing processing and display. On the memory map (register map) of the CPU, a register space and a video memory space that define the operation of each means are mapped. Access from the CPU is performed via the host interface means 1. The host interface unit 1 decodes an address input from the CPU, and writes or reads data in or from a register space or video memory space in the corresponding (mapped) unit.

  The CPU outputs the display list and the address of the video memory space for storing the display list to the host interface means 1 via the CPU bus 100. The host interface means 1 determines that the video memory space is accessed from the decoding result of the input address, and stores the display list in the video memory 8 via the video memory bus 101-2 (step ST110). The host interface unit 1 similarly stores other data necessary for graphics drawing (font data, vector data, bitmap data, etc.) in the video memory 8.

  The memory control means 7 adds an error check bit when the display list is stored in the video memory 8. (Step ST111).

  The CPU outputs a display list execution start command to the display list control means 2 assigned to the register space (performs a start setting for the display list execution command register. This is performed from the CPU only when the display list is started) (step ST112). .

  The host interface unit 1 allocates a buffer area used for drawing and display to the video memory 8 (step ST113).

  An example of a memory map image on the CPU bus 100 is shown in FIG. 2, and an example of a display list structure is shown in FIG. In FIG. 2, the display list is stored with the display list base_address of the video memory space as the head address.

  FIG. 5 is a flowchart showing a flow of processing for one frame in the image display device 10 according to the first embodiment when no error is detected.

The error detection means 4 reads the display list for one frame (step ST120).
Specifically, the display list control means 2 receives the display list execution start command and outputs a display list read request 102-1 to the memory control means 7. The memory control means 7 reads the display list from the display list base_address of the video memory space, and outputs an error check bit and read data (display list) 107-2 to the error detection means 4.

  The error detection means 4 detects a bit error bit by bit from the error check bit and read data (display list) 107-2 (step ST121). Here, a case where no bit error is detected will be described. The error detection means 4 outputs read data (display list 104-1) to the display list analysis means 3.

The display list analysis unit 3 analyzes the read data (display list 104-1) input from the error detection unit 4 (step ST122).
Based on the analyzed result, the display list analyzing unit 3 sets the drawing parameters and notifies the drawing execution command to the drawing processing unit 5 (step ST123).

  Drawing parameters include, for example, the drawing buffer start address in the video memory space, screen size (width, height), color format, scissor area, drawing position, shape information (point, line, polygon, circle, etc.), attribute information This is a parameter that includes (color, gradation presence / absence) and alpha value.

  The drawing processing means 5 generates drawing data according to the set drawing parameters (step ST124). The drawing processing unit 5 outputs the generated drawing data to the memory control unit 7 via the drawing bus 105-2. The memory control means 7 alternately writes the input drawing data into the first or second drawing area in the video memory 8 (step ST125).

  The display control unit 6 sets display parameters from information input from the CPU via the host interface unit 1 and the internal register bus 101-1. The display control means 6 generates a display timing based on the set display parameter (step ST126).

  Specifically, in the case of XGA (1024 × 768 @ 60 Hz) display, for example, when the dot clock is 65 MHz, the display control means 6 has a horizontal total pixel number: 1344, a vertical total line number: 806, an effective horizontal pixel number 1024, Display parameters are set from information such as the number of horizontal blank pixels 320, the number of vertical effective lines: 768, and the number of vertical blank lines: 38, and the display timing is generated.

  The display control means 6 sends a memory read request to the memory control means 7 via the display bus 106-2 from the display address and screen size (width and height) of the video memory 8 passed via the display control bus 102-4. And the corresponding drawing data is read for the screen size, and is output as the display image 106-1 in synchronization with the generated display timing (step ST127).

  Referring to FIG. 2, while the drawing processing means 5 is writing to the first drawing area (video memory address: A_buffer_base_address), the display control means 6 draws from the second drawing area (video memory address: B_buffer_base_address). Read data. While the drawing processing means 5 is writing to the second drawing area, the display control means 6 reads drawing data from the first drawing area.

  The switching between the first and second drawing areas is performed by the display list control means 2 in the display list execution status of the display list analysis information 103-1 output from the display list analysis means 3 (which frame is being processed). ), Completion of command processing notified from the drawing processing means 5, and display timing (vertical synchronization signal: Vsync) input from the display control means 6.

  As shown in FIG. 3, the display list defines drawing processing for one frame with commands 0 to M. Therefore, when all the drawing processes of commands 0 to M are completed, the drawing process for each frame is completed.

  When the drawing processing means 5 is currently writing in the first drawing area, the image display device 10 draws at the timing of the next display timing vertical synchronization signal (Vsync) after the completion of the drawing processing for each frame. The processing means 5 changes the area in which the drawing data is written from the first drawing area to the second drawing area (reading by the display control means 6 is from the second drawing area to the first drawing area). By repeatedly executing this from frame 0 to frame L, it is possible to perform graphics display (animation display) for L frames without displaying an image in the middle of drawing. If the drawing processing time is not completed in one frame time, the drawing frame rate is lowered.

6 to 8 are flowcharts showing a flow of image display processing in the image display apparatus 10 according to this embodiment.
The CPU (host device) sets the top address of the display list as a video memory address to the display list control means 2 via the host interface means 1 (step ST201). The CPU activates the display list via the host interface unit 1 (step ST202).

  The display list control means 2 outputs a display list read request 102-1 to the memory control means 7 (step ST203).

  The memory control means 7 reads the display list from the video memory 8 and outputs the read display list to the error detection means 4. Here, the memory control means 7 reads the command 0 (frame header: including information on the number of commands and the size) at the head of each frame (step ST204).

  The error detection means 4 detects a bit error in the input display list (step ST205). When a bit error is detected (step ST205; YES), the error detection means 4 outputs an error notification 104-2 to the display list control means 2 (step ST206). The display list control means 2 having received the error notification 104-2 outputs the display list read request 102-1 of the same video memory address again (step ST203).

  When the display list (here, the frame header) is normally read and no bit error is detected (step ST205; NO), the error detection means 4 outputs the received display list 104-1 to the display list analysis means 3. To do. The display list analysis means 3 analyzes the command type (here, the frame header), the number of commands processed in this frame, and the size from the input display list (step ST207).

The display list analysis means 3 outputs the analyzed result to the display list control means 2 as display list analysis information 103-1. Based on the display list analysis information 103-1, the display list control means 2 grasps the execution status of the display list.
The display list control means 2 sets the internal command number counter j to 0 (step ST208).

The display list control means 2 sets the start address of the next command as the next read video memory address (step ST209).
The display list control means 2 outputs the display list read request 102-1 for the display list (here, the command header of the command j) (step ST210).

  The memory control means 7 reads the display list from the video memory 8 and outputs the read display list to the error detection means 4. Here, the memory control means 7 reads the command header of the command j (including information on the command type, the number of parameters, and the size) (step ST211).

  The error detection means 4 detects a bit error in the input display list (step ST212). When a bit error is detected (step ST212; YES), the error detection means 4 outputs an error notification 104-2 to the display list control means 2 (step ST213). The display list control means 2 having received the error notification 104-2 outputs the display list read request 102-1 of the same video memory address again (step ST210).

  When the command header of the command j is normally read and no bit error is detected (step ST212; NO), the error detection means 4 outputs the received display list (command header) to the display list analysis means 3. The display list analyzing means 3 analyzes the input display list and determines whether the command type is an end command (step ST214). If the command type is an end command (step ST214; YES), the process ends.

  If the command type is not an end command (step ST214; NO), since the command type is a command header (not an end command), the display list analysis means 3 performs a drawing command to be executed with this command from the input display list. The type, the number of parameters, and the size are analyzed (step ST215). The display list analysis means 3 holds the analysis result and outputs it to the display list control means 2 as display list analysis information 103-1.

  The display list analyzing means 3 sets the internal parameter reception number counter i to 0 (step ST216).

  The display list control means 2 detects from the display list analysis information 103-1 that the command type is the command header of the command j, and adds one word to the current video memory address (step ST217). The display list control means 2 outputs a display list read request 102-1 to the video memory address added by one word (step ST218).

  The memory control means 7 reads the display list (here, command parameter (i + 1)) from the video memory 8 (step ST219).

  The error detection means 4 detects a bit error in the input display list (here, command parameter (i + 1)) (step ST220). When no bit error is detected (step ST220; NO), the error detection means 4 outputs the input display list (command parameter (i + 1)) to the display list analysis means 3. Since the display list analysis means 3 has already received the command header, it recognizes that the command type to be executed and the commands input thereafter are command parameters 1 to N, and the number N of the parameters. If no bit error is detected, the display list analysis unit 3 outputs the command parameter (i + 1) to the drawing processing unit 5, and the drawing processing unit 5 sets the input command parameter (step ST221).

  The drawing processing means 5 adds 1 to the parameter reception number counter i (step ST222). The drawing processing means 5 determines whether or not the held parameter reception number counter is less than the parameter number N set when the command header of the command 1 is input (step ST223). When the parameter reception number counter i to be held is less than the parameter number N set when the command header is input (step ST223; YES), steps ST217 to ST223 are repeated.

  When the retained parameter reception number counter i is greater than or equal to the parameter number N set when the command header is input (step ST223; NO), the display list analysis unit 3 outputs a drawing command to the drawing processing unit 5. The drawing processing means 5 executes drawing processing according to the set parameters and drawing commands (step ST224).

  The display list control means 2 adds 1 to the held command number counter j (step ST225). The display list control means 2 determines whether or not the held command number counter j is less than the command number M (step ST226). When the command number counter j is less than the command number M (step ST226; YES), the processing from step ST209 to step ST226 is repeated.

  If the command number counter j is equal to or greater than the command number M (step ST226; NO), the drawing processing means 5 outputs a drawing completion notice to the display list control means 2 (step ST227).

The display list control means 2 receives the drawing completion notice from the drawing processing means 5, and sets the head address of the next command as the video memory address to be read next (step ST228).
Thereafter, the process returns to step ST203, and the same process is performed for the next frame.

  When the error detection unit 4 receives a command parameter (i + 1) and detects a bit error (step ST220; YES), the error detection unit 4 outputs an error notification 104-2 to the display list control unit 2. The display list control means 2 notifies the display list analysis means 3 and the drawing processing means 5 that the command is invalid, and notifies the display control means 6 that the display image is not updated (step ST229).

  Upon receiving the command invalidity notification, the display list analyzing means 3 returns (initializes) the state being analyzed to the initial state (step ST230).

  Upon receiving the command invalid notice, the drawing processing means 5 stops writing to the first or second drawing area at that time (step ST231). As a result, the execution of the display list in which an error has occurred is stopped, and the execution of an unexpected drawing process can be suppressed.

  When the display image non-update notification is received, the display control means 6 does not switch the display area even when the next display timing elapses, and continues to display the display image of the previous frame (step ST232). Thus, there is an effect that the display image of the previous frame can be continuously displayed even when the drawing processing unit 5 stops writing the image data.

The display list control means 2 skips the remaining command in the frame where the error is detected, and sets the head address of the next frame as the video memory address to be read next (step ST233).
Thereafter, the process returns to step ST203, and the same process is performed for the next frame.

  As a result, since the remaining display list of the frame in which the bit error has occurred is not read, execution of an unexpected drawing process can be suppressed, display image disturbance can be suppressed, and malfunction and hang-up can be prevented. There is an effect.

  Next, buffer switching will be described with reference to FIG. Reading from the video memory 8 and execution of command processing are normally executed up to command 0 in the second frame.

  Since an error was detected when reading the video memory of command 1 in the second frame, command reading and command processing after command 2 in the second frame are skipped, and the first video memory address in frame 3 (command 0 in frame 3) Video memory reading and command processing are started.

  In the second frame, the drawing processing means 5 writes drawing data to the second drawing area, and the display control means 6 reads drawing data already written in the first drawing area. Since an error was detected during the drawing process of the second frame, the drawing processing means 5 does not change the drawing data of the third frame without changing the first and second drawing areas in the next third frame process. The display control means 6 continues to display the display image relating to the drawing data of the previous frame (first frame) written in the first drawing area.

  In the third frame process, since no bit error is detected, the first and second drawing areas are switched before the fourth frame drawing process. Thereafter, the processing is continued.

  Examples of display list operations and display operations when no bit error is detected are shown in FIGS. 10 and 11, respectively. FIG. 12 shows a display operation when a bit error is detected. As shown in FIGS. 10-12, when a bit error is detected, execution of the command is stopped in frame 2 where the error is detected, and display of the previous frame 1 is continued.

  In the above description, the case where the display list and the command are arranged in the continuous area on the video memory 8 has been described, but both are arranged in the discontinuous area by adding an address (jump instruction) to the next command. You may do it.

  In the above description, the case where the memory control unit 7 adds an error check bit for error detection and the error detection unit 4 performs error detection using the error check bit when reading the video memory has been described. The control means 7 may add ECC (Error Correction Code) or the like for error detection, and the error detection means 4 may perform error correction when the number of error bits is correctable. When error correction is possible, the error detection unit 4 may not perform the error notification 104-2 to the display list control unit 2 and thereafter perform the same processing as when no bit error is detected. .

  In the above description, if an error is detected when reading a command parameter in the display list, the display list control means 2 skips the subsequent command parameters and outputs a read request for the start address of the next frame. As described above, the display list control means 2 may make a read request (the most read request) to the same video memory address again without skipping the command parameter in which the error is detected.

  In that case, the display list control means 2 counts the number of times that a bit error has been detected, and if a bit error occurs repeatedly even at the time of a re-read request, reads the subsequent command parameters when the count value exceeds a predetermined threshold. It may be skipped and a read request for the start address of the next frame may be output.

  Further, in the above description, when an error is detected when reading the command parameter, the display list control unit 2 skips reading the display list up to the head address of the next frame. Depending on the command type, only the parameter group of the command in which an error has been detected (up to the next command in the same frame) may be controlled to skip the display list reading.

  In the above description, the image size is described as XGA. However, the image size may be arbitrarily changed according to the display to be displayed. Furthermore, the image size to be drawn may be different from the image size to be displayed.

  As described above, the image display apparatus 10 according to the first embodiment includes the video memory 8 that holds a display list including commands for generating drawing data for each frame, and the display for one frame that the video memory 8 holds. When the drawing processing unit 5 that generates drawing data from the list, the display control unit 6 that outputs the drawing data generated by the drawing processing unit 5 as a display image, and the drawing processing unit 5 inputs a display list for one frame. And an error detection means 4 for detecting a bit error occurring in the display list while the video memory 8 holds the display list. When the error detection means 4 detects a bit error, the drawing processing means 5 , The drawing data of the next frame of the frame related to the display list in which the bit error is detected is generated. And display control means 6, and configured to continue the output of the display image according to the drawing data of the previous frame. For this reason, the processing is stopped for the frame in which the bit error is detected, and even when a bit error occurs in the display list stored in the video memory 8, the display image is prevented from being disturbed, and malfunctions and hang-ups are prevented. An image display device can be provided.

  The image display device 10 according to the first embodiment also includes a display list area for holding a display list composed of commands for generating drawing data for each frame and a drawing list for holding drawing data for each frame. Drawing data is generated from a video memory 8 composed of first and second drawing areas, and a display list for one frame held in the video memory 8, and the generated drawing data is used as the first or second drawing area. While the drawing processing means 5 writes alternately to and the drawing processing means 5 is writing to the first or second drawing area, the drawing data written to the second or first drawing area When the display control means 6 for reading out and outputting as a display image and the drawing processing means 5 input a display list for one frame, the video memory 8 Error detection means 4 for detecting a bit error occurring in the display list while holding the image, and when the error detection means 4 detects a bit error, the drawing processing means 5 detects the bit error. The drawing data of the next frame of the frame related to the display list is written in the first or second drawing area, and the display control means 6 is used for the previous frame written in the second or first drawing area. The drawing data is continuously read and the display image is output. For this reason, the processing is stopped for the frame in which the bit error is detected, and even when a bit error occurs in the display list stored in the video memory 8, the display image is prevented from being disturbed, and malfunctions and hang-ups are prevented. An image display device can be provided.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described.
In the first embodiment, one window drawing process is performed per frame, and when an error is detected, the drawing process is skipped and the display image is not updated (control not to switch the buffer) for the entire screen. In the second embodiment, the drawing process is skipped, the display image is not updated (control not to perform buffer switching), and the like only for the drawing command of the window in which the error is detected.
FIG. 1 is a functional configuration diagram of an image display apparatus 10 according to the second embodiment. Hereinafter, the difference from the first embodiment will be mainly described.

The error detection means 4 detects a bit error for each of a plurality of display areas.
The drawing processing unit 5 generates drawing data for each of the plurality of display areas, and writes the generated drawing data of each display area in the first or second drawing area of each display area. When the error detecting unit 4 detects a bit error, the drawing processing unit 5 stores the drawing data of the next frame in the first or second drawing region of each display region for each display region in which the bit error is detected. Write.

  The display control means 6 reads the drawing data written in the second drawing area of each display area while the drawing processing means 5 is writing to the first drawing area of each display area. The display control means 6 reads the drawing data written in the first drawing area of each display area while the drawing processing means 5 is writing to the second drawing area of each display area. The display control means 6 outputs the read drawing data as a display image of each display area. When a bit error is detected, the display control means 6 reads the drawing data of the previous frame written in the second or first drawing area for each display area where the bit error is detected. And display image output continues.

  The video memory 8 includes first and second drawing areas for each of a plurality of display areas. In addition, the functions of each component are the same as the functions described in the first embodiment.

  FIG. 13 is a diagram illustrating an example of a display operation when an error is detected in the image display apparatus 10. As shown in FIG. 13, the execution of only the command related to window 1 in which an error has occurred when an error occurs is skipped. This processing can be realized by including the window number attribute information in each command of the display list and identifying which window the command is directed to.

  FIG. 14 is a diagram showing the mapping in the video memory of the image display device 10 and the structure of the display list. As shown in this figure, the video memory 8 includes a first drawing area and a second drawing area for each of a plurality of display areas.

  FIG. 15 is a diagram for explaining buffer switching in the image display apparatus 10. As shown in FIG. 15, reading from the video memory 8 is skipped only for the command parameter of the window 1 in which the bit error is detected. In the frame 3, the contents of the first and second drawing areas related to the window 1 are not changed.

  As described above, in the image display device 10 according to the second embodiment, the video memory 8 includes the first and second drawing areas for each of the plurality of display areas, and the drawing processing unit 5 stores the drawing data in the plurality of display areas. Generated for each display area, and the generated drawing data of each display area is written to the first or second drawing area of each display area, and the display control means 6 causes the drawing processing means 5 to write the first or second drawing area of each display area. During the writing to the drawing area, the drawing data written in the second or first drawing area of each display area is read and output as a display image of each display area, and the error detection means 4 Detects a bit error for each of a plurality of display areas, and when the error detection unit 4 detects a bit error, the drawing processing unit 5 draws the drawing data of the next frame for each display area in which the bit error is detected. In each display area Writing to the second drawing area, the display control means 6 reads out the drawing data of the previous frame written in the second or first drawing area for each display area in which the bit error is detected. The display image is output continuously. For this reason, in addition to the effect demonstrated in the said Embodiment 1, the image display apparatus which suppresses the skip of an image process and the non-update of a display image only to a required part can be provided.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  1 host interface means, 2 display list control means, 3 display list analysis means, 4 error detection means, 5 drawing processing means, 6 display control means, 7 memory control means, 8 video memory (holding means), 10 image display device.

Claims (3)

Holding means for holding, for each frame, a display list composed of commands for generating drawing data;
Drawing processing means for generating drawing data from a display list for one frame held by the holding means;
Display control means for outputting the drawing data generated by the drawing processing means as a display image;
An error detecting means for detecting a bit error generated in the display list while the holding means holds the display list when the drawing processing means inputs the display list for one frame;
When the error detection means detects the bit error,
The drawing processing unit generates drawing data of a frame next to a frame related to the display list in which the bit error is detected;
The display control means continues to output a display image related to drawing data of the previous frame. Consists of a display list area for holding a display list made up of commands for generating drawing data for each frame, and first and second drawing areas for holding the drawing data for each frame. Holding means;
Drawing processing means for generating drawing data from the display list for one frame held by the holding means, and alternately writing the generated drawing data in the first or second drawing area;
A display that reads out the drawing data written in the second or first drawing area and outputs it as a display image while the drawing processing means is writing to the first or second drawing area Control means;
An error detecting means for detecting a bit error generated in the display list while the holding means holds the display list when the drawing processing means inputs the display list for one frame;
When the error detection means detects the bit error,
The drawing processing means writes the drawing data of the next frame of the frame related to the display list in which the bit error is detected in the first or second drawing area,
The display control means continues to read the drawing data of the previous frame written in the second or first drawing area and output the display image. The holding means includes the first and second drawing areas for each of a plurality of display areas,
The drawing processing means generates the drawing data for each of the plurality of display areas, writes the generated drawing data of each display area to the first or second drawing area of each display area,
The display control means writes to the second or first drawing area of each display area while the drawing processing means writes to the first or second drawing area of each display area. Read out the drawn data and output it as a display image of each display area,
The error detection means detects the bit error for each of the plurality of display areas,
When the error detection means detects the bit error,
The drawing processing means writes the drawing data of the next frame into the first or second drawing area of each display area for each display area where the bit error is detected,
The display control means reads out the drawing data of the previous frame written in the second or first drawing area and outputs the display image for each display area in which the bit error is detected. The image display device according to claim 2, wherein the image display device is continued.

Images