JP2012222290A - Multilayer ceramic capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor which makes internal destruction such as cracks less likely to be caused in a laminated body and is suitable for achieving large capacity and downsizing.SOLUTION: A multilayer ceramic capacitor 1 includes: a laminated body 10 formed by alternately laminating multiple dielectric layers 120 and multiple internal electrode layers 110; and an external electrode 20 formed on an outer surface of the laminated body 10 and electrically connecting with the internal electrode layers 110. In the multilayer ceramic capacitor 1, the electric field intensity formed between the adjacent internal electrode layers 111, 112 at an outer layer side part of the laminated body 10 is smaller than the electric field intensity formed between the adjacent internal electrode layers 110 at a center part of the laminated body 10.

Description

  The present invention relates to a multilayer ceramic capacitor, and more particularly to a multilayer structure inside a multilayer body.

  A multilayer ceramic capacitor generally includes a multilayer body in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked, and an external electrode that is formed on the outer surface of the multilayer body and electrically connected to the internal electrode layer It has a structure with. Multilayer ceramic capacitors are broadly classified into class 1 of temperature compensation system and class 2 of high dielectric constant system. In a class 1 multilayer ceramic capacitor, a low dielectric constant type dielectric material mainly composed of titanium oxide or the like is used as a dielectric material. On the other hand, in a class 2 monolithic ceramic capacitor, a dielectric having a high dielectric constant (also referred to as a ferroelectric) whose main component is barium titanate or the like is used.

  In recent years, in order to increase the capacity of multilayer ceramic capacitors, the number of internal electrode layers has increased and the dielectric layers have become thinner. Along with this, particularly in class 2 monolithic ceramic capacitors, the phenomenon of internal structure destruction such as cracks in the laminate has increased. One cause of cracks is the piezoelectric effect of the dielectric layer. That is, since the dielectric layer which is a ferroelectric material has piezoelectricity, when a voltage is applied between the external electrodes, the dielectric layer is displaced in a direction parallel to the internal electrode layer. It is considered that a strain stress remains in the laminated body due to the displacement of the dielectric layer, thereby causing breakage such as cracks in the laminated body.

JP-A-9-180956

  A technique described in Patent Document 1 has been proposed as a technique for preventing the occurrence of such cracks.

  In the thing of patent document 1, the intermediate | middle layer for relieving stress is provided in the center part of the laminated body. The intermediate layer is made of the same material as that of the dielectric used in the capacitor forming portion, and the internal electrode layer in contact with the intermediate layer is arranged so as not to form a capacitor.

  However, since the capacitor described in Patent Document 1 cannot form a capacitor in the intermediate layer, there is a problem that it is disadvantageous for increasing the capacity and reducing the size. Further, the one described in Patent Document 1 is an idea that stress is absorbed by the intermediate layer, and in the intermediate layer, the displacement due to the piezoelectric effect does not occur. Therefore, when the displacement of the dielectric layer is larger, the dielectric layer It is considered that internal destruction such as cracks may occur at the interface with the intermediate layer. Similarly, in any one of the one described in Patent Document 1 and the above-described conventional multilayer ceramic capacitor, the outermost internal electrode layer, in other words, the outermost (front side) dielectric layer than the innermost electrode layer Since no voltage is applied to the cover layer, the cover layer is not displaced by the piezoelectric effect. For this reason, it is considered that strain stress remains at the interface between the dielectric layer where the displacement occurs and the cover layer where the displacement does not occur, which may cause internal destruction such as cracks.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer ceramic capacitor that is less likely to cause internal destruction such as cracks in the multilayer body and is suitable for downsizing. .

  In order to achieve the above object, the present invention provides a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and an external formed on the outer surface of the laminate and electrically connected to the internal electrodes. In a multilayer ceramic capacitor having electrodes, the electric field strength formed between adjacent internal electrode layers in the outer layer side portion of the multilayer body is smaller than the electric field strength formed between adjacent internal electrode layers in the central portion of the multilayer body It is characterized by.

  According to the present invention, since the electric field strength generated in the dielectric layer is smaller in the outer layer side portion of the laminate (in other words, on the surface side of the laminate) than in the central portion of the laminate, the displacement due to the piezoelectric effect is also small. The strain stress at the interface with the outermost internal electrode layer (in other words, the outer (front side) dielectric layer than the outermost internal electrode layer) is small. Thereby, occurrence of internal destruction such as cracks can be reduced.

  As an example of a preferred embodiment of the present invention, in the above-described multilayer ceramic capacitor, the thickness of the dielectric between the adjacent internal electrode layers is thicker in the outer layer side portion than in the central portion of the multilayer body. Can be mentioned. According to the present invention, since it is not necessary to change the dielectric constant of the dielectric in order to reduce the electric field strength, the same material can be used for all the dielectric layers, so that the manufacturing efficiency is high.

  As described above, according to the present invention, since the electric field strength generated in the dielectric layer is smaller in the outer layer side portion (in other words, the surface side of the laminate) of the laminate, the displacement due to the piezoelectric effect is also reduced. Therefore, the strain stress at the interface with the cover layer is small. Thereby, occurrence of internal destruction such as cracks can be reduced.

Cross section of multilayer ceramic capacitor Flow chart explaining manufacturing process of multilayer ceramic capacitor Cross-sectional view of a multilayer ceramic capacitor according to another example Cross-sectional view of a multilayer ceramic capacitor according to another example

  A multilayer ceramic capacitor according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a multilayer ceramic capacitor. It should be noted that in the present application, dimensions and shapes are appropriately modeled for simplicity of explanation.

  The multilayer ceramic capacitor 1 includes a substantially rectangular parallelepiped laminate 10 and a pair of external electrodes 20 formed at both ends in the longitudinal direction of the laminate 10.

  As shown in FIG. 1, the laminate 10 is made of a ceramic sintered body in which a plurality of internal electrode layers 110 and dielectric layers 120 are alternately laminated. The internal electrode layers 110 are arranged so as to overlap each other with a predetermined interval, and the end portions thereof are alternately exposed at one end face of the laminate 10 and are electrically connected to the external electrode 20 at the end face. Yes. That is, every other internal electrode layer 110 is electrically connected to the same external electrode 20. The internal electrode layer 110 is made of a base metal such as Ni or Cu, a noble metal such as Pd or Ag, or a metal mainly composed of an Ag—Pd alloy, but Ni is preferable from the viewpoint of cost reduction. In the present embodiment, the multilayer ceramic capacitor 1 is of a high dielectric constant class 2, and the dielectric layer 120 is made of a dielectric ceramic based on barium titanate. Note that the outermost layer side (surface side) internal electrode layer 111 of the dielectric layer 120 is referred to as a cover layer 121.

  The external electrode 20 is formed so as to wrap around from the both end surfaces in the longitudinal direction to the side surface adjacent to the end surface of the surface of the multilayer body 10. The external electrode 20 is made of a base metal such as Ni or Cu, a noble metal such as Pd or Ag, or a metal mainly composed of an Ag—Pd alloy, but Ni or Cu is preferable from the viewpoint of cost reduction. On the surface of the external electrode 20, a single-layer or multiple-layer plating layer (not shown) is formed in order to improve solderability.

  The characteristic point of the present invention is the layer structure in the laminate 10. That is, in the present invention, the electric field strength formed between the adjacent internal electrode layers 110 in the outermost layer side portion of the stacked body 10 (in other words, the surface side portion of the stacked body 10) is adjacent in the central portion of the stacked body 10. The electric field strength formed between the internal electrode layers 110 is smaller. In this embodiment, the electric field strength is controlled by the distance between the internal electrode layers 110, that is, the thickness of the dielectric layer 120.

  In the example of FIG. 1, the inner electrode layer 111 on the outermost layer side of the laminate 10 (in other words, the inner electrode layer 111 adjacent to the cover layer 121) and the inner electrode layer 112 on the inner layer side adjacent to the inner electrode layer 1111. The thickness D1 of the dielectric layer 122 therebetween is thicker than the thickness D0 of the dielectric layer 120 between all the other internal electrode layers 110. As a result, the electric field strength E1 in the dielectric layer 122 between the internal electrode layers 111 and 112 becomes smaller than the electric field strength E0 in the dielectric layer 120 between all the other internal electrode layers 110. On the other hand, no electric field is generated in the cover layer 121. Therefore, the displacement caused by the piezoelectric effect in the laminated body 10 has a relationship of (displacement in the cover layer 121 = 0) <(displacement in the dielectric layer 122) <(displacement in the other dielectric layers 120). Thereby, it is possible to prevent the strain stress remaining at the interface between each internal electrode layer 110 and each dielectric layer 120 from becoming excessive. In particular, the strain stress at the boundary surface between the cover layer 121 and the inner electrode layer 111 on the outermost layer side is small. Thereby, occurrence of internal destruction such as cracks can be reduced.

  Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described with reference to the flowchart of FIG. First, a raw material powder for forming a dielectric ceramic, an organic binder, a solvent, and other additives are mixed to prepare a ceramic slurry (step S1). Next, the ceramic slurry is formed and dried into a sheet shape by a doctor blade method or the like to obtain a ceramic green sheet (step S2). Here, the ceramic green sheets have different thicknesses for the dielectric layer 122, the other dielectric layer 120, and the cover layer 121, and at least the thickness for the dielectric layer 122 <the thickness for the other dielectric layer 120 It has become. The thickness of the ceramic green sheet for the cover layer 121 is not questioned, but it is preferably thicker than that for the dielectric layers 120 and 122 from the viewpoint of reducing the lamination process. Next, conductive paste for internal electrodes is printed in a predetermined pattern shape on the ceramic green sheet (step S3). It is preferable that a predetermined amount of ceramic raw material powder is mixed with the conductive paste as a co-fabric. Next, after laminating a predetermined number of patterns and number of ceramic green sheets printed with conductive paste, pressure bonding is performed to obtain a sheet laminate (step S4). Next, after cutting the sheet laminate into individual chips (step S5), the surface of the individual chips is polished by barrel polishing or the like (step S6). Next, the binder removal process is performed on the polished individual chips in the air or in a non-oxidizing gas such as nitrogen (step S7). Next, a conductive paste for an external electrode is applied to the exposed surface of the internal electrode of the individual chip after the binder removal process (step S8). Next, the individual chip coated with the conductive paste is baked in a nitrogen-hydrogen atmosphere at a predetermined temperature (step S9). Finally, the surface of the external electrode was plated to obtain a multilayer ceramic capacitor 1 (step S10).

  As described above, according to the present invention, the electric field strength generated in the dielectric layer 122 is smaller in the outer layer side portion of the multilayer body 10 than in the central portion of the multilayer body 10, so that the displacement due to the piezoelectric effect is small. The strain stress at is small. Thereby, occurrence of internal destruction such as cracks can be reduced.

  Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this. For example, in the above embodiment, the one dielectric layer 122 located inside the inner electrode layer 111 on the outermost layer side is formed thicker than the other dielectric layers 120. However, as shown in FIG. A plurality of dielectric layers 122 thicker than the other dielectric layers 120 may be formed. Further, for example, as shown in FIG. 4, the thickness of the dielectric layer may gradually decrease from the dielectric layer 122 located inside the innermost electrode layer 111 toward the center.

  In the above embodiment, the one having a capacitor of one circuit has been described. However, the present invention can also be applied to a capacitor array having a multi-circuit capacitor.

  DESCRIPTION OF SYMBOLS 1 ... Multilayer ceramic capacitor, 10 ... Laminated body, 110, 111, 112 ... Internal electrode layer, 120, 122 ... Dielectric layer, 121 ... Cover layer, 20 ... External electrode

Claims (2)

In a multilayer ceramic capacitor comprising a laminate in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and an external electrode formed on the outer surface of the laminate and electrically connected to the internal electrode,
A multilayer ceramic capacitor, wherein an electric field strength formed between adjacent internal electrode layers in an outer layer side portion of the multilayer body is smaller than an electric field strength formed between adjacent internal electrode layers in a central portion of the multilayer body. 2. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the dielectric between adjacent internal electrode layers is thicker in the outer layer side portion than in the central portion of the multilayer body.

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