JP2012222192A - Semiconductor integrated circuit and malfunction prevention method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide means capable of monitoring a power supply state during a real system operation.SOLUTION: A semiconductor integrated circuit comprises: an oscillator 14; a ring oscillator 11 having an oscillating frequency varying depending on a power supply voltage; an interval timer 13 measuring a predetermined determination period based on a signal of the oscillator 14; a frequency measurement counter 12 measuring an oscillating frequency oscillated by the ring oscillator 11 during the determination period; a nonvolatile memory 15 holding an upper limit value and a lower limit value of the oscillating frequency; and a voltage determination circuit 16 determining whether the oscillating frequency measured by the counter is within a range of a determination code of an upper limit voltage/lower limit voltage held by the nonvolatile memory 15 to output the determination result.

Description

  The present invention relates to prevention of malfunction in a semiconductor integrated circuit, and relates to a semiconductor integrated circuit having means for observing a power supply voltage at a predetermined portion and preventing malfunction based on the voltage data.

2. Description of the Related Art In recent years, semiconductor integrated circuits have been required to have power supply accuracy with respect to the semiconductor integrated circuit as process miniaturization, voltage reduction, and power consumption increase, and the importance of power supply monitoring is increasing.
As a power supply monitoring method for that purpose, a circuit for power supply monitoring (mainly composed of analog circuits) is provided on the substrate or in the semiconductor chip, and when the voltage falls below the set voltage range, the system is reset. However, the following problems occurred.
A semiconductor integrated circuit in recent years has a plurality of power supply sources, and if power supply voltage monitoring circuits are provided for all the power supply sources, the area increases and the chip cost increases. In addition, since it is mainly composed of analog circuits, flexibility during mask layout is reduced.

  In a semiconductor integrated circuit, power fluctuation due to unintended noise due to switching noise generated inside the chip or external electromagnetic waves is expected, and it is not sufficient to monitor the power supply of the power supply source alone. In addition, the design conditions and shipment inspection specifications for the voltage guarantee range of semiconductor integrated circuits are set in consideration of the amount of voltage drop that occurs on the chip surface, but each circuit operation largely depends on the user's operation setting state. However, it can no longer be guaranteed.

  For example, Patent Document 1 discloses a semiconductor integrated circuit and a method for measuring a power supply voltage drop amount that accurately measure a slight power supply voltage drop amount by a simple method without significantly increasing the area of the semiconductor integrated circuit. ing.

FIG. 11 is a diagram showing a configuration of the semiconductor integrated circuit disclosed in Patent Document 1. In FIG. In this technique, as shown in FIG. 11, a plurality of oscillation circuits (RingOSC) for measuring a power supply voltage drop amount are arranged on a chip surface. In this invention, a selection circuit for outputting the RingOSC clock output to the outside is provided, and this output is measured by a tester, whereby the voltage drop amount is accurately checked. This technology is also intended for use in shipping process testing.
Specifically, first, in the “non-operating state” in which the other parts except the RingOSC are not operated, the frequency characteristics with respect to the power supply voltages of all the RingOSCs arranged as shown in FIG. 12 are examined. Next, the characteristics of all RingOSCs with respect to the power supply voltage are similarly examined in the “operating state”. Based on the characteristic information examined in the “non-operating state” and “operating state”, the frequency fluctuation amount is converted into the power source fluctuation amount as shown in FIG. taking measurement.

JP 2004-146612 A

The invention of Patent Document 1 is a means for accurately screening a voltage drop amount in a chip surface in a product shipping process in a small area, monitoring a power supply state in a real system after product shipment, and a necessary fail. Safe processing (abnormality notification to the CPU or the like) cannot be performed.
However, in an actual system, the voltage supplied to the semiconductor integrated circuit is assumed to be below the guaranteed range of the product due to external factors such as noise as described above. Doing it is not enough. Therefore, a configuration capable of monitoring the power supply state during actual system operation is desired.

  One embodiment of a semiconductor integrated circuit according to the present invention includes a clock oscillator, a ring oscillator, an interval timer, a counter, a memory, and a determination unit. The clock oscillator is an oscillator that is not easily affected by voltage characteristics, such as a crystal oscillator, and can supply a clock having a stable period. The ring oscillator is an oscillator whose oscillation frequency changes according to a power supply voltage. The interval timer measures a predetermined determination period based on a signal from the clock oscillator. The counter supplies (generates) an oscillation frequency at which the ring oscillator oscillates at a predetermined time. The memory holds an upper limit value and a lower limit value of the oscillation frequency of the ring oscillator. The determination unit determines whether the oscillation frequency measured by the counter is within a range between an upper limit value and a lower limit value held in the memory, and outputs a determination result. A ring oscillator whose oscillation frequency changes according to the power supply voltage is arranged in the semiconductor integrated circuit. During operation of the semiconductor integrated circuit, the oscillation frequency of the ring oscillator is counted at a constant period to determine whether or not it is within a predetermined range. By notifying the determination result to the outside when the oscillation frequency is outside the predetermined range, it can be detected that the power supply voltage exceeds the operation guarantee range. Thereby, malfunction can be prevented.

  One aspect of the semiconductor integrated circuit malfunction prevention method according to the present invention includes a step of measuring a determination period based on a signal of a clock oscillator, and an oscillation frequency of a ring oscillator whose oscillation frequency changes according to a power supply voltage. At least a step of measuring during the determination period, a step of determining whether the measured oscillation frequency is within a range between an upper limit value and a lower limit value previously stored in a memory, and a step of outputting the determined result to the CPU carry out.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the structure which can monitor a power supply state during real system operation | movement.

It is a block diagram which shows the structural example of the power supply voltage monitoring circuit of Embodiment 1 of this invention. It is a timing chart (during normal operation) showing an operation example of Embodiment 1 of the present invention. It is a timing chart (during voltage drop operation) showing an example of operation of Embodiment 1 of the present invention. It is a device for writing the counter value of the power supply voltage monitoring circuit of the present invention into a nonvolatile memory. 3 is a voltage-oscillation frequency characteristic diagram of a ring oscillator 11. FIG. It is a figure which shows the correlation diagram of a measured value of a power supply voltage and a frequency measurement counter, and an operation allowable range. It is a block diagram which shows the detailed structural example of a power supply determination circuit. It is a block block diagram for measuring the power supply voltage of each part of a chip | tip with the power supply voltage monitoring circuit of this invention. It is a block diagram which shows the structural example of the power supply voltage monitoring circuit of Embodiment 2 of this invention. It is the timing chart which showed the operation example of Embodiment 2 of this invention. 1 is a diagram showing a configuration of a semiconductor integrated circuit disclosed in Patent Document 1. FIG. 10 is a graph showing the dependency of the period of an oscillation signal on the power supply voltage as an example of static characteristics disclosed in Patent Document 1. 6 is a graph showing the dependency of the oscillation frequency of the output signal on the power supply voltage as an example of the static characteristics disclosed in Patent Document 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

The power supply voltage monitoring means according to the present invention includes a plurality of oscillators A (for example, RingOSC) whose oscillation frequency changes according to the power supply voltage, and an oscillator B (for example, a clock having a stable cycle as compared with the plurality of oscillators A). Crystal oscillator), an interval timer that generates pulses for a predetermined period based on the output of the oscillator B, and a plurality of frequency measurement counters that count the output of the oscillator A for a predetermined period based on the output of the interval timer. By distributing the oscillator A in each part of the chip, the voltage fluctuation of each part of the chip is converted into the oscillation frequency of the oscillator A and observed by a frequency counter.
The oscillation frequency with respect to the allowable range of the operating voltage is measured in the shipping inspection, and the value is stored in the nonvolatile memory 15. As a result, the oscillation frequency of the oscillator in actual operation is compared with the data in the nonvolatile memory 15, and when the allowable range is exceeded, malfunction is prevented by stopping the operation of the semiconductor integrated circuit by means such as resetting.
Hereinafter, embodiments will be described with reference to the drawings.

Embodiment 1. FIG.
FIG. 1 is a block diagram showing a configuration example of a power supply voltage monitoring circuit according to the first embodiment of the present invention. A power supply voltage monitoring circuit 10 shown in FIG. 1 includes a ring oscillator (RingOSC) 11, a frequency measurement counter (counter) 12, an interval timer 13, an oscillator (OSC) 14, a nonvolatile memory (memory) 15, and a voltage determination circuit ( And a power supply voltage monitoring unit that converts power supply voltage fluctuations into frequency fluctuations of the ring oscillator 11 and monitors them.

The oscillation frequency of the ring oscillator 11 changes according to the power supply voltage.
The frequency measurement counter 12 is a frequency measurement counter that counts the number of pulses of the output clock of the ring oscillator 11.
The interval timer 13 sets a period (determination period) during which the frequency measurement counter 12 counts the number of pulses of the output clock of the ring oscillator 11.
The oscillator 14 is an oscillator that supplies a signal that becomes a count clock of the interval timer 13, and an oscillator that supplies a clock having a stable period as compared with the ring oscillator 11. For example, an oscillator that is not easily affected by voltage characteristics and can supply a clock having a stable period, such as a crystal oscillator, is used. The oscillator 14 is sometimes referred to as a “clock oscillator” in order to clearly distinguish it from the ring oscillator 11.
The voltage determination circuit 16 compares the value of the frequency measurement counter 12 with the determination code at a constant period based on the period of the interval timer 13 and outputs a comparison result.
In the first embodiment, a plurality of voltage monitoring units 17 including a ring oscillator 11, a frequency measurement counter 12, and a voltage determination circuit 16 are arranged in the chip surface, so that the power supply voltage of each part in the chip exceeds the guaranteed operating range. Judge that.

The nonvolatile memory 15 holds an upper limit value and a lower limit value of the oscillation frequency in the determination period of the ring oscillator 11. Specifically, in the product shipping process, the frequency of the ring oscillator 11 is measured by changing the power supply voltage value to be applied to the semiconductor integrated circuit, and the relationship between the oscillation frequency and the power supply voltage value that becomes the operation limit is obtained. An upper limit / lower limit determination code that satisfies the voltage guarantee range is calculated, and this determination code is written.
In addition to the configuration described above, the power supply voltage monitoring circuit 10 may include a selection circuit 18. The selection circuit 18 selects which voltage monitoring unit 17 outputs the value among the values of the frequency measurement counters 12 included in the plurality of voltage monitoring units 17. For example, the selection circuit 18 selects which RingOSC frequency measurement result is to be output when calculating the determination code in the product shipping process.

  By monitoring the power supply state generated in the chip surface by the output of the power supply voltage monitoring circuit 10 and notifying the CPU or the like when the voltage guaranteed range is exceeded, the safety of the system is improved. This prevents malfunction of the semiconductor integrated circuit.

  Next, the operation of the first embodiment will be described with reference to FIGS. FIG. 2 is an operation timing chart when the power supply voltage is in the operating voltage range, and FIG. 3 is an operation timing chart when the power supply voltage is lowered and the oscillation frequency of the ring oscillator 11 is lowered.

[Operation example when the power supply voltage is within the operating voltage range]
As shown in FIG. 2, the interval timer 13 outputs two outputs having different phases (output 1 and output 2) according to the output of the oscillator 14. The frequency measurement counter resets the counter in synchronization with the rising edge (T0 timing) of the output 1 of the interval timer 13, and synchronizes with the rising edge (T1 timing) of the output 2 of the interval timer 13. The count of the number of pulses of the output clock is started, the count is stopped at the falling edge (T2 timing) of the output 1 of the interval timer 13, and the counter value is held until the timing of the next rising edge of the interval timer 13.
The voltage determination circuit 16 compares the count value measured by the frequency measurement counter 12 with the determination code during the period from the falling edge (timing of T3) of the output 2 of the interval timer 13 to the rising edge of the output 1 of the interval timer 13. I do.
In this case, with respect to the upper limit “10” and lower limit “5” of the determination code, the count value is “6”, so the voltage determination circuit output does not change.

[Operation example when the power supply voltage falls below the operating voltage range]
FIG. 3 shows an example in which a voltage drop occurs at the timing T4 and the oscillation frequency of the oscillator 14 is lowered correspondingly. In this case, the frequency measurement counter starts counting at the timing T1 ′ and stops counting at the timing T2 ′. However, since the oscillation frequency of the ring oscillator 11 has decreased, the count value becomes “4” and the lower limit of the determination code. Below. Therefore, the output of the voltage determination circuit 16 changes at the timing of T3 ′, and notifies the outside that the power supply voltage has exceeded the allowable range.

Next, a method for setting the upper limit / lower limit voltage value of the operation guarantee range of the power supply voltage monitoring circuit 10 according to the first embodiment will be described with reference to FIGS.
In the circuit configuration shown in FIG. 4, the frequency characteristics (= for frequency measurement) with respect to the power supply voltage of each of the ring oscillators 11 arranged in the chip surface of the semiconductor integrated circuit 100 using the measuring device 50 used in the product shipping process. The value of the counter 12) is measured. The ring oscillator 11 has a characteristic in which the frequency changes according to the power supply voltage as shown in FIG. By this measurement, as shown in FIG. 6, a determination code (upper limit determination code / lower limit determination code) for the upper limit / lower limit voltage of the operation guarantee range of the product is obtained. This determination code is written into the nonvolatile memory 15 shown in FIG. 4 using the measuring device 50 in the shipping process. By selecting one of the plurality of frequency measurement counters 12 by the selection circuit 18, it becomes possible to measure the frequency measurement of each of the plurality of ring oscillators 11. FIG. 4 shows the ring oscillator 11 and the frequency measurement counter 12 required in the measurement process, and the voltage determination circuit 16 is omitted.

FIG. 7 is a block diagram illustrating a detailed configuration example of the voltage determination circuit. As shown in FIG. 7, the frequency measurement counter 12 of FIG. 4 performs a counting operation at a fixed period set by the interval timer 13 of FIG. 4, and the count value captured at a fixed period is obtained in FIG. A comparison is made with the determination code of the upper limit voltage / lower limit voltage indicating the voltage guarantee range, and if it is out of the decision code range (= out of the voltage guarantee range), a pulse output (= abnormal notification) is made to the CPU.
A plurality of voltage monitoring units 17 including the ring oscillator 11, the frequency measurement counter 12 shown in FIG. 4 and the voltage determination circuit 16 shown in FIG. 7 are arranged in the internal power supply region 81 in the chip surface as shown in FIG. Although not particularly illustrated, the internal power supply area 81 is appropriately provided with functional blocks including a CPU and the like. The oscillator 14 shown in FIGS. 4 and 8 is configured by a crystal oscillator or the like that is disposed in a stable external power supply region 82 and that can output a stable clock regardless of the power supply state. Although not particularly illustrated, the external power supply region 82 is provided with I / O pads to which various I / O pins are connected, input / output circuits (buffers, etc.), power supply circuits, and the like. As a result, the power supply state generated in the chip surface can be monitored, and when the voltage guarantee range is exceeded, an abnormality notification to the CPU or the like can be performed.

According to the power supply voltage monitoring unit of the first embodiment of the present invention, the following effects can be obtained.
Although there is a method of monitoring the power supply using an analog circuit such as a comparator, this embodiment can be configured only with a logic circuit, and can realize a power supply voltage monitoring means with a relatively small area. In addition, since it can be configured with a logic circuit, the layout is easier than a method using an analog circuit.
Power supply can be monitored using a logic circuit, and the power supply state can be monitored during actual system operation. Further, the voltage range for monitoring can be arbitrarily set according to the position of each monitoring circuit in the shipping process, and can be set flexibly according to the characteristics of the product.
By installing the power supply voltage monitoring circuit 10 in a microcomputer, the detection signal can be used to immediately trigger resets, interrupts, etc., thereby expanding the applicability of preventing malfunctions and improving system safety. Is possible.

Embodiment 2. FIG.
FIG. 9 is a block diagram illustrating a configuration example of the power supply voltage monitoring circuit according to the second embodiment of the present invention. In the power supply voltage monitoring circuit 20 of the present embodiment, a configuration example including three combinations of the ring oscillators 11-1, 11-2, and 11-3 and the frequency measurement counters 12-1, 12-2, and 12-3. However, the number is not limited to three, and up to n can be arranged if n <(count time / determination time) is satisfied.
In the present embodiment, the voltage determination circuit 26 is shared by a plurality of sets of the ring oscillator 11 and the frequency measurement counter 12. Therefore, a data selection circuit 28 for switching the output of each frequency measurement counter 12 and an address generation circuit 29 for sequentially reading the determination code from the nonvolatile memory 15 are added.

Next, the operation of the second embodiment will be described. FIG. 10 shows a timing chart of the present embodiment. In the first embodiment, the plurality of voltage determination circuits 16 determine the value of the frequency measurement counter 12 at the same timing. However, in the second embodiment, one voltage determination circuit 26 includes a plurality of frequency measurement counters 12-. The values 1 to 12-3 are determined at different timings. Therefore, the timing of T0 shown in the first embodiment is represented by Tx0, the timing of T1 is represented by Tx1, and the timings of T2 and T3 are represented by Tx2 and Tx3 (x = 1, 2, 3), respectively. The operations for resetting each frequency measurement counter at the timing of Tx0, starting the count at the timing of Tx1, stopping the count at the timing of Tx2, and determining at the timing of Tx3 are the same as in the first embodiment.
However, since the determination code input to the voltage determination circuit 26 needs to be switched according to timing, the determination code is fetched in synchronization with the rising edge of the output of the oscillator 14.

  According to the power supply voltage monitoring means of the second embodiment of the present invention, the voltage determination circuit 26 connected to each frequency measurement counter 12 can be shared, so that it can be configured with a smaller area than the first embodiment. it can.

As described above, the power supply voltage monitoring means according to each of the above embodiments of the present invention monitors the power supply voltage by arranging a plurality of ring oscillators whose oscillation frequency changes according to the power supply voltage in the semiconductor integrated circuit. And means for measuring the frequency of the ring oscillator 11, means for holding a determination code for determining the frequency, and means for determining the voltage.
Means for determining the frequency are the above-described ring oscillator 11, the frequency measurement counter 12, the interval timer 13 for counting the frequency measurement counter 12 at a constant period, and the clock of the interval timer 13. This is realized by the oscillator 14 which is not easily affected by the voltage characteristics.

The means for holding the determination code measures the frequency by changing the power supply voltage value to be applied to the ring oscillator 11 in the product shipping process, and determines the oscillation frequency (= count value of the frequency measuring counter 12) and the power supply voltage value. The upper limit / lower limit determination code that is the voltage guarantee range of the product is calculated, and this determination code is realized by the process of writing in the nonvolatile memory 15.
The voltage determination means uses voltage determination circuits 16 and 26 that compare the value of the frequency measurement counter 12 and the determination code recorded in the non-volatile memory 15 at a constant period based on the period (determination period) of the interval timer 13. Realize.
By disposing a plurality of combinations of the ring oscillator 11, the frequency measurement counter 12, and the voltage monitoring unit 17 including the voltage determination circuit 16, or the ring oscillator 11 and the frequency measurement counter 12 in the chip surface, the chip surface The safety of the system can be improved by monitoring the power supply state generated in the system and notifying the CPU or the like when the voltage guarantee range is exceeded.

  In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

10, 20 Power supply voltage monitoring circuit 11, 11-1, 11-2, 11-3 Ring oscillator (RingOSC)
12, 12-1, 12-2, 12-3 Frequency measurement counter (counter)
13 Interval timer 14 Oscillator (OSC)
15 Nonvolatile memories 16 and 26 Voltage determination circuit 17 Voltage monitoring unit 28 Data selection circuit 29 Address generation circuit 50 Measuring device 81 Internal power supply 82 External power supply 100 Semiconductor integrated circuit

Claims (8)

A clock oscillator,
A ring oscillator whose oscillation frequency changes according to the power supply voltage;
An interval timer for supplying a predetermined determination period based on the signal of the clock oscillator;
A counter that measures an oscillation frequency at which the ring oscillator oscillates during the determination period;
A memory for holding an upper limit value and a lower limit value of the oscillation frequency;
A semiconductor integrated circuit comprising: a determination unit that determines whether the oscillation frequency measured by the counter is within a range between an upper limit value and a lower limit value held by the memory and outputs a determination result. A plurality of power supply monitoring units having the ring oscillator, the counter, and the determination unit are provided in the own device,
The memory holds an upper limit value and a lower limit value according to the ring oscillator that each power supply monitoring unit has,
The semiconductor integrated circuit according to claim 1, wherein the determination units included in the plurality of power supply monitoring units perform the determination at a cycle of the determination period.   The semiconductor integrated circuit according to claim 2, wherein the power supply monitoring unit is arranged at a plurality of positions on an internal power supply. A plurality of combinations of the ring oscillator and the counter in its own device,
Each combination of the ring oscillator and the counter is configured so that the end of the determination period is at a different timing,
The memory holds an upper limit value and a lower limit value according to each ring oscillator,
The semiconductor integrated circuit according to claim 1, wherein the determination unit determines values of a plurality of counters at different timings.   5. The semiconductor integrated circuit according to claim 4, wherein the combination of the ring oscillator and the counter is arranged at a plurality of positions on an internal power source.   6. The semiconductor integrated circuit according to claim 1, wherein the determination unit outputs the determination result to a CPU.   The memory is applied as the upper limit value and the lower limit value by changing a power supply voltage value to the ring oscillator in a product shipping process, and based on the oscillation frequency measured by the counter, The semiconductor integrated circuit according to claim 1, wherein the calculated value is a calculated value. A method for preventing malfunction of a semiconductor integrated circuit,
Based on the clock oscillator signal, measure the judgment period,
Measure the oscillation frequency of the ring oscillator whose oscillation frequency changes according to the power supply voltage during the determination period,
Determine whether the measured oscillation frequency is within the range between the upper limit value and the lower limit value stored in the memory in advance,
A malfunction prevention method for outputting the determined result to the CPU.

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