JP2012221990A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with a MIM capacitor, in which a via hole is not essential and which can achieve large capacitor capacitance though in a small chip size and has a high degree of freedom in setting potentials of an inner electrode and an outer electrode of the MIM capacitor.SOLUTION: A semiconductor device 2 includes a semiconductor chip 10, an electronic circuit formed on a surface 10T of the semiconductor chip 10, and a MIM capacitor 20 formed on at least one lateral face 10L, 10R of the semiconductor chip 10 and having a laminate structure of an inner electrode 21, an insulation film 22 and an outer electrode 23 from the semiconductor chip 10 side. The semiconductor device 2 includes surface electrodes 30 planarly extending on the MIM capacitor 20 formed from the surface 10T of the semiconductor chip 10 to the lateral faces 10L, 10R to contact the inner electrode 21 of the MIM capacitor 20.

Description

  The present invention relates to a semiconductor device having a MIM (Metal Insulator Metal) capacitor and a method for manufacturing the same.

The MIM capacitor has a laminated structure of an electrode (Metal) / an insulating film (Insulator) / an electrode (Metal).
In a conventional semiconductor device having an MIM capacitor, as shown in FIG. 7 of Patent Document 3, an MIM capacitor having a laminated structure of an internal electrode, an insulating film, and an external electrode is formed on one surface of a semiconductor substrate. It has a structure.
For example, in a radio frequency (RF) device, a large-capacity MIM capacitor is required to form a high frequency short circuit.
However, in the conventional structure described above, since the large-capacity MIM capacitor occupies the substrate area, it is difficult to reduce the size of the device. Considering the reduction in device size, the capacity of the capacitor is limited. When a large capacity capacitor is absolutely necessary for the circuit configuration, the wiring is once drawn out from the integrated circuit and a chip capacitor etc. is externally attached. It corresponds by doing.

  Patent Documents 1 and 2 propose a semiconductor device in which a MIM capacitor is provided inside a via hole penetrating a semiconductor substrate (FIG. 1 of Patent Document 1, FIG. 1 of Patent Document 2, and the like). In such a configuration, the area occupied by the substrate of the MIM capacitor can be reduced, and a large capacity can be obtained while miniaturizing the chip.

Patent Document 3 proposes a semiconductor device in which an MIM capacitor is provided on at least a side surface or a back surface of a semiconductor chip (Claim 1, FIG. 1, and FIG. 2). In such a configuration, the area occupied by the substrate of the MIM capacitor can be reduced, and a large capacity can be obtained while miniaturizing the chip.
In the method of manufacturing a semiconductor device described in Patent Document 3, a step of etching a region to be a scribe line on the main surface of the semiconductor substrate with a certain depth to form a recess, and an electron formed on the main surface of the semiconductor substrate Forming a part of the circuit wiring up to the recess, protecting the main surface of the semiconductor substrate, dicing the semiconductor substrate along the scribe line and dividing it into semiconductor chips, and internal electrodes on the side and back surfaces of the semiconductor chip A step of depositing an insulating film on the internal electrode, a step of forming an external electrode on the insulating film, and a step of die-bonding the semiconductor chip on the lead frame and electrically connecting to the outside. (Claim 5 and FIG. 3).

Japanese Patent Laid-Open No. 03-99461 JP 11-195751 A JP 07-106515 A

  The configurations of Patent Documents 1 and 2 cannot be applied to a semiconductor chip having no via hole. In the configurations of Patent Documents 1 and 2, the maximum capacity of the MIM capacitor that can be formed in the via hole is determined by the inner area of the via hole. For this reason, when a larger capacity is required (for example, a smoothing capacitor requires as large a capacity as possible), it is necessary to extend the MIM capacitor on the substrate surface. Therefore, it is difficult to reduce the size of the chip.

  In each of the semiconductor devices of Patent Documents 1 to 3, the back surface side is mounted on a semiconductor package or the like. In these semiconductor devices, the back side is fixed to the ground potential, the input voltage to the capacitor can only be set to the ground potential, and can only be used on the output side of the device. When a capacitor is required on the input side of the device, an external chip capacitor or the like is required to prevent the chip from becoming large.

The semiconductor device of the present invention is
A semiconductor chip;
An electronic circuit formed on the surface of the semiconductor chip;
An MIM (Metal Insulator Metal) capacitor formed on at least one side surface of the semiconductor chip and having a laminated structure of an internal electrode, an insulating film, and an external electrode from the semiconductor chip side;
The semiconductor chip includes a surface electrode that extends in a plane from the surface of the semiconductor chip onto the MIM capacitor formed on the side surface and contacts the internal electrode of the MIM capacitor.

In the semiconductor device of the present invention, an MIM capacitor is formed on at least one side surface of the semiconductor chip. Therefore, in the semiconductor device of the present invention, a via hole is not essential, a large MIM capacitor area can be obtained without the MIM capacitor occupying the surface of the semiconductor chip, and a large capacitor capacity can be realized even with a small chip size. it can.
Furthermore, the semiconductor device of the present invention includes a surface electrode that extends in a planar manner from the surface of the semiconductor chip onto the MIM capacitor formed on the side surface of the semiconductor chip and contacts the internal electrode of the MIM capacitor. In such a configuration, since an arbitrary potential can be applied to the surface electrode or the external electrode of the MIM capacitor, the degree of freedom in setting the potentials of the internal electrode and the external electrode of the MIM capacitor is high.

  According to the present invention, a semiconductor having a MIM capacitor, which does not require a via hole, can realize a large capacitor capacity even in a small chip size, and has a high degree of freedom in setting potentials of an internal electrode and an external electrode of the MIM capacitor. An apparatus can be provided.

It is principal part sectional drawing which shows the one aspect | mode of the semiconductor device which concerns on 1st Embodiment. It is principal part sectional drawing which shows the other aspect of the semiconductor device which concerns on 1st Embodiment. FIG. 1B is a manufacturing process diagram of the semiconductor device of FIG. 1B. FIG. 1B is a manufacturing process diagram of the semiconductor device of FIG. 1B. FIG. 1B is a manufacturing process diagram of the semiconductor device of FIG. 1B. FIG. 1B is a manufacturing process diagram of the semiconductor device of FIG. 1B. It is principal part sectional drawing which shows the example of mounting of the semiconductor device of FIG. 1B. FIG. 10 is a cross-sectional view of a principal part showing another example of mounting the semiconductor device of FIG. 1B. FIG. 10 is a cross-sectional view of a principal part showing another example of mounting the semiconductor device of FIG. 1B. It is principal part sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. FIG. 5 is a manufacturing process diagram of the semiconductor device of FIG. 4. FIG. 5 is a manufacturing process diagram of the semiconductor device of FIG. 4. FIG. 5 is a manufacturing process diagram of the semiconductor device of FIG. 4. FIG. 5 is a manufacturing process diagram of the semiconductor device of FIG. 4.

“First Embodiment”
The configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. 1A and 1B are main part cross-sectional views showing aspects of the semiconductor device according to the present embodiment. 2A to 2D are manufacturing process diagrams of the semiconductor device of FIG. 1B. In order to facilitate visual recognition on the drawings, the scale and position of each member are appropriately different from the actual ones and simplified.

The semiconductor devices 1A and 1B shown in FIGS. 1A and 1B are obtained by forming at least one MIM (Metal Insulator Metal) capacitor 20 on a semiconductor chip 10.
The semiconductor chip 10 is an electronic circuit in which semiconductor elements, wirings, and the like are formed on a surface 10T (upper surface in the drawing) of a semiconductor substrate 11.

In the embodiment shown in FIG. 1A, the MIM capacitor 20 is formed on one side surface 10 </ b> L (the left side surface in the drawing) of the semiconductor chip 10.
In the embodiment shown in FIG. 1B, MIM capacitors 20 are formed on two side surfaces 10L (the left side surface in the drawing) and 10R (the right side surface in the drawing) of the semiconductor chip 10.
In any embodiment, the MIM capacitor 20 has a laminated structure of an internal electrode 21, an insulating film (capacitance film) 22, and an external electrode 23 from the semiconductor chip 10 side.

  The semiconductor devices 1 </ b> A and 1 </ b> B are provided with a surface electrode 30 that extends in a planar manner from the surface 10 </ b> T of the semiconductor chip 10 onto the MIM capacitor 20 formed on the side surface and contacts the internal electrode 21 of the MIM capacitor 20. . The number of surface electrodes 30 corresponds to the number of MIM capacitors 20 formed on the side surface of the semiconductor chip 10.

As shown in the figure, the internal electrode 21 of the MIM capacitor 20 is bent in an L shape in cross section across the side surface 10L or the side surface 10R of the semiconductor chip 10 and the lower surface of the surface electrode 30 protruding from the semiconductor chip 10. Is formed. On the internal electrode 21, an insulating film 22 having an L-shaped cross section is stacked along the shape of the internal electrode 21, and a flat external electrode 23 is stacked thereon.
The laminated pattern of the internal electrode 21 / insulating film 22 / external electrode 23 may be any design as long as the internal electrode 21 is in contact with the surface electrode 30 and the external electrode 23 is not in contact with the surface electrode 30.

The semiconductor substrate 11 is not particularly limited and includes a GaAs substrate.
If the main component of the internal electrode 21 and the external electrode 23 is an electroconductive metal, there will be no restriction | limiting in particular, TiPtAu, TiAu, Al, etc. will be mentioned. The main components of the internal electrode 21 and the external electrode 23 may be the same or non-identical. The thicknesses of the internal electrode 21 and the external electrode 23 are not particularly limited, and are preferably about 500 to 10,000 mm.
The insulating film (capacitance film) 22 is not particularly limited, and examples thereof include a SiN film. The thickness of the insulating film is not particularly limited, and is set to a thickness that provides a desired capacity density within a range of about 750 to 5000 mm. For example, in the case of a SiN film having a thickness of 1000 mm and an area size of 100 μm × 100 μm, a capacity of about 7 pF can be obtained.

  With reference to FIGS. 2A to 2D, an example of a method for manufacturing the semiconductor device 1B will be described.

[Step (1)]
First, a semiconductor substrate 11 on which a plurality of semiconductor chips 10 can be formed is prepared.
An electronic circuit including semiconductor elements and wirings is formed on the surface 10T of each chip formation region of the semiconductor substrate 11 described above. Thereafter, if necessary, the back surface side of the semiconductor substrate 11 can be partially removed to make the substrate 11 thinner. At this time, the surface 10T of the semiconductor substrate 11 may be held on a support substrate or the like.

[Step (2)]
Next, as shown in FIG. 2A, the surface electrodes 30 of the plurality of semiconductor devices 1B are patterned on the surface 10T of the semiconductor substrate 11 so that the surface electrodes 30 of the adjacent semiconductor chips 10 are connected to each other.

[Step (3)]
Next, as shown in FIG. 2B, the semiconductor substrate 11 is etched from the back side while leaving the front electrode 30, and the semiconductor substrate 11 is divided into a plurality of semiconductor chips 10 (etch cut).

[Step (4) to Step (5)]
Next, as shown in FIGS. 2B to 2D, MIM capacitors 20 are formed on the side surfaces 10L and 10R of the plurality of semiconductor chips 10 (step (4)), and the surface electrodes 30 of the semiconductor chips 10 adjacent to each other are separated (step (4)). Step (5)).

In the illustrated example, steps (4) to (5) are performed as follows.
By sputtering the material of the internal electrode 21 from the back surface 10B side to the semiconductor substrate 11 divided into a plurality of semiconductor chips 10, the back surface 10B of each semiconductor chip 10, the side surfaces 10L, 10R of each semiconductor chip 10, and The internal electrode 21 is formed on the exposed surface of the front electrode 30 on the back surface 10B side, and the insulating film 22 is further formed in a similar pattern thereon.
Next, a photoresist film having a predetermined pattern is formed on the back surface 10B side of the semiconductor substrate 11, and the external electrode 23 is formed into a pattern by sputtering the material of the external electrode 23 using this as a mask. At this time, the external electrode 23 is pattern-formed only on the side surfaces 10L and 10R of each semiconductor chip 10.
Thereafter, the internal electrode 21 and the insulating film 22 on the back surface 10B of the semiconductor substrate 11 and the laminated portion of the surface electrode 30, the internal electrode 21 and the insulating film 22 between the adjacent semiconductor chips 10 are etched away.
The film formation and patterning of each layer in step (4) to step (5) can be changed as appropriate.
The semiconductor device 1B is manufactured as described above.

  The semiconductor device 1B can be mounted on a ceramic package such as a ceramic as shown in FIGS. 3A to 3C. 3A to 3C, the same components are denoted by the same reference numerals.

In any of the examples shown in FIGS. 3A to 3C, the semiconductor device 1B is mounted on the inner bottom surface of the semiconductor package 50 via the insulating solder 51 (the insulating solder 51 is not shown in FIG. 3C). Lead wires 61 and 62 are connected to the two MIM capacitors 20 formed on the side surfaces 10L and 10R of the semiconductor device 1B, respectively. As the lead wires 61 and 62, a copper wire plated with gold can be used.
In any example, the lead wires 61 and 62 are electrically connected to the surface electrode 30 or the external electrode 23 of the MIM capacitor 20.

In the example shown in FIG. 3A, a lead wire 61 is inserted into the semiconductor package 50 from the right side of the figure, and the tip thereof is crimped to the external electrode 23 of the MIM capacitor 20 formed on the right side 10R of the semiconductor chip 10.
A lead wire 62 is inserted into the semiconductor package 50 from the left side in the figure, and the surface electrode 30 and the lead wire 62 that are in contact with the internal electrode 21 of the MIM capacitor 20 formed on the left side 10L in the figure of the semiconductor chip 10 are bonded by wire bonding. It is connected.

In the example shown in FIG. 3B, the internal electrode 52 is formed on the right inner wall surface of the semiconductor package 50 in the drawing, and the leading end of the lead wire 61 inserted into the semiconductor package 50 from the right side of the drawing is crimped to the internal electrode 52. . The external electrode 23 of the MIM capacitor 20 formed on the right side 10 </ b> R of the semiconductor device 1 </ b> B is in contact with the internal electrode 52.
A lead wire 62 is inserted into the semiconductor package 50 from the left side in the figure, and a tip thereof is crimped to the external electrode 23 of the MIM capacitor 20 formed on the left side 10L (left side in the figure) of the semiconductor chip 10.

In the example shown in FIG. 3C, a lead wire 61 is inserted into the semiconductor package 50 from the right side in the figure, and the tip thereof is crimped to the external electrode 23 of the MIM capacitor 20 formed on the right side 10R in the figure of the semiconductor chip 10. .
A lead wire 62 is inserted into the semiconductor package 50 from the left side in the figure, and a tip thereof is crimped to the external electrode 23 of the MIM capacitor 20 formed on the left side 10L (left side in the figure) of the semiconductor chip 10.

  The conductive connection structure between the lead wires 61 and 62 and the surface electrode 30 or the external electrode 23 of the MIM capacitor 20 can be appropriately changed in design.

In the semiconductor devices 1A and 1B of the present embodiment, the MIM capacitor 20 is formed on the side surface 10L of the semiconductor chip 10, or 10L and 10R.
In the present embodiment, the MIM capacitor 20 is formed on one or two side surfaces of the semiconductor chip 10, but the MIM capacitor 20 may be provided on three or more side surfaces.
In the semiconductor devices 1A and 1B of the present embodiment, a via hole is not essential, and a large capacitor capacity can be realized even with a small chip size.

When the MIM capacitor is formed in the via hole as in Patent Documents 1 and 2 listed in “Background Art”, for example, when the substrate thickness is 100 μm, the inner area of the straight via hole having a radius of 50 μmφ is If it is 15700 μm ² and there are six via holes in the semiconductor chip, 105975 μm ² is the maximum MIM capacitor area.
In contrast, when forming a MIM capacitor on the side surface of the semiconductor chip, for example, chip size 1000 .mu.m × 1000 .mu.m, with the conditions of the substrate thickness 100 [mu] m, may be the area of the MIM capacitor to the maximum 400000μm ^2.
In the configuration of this embodiment, the MIM capacitor 20 does not occupy the surface of the semiconductor chip 10 while realizing such a large capacitance, and the substrate occupation area of the MIM capacitor 20 is reduced as compared with the configuration using via holes. it can.
The semiconductor devices 1A and 1B of the present embodiment can be applied to a semiconductor chip having no via hole and have a wide application range.

Furthermore, the semiconductor devices 1 </ b> A and 1 </ b> B of the present embodiment extend planarly from the surface 10 </ b> T of the semiconductor chip 10 onto the MIM capacitor 20 formed on the side surface of the semiconductor chip 10, and contact the internal electrode 21 of the MIM capacitor 20. A surface electrode 30 is provided. In this configuration, as illustrated in FIGS. 3A to 3C, an arbitrary potential is applied to the surface electrode 30 or the external electrode 23 that is electrically connected to the internal electrode 21 of the MIM capacitor 20 via the lead wires 61 and 62. Therefore, the degree of freedom in setting the potentials of the internal electrode 21 and the external electrode 23 of the MIM capacitor 20 is high. Therefore, in this embodiment, the back side is not fixed to the ground potential as in Patent Documents 1 to 3 listed in the “Background Art” section, and can be used on either the input side or the output side of the device.
In the semiconductor devices 1A and 1B of the present embodiment, an external chip capacitor or the like is unnecessary, and the device can be reduced in size.

  As described above, according to the present embodiment, the MIM capacitor 20 is provided, a via hole is not essential, and a large capacitor capacity can be realized even with a small chip size. The internal electrode 21 and the external electrode of the MIM capacitor 20 can be realized. The semiconductor devices 1A and 1B having a high degree of freedom in setting the potential of 23 can be provided.

“Second Embodiment”
The configuration of the semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a fragmentary cross-sectional view of the semiconductor device according to the present embodiment. 5A to 5D are manufacturing process diagrams of the semiconductor device of FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the first embodiment, the aspect in which the MIM capacitor is formed on at least one side surface of the semiconductor chip 10 has been described. However, the MIM capacitor may be formed on at least one side surface and the back surface of the semiconductor chip 10.

In the semiconductor device 2 shown in FIG. 4, from the MIM capacitor 20 formed from one side surface 10 </ b> L (left side surface in the drawing) to the back surface 10 </ b> B of the semiconductor chip 10 and from the other side surface 10 </ b> R (right side surface in the drawing) of the semiconductor chip 10. MIM capacitors 20 (two MIM capacitors 20 in total) formed across the back surface 10B are formed. An opening 25 is formed between the two MIM capacitors 20.
The laminated structure of the MIM capacitor 20 is the same as that of the first embodiment.

Also in the present embodiment, two surface electrodes 30 that extend in a planar manner from the surface 10T of the semiconductor chip 10 onto the MIM capacitors 20 formed on the side surfaces 10L and 10R and are in contact with the internal electrodes 21 of the MIM capacitor 20 are provided. It has been. The number of surface electrodes 30 corresponds to the number of MIM capacitors 20 formed on the side surface of the semiconductor chip 10.
The connection structure between the MIM capacitor 20 formed on the side surfaces 10L and 10R of the semiconductor chip 10 and the surface electrode 30 is the same as in the first embodiment.

  An example of a method for manufacturing the semiconductor device 2 will be described with reference to FIGS. 5A to 5D.

[Step (1)]
First, a semiconductor substrate 11 on which a plurality of semiconductor chips 10 can be formed is prepared.
An electronic circuit including semiconductor elements and wirings is formed on the surface 10T of each chip formation region of the semiconductor substrate 11 described above. Thereafter, if necessary, the back surface side of the semiconductor substrate 11 can be partially removed to make the substrate 11 thinner. At this time, the surface of the semiconductor substrate 11 may be held on a support substrate or the like.

[Step (2)]
Next, as shown in FIG. 5A, the surface electrodes 30 of the plurality of semiconductor devices 2 are formed on the surface 10T of the semiconductor substrate 11 so that the surface electrodes 30 of the adjacent semiconductor chips 10 are connected to each other.

[Step (3)]
Next, as shown in FIG. 5B, the semiconductor substrate 11 is etched from the back side while leaving the front electrode 30, and the semiconductor substrate 11 is divided into a plurality of semiconductor chips 10 (etch cut).

[Step (4) to Step (5)]
Next, as shown in FIGS. 5B to 5D, the MIM capacitors 20 are respectively formed on the plurality of semiconductor chips 10 (step (4)), and the surface electrodes 30 of the semiconductor chips 10 adjacent to each other are separated (step (5)). ).

In the illustrated example, steps (4) to (5) are performed as follows.
By sputtering the material of the internal electrode 21 from the back surface 10B side to the semiconductor substrate 11 divided into a plurality of semiconductor chips 10, the back surface 10B of each semiconductor chip 10, the side surfaces 10L, 10R of each semiconductor chip 10, and The internal electrode 21 is formed on the exposed surface of the front electrode 30 on the back surface 10B side, and the insulating film 22 is further formed in a similar pattern thereon.
Next, a photoresist film having a predetermined pattern is formed on the back surface 10B side of the semiconductor substrate 11, and the external electrode 23 is formed into a pattern by sputtering the material of the external electrode 23 using this as a mask. At this time, the external electrode 23 having the opening 25 is formed in a pattern on the side surfaces 10L and 10R and the back surface 10B of each semiconductor chip 10.
Thereafter, the laminated portion of the internal electrode 21 and the insulating film 22 in the region of the opening 25 on the back surface 10B of the semiconductor substrate 11 and the laminated portion of the surface electrode 30, the internal electrode 21 and the insulating film 22 between the adjacent semiconductor chips 10 are formed. Etch away.
The film formation and patterning of each layer in step (4) to step (5) can be changed as appropriate.
The semiconductor device 2 is manufactured as described above.

  In the semiconductor device 2 of the present embodiment, the MIM capacitor 20 is formed on at least one side surface and the back surface of the semiconductor chip 10. Therefore, also in this embodiment, a via hole is not essential, and a large capacitor capacity can be realized even with a small chip size.

As described in the first embodiment, when the MIM capacitor is formed in the via hole as in Patent Documents 1 and 2 cited in “Background Art”, for example, when the substrate thickness is 100 μm, the radius is 50 μmφ. The inner area of each straight via hole is 15700 μm ² , and when there are six via holes in the semiconductor chip, 105975 μm ² is the maximum MIM capacitor area.
For example, when the MIM capacitor is formed on the entire side surface and back surface of the semiconductor chip under the conditions of a chip size of 1000 μm × 1000 μm and a substrate thickness of 100 μm, the area of the MIM capacitor can be made up to 1400000 μm ² at maximum. This area corresponds to about 12 times the area of the conventional configuration using via holes. In the configuration of this embodiment, the MIM capacitor 20 does not occupy the surface of the semiconductor chip 10 while realizing such a large capacity, and the area occupied by the substrate of the MIM capacitor 20 is reduced as compared with the configuration using via holes. it can.

Also in the semiconductor device 2 of the present embodiment, the planar extension extends from the surface 10T of the semiconductor chip 10 to the MIM capacitor 20 formed on the side surfaces 10L and 10R of the semiconductor chip 10, and contacts the internal electrode 21 of the MIM capacitor 20. The surface electrode 30 is provided. In this configuration, as in the first embodiment, an arbitrary potential can be applied to the surface electrode 30 or the external electrode 23 connected to the internal electrode 21 of the MIM capacitor 20 via a lead wire or the like. The degree of freedom in setting the potentials of the 20 internal electrodes 21 and the external electrode 23 is high. Therefore, also in this embodiment, the back side can be used for both the input side and the output side of the device without being fixed to the ground potential as in Patent Documents 1 to 3 mentioned in the “Background Art” section.
Also in the semiconductor device 2 of the present embodiment, an external chip capacitor or the like is unnecessary, and the device can be reduced in size.

  As described above, according to this embodiment, the MIM capacitor 20 is provided, a via hole is not essential, and a large capacitor capacity can be realized even with a small chip size. The internal electrode 21 and the external electrode of the MIM capacitor 20 can be realized. Thus, the semiconductor device 2 having a high degree of freedom in setting the potential 23 can be provided.

"Design changes"
The present invention is not limited to the above embodiment, and can be appropriately modified within a range not departing from the gist of the present invention.

1A, 1B, 2 Semiconductor device 10 Semiconductor chip 10T Front surface 10B Back surface 10L, 10R Side surface 11 Semiconductor substrate 20 MIM capacitor 21 Internal electrode 22 Insulating film 23 External electrode 30 Surface electrode 50 Semiconductor packages 61, 62 Lead wire

Claims (5)

A semiconductor chip;
An electronic circuit formed on the surface of the semiconductor chip;
An MIM (Metal Insulator Metal) capacitor formed on at least one side surface of the semiconductor chip and having a laminated structure of an internal electrode, an insulating film, and an external electrode from the semiconductor chip side;
A semiconductor device comprising a surface electrode extending planarly from above the surface of the semiconductor chip onto the MIM capacitor formed on the side surface and in contact with the internal electrode of the MIM capacitor.   The semiconductor device according to claim 1, wherein the MIM capacitor is formed across at least one of the side surfaces of the semiconductor chip and the back surface.   The semiconductor device according to claim 1, wherein a lead wire is electrically connected to the surface electrode or the external electrode of the MIM capacitor. A method for manufacturing a semiconductor device according to claim 1,
Preparing a semiconductor substrate capable of forming a plurality of the semiconductor chips (1);
Forming the surface electrodes of the plurality of semiconductor devices on the surface of the semiconductor substrate so that the surface electrodes of the semiconductor chips adjacent to each other are connected to each other;
Etching the semiconductor substrate from the back side while leaving the front surface electrode, and dividing the semiconductor substrate into a plurality of the semiconductor chips;
Forming the MIM capacitor on the plurality of semiconductor chips (4);
A method of manufacturing a semiconductor device, comprising sequentially separating (5) the surface electrodes of the semiconductor chips adjacent to each other. Step (5)
Forming the internal electrode from the back side of the semiconductor substrate;
The manufacturing method according to claim 4, further comprising: forming the insulating film from the back side of the semiconductor substrate; and forming the external electrode from the back side of the semiconductor substrate.

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