JP2012243237A - Method for improving reliability in activation and shortening post time and computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an activation method of a computer for compatibly stabilizing an operation and shortening POST time.SOLUTION: A BIOS_ROM 33 stores a first POST code and a second POST code for ending processing in a shorter time period than the first POST code. After a processor 11 is reset and before loading of an OS is started, an opening sensor 39 detects presence/absence of opening of a cover lid and determines a possibility that physical access is performed to an internal device. The first POST code is executed when it is determined that the possibility of the physical access is high, and the second POST code is executed when it is determined that the possibility of the physical access is low.

Description

  The present invention relates to a technique for achieving both shortening of POST time and stability of operation when starting a computer.

  When the computer is turned on, the BIOS code stored in the BIOS_ROM is executed before the operating system (OS) is loaded into the main memory. The BIOS code includes a POST (Power On Self Test) code that detects a device mounted on the computer and performs inspection and initialization. When reset, the processor (CPU) executes the POST code before starting to load the OS.

  Patent Document 1 discloses a fast startup method for ending POST in a short time. The user disables fast startup and then opens the system housing to change the configuration. When it is subsequently powered on, fast startup is enabled. At the first startup after the current startup is enabled, normal startup is executed and the contents set at that time are stored in the BIOS chip. If it is not the first startup, the POST time is shortened by setting the parameter stored in the BIOS chip in the register of the controller.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a method of quickly stopping a platform restart that is performed in order for the OS to update a registry key or restart the OS environment when new software is loaded. This document describes that when it is detected that there is no hardware change for the platform, the entire platform is not restarted or all hardware is not reinitialized. Also, Windows (registered trademark) has a function called Fast Boot, which refers to previous boot status and hardware change information, and simplifies initialization by BIOS as much as possible to speed up computer booting. .

U.S. Pat. No. 7,213,139 JP 2010-123125 A

  In order to stabilize the operation of the device under the OS environment, it is desirable to detect, inspect and initialize all devices mounted at that time by POST. The POST that detects, inspects, and initializes all devices in this way is referred to as a basic POST. On the other hand, the POST time is preferably as short as possible since it is a waiting time until the computer becomes usable after the computer is turned on. Therefore, it is not preferable to execute basic POST at every start-up in a general situation where the configuration of the computer device is not changed, added, or removed in general.

  When POST that completes booting in a short time (hereinafter referred to as high-speed POST) as described in Patent Document 1 or Patent Document 2 is performed, the operation of a device whose configuration has been changed is performed. There is a possibility that it becomes unstable and POST hangs up. If the basic POST is executed when the configuration of the device is changed, and the high-speed POST is executed when the configuration is not changed, both the stability of the operation and the shortening of the boot time can be achieved. However, the conventional BIOS code cannot detect that the device configuration has been changed.

  In Patent Document 1, after disabling the fast startup, the computer housing is opened, the device configuration is changed, and then the device is booted and the device is initialized before the fast startup is enabled. It is described that there is no problem even if the configuration is changed. However, if the device is changed by opening the housing after first startup is enabled, the content stored in the BIOS chip is set to the changed device. It mentions what can happen.

  In the case of the invention of Patent Document 1, in this case, if it is not possible to restart more than three times, first startup is disabled and then the device is inspected and initialized again, and then the first startup is enabled. I try to make it. It can be restarted, but when the device is unstable, it is set to enable after the user has restarted after setting fast startup to disabled.

  Some devices, such as wireless modules, are desired not to automatically begin operation upon completion of booting in an inappropriate location. It is desirable that such a device is reliably detected at the POST stage to stop its operation or set parameters appropriately. In addition, if a plurality of restarts are repeated after an error has occurred in POST, a boot delay may occur. Therefore, when both high-speed POST and basic POST are used, if the BIOS code determines whether or not the device configuration has been changed and selects one of the POST codes, the operation can be stabilized with a small burden on the user. And shortening the boot time.

  Accordingly, an object of the present invention is to provide a method for selecting an appropriate POST from a basic POST and a high-speed POST coexisting in a computer and shifting from a power-off state to a power-on state. A further object of the present invention is to provide a method for achieving both stable operation and shortened boot time. A further object of the present invention is to provide a computer and a computer program for executing such POST.

  The present invention relates to the operation of the BIOS code from when the processor is reset to when it starts loading the operating system. In the present invention, the first POST code and the second POST code capable of finishing the processing in a shorter time than the first POST code are mounted inside the computer casing. The second POST code can be configured to restore parameters set at the time of initialization earlier to at least some internal devices. Alternatively, the second POST code can be configured to omit inspection and initialization for at least some internal devices.

  The computer determines the possibility of physical access to the internal device housed in the housing between the last reset of the processor and the current reset. Since the cover lid of the casing may be opened to physically access the internal device housed in the casing, the possibility of physical access can be determined by detecting the opening of the cover lid. . At that time, it can be determined that the screw for attaching the cover lid has been removed.

  When it is determined that the possibility of physical access is high, the first POST code is executed, and when it is determined that the physical access possibility is low, the second POST code is executed. With this configuration, it is possible to select an appropriate POST code according to the possibility that the configuration of the internal device has been changed, and to achieve both stable operation of the device and shortening of the POST time.

  In the present invention, it is possible to compensate for an error in determining the possibility of physical access by examining the power supply state of the power source of the computer. For example, when it is erroneously determined that the possibility of physical access is low, the power supply state of the power source between the previous reset of the processor and the current reset is further confirmed. When opening the cover lid, the user stops all power sources that drive the computer to ensure safety before accessing. In the case where the power source is composed of a secondary battery and an AC power source, the secondary battery is removed from the housing and the AC power source is disconnected to stop all the power sources.

  Therefore, when it is determined that one of the power sources is supplying power, it is determined that the possibility that the configuration of the internal device has been changed is low, and the second POST code can be executed. The power supply by the secondary battery and the AC power supply may be stopped even when the purpose is not to access the internal device. Therefore, when it is determined that both the secondary battery and the AC power supply have stopped supplying power, immediately determine the possibility of access to the internal device without executing the first POST code. Is desirable.

  Generally, a user who physically accesses the internal device does not wait for the battery pack to be completely discharged and suddenly removes the battery pack from the housing to ensure safety while the voltage remains. On the other hand, when the AC power is not supplied by the AC power supply, the battery pack voltage is supplied to the device in the power-on state or standby power is supplied in the power-off state. It decreases and gradually decreases to the critical voltage. When the critical voltage is reached, all the power sources of the computer will stop supplying power in any case, but in the present invention, the possibility of access to the internal device is determined by examining the progress to that point. be able to.

  First, it is determined whether or not the voltage of the secondary battery has dropped below a predetermined value in the power-on state. If the computer continues to be driven by a battery, even if the internal device is not accessed, the voltage of the secondary battery drops below a predetermined value in the power-on state. In the present invention, when it is determined that the voltage of the secondary battery has dropped below a predetermined value in the power-on state, the configuration of the internal device has been changed even when all the power sources have stopped power supply. Since the possibility is low, the second POST code can be executed.

  Even when it is determined that all power sources stop supplying power and the voltage of the secondary battery is maintained at a predetermined value or higher in the power-on state, do not immediately execute the first POST code, It is also desirable to determine the possibility of access to the internal device. Even when the voltage of the secondary battery is maintained at a predetermined value or higher in the power-on state, the user may suddenly remove the secondary battery in the power-off state to access the internal device.

  If the AC / DC adapter is removed from the computer equipped with the secondary battery and left for a long period of time, the voltage of the secondary battery drops to a predetermined value in the power-off state. Accordingly, when it is determined that the voltage of the secondary battery has dropped below a predetermined value in the power-off state, it is unlikely that the device configuration has been changed, so the second POST code can be executed. . Furthermore, when it is determined that all the power sources are stopped and the voltage of the secondary battery has maintained a predetermined value or more in both the power-on state and the power-off state, access to the internal device Therefore, the first POST code can be executed by determining that the user has suddenly removed the secondary battery before the voltage drops below a predetermined value.

  The power-off state can be a power state from the S1 state to the S5 state excluding the G3 state defined in ACPI. Further, when a new external device is connected in the power-on state, initialization with a POST code may be required. In this case, when it is determined that a new external device is connected, the first POST code can be executed.

  In the present invention, when the first POST code is executed, the procedure is more reliable than the second POST code and is simplified than the complete execution of the first POST code. can do. As an example, all device checks can be performed, an error can be displayed when an error occurs as a result of the device check, and an operating system load can be initiated when no error occurs. When an error is displayed, the user usually takes some action, so that when it is restarted, it can initialize all internal devices that have completed the action by executing all of the first POST code.

  According to the present invention, it is possible to provide a method for selecting an appropriate POST from a basic POST and a high-speed POST coexisting in a computer and shifting from a power-off state to a power-on state. Furthermore, according to the present invention, a method for achieving both stabilization of operation and shortening of the POST time can be provided. Further, according to the present invention, it is possible to provide a computer and a computer program for executing such POST.

It is a functional block diagram which shows the main structures of the computer 10 concerning this Embodiment. 3 is a diagram illustrating a data structure of a BIOS_ROM 33. FIG. 4 is a diagram showing a part of set-up data in an RTC memory 22. FIG. It is a figure explaining the structure of the open | release sensor 39. FIG. It is a figure which shows the structure relevant to this Embodiment of EC29. 6 is a flowchart showing a procedure when a selection POST bit of the RTC memory 22 is set to enable and each state setting bit of the EEPROM 30 is set. It is a flowchart which shows the execution procedure of selection POST. It is a flowchart which shows the execution procedure of selection POST. It is a flowchart which shows the execution procedure of selection POST.

[Computer configuration]
FIG. 1 is a functional block diagram showing a main configuration of a computer 10 according to the present embodiment. Throughout this specification, identical elements are provided with identical reference numbers. The computer 10 can be a notebook portable computer (hereinafter referred to as a notebook PC) on which a battery pack 41 is mounted and an AC / DC adapter 45 can be connected. The CPU 11 adopts an Intel (registered trademark) X86 series architecture, and can operate in a real mode (Real Address Mode) for executing the BIOS and a protected virtual address mode (Protected Virtual Address Mode) for executing the OS. it can. The protected virtual address mode is sometimes simply referred to as protected mode.

  The memory controller hub (MCH) 13 is a memory controller function for controlling an access operation to the main memory 15 and data for absorbing a difference in data transfer speed between the CPU 11 and other devices. A chip set that includes a buffer function. A CPU 11, a main memory 15, a graphic processing unit (GPU) 17, and an I / O controller hub (ICH) 21 are connected to the MCH 13.

  The main memory 15 is a volatile RAM that is used as a program area executed by the CPU 11 and a BIOS code reading area and a work area where processing data is written. An LCD 19 is connected to the GPU 17. The GPU 17 is a dedicated processor for writing an image to the VRAM based on a drawing command received from the CPU 11 and sending image image data to the LCD 19 at a predetermined timing, and is also called a graphics accelerator.

  The ICH 21 is a chip set that processes data transfer related to peripheral input / output devices. The ICH 21 includes controllers such as USB (Universal Serial Bus), serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count). In addition to the HDD 23 and the LPC bus 28, various devices such as a USB connector, a wireless module, a microphone, a speaker, and a camera described as the peripheral device 25 are connected.

  The ICH 21 includes an RTC (Real Time Clock) and an RTC memory 22 inside. The RTC and RTC memory 22 can be supplied with power from the button battery 27 when the ICH 21 is not supplied with power from the DC / DC converter 35. The RTC memory 22 is a volatile memory that stores BIOS setup data, time information generated by the RTC, and the like. The HDD 23 is a boot disk and stores a boot image when the computer 10 is started. Devices that do not require high-speed data transfer, such as an embedded controller (EC) 29 and BIOS_ROM 33, are connected to the LPC bus 28.

  The EC 29 is a microcomputer composed of a CPU, a ROM, an EEPROM, a DMA controller, an interrupt controller, a timer, and the like, and further includes an A / D input terminal, a D / A output terminal, an SM bus port, and an SPI bus port. And digital input / output terminals. The EC 29 operates independently of the CPU 11 and controls the power supplied to the device mounted on the notebook PC 10 according to the power state, and manages the temperature inside the system housing.

  A battery pack 41, a power management controller (PMC) 31, and an open sensor 39 are connected to the EC 29. The battery pack 41 conforms to the smart battery standard and supplies power to the DC / DC converter 35 when the AC / DC adapter 45 is not connected. The EC 29 acquires information on the state of the battery from the battery pack 41 through the SM bus. The AC / DC adapter 45 supplies power to the charger 43 to charge the battery pack 41 and supplies power to the DC / DC converter 35.

  The BIOS_ROM 33 is a non-volatile memory in which stored contents can be electrically rewritten, and stores a BIOS code. The PMC 31 is a wired logic digital control circuit (ASIC) that controls the power of the notebook PC 10. The PMC 31 includes a G3 detection register 32 that stores G3 bits. The notebook PC 10 supplies power to devices in the necessary range according to the power state, but the PMC 31 receives power from either the battery pack 41 or the AC / DC adapter 45 in all power states except the G3 state. Supplied.

  The G3 detection register 32 is referred to by the POST selection code 105 (FIG. 2). The POST selection code 105 is set when the G3 bit is not set after referring to the G3 detection register 32. The G3 detection register 32 is released when the power of the PMC 31 is stopped. Since the power of the PMC 31 is stopped only when the AC / DC adapter 45 and the battery pack 41 do not supply power to the notebook PC 10, when the POST selection code 105 detects the release of the G3 bit, the notebook PC 10 This means that the state has transitioned to the G3 state from the start to the current start.

  A control circuit for the start switch 37 and the DC / DC converter 35 is connected to the PMC 31. The activation switch 37 operates when the notebook PC 10 is activated, and includes a power button that is pressed by the user and a lid sensor that detects opening and closing of the lid of the housing. The DC / DC converter 35 is configured to output a plurality of voltages, and supplies power of a predetermined voltage to devices constituting the notebook PC 10 according to the power state. The PMC 31 controls the operation of the DC / DC converter 33 based on an instruction from the EC 29.

  The devices shown in FIG. 1 are housed in the casing of the notebook PC 10 and are hereinafter referred to as internal devices. In contrast, a device connected through a USB terminal, a VGA terminal, an eSATA terminal, or the like of a notebook PC is referred to as an external device. The open sensor 39 detects that a housing or a device bay lid (hereinafter referred to as a cover lid) that needs to be opened when replacing, adding, or removing an internal device is opened, and outputs a signal to the EC 29. To do.

[Power State]
The notebook PC 10 conforms to the ACPI standard, and can transition to four global system states of G0 state, G1 state, G2 state, and G3 state. The G0 state corresponds to the S0 state as a power state, and the CPU 11 is in a state in which an application program can be executed. The peripheral device is supplied with power, but performs a power saving operation based on a unique function. The S0 state is also called a power-on state. The G1 state is also called a sleeping state, and corresponds to the S1 state to the S4 state as power states.

  The S3 state is also referred to as a suspend state, and most of the devices are powered off except for the device that is required to hold the memory of the main memory 15. The S4 state is also called a hibernation state, and the system context is stored in the HDD 22 and the power of most devices is stopped. The G2 state corresponds to the S5 state as a power state, which is also called soft-off, and most devices are powered off without storing the system context in the HDD 23. The G3 state is also called a mechanical off state, and all the power sources of the notebook PC 10 are stopped except for the button battery 27.

  In the G3 state, the AC / DC adapter 45 and the battery pack 41 are removed from the notebook PC 10 or they are not supplied with power, and there is no power source other than the button battery 27 in the notebook PC 10. In this specification, the button battery 27 is not treated as a power source of the notebook PC 10, and all power sources of the notebook PC 10 are stopped when the AC / DC adapter 45 and the battery pack 41 are in the G3 state where the power supply is stopped. I will decide.

  The G3 state is also defined in the ACPI standard as a state in which electrical safety for accessing an internal device of the notebook PC 10 is ensured. In this specification, the sleeping state from the S1 state to the S4 state and the soft-off of the S5 state are referred to as the Sx state. The Sx state is also called a power-off state. In this specification, the transition from the S1 state to the S3 state to the S0 state and the operation state of the notebook PC 10 is called resume, and the transition from the S4 state or the S5 state to the S0 state and the operation state is cold. -Let's say boot or just boot. In addition, the transition of the power state of the notebook PC 10 from the Sx state to the S0 state is referred to as activation.

  Note that FIG. 1 is only a simplified description of the main hardware configuration and connection relations related to the present embodiment in order to describe the present embodiment. In addition to those mentioned in the above description, many devices are used to configure the notebook PC 10. However, they are well known to those skilled in the art and will not be described in detail here. A person skilled in the art also arbitrarily selects a plurality of blocks described in the figure as one integrated circuit or device, or conversely, a block is divided into a plurality of integrated circuits or devices. Is included in the scope of the present invention.

[Configuration of BIOS_ROM]
FIG. 2 shows the data structure of the BIOS_ROM 33. As shown in FIG. The BIOS_ROM 33 includes a BIOS area 51 and a data area 53 in which a BIOS code is stored. The BIOS_ROM 33 employs a boot block method in order to reduce the risk associated with rewriting the BIOS code. The BIOS area 51 is divided into a boot block 55 and a system block 57. The boot block 55 is a write-protected storage area, and the program or code stored here is treated as a CRTM (Core Root of Trust for Measurement) defined in the TPM (Trusted Platform Module) specifications and has special authority. It is impossible to rewrite without it.

  In the boot block 55, the basic device initialization code 101, the consistency authentication code 103, and the POST selection code 105 are stored as CRTM. The CRTM is configured as a consistent part of the BIOS code and is always executed first when the notebook PC 10 boots. All consistency measurements regarding the platform of the notebook PC 10 are performed by the consistency authentication code 103.

  The user is required to authenticate Physical Presence for some privileged operations among those permitted based on TPM ownership. The consistency authentication code 103 also authenticates the physical presence. The basic device initialization code 101 is stored in the CPU 11 and the main memory 15 which are necessary for loading the BIOS code into the main memory 15 and starting the execution when the notebook PC 10 is activated and transits from the Sx state to the S0 state. And other basic device detection, inspection and initialization to the extent necessary. The POST selection code 105 determines the possibility that the configuration of the internal device has changed from the previous activation to the current activation, selects an appropriate POST code from a plurality of POST codes prepared in advance, To achieve both stabilization of device operation after POST and shortening of POST time.

  The POST is a parameter in which the POST code stored in the BIOS_ROM 33 is supplied to the chip set controller during the period from when the reset signal is supplied to the CPU 11 until the OS is loaded when the Sx state transitions to the S0 state. The work to set and use. POST is all processing performed by the BIOS code from when the CPU 11 is reset to when the OS starts loading, or initialization of basic devices such as the CPU 11 and the main memory 13 is excluded. It may be processing. The time from the start of execution of the POST code to the end thereof is referred to as the POST time.

  The basic POST code 107 performs complete POST processing such as detection, inspection, and initialization for all internal devices. The basic POS code 107 outputs an error due to a beep sound or a screen display when a predetermined device cannot be detected or when it is determined that the device does not operate normally as a result of the inspection. The basic POST code 107 acquires parameters from the devices connected to the MCH 13 and the ICH 21, selects the optimum parameters in the current system, and sets them in the controller included in the MCH 13 and the ICH 21.

  In this specification, it is called initialization, and setting the optimal parameter selected based on the information acquired from the inspection of the internal device in this way is the past, and the past saved in any place Setting the parameter set in (1) to the corresponding controller is called restoration. Restoration can be completed in a shorter time than initialization because the processing for internal device detection, inspection, and optimal parameter selection is omitted, but operation is not possible when the device configuration is changed. There is a possibility that it becomes stable and POST hangs up.

  The high-speed POST1 code 109 and the high-speed POST2 code 111 perform the high-speed POST1 and the high-speed POST2, respectively, with fewer procedures than the basic POST. The basic POST code 107 has a longer execution time than the high-speed POST1 code 109 and the high-speed POST2 code 111. As an example, the high-speed POST 1 can be a Fast Post employed by the applicant of the present invention.

  Fast POST is a technique that omits detection, inspection, and selection of optimal parameters based on the premise that some predetermined devices are always mounted. Fast POST targets include internal devices that spend a lot of time for initialization, such as HDDs 23, USB devices, and wireless modules, and even if the OS is initialized from the timing of operation. It is possible to select an internal device that does not have any. When Fast POST is executed, if the configuration of an internal device that omits processing is changed, the operation may become unstable, or POST may hang up.

  As an example, the high-speed POST 2 stores the optimum parameters set by first executing the basic POST and information on the device at that time (hereinafter referred to as parameters) in the data area 53 of the BIOS_ROM 33 and other nonvolatile storage areas. In the next POST, a method of shortening the POST time by restoring the parameters stored except for the basic device can be employed.

  Here, the POST when resuming from the S3 state to the S0 state will be described. The POST code executed at the time of activation and the parameters set in the controller are stored in the main memory 15 in the S0 state. When suspending from the S0 state to the S3 state, the storage of the POST code and parameters stored in the main memory 15 is maintained. When resuming from the S3 state to the S0 state, the setting of the controller can be completed in a short time by executing the POST code stored in the main memory 15 and setting the parameters stored in the main memory 15. . Note that the BIOS code stored in the boot block 55 is always executed when resuming.

  In the high-speed POST2, when the voltage of the battery pack 49 decreases in the S3 state or when a predetermined time has elapsed, the POST code and parameters stored in the main memory 15 without being recognized by the OS are converted into the S0 state. After being stored in the HDD 23 or other nonvolatile memory via, the transition to the S5 state is made. At this time, the OS recognizes that the system has transitioned to the S3 state. Then, when the state transitions from the S5 state to the S0 state next time, the POST code stored in the HDD 23 sets the parameter stored in the HDD 23 in the controller, whereby the processing can be completed in a short time.

  The I / O code 113 provides an input / output interface for accessing peripheral devices when the CPU 11 operates in the real mode. The BIOS setup code 115 provides an interface for the user to customize settings for internal devices such as boot drive selection, enable / disable features of each device, enable / disable security, etc. . When the notebook PC 10 is booted, if a predetermined key is operated before the OS is loaded, the BIOS setup code 115 is executed and the BIOS setting screen is displayed on the LCD 19.

  The setup data set by the user is stored in the RTC memory 22 in the ICH 21. When executing the basic POST code 107, the high-speed POST code 109, and the high-speed POST code 111, the setup data stored in the RTC memory 22 is referred to. The environmental utility code 117 controls the temperature and power of the notebook PC 10. The authentication code 119 performs authentication such as a power-on password, HDD password, and administrator password.

  Note that the present invention can also be applied to the BIOS_ROM 33 that does not employ the boot block method, or the BIOS_ROM in which the entire BIOS area is the boot block. Both high-speed POST1 and high-speed POST2 adopt another method as long as the OS can be loaded in a shorter time by simplifying the procedure than the basic POST or omitting a part of the basic POST. You can also. However, the high-speed POST1 and the high-speed POST2 according to the present invention have characteristics that the operation of the internal device may become unstable or the POST may stop when executed when the configuration of the internal device is changed. .

[RTC memory]
FIG. 3 is a diagram showing a part of the setup data of the RTC memory 22. The RTC memory 22 stores set-up data set by the BIOS set-up code 115 and setting information and time information regarding schedule wake-up using the RTC. The selection POST bit 141 is an item for setting the selection POST executed in the procedure of FIGS. 6 to 9 to enable or disable. When the selected POST bit 141 is set to enable, POST is executed according to the procedure shown in FIGS. 7 to 9 when the computer is started. However, when the computer is disabled, only basic POST is executed as usual. The selection POST bit 141 is referred to when the POST selection code 105 controls the FET 46 shown in FIG.

  The S0 high-speed POST bit 143 is an item for setting the type of high-speed POST executed in the procedure of block 367 in FIG. In the present embodiment, either high-speed POST1 or high-speed POST2 is set. When no high-speed POST is set, the basic POST is executed according to the procedure of block 367. The Sx high-speed POST bit 143 is an item for setting the type of high-speed POST executed in the procedure of block 371 in FIG. In the present embodiment, either high-speed POST1 or high-speed POST2 is set. When no type of high-speed POST is set, basic POST is executed according to the procedure of block 371. The complete POST bit 147 is an item for setting which of the block 403 and the block 405 to move to in the procedure of the block 401 in FIG.

[Open sensor]
FIG. 4 is a diagram illustrating an example of the configuration of the open sensor 39. 4A is a plan view showing a state where a cover lid 203 is formed on the bottom surface of the casing 201 of the notebook PC 10, and FIG. 4B is a side view. When replacing the internal device of the notebook PC 10, it is necessary to remove the cover lid 203. The cover lid 203 is an example of a physical access path for changing the configuration of the internal device. Another example of the physical access path is a device bay lid formed on the side surface of the housing 201. On the inner surface of the keyboard 207, a tapping boss 209 with a screw cut therein is formed. The cover lid 203 is attached to the housing 201 with screws 205 and 207.

  The screw 205 is coupled to the tapping boss 209 when the cover lid 203 is fixed to the housing 201. The screw 205 passes through the mother board 213. Divided female screws 211a and 211b are attached to the mother board 213 at positions where the screws 205 penetrate. When the screw 205 is coupled to the tapping boss 209, the screw 205 is coupled to the divided female screws 211a and 211b. 4C shows a state where the divided female screws 211a and 211b and the screw 205 are coupled, and FIG. 4D shows a state where the divided female screws 211a and 211b and the screw 205 are not coupled.

  The screw 207 has the same structure and is coupled to another tapping boss and a split female screw. 4C shows a state where the cover lid 203 is attached to the system casing 201, and FIG. 4D shows a state where the cover lid 203 has been removed from the system casing 201. FIG. The divided female screw 211b is connected to the power supply line, and the divided female screw 211a is connected to the ground. When the screw 205 is coupled, the divided female screw 211b and the divided female screw 211a are conducted, and the potential of the divided female screw 211b becomes the ground level. When the screw 205 is not coupled, the potential of the divided female screw 211b is the power source. Potential.

  The opening sensor 39 detects a state in which the cover lid 203 is opened using the change in potential. The open sensor 39 is not limited to the embodiment shown in FIG. For example, a conductive plate may be attached to the inner surface of the cover lid 203 made of plastic, and two electrodes may be formed on the housing 201 side to detect continuity of the electrodes due to the cover lid 203 being attached. Good. Further, a micro switch for detecting the attachment of the cover lid 203 or a magnet type sensor may be provided.

[Structure of EC]
FIG. 5 is a diagram showing a configuration related to the present embodiment of the EC 29. The EC 29 includes an open detection circuit 151 configured by an EEPROM 30 and a hardware logic circuit. A plurality of state setting bits 153 to 161 are set in the EEPROM 30. The POST selection code 105 can refer to the status setting bits 153 to 161. The opening bit 153 indicates a state where the cover lid 203 is opened. A voltage is applied to the open detection circuit 151 from the DC / DC converter 35 and the button battery 27 by a so-called wired OR circuit via respective diodes.

  While the battery pack 41 or the AC / DC adapter 45 supplies power, the DC / DC converter 45 supplies power to the open detection circuit 151, but the button battery 27 supplies power when the notebook PC 10 transitions to the G3 state. To do. One end of the open sensor 39 is connected to the open detection circuit 151, and the other end is connected to the ground. When the cover lid 203 is closed, current flows from the DC / DC converter 35 or the RTC memory 27 to the ground.

  The voltage at one end of the open sensor 39 is at the ground level when the cover lid 203 is closed, but increases to the voltage of the DC / DC converter 35 or the button battery 27 when the cover lid 203 is opened. The opening detection circuit 151 sets the opening bit 153 when the voltage at one end of the opening sensor 39 rises to a predetermined value after being instructed by the POST selection code 105. After the POST selection code 105 refers to the release bit 153, if it is set, the POST selection code 105 is canceled to execute the selection POST at the next activation.

  When the button battery 27 backs up the power of the opening detection circuit 151, the opening detection circuit 151 detects the state when the cover lid 203 is opened after the transition to the G3 state, and sets the opening bit 153. can do. However, in the present invention, even when the power of the open detection circuit 151 is not backed up by the button battery 27, the selection POST can be executed by the procedure after the block 363 in FIG.

  Since the notebook PC 10 is supplied with power from the battery pack 41 or the AC / DC adapter 45 in the power-on state or the power-off state, the button battery 27 is not consumed due to the open detection circuit 151, but is shipped from the factory. When the state of the G3 state continues for a long time as before, the consumption of the button battery 27 becomes intense. In order to avoid unnecessary consumption of the button battery 27, the FET 46 is connected to the cathode of the diode connected to the button battery 27. The FET 46 is controlled by a control circuit 47 that receives power from the button battery 27. The POST selection code 105 instructs the control circuit 47 to turn on the FET 46 when the selection POST bit 141 of the RTC memory 22 is set to enable, and turns it off when set to disable.

  Each of the S0_BATT_Low bit and the Sx_BATT_Low bit indicates that the voltage of the battery pack 41 has decreased to a value lower than a predetermined value (critical voltage) to stop discharging. When the voltage of the battery pack 41 is lowered to the critical voltage during the S0 state and the discharge is stopped during the S0 state, the EC 29 is lowered to the critical voltage during the Sx state and when the discharge is stopped. The Sx_BATT_Low bit indicating the state is set. If the POST selection code 105 is set after referring to the S0_BATT_Low bit and the Sx_BATT_Low bit, the POST selection code 105 is canceled to execute the selection POST at the next activation.

  The PnP bit 159 indicates a state in which an external device is connected by plug and play under the operating environment of the OS. The EC 29 sets the PnP bit 159 when it receives notification from the OS that an external device has been connected by plug and play during the S0 state. If the POST selection code 105 is set after referring to the PnP bit 159, the POST selection code 105 is canceled to execute the selection POST at the next activation.

  In the notebook PC 10, when the transition from the Sx state to the S0 state is performed, different processing is performed depending on the power state of the transition source. The power state bit 161 indicates the power state of the transition source when transitioning from the Sx state to the S0 state. The power state bit 161 is set as a transition destination power state when the EC 29 notified from the ICH 21 transitions from the S0 state to the Sx state, and is released when the EC 29 transitions from the Sx state to the S0 state.

[Selected POST procedure]
Next, the execution procedure of the selection POST in the notebook PC 10 will be described with reference to the flowcharts of FIGS. FIG. 6 is a flowchart showing a procedure when the selection POST bit of the RTC memory 22 is set to enable and each state setting bit of the EEPROM 30 is set. In block 301 of FIG. 6, the notebook PC 10 is activated by operating the activation switch 37 in the S4 state or S5 state. The EC 29 operates the DC / DC converter 35 through the PMC 31 in order to transit to the S0 state.

  ICH21 which received the signal which changes to S0 state from EC29 sends a reset signal to CPU11. The CPU 11 that has received the reset signal initializes the internal cache and the register when the voltage is stabilized. The CPU 11 then accesses a predetermined address (reset vector) of the main memory 15 to fetch an instruction.

  When the notebook PC 10 boots, the BIOS code stored in the boot block 55 is executed from a predetermined address. The MCH 13 determines that the power state of the transition source is the S4 state or the S5 state, and switches the access to the reset vector to the address of the basic device initialization code 101 stored in the boot block 55 of the BIOS_ROM 33. The CPU 11 reads the basic device initialization code 101 into the cache, and performs basic device detection, inspection, and initialization necessary for executing the BIOS code such as the main memory 15 and the MCH 13.

  The basic device initialization code 101 writes the parameters set in the controller for initialization in the data area 53 and other nonvolatile memory as necessary. Subsequently, the basic device initialization code 101 loads a predetermined code stored in the BIOS_ROM 33 to the main memory 15 so that the main memory 15 can be used as a shadow RAM. Thereafter, the CPU 11 accesses the main memory 15 and executes the BIOS code.

  Next, the consistency authentication code 103 performs authentication related to modification of the BIOS code stored in the system block 57. When the authentication is completed, the POST selection code 105 is executed. At this time, since the selection POST bit 141 of the RTC memory 22 is disabled, the selection POST according to the procedure shown in FIGS. 7 to 9 is not executed. The POST selection code 105 asserts that power is supplied to the PMC 31 by setting the G3 bit in the G3 detection register 32. In block 303, before the OS loading starts, the user presses a predetermined key to call the BIOS setup code 115 to store the setup data in the RTC memory 22. In block 305, the user sets the selected POST bit 141 to enabled.

  In block 307, the user sets the type of fast POST. The S0 high-speed POST bit 143 and the Sx high-speed POST bit 145 are objects to be determined by the POST selection code 105 in blocks 367 and 371 in FIG. 7, respectively. The possibility of accessing the internal device is higher in the Sx state than in the S0 state. Therefore, it is desirable to perform more reliable POST in the state of the block 369 in which the voltage of the battery pack 41 is reduced to the critical voltage in the S0 state than in the state of the block 365 in the Sx state. Therefore, in block 307, the user sets the high-speed POST2 for restoring parameters in the S0 high-speed POST bit 143, and sets the high-speed POST1 for initializing parameters except for some internal devices in the Sx high-speed POST bit 145.

  At block 309, the user sets or clears the complete basic POST bit 147. In block 311, the basic POST code 107 is executed when the user saves the setup data in the RTC memory 22 and exits the BIOS setup code 115. The basic POST code 107 detects, inspects, and initializes all remaining devices that are not processed by the basic device initialization code 101. The basic POST code 107 writes the parameters set in the controller for initialization into the data area 53 and other nonvolatile memory as required. In block 313, the OS and application program are loaded and executed following the basic POST code 107.

  At this point, the main memory 15 stores the BIOS code and parameters set in the controller. The storage area of the main memory 15 for storing data other than the BIOS code and parameters necessary for resuming from the S1 state to the S3 state where the storage of the main memory 15 is maintained is used for the use of a general program. For free.

  In block 315, when a new external device is connected by plug-and-play, the EC 29 notified from the OS sets the PnP bit 159 in the EEPROM 30. Further, when the EC 29 detects that the voltage of the battery pack 41 has dropped to the critical voltage, the EC 29 refers to the power state bit 161 and sets the S0_BATT_Low bit 155. In block 317, the notebook PC 10 transitions to the Sx state by operating the start switch 37, operating through the OS interface, or executing power management.

  The ICH 21 that has received notification that the preparation for the transition from the OS to the Sx state has been completed sets the power state of the transition destination in the power state bit 161 of the EEPROM 30. When the transition is made from the S1 state to the S3 state, the storage of the main memory 15 is maintained, so that the storage of the BIOS code and parameters stored in the main memory 15 at the most recent start-up is maintained. The When the state transits to the S4 state or the S5 state, the power source of the main memory 15 is lost, and therefore all data stored in the main memory 15 is lost.

  When the state transitions to the Sx state, the operation of the CPU 11 stops, and the power of the internal device determined in advance according to the power state also stops. While the operation of the notebook PC 10 is stopped during the Sx state, when the AC / DC adapter 45 is connected, the EC 29 is connected to the battery when the voltage of the battery pack 41 drops to a predetermined value due to standby power. A charge request is received from the pack 41 and the charger 43 is operated to charge. In addition, when the AC / DC adapter 45 is not connected, the battery pack 41 supplies standby power in the Sx state, so that the critical voltage may be lowered. In block 321, when the EC 29 detects that the voltage of the battery pack 41 has dropped to the critical voltage during the Sx state, the Sx_BATT_LOW bit 157 is set with reference to the power state bit 161.

  7 to 9 are flowcharts showing the execution procedure of the selected POST. In block 351, when the notebook PC 10 is transitioning to the Sx state, the EC 29 is triggered by the operation of the start switch 37, the reception of the WOL magic packet, or the arrival of the wake-up time due to the schedule wake-up. An activation signal is sent to. The ICH 21 that has received the activation signal from the EC 29 instructs the EC 29 to supply power to all devices in order to shift to the S0 state, and further sends a reset signal to the CPU 11.

  The CPU 11 that has received the reset signal accesses the reset vector in the main memory 15. The MCH 13 switches the CPU 11 access to the reset vector to the address of the basic device initialization code 101 stored in the boot block 55 of the BIOS_ROM. The basic device initialization code 101 that has completed the initialization of the basic device refers to the power state bit 161 of the EEPROM 30 in block 355 to determine the power state of the transition source. When the transition source power state is the S1 state to the S3 state, since the POST code and parameters executed at the previous activation are stored in the main memory 15, the process proceeds to block 357 and the CPU 11 accesses The destination is switched to the address where the POST code of the main memory 15 is stored.

  In block 357, the POST code stored in the main memory 15 sets the controller based on the device information and parameters stored in the main memory 15 as well. This operation can shift to a state in which the OS is loaded in a short POST time in order to omit device detection, inspection, and selection of optimum parameters. If the selected POST bit 141 is set to enable at the time of the previous activation, the POST selection code 105 is executed, and there is a possibility of physical access to the internal device in the procedure from the block 359. The POST code 107 is executed.

  When the basic device initialization code 101 determines in block 355 that the power state of the transition source is the S4 state or the S5 state, the BIOS code of the boot block 55 is sequentially executed in the same procedure as in the block 301 thereafter. Then, the process proceeds to block 359. This time, since the selection POST bit 141 of the RTC memory 22 is set to enable, the CPU 11 completely executes the POST selection code 105. At block 359, the POST selection code 105 confirms the PnP bit 159 of the EEPROM 30.

  An external device newly connected under the operating environment of the OS can be basically excluded from the target of POST because the OS only needs to be initialized or restored, but the external device is set as the highest priority boot device. In some cases, such as a USB device, it is desirable for the BIOS code to initialize it. When the PnP bit 159 is set, the procedure can be shifted to the procedure of the node A in principle to execute the basic POST, and when the PnP bit 159 is not set, the procedure can be shifted to the block 361. Note that the determination of block 359 may be omitted, assuming that the OS performs all settings for external devices attached by plug and play.

  In block 361, the POST selection code 105 refers to the opening bit 153 of the EEPROM 30 to determine whether or not the cover lid 203 has been opened between the previous activation and the current activation. The POST selection code 105 cancels the opening bit 153 when the opening bit 153 is referred to, and then sets the opening bit 153 when the opening sensor 39 indicates the opening of the cover lid 203. 151 is controlled.

  When the release bit 153 is set, it is highly likely that the configuration of the internal device has been changed by replacement, addition, or removal, and therefore the procedure proceeds to the node A procedure. When the opening bit 153 is not set, it is considered that the possibility that the configuration of the internal device has been changed is very low because the cover lid 203 is not physically opened, and even if the high-speed POST1 or the high-speed POST2 is executed. It can be said that there is no instability in operation.

  However, when adopting a method in which the power of the opening detection circuit 151 for detecting the opening of the cover lid 203 is not backed up by the button battery 27 or when the button battery 27 is exhausted, the state is changed to the G3 state. The open detection circuit 151 cannot detect the state in which the cover lid 203 is opened. Furthermore, even if the voltage of the button battery 27 is maintained, the open sensor 39 or the open detection circuit 151 may not operate normally, so that the opening of the cover lid 203 may not be detected correctly. Furthermore, the internal device may be mounted in a form that can be replaced without opening the cover lid 203.

  In the present embodiment, when it is determined that the cover lid 203 is not opened, the high-speed POST1 or the high-speed POST2 is not executed immediately, but the possibility of access to the internal device is further determined to determine the basic POST with high reliability. Determine if there is a need to do so. Here, in the maintenance manual of the notebook PC 10, when changing the configuration of the internal device, the battery pack 41 and the AC / DC adapter 45 are removed to be in an electrically safe G3 state, and then the housing is opened. It is stipulated in.

  In the present embodiment, when the opening of the cover lid 203 is not detected using the probability that the user accesses the internal device in accordance with the maintenance manual, the notebook PC 10 executes the steps of blocks 363, 365, and 369 to execute the G3 state. And whether or not the reason for transition to the G3 state was for the purpose of accessing the internal device. In block 363, the POST selection code 105 refers to the G3 detection register 32 of the PMC 31, and confirms whether the notebook PC 10 has transitioned to the G3 state between the previous activation and the current activation. If the G3 bit of the register 32 has been released, the transition to the G3 state has occurred, and the process moves to block 365. After confirming that the G3 bit is released, the POST selection code 105 sets the G3 bit for the next selection POST.

  When the G3 bit is set, it means that at least one of the battery pack 41 and the AC / DC adapter 45 of the notebook PC 10 is connected as a power source, and it is unlikely that the configuration of the internal device has been changed. Therefore, the procedure shifts to the procedure of the node B based on the high-speed boot. Incidentally, the transition of the notebook PC 10 to the G3 state is not limited to the case where the user removes the AC / DC adapter 45 and the battery pack 41 in order to replace the internal device. If the voltage of the battery pack 41 decreases to the critical voltage when the notebook PC 10 is being used in a battery-driven state, the battery pack 41 stops outputting and the notebook PC 10 transitions to the G3 state.

  Even when the notebook PC 10 is in the Sx state, when the AC / DC adapter 45 is not connected, the battery pack 41 voltage drops to the critical voltage due to standby power consumption and enters the G3 state. There may be transitions. Thus, the transition to the G3 state due to the voltage of the battery pack 41 being lowered to the critical voltage is a phenomenon that can occur regardless of the access of the internal device.

  In block 365, the POST selection code 105 confirms the S0_BATT_Low bit 155. When the S0_BATT_Low bit 155 is set, it means that the voltage of the battery pack 41 gradually decreases to the critical voltage in the S0 state and transitions to the G3 state, and it is unlikely that the internal device has been accessed. 367. If the S0_BATT_Low bit 155 is not set in block 365, the battery pack 41 may have been suddenly removed and access to the internal device may have occurred. However, in the Sx state, the critical voltage gradually decreases to the G3 state. Since the possibility of the transition remains, the process proceeds to block 369.

  At block 369, the POST selection code 105 confirms the Sx_BATT_Low bit 157. When the Sx_BATT_Low bit 157 is set, it means that the voltage of the battery pack 41 gradually decreases to the critical voltage in the Sx state and transitions to the G3 state, and it is unlikely that the internal device has been accessed. 371. When the Sx_BATT_Low bit 157 is not set in the block 369, it is highly possible that the battery pack 41 is suddenly removed based on the determination from the block 361 to the block 369. Then, when the battery pack 41 is suddenly removed, there is a high possibility that the internal device has been accessed, and the process proceeds to the note A.

  Both block 367 and block 371 show a procedure for selecting whether to execute basic POST, high-speed POST 1 or high-speed POST 2 when the voltage of the battery pack 41 drops to the critical voltage. The POST selection code 105 refers to the S0 fast POST bit 143 of the RTC memory 22 at block 367 and refers to the Sx fast POST bit 145 at block 371 to select whether to execute node A or node B.

  FIG. 8 is a flowchart showing a procedure based on the execution of the basic POST. As shown in the procedure of FIG. 7, the basic POST code 107 is executed when there is a high possibility that the configuration of the internal device has been changed. When the basic POST code 107 is executed, it is desirable to be able to detect the internal device whose configuration has been changed in as short a time as possible and complete its inspection and initialization. Therefore, some procedures can be omitted when the basic POST code 107 is executed.

  In block 401, the operation shifts from the POST selection code 105 to the basic POST code 107. The basic POST code 107 first confirms the complete basic POST bit 147 of the RTC memory 22. If the complete basic POST bit 147 is set, go to block 403 to execute all basic POST codes 107 to detect, inspect, and initialize the device, then go to block 417 to load the OS To do.

  If the complete basic POST bit 147 is not set at block 401, only the internal device is tested at block 405. In block 407, if the basic POST code 107 checks all internal devices and no error occurs, the process proceeds to block 409, restores the parameters stored in the data area 53, and then proceeds to block 417. . If an error occurs in block 407, the process moves to block 411 to set the complete basic POST bit 147 and display the error to the user.

  In block 413, the user opens the cover lid 203, takes action if there is an abnormality in the internal device whose configuration has been changed, and restarts. Thereafter, the procedure from block 351 is started. In block 401, since the complete basic POST bit 147 is set, the basic POST code 107 is completely executed in block 403.

  FIG. 9 is a flowchart showing a procedure for executing the high-speed POST. In block 453, the operation shifts from the POST selection code 105 to the high-speed POST code 109 or 111 selected in blocks 367 and 371 in FIG. If operation has moved to the fast POST1 code 109, block 457 examines and initializes the given device. When the high-speed POST1 code 109 detects an error in block 459, the process proceeds to block 451. In block 451, the operation moves to the basic POST code 107, and after the basic POST code 107 is completely executed, the operation moves to block 455.

  If no error is detected in block 459, the process moves to block 455. At block 455, the OS and application programs are loaded. When the operation moves to the high-speed POST2 code 111 in block 453, the parameters stored in the main memory 15, the data area 53, the HDD 23, or the like are restored in block 453, and the processing moves to block 455.

  The procedure of blocks 363, 365, and 367 in FIG. 7 is meaningful to compensate for an error that the open detection circuit 151 does not detect the cover lid 203 that is actually opened in the block 361. This is because the structure of the circuit for detecting the opening of the cover lid 203 shown in FIG. 5 is less likely to output that the screw 205 is not connected although it is actually connected. In the present invention, the error that the opening detection circuit 151 outputs when the cover lid 203 is closed even when the cover lid 203 is closed can be supplemented using the procedure of blocks 363, 365, and 367 in FIG.

  Specifically, when it is determined in block 361 that the cover lid 203 has been opened, the process proceeds to the path from block 363 to block 371 without immediately shifting to node A. Then, if the transition to the note A is made via the blocks 367, 369, 371, the error that determines that the cover lid 203 has been opened is the transition to the G3 state from the previous activation to the current activation. The presence or absence and the state of the battery pack 41 can be determined and complemented.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

10 ... Notebook PC
22 ... RTC memory 29 ... Embedded controller 30 ... EEPROM
33 ... BIOS_ROM
39 ... Open sensor 51 ... BIOS area 53 ... Data area 55 ... Boot block 57 ... System block

Claims (20)

A method in which a computer that implements a first POST code and a second POST code capable of completing processing in a shorter time than the first POST code shifts from a power-off state to a power-on state. ,
Determining whether the computer has made physical access to the internal device housed in the housing between the last reset of the processor and the current reset;
Executing the first POST code when determining that the possibility of physical access is high;
Executing the second POST code when determining that the possibility of physical access is low. Executing the second POST code;
Determining whether all power sources have stopped supplying power between a previous reset of the processor and a current reset;
2. The method of claim 1, further comprising executing the second POST code when it is determined that any power source is supplying power. All the power sources are composed of secondary batteries and AC power sources,
Executing the second POST code;
When it is determined that both the secondary battery and the AC power supply have stopped supplying power between the previous reset of the processor and the current reset, the voltage of the secondary battery is predetermined in the power-on state. Determining whether it has dropped below a value;
3. The method of claim 2, comprising executing the second POST code when it is determined that it has dropped below a predetermined value. Executing the second POST code;
Whether or not the voltage of the secondary battery has decreased below the predetermined value in the power-off state when it is determined that the voltage of the secondary battery has been maintained at the predetermined value or higher in the power-on state. A step of determining
Executing the second POST code when it is determined that the value has fallen below the predetermined value;
The method according to claim 3, further comprising the step of executing the first POST code when it is determined that the predetermined value or more is maintained. Implementing a third POST code that allows the computer to finish processing in a shorter time than the second POST code;
The method according to any one of claims 1 to 4, further comprising the step of selecting either the second POST code or the third POST code. Determining whether an external device is connected in the power-on state; and
The method according to claim 1, further comprising executing the first POST code when it is determined that the external device is connected.   The method according to claim 1, wherein the step of determining the possibility that the physical access has been performed includes a step of determining that a cover cover of the housing is opened.   8. The method of claim 7, wherein determining the possibility that the physical access has occurred comprises determining that a screw that attaches the cover lid has been removed. Executing the first POST code comprises:
Performing an inspection of the internal device;
Displaying the error when an error occurs as a result of the inspection of the internal device;
The method according to claim 1, further comprising: executing all the first POST codes when the error is displayed and then restarted. A method of starting a computer that houses a plurality of internal devices in a housing,
Preparing a first code for setting parameters by inspecting and initializing the plurality of internal devices, and a second code for setting parameters by a simpler procedure than the first code;
Receiving a reset signal by the processor;
The computer determining the possibility of physical access to the internal device;
Executing the first code when determining that there is a high probability of physical access to the internal device;
Executing the second code when determining that the possibility of physical access to the internal device is low;
Having a method.   The method according to claim 10, wherein the step of determining the possibility of physical access includes the step of determining a power supply state of a power source for the computer between a previous reset of the processor and a current reset. . The power source includes a secondary battery;
Determining the power supply state of the power source,
Determining whether all power sources to the computer have stopped supplying power;
The method according to claim 11, further comprising: determining whether or not the voltage of the secondary battery has dropped below a predetermined value when it is determined that all power sources have stopped supplying power. A portable computer that houses an internal device in a housing and receives power from a battery pack and an AC / DC adapter,
A processor;
Basic POST code that causes the computer to function to set parameters in the internal device when the processor is reset;
A high-speed POST code that causes the computer to function to set parameters in a shorter time than the basic POST code when the processor is reset;
A detection unit for detecting a state indicating a possibility of physical access to the internal device;
A function of selecting the basic POST code when detecting a state indicating the possibility of physical access and selecting the high-speed POST code when not detecting a state indicating the possibility of physical access; A portable computer having a POST selection code to be realized by the computer.   The POST selection code determines whether or not at least one of the battery pack and the AC / DC adapter has continued to supply power between the time when the processor was reset last time and the time when it is reset this time. 14. A portable computer according to claim 13 comprising:   When the POST selection code determines that the battery pack and the AC / DC adapter have stopped supplying power, the voltage of the battery pack is less than a predetermined value between the previous reset of the processor and the current reset. The portable computer according to claim 14, wherein it is determined whether or not the voltage has dropped.   The portable computer according to any one of claims 13 to 15, wherein the detection unit detects an open state of a cover lid that opens the housing.   The portable computer according to any one of claims 13 to 16, wherein the detection unit is supplied with power from a button battery that supplies power to a real time clock. When the computer storing the internal device in the housing is started,
Detecting the possibility of physical access made to the internal device between the previous activation and the current activation;
Performing inspection and initialization of the internal device upon detecting the possibility of physical access;
A BIOS for executing a process including at least the check and a step of restoring a parameter stored in a nonvolatile memory by omitting a part of the initialization when the possibility of physical access is not detected code.   The step of detecting the possibility of physical access includes the step of determining whether or not all power sources of the computer have stopped supplying power between the previous start and the current start. The BIOS code according to.   The step of detecting the possibility of physical access includes a step of determining whether or not the voltage of the secondary battery has maintained a predetermined value or more between the previous activation and the current activation. The BIOS code according to claim 18 or claim 19.

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