JP2012134526A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for improving manufacturing yield of a semiconductor device comprising a plurality of semiconductor chips laminated in three-dimensional manner.SOLUTION: A through electrode 17 is formed to reach a pad 3 from a second surface 1b of a semiconductor substrate 1. Through space inside the through electrode 17 comprises a first hole 7 and a second hole 11 with a pore diameter smaller than that of the first hole 7. The first hole 7 is formed from the second surface 1b of the semiconductor substrate 1 up to the middle of an interlayer insulating film 2 through the semiconductor substrate 1. The second hole 11 is formed from the bottom of the first hole 7 to reach the pad 3 through the interlayer insulating film 2. At this time, the interlayer insulating film 2 formed on the first surface 1a of the semiconductor substrate 1 is step shaped as a result of reflecting the shape of a step between the bottom surface of the first hole 7 and the first surface 1a of the semiconductor substrate 1. That is, a thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 is smaller than that of the interlayer insulating film 2 at other locations.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a plurality of three-dimensionally stacked semiconductor chips and a technique effective when applied to the manufacturing technique.

  Japanese Patent Laid-Open No. 11-204720 (Patent Document 1) describes a technique for performing electrical connection between stacked semiconductor chips in a three-dimensional stacked SiP (System in Package) by wire bonding. Yes.

  Japanese Patent Application Laid-Open No. 2000-260934 (Patent Document 2) discloses an upper and lower semiconductor chip in which electrodes through which solder or a low-melting-point metal is embedded by electrolytic plating or electroless plating are formed in through holes formed in a semiconductor chip. The technology to form is described. Then, after heating, the electrodes embedded in the through holes of the upper and lower semiconductor chips are connected by fusion bonding, thereby making electrical connection between the stacked upper and lower semiconductor chips.

  Japanese Patent Laying-Open No. 2005-340389 (Patent Document 3) forms a stud bump electrode on a semiconductor chip arranged on the upper side of stacked semiconductor chips and forms a through electrode on a semiconductor chip arranged on the lower side. The technology to do is described. Then, the stud bump electrode formed on the upper semiconductor chip is deformed and injected into the through electrode formed on the lower semiconductor chip by pressure contact, and the stud bump electrode and the through electrode are geometrically caulked to vertically The electrical connection between the semiconductor chips is performed.

  Japanese Patent Laying-Open No. 2005-93486 (Patent Document 4) describes a technique for forming an electrode to be drawn out from a pad electrode formed on the surface of a silicon substrate via an interlayer insulating film to the back surface of the silicon substrate. In this technique, the silicon substrate is etched from the back surface of the silicon substrate using a hard mask as a mask to form an opening having an interlayer insulating film as a bottom surface (FIG. 4C of Patent Document 4). Then, after removing the hard mask (FIG. 5A of Patent Document 4), an insulating film is formed on the entire back surface of the silicon substrate including the inside of the opening (FIG. 5B of Patent Document 4). Then, the pad electrode is exposed on the bottom surface of the opening by etching the interlayer insulating film using a resist film (FIG. 5C of Patent Document 4) covering the side wall of the opening and the portion other than the opening as a mask (patent) FIG. 6 (A) in Document 4. Thereby, the through-hole which reaches a pad electrode from the back surface of a silicon substrate can be formed. By embedding a metal material in the through hole, an electrode that is electrically connected to the pad electrode and reaches the back surface of the silicon substrate can be formed. Here, when the hard mask used for etching the silicon substrate is removed, the interlayer insulating film exposed from the bottom surface of the opening is also slightly etched to reduce the film thickness.

  Japanese Patent Laying-Open No. 2006-32699 (Patent Document 5) describes a semiconductor device manufacturing technique described below. That is, a first insulating film is formed on the surface of the semiconductor substrate, and a portion of the first insulating film from the surface side of the semiconductor substrate is selectively etched to a halfway through the film thickness to reduce the thickness. . By this etching, a recess having a bottom surface formed by thinning the first insulating film is formed. Thereafter, a pad electrode is formed on the first insulating film including the inside of the recess (FIG. 16 of Patent Document 5). Subsequently, after forming a second insulating film on the back surface of the semiconductor substrate, etching is performed so that the second insulating film and the semiconductor substrate at positions corresponding to the concave portions of the first insulating film are opened larger than the concave portions. By this etching, a via hole having an opening diameter larger than that of the recess and penetrating the second insulating film and the semiconductor substrate is formed (FIG. 17 of Patent Document 5). Next, after a third insulating film is formed on the second insulating film including the inside of the via hole (FIG. 18 of Patent Document 5), etching is performed from the back surface of the semiconductor substrate. By this etching, the third insulating film formed on the second insulating film, the third insulating film formed on the bottom surface of the via hole, and the thinned first insulating film are removed. As a result, the pad electrode is exposed on the bottom surface of the via hole (FIG. 19 of Patent Document 5). By embedding a metal material in the through hole, an electrode that is electrically connected to the pad electrode and reaches the back surface of the silicon substrate can be formed.

  Japanese Patent Application Laid-Open No. 2007-53149 (Patent Document 6) describes a technique of processing a contact electrode (through electrode) connected to a pad from the back surface of a semiconductor substrate when a plurality of semiconductor chips are stacked. Specifically, after forming a mortar-shaped through hole from the back surface of the semiconductor substrate, an insulating film is formed on the back surface of the semiconductor substrate including the inside of the through hole. And after removing the insulating film of the bottom face of a through-hole, it is supposed that a contact electrode will be formed by forming and patterning a conductor film in the wall surface of a through-hole.

  Japanese Patent Laying-Open No. 2006-222138 (Patent Document 7) describes a semiconductor device manufacturing technique described below. Specifically, a method of forming a through electrode penetrating in the thickness direction of the semiconductor substrate is described. In this technique, a first insulating film is formed on the surface of a semiconductor substrate, and a second insulating film is formed on the back surface of the semiconductor substrate (FIG. 1A of Patent Document 7). Then, a first etching stop layer made of a conductive member having an etching rate different from that of the semiconductor substrate is formed on the second insulating film (FIG. 1B of Patent Document 7). Next, a recess that penetrates through the first insulating film, the semiconductor substrate, and the second insulating film to reach the first etching stop layer is formed at the formation position of the through electrode (FIG. 1C of Patent Document 7). . Thereafter, a through electrode is formed by embedding a conductive material in the recess by plating using the first etching stop layer as a seed layer (FIGS. 1D to 1F of Patent Document 7).

JP-A-11-204720 JP 2000-260934 A Japanese Patent Laid-Open No. 2005-340389 JP 2005-93486 A JP 2006-32699 A JP 2007-53149 A JP 2006-222138 A

  In recent years, development of SiP (System in Package) that realizes a high-performance system in a short period of time by mounting a plurality of semiconductor chips at high density has progressed, and various mounting structures have been proposed by various companies. In particular, SiP in which a plurality of chips are three-dimensionally stacked is excellent in terms of mounting area.

  As shown in Japanese Patent Laid-Open No. 11-204720 (Patent Document 1), in a three-dimensional stacked SiP, connection between semiconductor chips by wire bonding is common. However, connection between semiconductor chips by wire bonding requires rewiring by dropping the wiring onto the mounting substrate. As a result, the wiring between the semiconductor chips becomes long, and the wiring on the mounting substrate becomes dense. As a result, the inductance between the wirings increases, making high-speed transmission difficult, and increasing the density of the wirings formed on the mounting substrate deteriorates the yield, leading to an increase in the cost of the semiconductor device.

  In order to cope with these wire bonding connection problems, a method of forming an electrode penetrating the inside of a semiconductor chip and stacking a plurality of chips has been proposed. For example, in Japanese Patent Laid-Open No. 2000-260934 (Patent Document 2), upper and lower electrodes in which electrodes embedded with solder or a low melting point metal are electrolytically deposited or electroless plated in through holes formed in a semiconductor chip. A technique for forming a semiconductor chip is described. Then, after heating, the electrodes embedded in the through holes of the upper and lower semiconductor chips are connected by fusion bonding, thereby making electrical connection between the stacked upper and lower semiconductor chips.

  Japanese Patent Laying-Open No. 2005-340389 (Patent Document 3) discloses that a stud bump electrode is formed on a semiconductor chip arranged on the upper side of stacked semiconductor chips, and a through electrode is formed on the semiconductor chip arranged on the lower side. Techniques for forming are described. Then, the stud bump electrode formed on the upper semiconductor chip is deformed and injected into the through electrode formed on the lower semiconductor chip by pressure contact, and the stud bump electrode and the through electrode are geometrically caulked to vertically The electrical connection between the semiconductor chips is performed.

  For example, in the technique disclosed in Japanese Patent Laid-Open No. 2005-340389 (Patent Document 3), a through electrode that reaches a pad formed on the front surface of the semiconductor wafer from the back surface of the semiconductor wafer is formed. In a semiconductor wafer on which a highly integrated circuit such as a microcomputer is mounted, since a wiring layer is formed in multiple layers, there is a thick interlayer insulating film on the surface of the semiconductor wafer. Therefore, in order to form a through electrode reaching the pad formed on the surface of the semiconductor wafer from the back surface of the semiconductor wafer, the thick interlayer insulating film must be processed through the hole. When a hole reaching the pad with the same diameter as the through electrode is formed as in the process proposed in Japanese Patent Laid-Open No. 2005-340389 (Patent Document 3), most of the pad supports the adjacent interlayer insulating film. The problem arises that the pad strength decreases.

  Therefore, in order to suppress a decrease in pad strength, a technique is considered in which the hole diameter is changed during the processing of the hole, and a small-diameter hole (second hole) is formed in the interlayer insulating film adjacent to the pad. In this technique, the semiconductor substrate is etched until the interlayer insulating film is exposed to form a large-diameter hole (first hole), and then the interlayer insulating film is processed to form a small-diameter hole (second hole). Form. At this time, it is necessary to form a resist mask inside the large-diameter hole (first hole). At this time, the interlayer insulating film is etched using the formed resist mask as a mask. However, in the etching of the interlayer insulating film, the resist mask is easily etched. That is, the resist mask is selectively processed as compared with the interlayer insulating film, and the resist mask disappears before the processing of the interlayer insulating film is completed. As a result, it is necessary to form a resist mask a plurality of times before the formation of small-diameter holes (second holes) in the interlayer insulating film.

  However, since the diameter of the hole (second hole) is small, the resist mask inside the hole (second hole) cannot be completely removed by cleaning, and the interlayer insulating film is processed due to multiple misalignment of the resist mask. It is difficult to form a resist mask for the second and subsequent times inside the large-diameter hole (first hole) because the bottom surface of the hole (second hole) becomes rough and exposure of the lithography process cannot be performed well. As a result, the processing state of the interlayer insulating film becomes nonuniform in the small-diameter hole (second hole), which causes a problem that the manufacturing yield of the semiconductor device is lowered.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device having a plurality of semiconductor chips stacked three-dimensionally.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to a method of manufacturing a semiconductor device according to the present invention, (a) an interlayer insulating film is formed on a semiconductor element formed on a first surface of a semiconductor substrate, and the semiconductor is connected via a wiring formed in the interlayer insulating film. Forming a pad electrically connected to the element on the surface of the interlayer insulating film; and (b) forming a first resist film on a second surface of the semiconductor substrate opposite to the first surface. (C) patterning the first resist film so as to have a first opening at a position facing the pad; and (d) masking the first resist film in which the first opening is formed. Etching the semiconductor substrate to form a first hole in the semiconductor substrate exposing the interlayer insulating film on the bottom surface; (e) removing the first resist film; and (f). Exposed on the bottom surface of the first hole Etching the interlayer insulating film to form a bottom surface of the first hole on the interlayer insulating film at a position closer to the pad than the boundary between the semiconductor substrate and the interlayer insulating film; ) Forming an insulating film on the second surface of the semiconductor substrate including the inner wall of the first hole; (h) forming a second resist film on the insulating film; and (i) the first Patterning the second resist film so as to have a second opening having a diameter smaller than the diameter of the first hole on the bottom surface of one hole; and (j) the second resist film in which the second opening is formed. Etching the insulating film and the interlayer insulating film to form a second hole exposing the pad on the bottom surface, and (k) an inner wall of the first hole and an inner wall of the second hole A conductor on the second surface of the semiconductor substrate including Forming a through electrode that reaches the first surface from the second surface of the semiconductor substrate and is electrically connected to the pad by patterning the conductive film, and The surface of the interlayer insulating film on the semiconductor substrate side has a step shape reflecting the step between the bottom surface of the first hole and the first surface of the semiconductor substrate, and the surface of the conductor film is formed on the semiconductor substrate. The step shape reflects the step difference between the second surface and the bottom surface of the first hole.

  The semiconductor device according to the present invention includes (a) a semiconductor substrate, (b) a semiconductor element formed on the first surface of the semiconductor substrate, and (c) formed on the first surface of the semiconductor substrate. An interlayer insulating film; (d) a pad formed on the interlayer insulating film; (e) a bump electrode formed on the pad; and (f) an opposite side of the first surface of the semiconductor substrate. A through electrode reaching the pad from a second surface, and the through electrode (f1) reaches the interlayer insulating film from the second surface opposite to the first surface of the semiconductor substrate. A first hole in which a bottom surface of the first hole is formed to a position closer to the pad than a boundary between the interlayer insulating film and the semiconductor substrate; and (f2) a hole diameter of the first hole. Is formed to reach the pad from the bottom surface of the first hole. (F3) an insulating film formed on the second surface of the semiconductor substrate, and (f4) a bottom surface and a side surface of the second hole, and the insulation. The semiconductor substrate of the interlayer insulating film, comprising: a bottom surface and a side surface of the first hole through the film; and a conductive film formed on the second surface of the semiconductor substrate and electrically connected to the pad. The side surface has a step shape reflecting the step between the bottom surface of the first hole and the first surface of the semiconductor substrate, and the surface of the conductor film is formed between the second surface of the semiconductor substrate and the second surface of the semiconductor substrate. It is characterized by a step shape reflecting the step due to the bottom surface of the first hole.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The manufacturing yield of a semiconductor device having a plurality of semiconductor chips that are three-dimensionally stacked can be improved.

It is a top view which shows a part of semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows the cross section cut | disconnected by the AA line of FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 14; FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 15; FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 18; FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 19; FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 20; FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; It is sectional drawing which shows the semiconductor chip in Embodiment 1, and is a figure showing the dimension of the predetermined | prescribed site | part as a variable. It is a graph which shows the predetermined relationship using the dimension shown in FIG. FIG. 28 is a cross-sectional view showing a configuration of a semiconductor chip when included in a region I shown in FIG. 27. FIG. 28 is a cross-sectional view showing a configuration of a semiconductor chip when included in a region II shown in FIG. 27. FIG. 28 is a cross-sectional view showing a configuration of a semiconductor chip when included in a region III shown in FIG. 27. FIG. 28 is a cross-sectional view illustrating a configuration of a semiconductor chip when included in a region IV illustrated in FIG. 27. 6 is a cross-sectional view showing a semiconductor device in a modification of the first embodiment. FIG. FIG. 6 is a plan view showing a part of a semiconductor chip in a second embodiment. It is sectional drawing which shows the cross section cut | disconnected by the AA line of FIG. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. 36 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 35; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the modified example of the second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the third embodiment. FIG. 39 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 38; FIG. 40 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 39; FIG. 41 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 40; FIG. 10 is a cross-sectional view showing a semiconductor device in a fourth embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

(Embodiment 1)
In the first embodiment, a semiconductor device mounted with a highly integrated circuit such as a microcomputer chip will be described as an example with reference to the drawings.

  FIG. 1 is a plan view showing a semiconductor chip according to the first embodiment. FIG. 1 is a view of a part of a semiconductor chip as viewed from above a second surface (back surface) 1b side of a semiconductor substrate 1. As shown in FIG. 1, the semiconductor chip is composed of a rectangular semiconductor substrate 1, and a plurality of through electrodes 17 are formed on the second surface 1 b of the semiconductor substrate 1. The plurality of through electrodes 17 are each connected to a wiring made of the conductor film 15, and a wiring pattern is formed on the second surface 1 b of the semiconductor substrate 1 by these wirings. As described above, in the first embodiment, a plurality of through electrodes 17 are formed in the semiconductor chip. As shown in FIG. 1, the through electrodes 17 form a double ring in a plane. It is configured. This is because, as will be described later, the penetration space by the penetration electrode 17 is formed by the first hole having a larger diameter and the second hole having a smaller diameter than the first hole.

  2 is a cross-sectional view showing a cross section taken along line AA of FIG. As shown in FIG. 2, the semiconductor substrate 1 has a flat plate shape, and has a first surface (front surface) 1a and a second surface (back surface) 1b. On the first surface 1a of the semiconductor substrate 1, a semiconductor element (not shown) (not shown) such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed, and the semiconductor substrate on which this semiconductor element is formed. An interlayer insulating film 2 is formed on one first surface 1a. In the interlayer insulating film 2, wirings connecting a plurality of semiconductor elements are formed in multiple layers, and a plurality of semiconductor elements formed on the first surface 1a of the semiconductor substrate 1 and wirings connecting these semiconductor elements are used. A highly integrated circuit is formed on the first surface 1 a of the semiconductor substrate 1. Here, the first embodiment is directed to a semiconductor chip on which a highly integrated circuit such as a microcomputer chip is formed. The feature is that the number of wiring layers increases. For this reason, there exists a tendency for the film thickness of the interlayer insulation film 2 which forms the wiring layer over a multilayer to become thick. Thus, the first embodiment is intended for a semiconductor device in which the interlayer insulating film 2 has a relatively large thickness.

  Next, a pad (electrode) 3 is formed on the uppermost surface of the interlayer insulating film 2. The pad 3 is electrically connected to the semiconductor element via a wiring formed in the interlayer insulating film 2, and the pad 3 is connected between the highly integrated circuit formed on the semiconductor substrate 1 and the outside of the semiconductor chip. Functions as an external terminal for interface. A stud bump electrode 18 is formed on the pad 3.

  On the other hand, a through electrode 17 is formed so as to penetrate from the second surface 1b of the semiconductor substrate 1 to the first surface 1a of the semiconductor substrate 1 and further through the interlayer insulating film 2 to be electrically connected to the pad 3. Yes. The through electrode 17 is required when a plurality of semiconductor chips are three-dimensionally stacked and packaged. In other words, the first embodiment is premised on the SiP structure in which semiconductor chips are stacked and packaged. In order to electrically connect semiconductor chips arranged above and below when stacking semiconductor chips. Is used. Thus, in each semiconductor chip, the stud bump electrode 18 is formed on one side of the pad 3, and the through electrode 17 is formed on the other side of the pad 3. And when laminating a plurality of semiconductor chips, the stud bump electrode 18 of the other semiconductor chip is deformed and injected into the through electrode 17 of one semiconductor chip by pressure contact and geometrically caulked, so that both semiconductors The chips are stacked up and down so as to be electrically connected. As described above, the first embodiment is based on the premise that the semiconductor chip is stacked using the through electrode 17 and the stud bump electrode 18. In the region where the through electrode 17 is formed, a semiconductor element constituting a highly integrated circuit is not formed. That is, the semiconductor element is formed on the first surface 1a of the semiconductor substrate 1, but the semiconductor element is formed in a region separated from the region where the through electrode 17 is formed.

  Next, the configuration of the through electrode 17 will be described. As shown in FIG. 2, the penetration space by the penetration electrode 17 is formed by the first hole 7 and the second hole 11. That is, the first hole 7 is formed from the second surface 1 b of the semiconductor substrate 1, and the second hole 11 having a smaller hole diameter than the first hole 7 is formed on the bottom surface of the first hole 7. The pad 3 is exposed on the bottom surface of the second hole 11. An insulating film 8 is formed on the bottom surface and side surface of the first hole 7 and the second surface 1 b of the semiconductor substrate 1, and further, the bottom surface and side surface of the second hole 11 and the first hole 7 through the insulating film 8 are formed. A seed layer 12 and a plating layer 14 are laminated and formed on the bottom and side surfaces and the second surface 1 b of the semiconductor substrate 1 with the insulating film 8 interposed therebetween. The seed layer 12 and the plating layer 14 are collectively referred to as a conductor film 15. The conductor film 15 formed on the second surface 1b of the semiconductor substrate 1 forms the wiring pattern shown in FIG. In this way, the through electrode 17 is configured. In order to insert the stud bump electrode 18 formed in another semiconductor chip to be laminated, the inside is hollow and the through space is formed in the through electrode 17. Is formed. For this reason, the conductor film 15 constituting the through electrode 17 reflects the step due to the bottom surface of the second surface 1 b and the first hole 7 of the semiconductor substrate 1 and the step due to the bottom surface of the first hole 7 and the bottom surface of the second hole 11. It has a stepped shape. In other words, according to the through electrode 17 according to the first embodiment, the inside of the first hole 7 and the second hole 11 is not configured to be completely filled with the conductor film 15, and a through space is formed inside. It is configured to be. That is, when the inside of the through electrode 17 is completely filled with the conductor film 15, the surface of the conductor film 15 coincides with the second surface 1 b of the semiconductor substrate 1 and no step is generated. On the other hand, as a result of having a configuration in which a cavity exists inside the through electrode 17, the conductor film 15 constituting the through electrode 17 has a step and a first hole due to the second surface 1 b of the semiconductor substrate 1 and the bottom surface of the first hole 7. 7 and a step shape reflecting the step formed by the bottom surface of the second hole 11.

  Next, the reason why the through electrode 17 is formed from the first hole 7 and the second hole 11 having a smaller diameter than the first hole 7 will be described. For example, the hole diameter of the first hole 7 is formed in accordance with the size of the stud bump electrode 18 to be inserted therein. However, if the through electrode 17 is composed only of the first hole 7 having a large hole diameter, the following disadvantages occur. . The through electrode 17 is configured to penetrate from the second surface 1 b of the semiconductor substrate 1 to the pad 3, but the through hole penetrating from the second surface 1 b of the semiconductor substrate 1 to the pad 3 is formed by the first hole 7. The semiconductor substrate 1 and the interlayer insulating film 2 that are removed by forming the first hole 7 increase. The pad 3 is formed on the surface of the interlayer insulating film 2. In this case, as a result of removing the interlayer insulating film 2 to which most of the pad 3 is in contact, the pad 3 loses the support by the interlayer insulating film 2, and the pad 3 The problem of lowering the strength of the material becomes obvious. Therefore, the second hole 11 having a smaller hole diameter than the first hole 7 is formed between the first hole 7 and the pad 3 without forming the through electrode 17 only by the first hole 7 having a larger hole diameter. . That is, by forming the second hole 11 having a smaller hole diameter than the first hole 7 in the interlayer insulating film 2, it is possible to reduce the interlayer insulating film 2 that is removed by forming the through electrode 17. Thereby, the interlayer insulating film 2 supporting the pad 3 can be secured, and the strength reduction of the pad 3 can be suppressed. Thus, by forming the through electrode 17 from the first hole 7 and the second hole 11 having a smaller hole diameter than the first hole 7, it is possible to suppress a decrease in strength of the pad 3. At this time, the strength reduction of the pad 3 caused by forming the through electrode 17 is a problem that occurs particularly when a cavity exists inside the through electrode 17. For example, when the inside of the through electrode 17 is embedded with the conductor film 15, the pad 3 is supported by the conductor film 15 embedded in the through electrode 17, and thus it is necessary to form the through electrode 17 with holes having different hole diameters. Absent. That is, the through electrode 17 is configured by the first hole 7 having a large hole diameter and the second hole 11 having a smaller hole diameter than the first hole 7, and the configuration in which the pad 3 is exposed on the bottom surface of the second hole 11 is the through electrode 17. It turns out that it is useful when it is the structure where the inside of is hollow. In other words, in the case where the inside of the through electrode 17 is embedded with the conductor film 15, the through electrode 17 is usefully configured by the first hole 7 having a large hole diameter and the second hole 11 having a smaller hole diameter than the first hole 7. It can be said that there is no sex.

  The structure in which the inside of the through electrode 17 is made hollow and the through electrode 17 is formed by the first hole 7 and the second hole 11 having a smaller diameter than the first hole 7 is a premise of the present invention.

  Here, there is a problem in which region the first hole 7 and the second hole 11 constituting the through electrode 17 are switched. Actually, the semiconductor substrate 1 is made of silicon, and the interlayer insulating film 2 is made of a silicon oxide film. From this, the first hole 7 is formed by etching silicon from the second surface 1b of the semiconductor substrate 1 to the first surface 1a of the semiconductor substrate 1 which is the boundary between the semiconductor substrate 1 and the interlayer insulating film 2, and thereafter The second hole 11 is formed by etching the interlayer insulating film 2 formed of the silicon oxide film until the pad 3 is exposed from the first surface 1a of the semiconductor substrate 1 which is the boundary between the semiconductor substrate 1 and the interlayer insulating film 2. Is considered common. A stud bump electrode 18 formed in another semiconductor chip is inserted into the first hole 7. However, since the thickness of the semiconductor substrate 1 is usually larger than the height of the stud bump electrode 18, the first hole 7 is a semiconductor that is a boundary between the semiconductor substrate 1 and the interlayer insulating film 2 from the second surface 1 b of the semiconductor substrate 1. There is no problem when forming up to the first surface 1 a of the substrate 1.

  Thus, silicon is etched to form the first hole 7 from the second surface 1b of the semiconductor substrate 1 to the first surface 1a of the semiconductor substrate 1 which is the boundary between the semiconductor substrate 1 and the interlayer insulating film 2, and then The second hole 11 is formed by etching the interlayer insulating film 2 formed of the silicon oxide film until the pad 3 is exposed from the first surface 1a of the semiconductor substrate 1 which is the boundary between the semiconductor substrate 1 and the interlayer insulating film 2. In this case, the following inconvenience occurs. In the first embodiment, a semiconductor chip on which a highly integrated circuit such as a microcomputer chip is formed is targeted, but the feature is that the number of wiring layers increases. For this reason, there exists a tendency for the film thickness of the interlayer insulation film 2 which forms the wiring layer over a multilayer to become thick. Thus, it is difficult to form the second hole 11 in the thick interlayer insulating film 2. The reason for this will be described.

  In order to form the second hole 11, first, the semiconductor substrate 1 made of silicon is etched to form the first hole 7, and then on the second surface 1 b of the semiconductor substrate 1 including the bottom surface of the first hole 7. An insulating film 8 is formed. Thereafter, a resist film is formed on the second surface 1 b of the semiconductor substrate 1 including the bottom surface of the first hole 7 via the insulating film 8. Then, the resist film is patterned to form an opening smaller than the diameter of the first hole 7 on the bottom surface of the first hole 7. Then, using the patterned resist film as a mask, the insulating film 8 and the interlayer insulating film 2 made of the silicon oxide film are etched to form the second hole 11. Here, when etching the insulating film 8 and the interlayer insulating film 2 made of the silicon oxide film, the resist film used as a mask is easily etched. Therefore, if the interlayer insulating film 2 is thick, the resist film disappears before the second hole 11 formed in the interlayer insulating film 2 reaches the pad 3 through the interlayer insulating film 2. Therefore, after forming a new resist film and patterning again, it is necessary to etch the interlayer insulating film 2 made of a silicon oxide film. That is, since the resist film is also etched when the second hole 11 is formed, the second hole 11 reaches the pad 3 through the interlayer insulating film 2 when the interlayer insulating film 2 is thick. Prior to this, it is necessary to form a mask with a resist film a plurality of times.

  At this time, since the hole diameter of the second hole 11 is small, the resist film inside the second hole 11 cannot be completely removed by cleaning, and further, during the processing of the interlayer insulating film 2 due to multiple mask misalignments. It is difficult to form the second and subsequent masks on the bottom surface of the first hole 7 because the bottom surface of the second hole 11 is rough and exposure in the lithography process cannot be performed well. As a result, the processing state of the interlayer insulating film 2 becomes uneven in the second hole 11, and the pad 3 may not be normally exposed on the bottom surface of the second hole 11. As a result, the through electrode 17 cannot be formed normally, and the manufacturing yield of the semiconductor device is reduced.

  Therefore, in the first embodiment, as shown in FIG. 2, the first hole 7 is formed to a position deeper than the first surface 1 a of the semiconductor substrate 1 which is the boundary between the semiconductor substrate 1 and the interlayer insulating film 2. . That is, the first hole 7 is formed not only in the semiconductor substrate 1 made of silicon but also in the middle of the interlayer insulating film 2. Thereby, the film thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 is reduced. Then, the second hole 11 is formed in the interlayer insulating film 2 having a reduced thickness. That is, one of the features of the first embodiment is that when the first hole 7 is formed, not only the semiconductor substrate 1 made of silicon but also the interlayer insulating film 2 is etched so that the bottom surface of the first hole 7 is made to be an interlayer. The point is that the insulating layer 2 is formed to a position closer to the pad 3 than the boundary between the semiconductor substrate 1 and the interlayer insulating film 2 (the first surface 1a of the semiconductor substrate 1). Thereby, for example, even in a semiconductor device having a thick interlayer insulating film 2 such as a microcomputer chip in which a highly integrated circuit is formed, the interlayer insulating film 2 to be etched to form the second hole 11 can be formed. The film thickness can be reduced.

  By forming the first hole 7 partway through the interlayer insulating film 2, the thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 can be reduced. When the second hole 11 reaching the pad 3 from the bottom surface is formed, the second hole 11 reaching the pad 3 can be formed by using the resist film mask only once. That is, the second hole 11 is formed with a film thickness that combines the interlayer insulating film 2 remaining between the bottom surface of the first hole 7 and the pad 3 and the insulating film 8 formed on the bottom surface of the first hole 7. In this case, the thickness of the second hole 11 can be formed before the first resist film used as a mask disappears. Thereby, the bottom surface of the second hole 11 is roughened during the processing of the interlayer insulating film 2 due to a plurality of misalignment of the mask, and the processing defect of the second hole 11 due to the poor exposure of the lithography process is improved. Can do. Therefore, the reliability of the through electrode 17 can be improved, and the manufacturing yield of the semiconductor device can be improved. Furthermore, since the variation in the connection between the second hole 11 and the pad 3 due to the processing failure of the interlayer insulating film 2 can be suppressed, it is possible to suppress the variation in the connection resistance between the through electrode 17 and the pad 3.

  One of the features of the first embodiment is that the thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 is increased by forming the first hole 7 partway through the interlayer insulating film 2. The structure of the semiconductor device according to the first embodiment is that the surface of the interlayer insulating film 2 in contact with the semiconductor substrate 1 is formed by the bottom surface of the first hole 7 and the first surface 1a of the semiconductor substrate 1. It becomes apparent as a structure that has a step shape reflecting the step. That is, in the region where the first hole 7 is not formed, the first surface 1a of the semiconductor substrate 1 serves as a boundary between the semiconductor substrate 1 and the interlayer insulating film 2, and in the region where the first hole 7 is formed, the first surface 1a. The bottom surface of the hole 7 becomes a boundary with the interlayer insulating film 2. In this case, since the bottom surface of the first hole 7 is formed partway through the interlayer insulating film 2 beyond the first surface 1a of the semiconductor substrate 1, the surface of the interlayer insulating film 2 in contact with the semiconductor substrate 1 has a step shape. It becomes.

  The semiconductor chip in the first embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  First, the semiconductor substrate 1 is prepared. At this time, the semiconductor substrate 1 is in a state of a substantially disk-shaped semiconductor wafer, and a plurality of chip regions are formed on the semiconductor wafer. In the following process, the semiconductor substrate 1 is processed in the state of a semiconductor wafer.

  As shown in FIG. 3, a plurality of semiconductor elements (not shown) are formed on the first surface 1a of the semiconductor substrate 1 using a normal MISFET forming technique, and the first surface of the semiconductor substrate 1 on which the semiconductor elements are formed. An interlayer insulating film 2 is formed on 1a. The interlayer insulating film 2 is formed from, for example, a silicon oxide film. A plurality of wirings (not shown) are formed in the interlayer insulating film 2 to connect a plurality of semiconductor elements with the wirings. Then, a pad 3 that is electrically connected to the semiconductor element via a wiring formed inside the interlayer insulating film 2 is formed on the surface of the interlayer insulating film 2. The pad 3 is formed from, for example, an aluminum film.

  When the semiconductor substrate 1 is thinned to about 10 μm to 50 μm, for example, the depth of a through electrode formed in a process described later becomes shallow and the difficulty of processing decreases. However, the strength of the semiconductor substrate 1 accompanying the thinning of the semiconductor substrate 1 decreases. The yield and yield decrease due to warpage of the semiconductor substrate 1 occur.

  Therefore, in the first embodiment, as shown in FIG. 4, the adhesive layer 4 is applied to the surface of the interlayer insulating film 2 on which the pads 3 are formed, and a support substrate made of, for example, quartz, glass, a silicon substrate, or the like. 5 and the semiconductor substrate 1 are bonded together. By bonding the support substrate 5 to the semiconductor substrate 1, it is possible to suppress a decrease in strength due to the thinning of the semiconductor substrate 1 and warpage of the semiconductor substrate 1. The adhesive layer 4 has a function of bonding the support substrate 5 and the semiconductor substrate 1 and also has a function of protecting the integrated circuit formed on the semiconductor substrate 1.

  Next, as shown in FIG. 5, the back grinding process is performed on the second surface 1 b of the semiconductor substrate 1 to reduce the thickness of the semiconductor substrate 1. The back grinding process can be performed by grinding or polishing. Since the flatness after the back grinding process affects the accuracy of the through electrode formed on the second surface 1b of the semiconductor substrate 1, after the back grinding process is performed, dry polishing, etching, or CMP (Chemical Mechanical Polishing) method is performed. It is desirable to planarize the second surface 1b of the semiconductor substrate 1 by performing polishing according to the above.

  Subsequently, as shown in FIG. 6, a resist film 6 is applied on the second surface 1 b of the semiconductor substrate 1. Then, the resist film 6 is patterned by using a photolithography technique. The patterning is performed so as to form an opening 6 a at a position facing the pad 3 of the resist film 6. As a method for applying the resist film 6 on the second surface 1b of the semiconductor substrate 1, for example, a spinner application method can be used. Furthermore, the position where the opening 6a is formed when patterning the resist film 6 is determined by confirming the pattern (device pattern) of the semiconductor element formed on the first surface 1a of the semiconductor substrate 1 with an infrared microscope. To do. Then, the semiconductor substrate 1 made of silicon is etched using the patterned resist film 6 as a mask.

That is, as shown in FIG. 7, the first hole 7 reaching the interlayer insulating film 2 from the second surface 1b of the semiconductor substrate 1 made of silicon is formed. This etching is anisotropic etching, and is performed by, for example, ICP-RIE (Inductively coupled plasma Reactive ion etching). As the etching gas, SF ₆ and C ₄ H ₈ are used. Usually, in dry etching of silicon, a silicon oxide film serves as an etching stopper. Therefore, in the etching using SF ₆ and C ₄ H ₈ , the etching stops at the interlayer insulating film 2 containing the silicon oxide film as a main component. The depth of the first hole 7 at this time is determined by the thickness of the semiconductor substrate 1.

Next, as shown in FIG. 8, after removing the patterned resist film 6, the etching gas is changed from SF ₆ and C ₄ H ₈ to C ₃ F ₈ , Ar, CHF without forming a mask with a new resist film. ₄ is used to etch the interlayer insulating film 2 exposed to the bottom surface of the first hole 7 halfway. That is, the semiconductor substrate 1 made of silicon and the interlayer insulating film 2 exposed on the bottom surface of the first hole 7 are etched using the first hole 7 formed in the semiconductor substrate 1 as a mask. Thereby, the film thickness of the interlayer insulating film 2 existing between the bottom surface of the first hole 7 and the pad 3 can be reduced. That is, the purpose is to perform the step of etching the semiconductor substrate 1 made of silicon intentionally and the interlayer insulating film 2 exposed on the bottom surface of the first hole 7 using the first hole 7 formed in the semiconductor substrate 1 as a mask. This is one of the features of the first embodiment. By intentionally etching the interlayer insulating film 2 using the first hole 7 as a mask, the interlayer insulating film has a hole diameter equal to the hole diameter (see FIG. 7) at the bottom surface of the first hole 7 formed in the semiconductor substrate 1 made of silicon. Etching 2 progresses. For this reason, as shown in FIG. 8, the bottom surface of the first hole 7 formed by etching the interlayer insulating film 2 is substantially equal to the bottom surface of the first hole 7 formed by etching silicon shown in FIG. It becomes a hole diameter. By performing this step, in the region where the first hole 7 is not formed, the first surface 1a of the semiconductor substrate 1 becomes the boundary between the semiconductor substrate 1 and the interlayer insulating film 2, and the first hole 7 is formed. In the region that is formed, the bottom surface of the first hole 7 becomes a boundary with the interlayer insulating film 2. In this case, since the bottom surface of the first hole 7 is formed partway through the interlayer insulating film 2 beyond the first surface 1a of the semiconductor substrate 1, the surface of the interlayer insulating film 2 in contact with the semiconductor substrate 1 has a step shape. Become.

  By intentionally etching the interlayer insulating film 2 exposed from the first hole 7 halfway, the thickness of the interlayer insulating film 2 existing between the bottom surface of the first hole 7 and the pad 3 can be reduced. As well as the following effects.

  In the step of forming the first hole 7 by etching the semiconductor substrate 1 made of silicon, over-etching is performed in order to completely expose the bottom surface of the first hole 7. That is, a plurality of first holes 7 are formed in the semiconductor substrate 1. At this time, there may be a difference in etching rate depending on where the first holes 7 are formed. For example, the etching proceeds sufficiently in the first hole 7 formed in a certain region, and the interlayer insulating film 2 is exposed on the bottom surface of the first hole 7, but the etching is performed in the first hole 7 formed in another certain region. Is insufficient, and the interlayer insulating film 2 is not exposed. In this case, if over-etching is not performed, silicon remains on the bottom surface of the first hole 7 where etching of silicon is insufficient. Then, there is a possibility that a normal through electrode cannot be formed thereafter. Therefore, by performing over-etching, silicon is completely removed even at the bottom surface of the first hole 7 in a region where etching is insufficient, so that the interlayer insulating film 2 is exposed at the bottom surface of the first hole 7.

  However, when over-etching is performed, there is a problem that a notch is generated in the first hole 7 where etching is sufficiently advanced. That is, when the silicon is further etched in the first hole 7 where the etching is sufficiently advanced, the interlayer insulating film 2 serving as an etching stopper is exposed at the bottom surface of the first hole 7, so that the etching is performed in the depth direction. Does not progress. However, silicon is eroded in the lateral direction (side direction) from the bottom surface of the first hole 7 to generate a notch. If the notch is generated, the semiconductor device is defective.

  Here, in the first embodiment, the first hole 7 is formed by etching the semiconductor substrate 1 made of silicon, and then the interlayer insulating film 2 is etched using the first hole 7 as a mask so as to have the same diameter. The first hole 7 is formed. Accordingly, even if the semiconductor substrate 1 made of silicon is not over-etched, the silicon remaining on the bottom surface of the first hole 7 where etching of the silicon is insufficient due to the etching of the interlayer insulating film 2 using the first hole 7 as a mask. Can also be removed. That is, the silicon slightly remaining on the bottom surface of the first hole 7 is also removed during the etching of the interlayer insulating film 2 whose main component is a silicon oxide film. From this, it is possible to suppress over-etching in the step of forming the first hole 7 by etching the semiconductor substrate 1 made of silicon. As described above, according to the first embodiment, since over-etching can be suppressed, it is possible to suppress the occurrence of a notch in the first hole 7 where etching is sufficiently advanced.

  Further, according to the first embodiment, another effect can be obtained. For example, when the semiconductor substrate 1 is processed, problems such as stress generated in the semiconductor substrate 1 and warping in the semiconductor substrate 1 are likely to occur. However, the first embodiment intentionally includes a step of etching the interlayer insulating film 2 exposed on the bottom surface of the first hole 7 using the first hole 7 formed in silicon as a mask without using the resist film as a mask. Have been implemented. Thus, when dry etching is performed in a state where silicon is exposed without using a resist film, the stress generated in the semiconductor substrate 1 can be relieved (stress relief effect).

  Subsequently, as illustrated in FIG. 9, the insulating film 8 is formed on the second surface 1 b of the semiconductor substrate 1 including the inside of the first hole 7 by, for example, a CVD (Chemical Vapor Deposition) method. The insulating film 8 is formed so as to cover these surfaces along the bottom surface and side surfaces of the first hole 7 and the second surface 1 b of the semiconductor substrate 1. The insulating film 8 has a function of insulating a through electrode described later and the semiconductor substrate 1. As the insulating film 8, for example, a silicon oxide film, a silicon nitride film, or a polyimide resin is used.

  Next, as shown in FIG. 10, an aluminum film 9 is formed on the insulating film 8 formed on the second surface 1 b of the semiconductor substrate 1 including the inside of the first hole 7. The aluminum film 9 is a film provided to protect the insulating film 8, and can be formed by, for example, a sputtering method or a vapor deposition method.

  Subsequently, as shown in FIG. 11, a resist film 10 is applied on the aluminum film 9 formed on the second surface 1 b of the semiconductor substrate 1 including the inside of the first hole 7. For example, as a resist film coating method, there are a spinner coating method and a spray coating method. In the case of a spinner coating method, it is desirable to use a resist film 10 that can be applied to a thickness of 5 μm to 30 μm in order to apply the resist film 10 along the bottom and side surfaces of the first hole 7. Furthermore, if bubbles remain in the resist film 10, the exposure process in the photolithography technique becomes difficult and patterning defects occur. Therefore, it is desirable to remove bubbles in the resist film 10 by vacuum defoaming. In the case of the application method by spraying, unlike the application method by a spinner, the resist film 10 is applied along the first hole 7.

  Thereafter, as shown in FIG. 12, the resist film 10 is patterned using a photolithography technique. The patterning of the resist film 10 is performed so as to form an opening 10 a on the bottom surface of the first hole 7. The diameter of the opening 10 a is formed to be smaller than the diameter of the first hole 7. The aluminum film 9 is exposed from the opening 10a.

  Next, as shown in FIG. 13, the aluminum film 9 exposed from the opening 10a formed in the resist film 10 is removed by etching. As a result, the insulating film 8 formed under the aluminum film 9 is exposed in the opening 10a. For the etching of the aluminum film 9, for example, an etching solution mainly containing phosphoric acid or dilute hydrofluoric acid can be used.

Subsequently, as shown in FIG. 14, the insulating film 8 exposed from the opening 10a and the interlayer insulating film 2 formed under the insulating film 8 are all removed by etching. Thereby, the second hole 11 having a diameter smaller than the hole diameter of the first hole 7 can be formed on the bottom surface of the first hole 7. The pad 3 is exposed on the bottom surface of the second hole 11. For etching the insulating film 8 and the interlayer insulating film 2, a mixed gas mainly containing CHF ₃ or C ₄ H ₈ is used as an etching gas. In this etching process, the resist film 10 is also slightly etched.

  Here, in the first embodiment, by forming the first hole 7 partway through the interlayer insulating film 2 as shown in FIG. 8, the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 is formed. The film thickness is reduced. Therefore, when the second hole 11 reaching the pad 3 from the bottom surface of the first hole 7 is formed, the second hole 11 reaching the pad 3 can be formed by using the mask of the resist film 10 only once. . In other words, the second hole 11 is formed with the total thickness of the interlayer insulating film 2 remaining between the bottom of the first hole 7 and the pad 3 and the insulating film 8 formed on the bottom surface of the first hole 7. In this case, the thickness of the second hole 11 can be formed before the first resist film 10 used as a mask disappears. Thereby, the bottom surface of the second hole 11 is roughened during the processing of the interlayer insulating film 2 due to a plurality of misalignment of the mask, and the processing defect of the second hole 11 due to the poor exposure of the lithography process is improved. Can do.

  Next, as shown in FIG. 15, the patterned resist film 10 is removed. The removal of the resist film 10 is performed by using an organic solvent or oxygen ashing, for example. Then, as shown in FIG. 16, the aluminum film 9 for protecting the insulating film formed under the resist film 10 is removed. At this time, a pad 3 made of an aluminum film is formed at the bottom of the second hole 11, but since a barrier conductor film such as a titanium / titanium nitride film is usually formed on the surface of the pad 3, the pad 3 Is not etched.

  Subsequently, as shown in FIG. 17, the bottom surface and the side surface of the second hole 11, the bottom surface and the side surface of the first hole 7 through the insulating film 8, and further the second surface of the semiconductor substrate 1 through the insulating film 8. A seed layer 12 is formed on 1b. The seed layer 12 can be formed by using, for example, a sputtering method. As the seed layer 12, for example, a laminated film composed of a titanium film (Ti film) and a gold film (Au film) can be considered. At this time, the titanium film is formed with a thickness of about 0.02 μm to 0.3 μm in order to ensure adhesion between the insulating film 8 and the gold film, and the gold film is used as a base film (electrode film) of the plating film. The thickness should be about 0.3 μm to 2 μm. As the seed layer 12, in addition to a laminated film of a titanium film and a gold film, for example, a laminated film of a chromium film (Cr film) and a gold film may be used.

  Next, as shown in FIG. 18, after the resist film 13 is applied, the resist film 13 is patterned by using a photolithography technique. The patterning is performed so as to expose the wiring formation region in the first hole 7 and the second hole 11 and on the second surface 1b of the semiconductor substrate 1.

  Subsequently, as shown in FIG. 19, a plating film 14 is formed on the seed layer 12 exposed from the patterned resist film 13. The plating film 14 can be formed by, for example, an electrolytic plating method. As a result, the conductor film 15 composed of the seed layer 12 and the plating film 14 can be formed in the first hole 7 and the second hole 11 and further in the wiring formation region on the second surface 1 b of the semiconductor substrate 1. The thickness of the plating film 14 is preferably 1 μm or more in consideration of electric resistance. However, since the inner diameter of the through electrode is determined by the thickness of the plating film 14, the inner diameter of the through electrode becomes a predetermined diameter. Adjust as follows. The plating film 14 is formed of, for example, a gold film, and can be formed by an electroless plating method or a sputtering method in addition to the electrolytic plating method. In addition to the gold film, a laminated film of a gold film and a copper film (Cu film) is also conceivable as the plating film 14, but from the viewpoint of the SiP structure in which semiconductor chips are laminated, the surface of the plating film 14 is a gold film. It is desirable.

  Thereafter, as shown in FIG. 20, the resist film 13 is removed by using an organic solvent or oxygen ashing. Then, as shown in FIG. 21, after a resist film 16 is applied onto the second surface 1b of the semiconductor substrate 1, the resist film 16 is patterned by a photolithography technique. The patterning of the resist film 16 is performed so as to cover the first hole 7, the second hole 11, and the wiring formation region formed in the second surface 1 b of the semiconductor substrate 1.

  Next, as shown in FIG. 22, the seed layer 12 exposed from the patterned resist film 16 is removed. Since the seed layer 12 is composed of a laminated film of a titanium film and a gold film, each film is removed using an etching solution for the titanium film and an etching solution for the gold film. As an etching solution for the gold film, for example, a mixed solution of iodine and ammonium iodide can be considered, and as an etching solution for the titanium film, for example, hydrofluoric acid can be considered. It may be a solution.

  Subsequently, as shown in FIG. 23, by removing the patterned resist film 16, the processing of the semiconductor substrate 1 in the semiconductor wafer state is completed. Thereby, the through electrode 17 connected to the pad 3 can be formed. Then, as shown in FIG. 24, the support substrate 5 that supports the semiconductor substrate 1 is peeled off. For example, if the adhesive layer 4 that bonds the semiconductor substrate 1 and the support substrate 5 has thermoplastic properties, the semiconductor substrate 1 and the support substrate 5 are heated by heating the semiconductor substrate 1. Peel off. After the semiconductor substrate 1 is peeled off from the support substrate 5, the semiconductor substrate 1 in a semiconductor wafer state is divided into semiconductor chips by dicing. Although the semiconductor chip can be separated into individual pieces, the semiconductor substrate 1 can be attached to the support substrate 5. However, the support substrate 5 is cut and the support substrate 5 can be reused. become unable. Therefore, when the semiconductor substrate 1 is peeled off from the support substrate 5, the semiconductor substrate 1 is thin, so that handling (transport) becomes difficult. However, by removing the support substrate 5 and dicing, the support substrate 5 can be reused. Become.

  Finally, as shown in FIG. 25, in the separated semiconductor chip, the stud bump electrode 18 is formed on the pad 3 formed on the surface of the interlayer insulating film 2 by, for example, the stud bump method. As a method of forming the bump electrode, a solder paste bump method, a plating method, a vapor deposition method, or the like can be used.

  In this manner, the semiconductor chip in the first embodiment can be formed. According to the first embodiment, the first hole 7 is formed partway through the interlayer insulating film 2 beyond the semiconductor substrate 1 made of silicon, so that the interlayer insulation between the bottom surface of the first hole 7 and the pad 3 is formed. The film 2 is made thin. For this reason, when forming the 2nd hole 11 which reaches the pad 3 from the bottom face of the 1st hole 7, since the film thickness of the interlayer insulation film 2 is thin, a manufacturing process becomes easy. Specifically, when the second hole 11 reaching the pad 3 from the bottom surface of the first hole 7 is formed in the interlayer insulating film 2, the number of resist masks that open the interlayer insulating film 2 can be reduced. For this reason, it is possible to reduce processing defects of the interlayer insulating film 2 due to misalignment of the masks a plurality of times. In the plurality of through electrodes 17 having the first hole 7 and the second hole 11 as the through space, the interlayer insulating film 2 By making the film thinner, the through electrode 17 can be uniformly processed.

  Thus, the reliability of the through electrode 17 can be improved, and the manufacturing yield of the semiconductor device can be improved. Furthermore, since the variation in the connection between the second hole 11 and the pad 3 due to the processing failure of the interlayer insulating film 2 can be suppressed, it is possible to suppress the variation in the connection resistance between the through electrode 17 and the pad 3.

  In addition, since variations in processing can be reduced in the formation process of the through electrode 17, the process margin is increased and the manufacturing yield of the semiconductor device is improved.

  Further, since the first hole 7 having a large diameter is not formed so as to reach the pad 3, the second hole 11 having a diameter smaller than that of the first hole 7 is formed and connected to the pad 3. A large amount of the interlayer insulating film 2 that supports the pad 3 can be left, and the strength reduction of the pad 3 can be suppressed. That is, the reliability at the time of forming the stud bump electrode 18 on the pad 3 can be improved.

  In the first embodiment, when the second hole 11 reaching the pad 3 from the bottom surface of the first hole 7 is formed, the film thickness of the interlayer insulating film 2 is reduced, so that the processing process is facilitated. For this reason, the advantage which can improve a manufacturing yield in the formation process of the 2nd hole 11 is acquired. On the other hand, since the thickness of the interlayer insulating film 2 existing between the first hole 7 and the pad 3 becomes thin, there is a concern that the strength of the interlayer insulating film 2 that supports the pad 3 is lowered. However, even if the thickness of the interlayer insulating film 2 is reduced as in the first embodiment, the thickness of the conductor film 15 formed on the bottom and side surfaces of the second hole 11, the interlayer insulating film 2 and the first hole 7, the thickness of the insulating film 8 formed on the bottom portion 7 and the hole diameter of the second hole 11 satisfy a predetermined relationship, so that a decrease in the strength of the pad 3 can be suppressed, and the stud bump electrode 18 can be normally formed on the pad 3. Will be described.

  FIG. 26 is a cross-sectional view showing the semiconductor chip according to the first embodiment, and represents the dimensions of predetermined portions as variables. Specifically, the film thickness of the conductor film 15 (the film in which the plating film 14 and the seed layer 12 are combined) formed on the bottom surface and the side surface of the second hole 11 is a, and between the first hole 7 and the pad 3. The film thickness of the interlayer insulating film 2 existing and the film thickness of the insulating film 8 formed on the bottom surface of the first hole 7 (hereinafter referred to as the bottom insulating film) is b. Furthermore, the hole diameter of the second hole 11 is c.

  FIG. 27 is a graph showing the relationship between the variables a, b, and c shown in FIG. In FIG. 27, the horizontal axis indicates the film thickness (a) of the conductor film 15 with respect to the total film thickness (a + b). The vertical axis (left side) shows the film thickness (b) of the bottom insulating film (interlayer insulating film 2 and insulating film 8) relative to the total film thickness (a + b), and the vertical axis (right side) shows the total film thickness. The hole diameter (c) of the 2nd hole 11 with respect to (a + b) is shown. As shown in FIG. 27, four regions including a region where the stud bump electrode 18 can be normally formed on the pad 3 and a region where the stud bump electrode 18 cannot be normally formed on the pad 3 according to the values of the variables a, b and c. It can be seen that it can be classified into (region I to region IV). In FIG. 27, the film thickness of the pad 3 is determined by the design rule, and therefore is considered as a constant film thickness.

  First, the region I will be described. FIG. 28 is a diagram showing a configuration of a semiconductor chip when the relationship between variables a, b, and c is included in region I. FIG. 28 shows that the film thickness a of the conductor film 15 is sufficiently thick with respect to the hole diameter c of the second hole 11 and that the film thickness b of the bottom insulating film is sufficient to maintain the strength of the pad 3. ing. Therefore, it can be seen that the stud bump electrode 18 can be normally formed on the pad 3 in the configuration included in the region I.

  Subsequently, the region II will be described. FIG. 29 is a diagram showing a configuration of a semiconductor chip when the relationship between the variables a, b, and c is included in the region II. In the configuration of the semiconductor chip shown in FIG. 29, the film thickness b of the bottom insulating film is sufficient to maintain the strength of the pad 3, but the conductor film 15 with respect to the hole diameter c of the second hole 11. The film thickness a is thin. For this reason, when the stud bump electrode 18 is pressed onto the pad 3, the conductor film 15 is deformed and the electrical connection between the stud bump electrode 18 and the conductor film 15 becomes poor. Therefore, it can be seen that the stud bump electrode 18 cannot be normally formed on the pad 3 in the configuration included in the region II.

  Next, the region III will be described. FIG. 30 is a diagram showing the configuration of the semiconductor chip when the relationship between the variables a, b, and c is included in the region III. In the configuration of the semiconductor chip shown in FIG. 30, the film thickness a of the conductor film 15 is sufficiently thick with respect to the hole diameter c of the second hole 11, but the film thickness b of the bottom insulating film is thin. For this reason, when the stud bump electrode 18 is pressed onto the pad 3, the pad 3 is not sufficiently supported by the bottom insulating film, and a crack 19 is generated in the interlayer insulating film 2 constituting the bottom insulating film. Therefore, it can be seen that the stud bump electrode 18 cannot be normally formed on the pad 3 in the configuration included in the region III.

  Subsequently, the region IV will be described. FIG. 31 is a diagram showing a configuration of the semiconductor chip when the relationship between the variables a, b, and c is included in the region IV. In the configuration of the semiconductor chip shown in FIG. 31, the film thickness a of the conductor film 15 is thinner than the hole diameter c of the second hole 11, and the film thickness b of the bottom insulating film is also thinner. For this reason, when the stud bump electrode 18 is pressed onto the pad 3, the conductor film 15 is deformed, resulting in poor electrical connection between the stud bump electrode 18 and the conductor film 15, and the pad 3 formed by the bottom insulating film. This is not sufficient, and a crack 19 is generated in the interlayer insulating film 2 constituting the bottom insulating film. Therefore, it can be seen that the stud bump electrode 18 cannot be normally formed on the pad 3 in the configuration included in the region IV.

  From the above, it can be seen that the region I must include the relationship between the variables a, b, and c in order to normally form the stud bump electrode 18 on the pad 3. For this reason, in the first embodiment, the first hole 7 is formed so as to extend partway through the interlayer insulating film 2 beyond the semiconductor substrate 1 made of silicon, whereby an interlayer between the bottom surface of the first hole 7 and the pad 3 is formed. While taking the configuration in which the film thickness of the insulating film 2 is reduced, the dimensions of the respective parts are defined so that the relationship between the variables a, b, and c is included in the region I. As a result, the process of forming the second hole 11 can be facilitated, and the stud bump electrode 18 can be normally formed on the pad 3 while maintaining sufficient strength of the pad 3. Specifically, as can be seen from FIG. 27, the film thickness of the conductive film 15 formed on the pad 3 which is the bottom surface of the second hole 11 is a, and the film is formed between the bottom surface of the first hole 7 and the pad 3. When the total thickness of the interlayer insulating film 2 and the thickness of the insulating film 8 formed on the bottom surface of the first hole 7 is b, at least the value of a / (a + b) is 0. It can be seen that the strength of the pad 3 can be sufficiently ensured by configuring it to be .11 or more.

  Here, in the first embodiment, as shown in FIG. 26, a configuration in which the conductor film 15 is formed on the bottom surface and the side surface of the second hole 11 and a cavity exists inside the second hole 11 will be described. ing. However, as shown in FIG. 32, the conductor film 15 can be formed so as to fill the inside of the second hole 11 having a small hole diameter by increasing the film thickness of the conductor film 15. In this case, since the pad 3 is supported by the conductor film 15 embedded in the second hole 11 together with the interlayer insulating film 2, further reduction in the strength of the pad 3 can be suppressed. At this time, it goes without saying that the inside of the first hole 7 having a larger hole diameter than the second hole 11 is a cavity for inserting the stud bump electrode 18 formed in another semiconductor chip.

(Embodiment 2)
In the first embodiment, a semiconductor chip in which a highly integrated circuit is formed such as a microcomputer chip has been described. In the second embodiment, a semiconductor chip for performing rewiring such as an interposer chip will be described.

  For example, when a plurality of semiconductor chips are stacked three-dimensionally, a stud bump electrode formed on another semiconductor chip disposed above is deformed and inserted into a through electrode formed on the semiconductor chip disposed below. By doing so, the upper and lower semiconductor chips are electrically connected. At this time, the semiconductor chip disposed on the upper side and the semiconductor chip disposed on the lower side often have different functions in which separate integrated circuits are formed. Therefore, the upper and lower semiconductor chips have different layout patterns. For this reason, the position of the through electrode of the semiconductor chip disposed below and the position of the stud bump electrode of the semiconductor chip disposed above are not necessarily aligned. In this case, the semiconductor chip inserted between the upper and lower semiconductor chips is an interposer chip. That is, in the interposer chip, a through electrode is formed so as to match the formation position of the stud bump electrode of the semiconductor chip disposed above, and the semiconductor chip disposed on the interposer chip is connected to the interposer chip. Then, in the interposer chip, a wiring connected to the above-described through electrode is formed, and a stud bump electrode connected to this wiring is formed so as to be aligned with a position where the through electrode of the lower semiconductor chip is formed. Thereby, the stud bump electrode formed on the interposer chip and the through electrode formed on the lower semiconductor chip are connected. In this way, the arrangement position of the stud bump electrode formed on the semiconductor chip disposed on the upper side and the arrangement position of the through electrode formed on the semiconductor chip disposed on the lower side are shifted. However, the upper and lower semiconductor chips can be electrically connected by sandwiching the interposer chip between the upper and lower semiconductor chips.

  Next, the configuration of the interposer chip will be described with reference to the drawings. The interposer chip in the second embodiment and the semiconductor chip in the first embodiment have substantially the same configuration. FIG. 33 is a plan view showing a semiconductor chip according to the second embodiment. FIG. 33 is a view of a part of the semiconductor chip as viewed from above on the second surface (back surface) 1 b side of the semiconductor substrate 1. As shown in FIG. 33, the semiconductor chip is composed of a rectangular semiconductor substrate 1, and a plurality of through electrodes 17 are formed on the second surface 1 b of the semiconductor substrate 1. The plurality of through electrodes 17 are each connected to a wiring made of the conductor film 15, and a wiring pattern is formed on the second surface 1 b of the semiconductor substrate 1 by these wirings.

  34 is a cross-sectional view showing a cross section taken along line AA of FIG. As shown in FIG. 34, the difference between the semiconductor chip in the second embodiment and the semiconductor chip in the first embodiment shown in FIG. 2 is that the formation position of the through electrode 17 and the stud bump electrode are different in the second embodiment. The formation position of 18 is different from the opposing position. This is a case where the arrangement position of the stud bump electrode formed on the semiconductor chip arranged on the upper side and the arrangement position of the through electrode formed on the semiconductor chip arranged on the lower side are shifted. The upper and lower semiconductor chips can be electrically connected by sandwiching the interposer chip according to the second embodiment between the upper and lower semiconductor chips. The through electrode 17 and the stud bump electrode 18 are electrically connected by the pad 3 and the wiring. However, the formation position of the through electrode 17 and the formation position of the stud bump electrode 18 may be the same.

  Furthermore, the difference between a semiconductor chip on which a highly integrated circuit is formed, such as a microcomputer chip, and an interposer chip is the film thickness of the interlayer insulating film 2. A semiconductor chip on which a highly integrated circuit is formed, such as a microcomputer chip, has many wirings and the interlayer insulating film 2 is thick. On the other hand, since the interposer chip in the second embodiment is intended for rewiring, the wiring formed inside the interlayer insulating film 2 is a single layer, and the film thickness of the interlayer insulating film 2 is relatively There is a feature that becomes thinner. Other configurations are substantially the same as those of the first embodiment.

  The interposer chip in the second embodiment is configured as described above, and the manufacturing method thereof will be described below. The manufacturing method in the second embodiment is also the same as that in the first embodiment, and the characteristic points will be mainly described. As shown in FIGS. 3 to 7, a first hole 7 reaching the interlayer insulating film 2 from the second surface 1 b of the semiconductor substrate 1 is formed. Thereafter, as shown in FIG. 35, the resist film 6 formed on the second surface 1b of the semiconductor substrate 1 is removed. Here, in the second embodiment, the film thickness of the interlayer insulating film 2 is thinner than that in the first embodiment, but from the viewpoint of further facilitating the processing process of the second hole, for example, as shown in FIG. In addition, the semiconductor substrate 1 made of silicon and the interlayer insulating film 2 exposed to the bottom surface of the first hole 7 may be etched halfway using the first hole 7 formed in the semiconductor substrate 1 as a mask. That is, the second embodiment may have the same steps as in the first embodiment.

  On the other hand, in the second embodiment, if the thickness of the interlayer insulating film 2 is sufficiently thin and there is no problem even in the processing process of the second hole, the etching of the interlayer insulating film 2 is performed as shown in FIG. It is not necessary to do.

  Thereafter, the steps shown in FIGS. 9 to 24 are performed. Then, as shown in FIG. 34, the stud bump electrode 18 is formed at a position different from the position facing the through electrode 17. However, the stud bump electrode 18 may be formed at a position facing the through electrode 17. In this way, the interposer chip according to the second embodiment can be formed. According to the second embodiment, since the interlayer insulating film 2 is sufficiently thin, after the first hole 7 is formed in the semiconductor substrate 1 made of silicon, the interlayer insulating film exposed on the bottom surface of the first hole 7 is formed. It is not always necessary to etch 2. However, in terms of facilitating the processing of the second hole 11, that is, when the interlayer insulating film has a film thickness that cannot form the second hole 11 by a single photolithography technique, the first hole It is desirable to further reduce the thickness of the interlayer insulating film 2 by etching the interlayer insulating film 2 exposed on the bottom surface of the halfway partway. As described above, the present invention can flexibly cope with the thickness of the interlayer insulating film 2 formed on the semiconductor substrate 1. In the second embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
In the first embodiment, an example in which the insulating film 8 is used is described. In the third embodiment, an example in which a photosensitive insulating film is used instead of the insulating film 8 will be described. Below, the manufacturing method of the semiconductor chip in this Embodiment 3 is demonstrated.

  The first holes 7 reaching the interlayer insulating film 2 from the second surface 1b of the semiconductor substrate 1 are formed by performing the steps shown in FIGS. Then, as shown in FIG. 38, after removing the resist film 6, the semiconductor substrate 1 made of silicon and the first hole 7 formed in the semiconductor substrate 1 are used as a mask to expose the interlayer insulation exposed on the bottom surface of the first hole 7. The film 2 is etched halfway.

  Next, as shown in FIG. 39, a photosensitive insulating film 8 a is formed on the second surface 1 b of the semiconductor substrate 1 including the inside of the first hole 7. The photosensitive insulating film 8 a is formed so as to cover these surfaces along the bottom and side surfaces of the first hole 7 and the second surface 1 b of the semiconductor substrate 1. The photosensitive insulating film 8a has a function of insulating a through electrode described later and the semiconductor substrate 1 from each other.

  Subsequently, as shown in FIG. 40, the photosensitive insulating film 8a is patterned by using a photolithography technique. The patterning is performed so as to form the opening 10 a on the bottom surface of the first hole 7. As an exposure apparatus in the photolithography technique, a stepper apparatus, a laser exposure apparatus, or the like is used.

  Thereafter, as shown in FIG. 41, all the interlayer insulating film 2 exposed from the opening 10a is removed by etching. Thereby, the second hole 11 having a diameter smaller than the hole diameter of the first hole 7 can be formed on the bottom surface of the first hole 7. The pad 3 is exposed on the bottom surface of the second hole 11.

  Here, in Embodiment 3, the first hole 7 is formed partway through the interlayer insulating film 2 as shown in FIG. 38, so that the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 is formed. The film thickness is reduced. Therefore, when the second hole 11 reaching the pad 3 from the bottom surface of the first hole 7 is formed, the second hole 11 reaching the pad 3 is formed only by using the mask of the photosensitive insulating film 8a once. Can do. In other words, the film thickness of the interlayer insulating film 2 remaining between the bottom of the first hole 7 and the pad 3 is set so that the photosensitive insulating film 8a used as a mask disappears when the second hole 11 is formed. The film thickness can be such that the second hole 11 can be formed.

  Then, the semiconductor chip in this Embodiment 3 can be manufactured by implementing the process shown in FIGS.

  The feature of the third embodiment is that a photosensitive insulating film 8a is used. In the first embodiment, after the insulating film 8 and the aluminum film 9 are formed in the first hole 7, the resist film 10 is formed on the aluminum film 9. Then, after forming the opening 10a in the resist film 10, the aluminum film 9, the insulating film 8 and the interlayer insulating film 2 exposed from the opening 10a are etched to reach the pad 3 from the bottom surface of the first hole 7. Two holes 11 are formed. Here, the insulating film 8 has a function of insulating the through electrode 17 and the semiconductor substrate 1, and the resist film 10 has a function of forming the opening 10a. Therefore, in the third embodiment, the photosensitive insulating film 8a is used as a film having the functions of the insulating film 8 and the resist film 10 described above. In the first embodiment, a process for forming the insulating film 8 and the resist film 10 is required. In the third embodiment, these processes can be replaced with a process for forming the photosensitive insulating film 8a. That is, according to the third embodiment, there is an advantage that the manufacturing process of the semiconductor chip can be simplified. The advantage that the process can be simplified by using the photosensitive insulating film 8a is that the thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3, which is one of the features of the present invention, is reduced. It becomes realizable by using together with a process.

  That is, although the photosensitive insulating film 8a has low etching resistance, the film thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3 is reduced, so that before the photosensitive insulating film 8a disappears. In addition, the second hole 11 can be formed in the interlayer insulating film 2.

  The photosensitive insulating film 8 a is a film that substitutes for the insulating film 8 and needs to remain on the semiconductor substrate 1 even after the second hole 11 is formed. That is, it is necessary that the photosensitive insulating film 8a is not lost by etching the interlayer insulating film 2 using the photosensitive insulating film 8a as a mask. In consideration of this point, the photosensitive insulating film 8a can be obtained by adding a step of reducing the film thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3, which is one of the features of the present invention. Usefulness is born. For example, when the photosensitive insulating film 8a is used in order to simplify the process, the film thickness of the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3, which is one of the features of the present invention, is reduced. If this step is not performed, the thick interlayer insulating film 2 is etched, and the photosensitive insulating film 8a having low etching resistance disappears during the etching of the thick interlayer insulating film 2, and the photosensitive insulating film The advantage of using 8a is lost.

  From the above, the advantage of simplification of the process caused by using the photosensitive insulating film 8a is the interlayer insulating film 2 between the bottom surface of the first hole 7 and the pad 3, which is one of the features of the present invention. It is obtained by carrying out the process of reducing the film thickness of the film. An advantage of using the photosensitive insulating film 8a is that only the interlayer insulating film 2 needs to be etched when the second hole 11 is formed. That is, in the case of the first embodiment, it is necessary to etch the portion of the insulating film 8 and the interlayer insulating film 2 existing under the resist film 10, but in the third embodiment, the photosensitive property is required. Since the insulating film 8a itself serves as a mask, when forming the second hole 11, only the interlayer insulating film 2 formed below the photosensitive insulating film 8a has to be etched. Therefore, since the film thickness of the film to be removed when processing the second hole 11 is reduced, the processing step of the second hole 11 is further facilitated. In the third embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 4)
In the fourth embodiment, for example, a SiP structure semiconductor device in which the semiconductor chips manufactured in the first to third embodiments are three-dimensionally stacked will be described.

  FIG. 42 is a cross-sectional view showing the semiconductor device according to the fourth embodiment. As shown in FIG. 42, for example, a semiconductor chip 20a composed of a microcomputer chip and a semiconductor chip 20c composed of an SDRAM are three-dimensionally stacked via a semiconductor chip 20b serving as an interposer chip for performing rewiring. Yes. The three stacked semiconductor chips 20 a to 20 c are mounted on the wiring board 21.

  A semiconductor chip 20a composed of a microcomputer chip is a semiconductor chip on which a highly integrated circuit is formed, and a through electrode 17a and a stud bump electrode 18a are formed. Similarly, the semiconductor chip 20c made of SDRAM is a semiconductor chip on which a highly integrated circuit is formed, and a through electrode 17c and a stud bump electrode 18c are formed. On the other hand, the semiconductor chip 20b is an interposer chip, and a through electrode 17b and a stud bump electrode 18b are formed. The semiconductor chip 20a is mounted on the wiring substrate 21 so as to electrically connect the stud bump electrode 18a formed on the semiconductor chip 20a and the electrode 22 formed on the wiring substrate 21. Further, a semiconductor chip 20b is mounted on the semiconductor chip 20a. At this time, the electrical connection between the semiconductor chip 20a and the semiconductor chip 20b is performed by inserting the stud bump electrode 18b formed in the semiconductor chip 20b into the through electrode 17a formed in the semiconductor chip 20a. Yes. Further, a semiconductor chip 20c is mounted on the semiconductor chip 20b. The electrical connection between the semiconductor chip 20b and the semiconductor chip 20c is performed by inserting the stud bump electrode 18c formed in the semiconductor chip 20c into the through electrode 17b formed in the semiconductor chip 20b. Yes.

  A solder bump electrode 23 is formed on the surface of the wiring substrate 21 opposite to the surface on which the semiconductor chips 20a to 20c are mounted. The solder bump electrode 23 is electrically connected to the electrode 22 through the inside of the wiring board. The solder bump electrode 23 has a function as an external terminal for electrical connection with the outside of the semiconductor device.

  Further, a sealing adhesive 24 is formed so as to fill a gap between the wiring substrate 21 and the semiconductor chips 20a to 20c. The sealing adhesive 24 has a function of enhancing the mechanical strength of the semiconductor device, improving the handling property in the assembly process of the semiconductor device, and protecting the semiconductor device from the external environment.

  The semiconductor device according to the fourth embodiment is configured as described above, and a method for stacking the semiconductor chips 20a to 20c will be described below.

  For example, the first semiconductor wafer is used as the semiconductor substrate, and the processing described in the first embodiment is performed on the individual chip regions on the first semiconductor wafer to form the individual chip regions on the first semiconductor wafer. A through electrode 17a (first through electrode) that is electrically connected to the formed first pad is formed. Thereafter, the first semiconductor wafer is divided into a plurality of semiconductor chips to obtain the semiconductor chip 20a (first semiconductor chip). In the semiconductor chip 20a, the stud bump electrode 18a is formed on the first pad opposite to the side connected to the through electrode 17a.

  Similarly, the second semiconductor wafer is used as the semiconductor substrate, and the processing described in the second embodiment is performed on the individual chip regions on the second semiconductor wafer, so that the individual chip regions on the second semiconductor wafer are processed. A through electrode 17b (second through electrode) that is electrically connected to the formed second pad is formed. Thereafter, the second semiconductor wafer is divided into a plurality of semiconductor chips to obtain the semiconductor chip 20b (second semiconductor chip). Then, in the semiconductor chip 20b, the stud bump electrode 18b is formed on the second pad opposite to the side connected to the through electrode 17b.

Subsequently, the semiconductor chip 20b is stacked on the semiconductor chip 20a and electrically connected. This step is performed by deforming and injecting the stud bump electrode 18b formed on the semiconductor chip 20b into the through electrode 17a formed on the semiconductor chip 20a by pressure contact.
Thus, after forming the semiconductor chip 20a and the semiconductor chip 20b, respectively, a semiconductor device can be formed by stacking. The same applies when the semiconductor chip 20c is stacked on the semiconductor chip 20b.

  Next, another method for stacking the semiconductor chips 20a to 20c will be described. For example, by performing the processing described in the first embodiment on the individual chip regions in the first semiconductor wafer, it is electrically connected to the first pads formed in the individual chip regions of the first semiconductor wafer. After the through electrode 17a to be formed is formed, the stud bump electrode 18a is formed on the first pad opposite to the side connected to the through electrode 17a. Thus, the stud bump electrode 18a can be formed in the state of the semiconductor wafer.

  Similarly, the processing described in the second embodiment is performed on the individual chip regions in the second semiconductor wafer to electrically apply the second pads formed in the individual chip regions of the second semiconductor wafer. After forming the through electrode 17b to be connected, the stud bump electrode 18b is formed on the second pad opposite to the side connected to the through electrode 17b.

  Thereafter, the second semiconductor wafer is stacked on the first semiconductor wafer and electrically connected. This step is performed by deforming and implanting the stud bump electrode 18b formed on the second semiconductor wafer into the through electrode 17a formed on the first semiconductor wafer by pressure contact. Thus, it can also laminate | stack in the state of a semiconductor wafer.

  Next, the first semiconductor wafer and the second semiconductor wafer are separated into semiconductor chips in a stacked state. Thereby, a laminated structure of the semiconductor chip 20a and the semiconductor chip 20b can be obtained. The same applies when the semiconductor chip 20c is stacked on the semiconductor chip 20b.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Finally, Patent Document 4 (Japanese Patent Laid-Open No. 2005-93486) and the present invention will be compared. In Patent Document 4 and the present invention, the through electrode is formed by the first hole and the second hole having a smaller diameter than the first hole, and the interlayer insulating film exposed at the bottom surface of the first hole is etched. Seems to be similar. However, in Patent Document 4, the inside of the through electrode is completely filled with the conductor film, whereas the present invention is different in that a cavity is formed inside the through electrode. This difference is a big difference. That is, the present invention employs a structure in which a plurality of semiconductor chips are stacked by deforming and injecting stud bump electrodes into the through electrodes. For this reason, a space for injecting the stud bump electrode is required inside the through electrode. Therefore, a first hole for inserting the stud bump electrode is formed in the through electrode. At this time, the first hole can be formed so as to reach the pad from the through electrode. However, if the first hole having a large hole diameter is formed so as to reach the pad, the interlayer insulating film supporting the pad is removed, and the strength reduction of the pad becomes obvious. Therefore, in the present invention, the first hole is formed partway through the semiconductor substrate, and the second hole having a smaller hole diameter than the first hole is formed as a hole reaching the pad from the bottom surface of the first hole. Thereby, a sufficient interlayer insulating film can be left around the second hole, and a decrease in the strength of the pad can be prevented. Thus, the technical idea of forming the through electrode by the first hole and the second hole is effective as a solution to the problem of a decrease in pad strength that occurs because the inside of the through electrode is a cavity. Furthermore, the problem of a decrease in pad strength becomes a problem when stud bump electrodes are formed on the pad. That is, the configuration of the present invention is premised on the configuration in which the stud bump electrode is formed on the pad.

  On the other hand, in Patent Document 4, the through electrode is formed by the first hole and the second hole having a smaller hole diameter than the first hole, but the inside of the through electrode is filled with a conductor film. Therefore, since the strength of the pad is supported by the conductor film filled in the through electrode, there is no problem that the strength of the pad is lowered in the first place. Furthermore, since the stud bump electrode is not formed on the pad, there is no problem of pad strength. That is, the through electrode is formed by the first hole and the second hole having a smaller hole diameter than the first hole, but neither the purpose nor the effect is described or suggested in Patent Document 4. In Patent Document 4, since the insulating film is formed on the side surface of the first hole, and then the second hole is processed, only the film thickness of the insulating film formed on the side surface of the first hole is obtained. It is considered that the hole diameter of the second hole is only small. That is, in the present invention, the second hole smaller than the hole diameter of the first hole is intentionally a hole reaching the pad from the bottom surface of the first hole regardless of the film thickness of the insulating film formed on the side surface of the first hole. Is formed. From this, it is considered that there is no description in Patent Document 4 that motivates the present invention easily.

  Subsequently, the present invention is characterized in that the interlayer insulating film exposed on the bottom surface of the first hole is etched to control to intentionally reduce the film thickness of the interlayer insulating film. By controlling the thickness of the interlayer insulating film existing between the first hole and the pad in this way, the second hole formed by etching the interlayer insulating film can be easily processed. The advantage that the reliability of forming the hole can be improved is obtained.

  On the other hand, Patent Document 4 is similar in that the interlayer insulating film exposed on the bottom surface of the first hole is etched, but in Patent Document 4, the hard mask used when forming the first hole is removed. At this time, the interlayer insulating film exposed to the bottom surface of the first hole is also etched. That is, in Patent Document 4, there is no description or suggestion of the technical idea of intentionally etching the interlayer insulating film exposed on the bottom surface of the first hole to control the film thickness, and the present invention is easily conceived. There seems to be no description that motivates them to do so.

  As described above, it is considered that Patent Document 4 discloses a configuration that is seemingly similar to the present invention. However, when examined in detail, the present invention and Patent Document 4 are completely different technical ideas. It is clear that there is no description in 4 that will motivate the present invention easily. Therefore, even those skilled in the art will find it difficult to easily come up with the present invention from the description in Patent Document 4.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a 1st surface 1b 2nd surface 2 Interlayer insulating film 3 Pad 4 Adhesive layer 5 Support substrate 6 Resist film 6a Opening 7 First hole 8 Insulating film 8a Photosensitive insulating film 9 Aluminum film 10 Resist film 10a Opening 11 Second hole 12 Seed layer 13 Resist film 14 Plating film 15 Conductor film 16 Resist film 17 Through electrode 17a Through electrode 17b Through electrode 17c Through electrode 18 Stud bump electrode 18a Stud bump electrode 18b Stud bump electrode 18c Stud bump electrode 19 Crack 20a Semiconductor chip 20b Semiconductor chip 20c Semiconductor chip 21 Wiring board 22 Electrode 23 Solder bump electrode 24 Sealing adhesive

Claims (4)

A semiconductor substrate;
An interlayer insulating film formed on the first surface of the semiconductor substrate;
A pad formed on the interlayer insulating film;
A hole reaching the interlayer insulating film from a second surface opposite to the first surface of the semiconductor substrate;
An insulating film formed on a side surface of the hole;
A conductor member formed on the bottom and side surfaces of the hole through the insulating film and electrically connected to the pad;
A semiconductor device in which a bottom surface of the hole is formed to a position closer to the pad than a boundary between the interlayer insulating film and the semiconductor substrate. The semiconductor device according to claim 1,
A semiconductor device comprising another hole that is smaller than the hole diameter of the hole and formed from a bottom surface of the hole to a position closer to the pad. The semiconductor device according to claim 2,
The hole is a semiconductor device having a hollow inside. The semiconductor device according to claim 1,
A semiconductor device comprising a bump electrode on the pad.

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