JP2012114312A - Tape carrier for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tape carrier for a semiconductor device capable of: suppressing a short circuit between semiconductor device bonding bumps and between the semiconductor device bonding bump and a wiring; and facilitating pitch miniaturization.SOLUTION: A tape carrier for a semiconductor device comprises an insulating substrate 10 having a first principal surface S1 on which a wiring 21 is formed and a second principal surface S2 on which a plurality of semiconductor device bonding bumps 31 are formed. Each semiconductor device bonding bump 31 is disposed independently in a dispersed state on the second principal surface S2 and is electrically connected to the wiring 21 on the first principal surface S1 through a via 12 which pierces the insulating substrate 10.

Description

  The present invention relates to a tape carrier for a semiconductor device including a bump for bonding a semiconductor device.

  The tape carrier for semiconductor devices is a tape carrier for semiconductor devices such as TAB (Tape Automated Bonding) method and TCP (Tape Carrier Package) method, in which a wiring pattern is formed on a flexible insulating substrate with copper foil. These are referred to as TAB tapes). Currently, TAB tape is used in some applications such as IC packages and is mass-produced.

  As shown in the cross-sectional view of FIG. 5A1, the TAB tape described above includes, for example, semiconductor device bonding bumps 531 on the same side as the surface on which the wiring 521 of the insulating substrate 510 is formed. The bonding bump 531 was physically bonded to the bonding pad 620 and the like included in the semiconductor device 610. FIG. 5 (a2) shows a cross-sectional view of the TAB tape as viewed from the direction perpendicular to the cross section of FIG. 5 (a1). The semiconductor device bonding bumps 531 are formed on the wiring 521 by metal plating or the like after the wiring 521 is formed on the insulating substrate 510, for example. For example, Patent Document 1 and Patent Document 2 disclose bumps formed by plating gold (Au) or an alloy of gold and copper (Cu).

  In recent years, the need for a TAB tape having a high conduction speed has been increased in response to the increase in frequency corresponding to the improvement in characteristics of semiconductor devices. For this reason, for example, a two-metal TAB tape (double-sided wiring tape) in which wiring is formed on both surfaces of an insulating substrate provided in the TAB tape has come to be used.

JP 2006-324635 A JP 2008-288327 A

  However, the conventional TAB tape in which the wiring and the semiconductor device bonding bump as described above are formed on the same surface of the insulating substrate has some problems. For example, in a conventional TAB tape, sufficient clearance cannot be obtained between semiconductor device bonding bumps. For example, when the semiconductor device bonding bumps are displaced with respect to the wiring, as shown in FIG. In some cases, the semiconductor device bonding bumps 531a and 531b contact each other, or the semiconductor device bonding bumps 531d and the wiring 521c come into contact with each other.

  In particular, when the bumps for joining a semiconductor device are formed by metal plating as described above, the conductor material used for plating grows radially from the wiring surface, and thus grows laterally from the wiring side surface. For this reason, when designing the wiring of the TAB tape, it has been necessary to set the clearance in consideration of the lateral growth of the bumps for bonding the semiconductor device. Such a problem became more prominent when the fine pitch of the TAB tape progressed, and hindered the fine pitch.

  An object of the present invention is to provide a tape carrier for a semiconductor device that can suppress a short circuit between semiconductor device bonding bumps or between a semiconductor device bonding bump and a wiring, and facilitates a fine pitch.

  According to the first aspect of the present invention, the semiconductor device bonding bump includes an insulating substrate having a first main surface on which wiring is formed and a second main surface on which a plurality of semiconductor device bonding bumps are formed. A tape carrier for a semiconductor device which is arranged in a distributed manner on the second main surface, and is electrically connected to the wiring on the first main surface through vias penetrating the insulating substrate. Provided.

  According to the second aspect of the present invention, the wiring and the bump for joining a semiconductor device are formed by patterning the metal thin films formed on the first main surface and the second main surface, respectively. A tape carrier for a semiconductor device according to the first aspect is provided.

  According to a third aspect of the present invention, there is provided the semiconductor device tape carrier according to the first or second aspect, wherein each of the bumps for joining a semiconductor device has a substantially uniform height and width.

  According to a fourth aspect of the present invention, there is provided the semiconductor device tape carrier according to any one of the first to third aspects, wherein the semiconductor device bonding bump has a substantially flat bonding surface.

  According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the bump for joining the semiconductor device and the wiring on the first main surface are made of the same conductor material. A tape carrier is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device tape carrier which suppresses the short circuit between bumps for semiconductor device joining, or the bump for semiconductor device joining and wiring, and becomes easy to make a fine pitch is provided.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows a part of tape carrier for semiconductor devices which concerns on one Embodiment of this invention, Comprising: (a1) is the perspective view seen from the 1st main surface side of the insulating board | substrate, (a2) is an insulating board | substrate. It is the perspective view seen from the 2nd main surface side of this, (b) is sectional drawing showing a part of AA cross section of (a1), (c) is one of the BB cross sections of (a1). It is sectional drawing showing a part. It is a figure which shows a mode that a semiconductor device is mounted in the tape carrier for semiconductor devices which concerns on one Embodiment of this invention, (a1) is the perspective view seen from the 2nd main surface side of an insulating board | substrate, (a2) is It is the perspective view seen from the 1st main surface side of an insulating board | substrate, (b) is sectional drawing showing a part of AA cross section of (a2), (c) is BB of (a2). It is sectional drawing showing a part of cross section. It is process drawing which shows each process of the manufacturing method of the tape carrier for semiconductor devices which concerns on one Embodiment of this invention with sectional drawing of the same direction side as the AA cross section of FIG. 1 (a1). It is process drawing which shows each process of the manufacturing method of the tape carrier for semiconductor devices which concerns on one Embodiment of this invention with sectional drawing on the same direction side as the BB cross section of FIG. 1 (a1). (A1) is sectional drawing which shows the tape carrier for semiconductor devices which concerns on a prior art example, (a2) is sectional drawing of the tape carrier for semiconductor devices seen from the orthogonal | vertical direction with respect to the cross section of (a1), (b) These are sectional drawings explaining the subject of the tape carrier for semiconductor devices which concerns on a prior art example.

<One Embodiment of the Present Invention>
Below, the tape carrier for semiconductor devices which concerns on one Embodiment of this invention is demonstrated.

(1) Structure of Tape Carrier for Semiconductor Device First, the structure of a TAB tape as a tape carrier for a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a view showing a part of a TAB tape according to this embodiment, wherein (a1) is a perspective view seen from the first main surface side of the insulating substrate, and (a2) is a first view of the insulating substrate. 2 is a perspective view seen from the main surface side, (b) is a sectional view showing a part of the AA section of (a1), (c) is a part of the BB section of (a1). It is sectional drawing represented. The TAB tape according to the present embodiment is a long film having flexibility, and extends in the long direction in the horizontal direction of the BB cross section of FIG. .

  As shown in FIG. 1, the TAB tape includes an insulating substrate 10 having, for example, a first main surface S1 on which wirings 21 are formed and a second main surface S2 on which a plurality of semiconductor device bonding bumps 31 are formed. Yes. The insulating substrate 10 is made of a flexible resin, for example, polyimide (PI) having a thickness of 20 μm to 50 μm. In the insulating substrate 10, vias 12 in which, for example, copper (Cu) is filled in via holes penetrating the insulating substrate 10 are formed. On the first main surface S1 side, the via 12 is filled to the same height as the upper surface of the wiring 21 formed on the insulating substrate 10, and the side surface of the via 12 protruding from the surface of the insulating substrate 10 and the wiring 21. The side is in close contact. On the second main surface S 2 side, the via 12 is filled to the same height as the surface of the insulating substrate 10, and the back surface of the semiconductor device bonding bump 31 formed on the insulating substrate 10 and the lower end of the via 12. The part is in close contact. In this way, the wiring 21 on the first main surface S1 side and the semiconductor device bonding bump 31 on the second main surface S2 side are electrically connected via the via 12.

  The wiring 21 formed on the first main surface S1 of the insulating substrate 10 has, for example, a width (line width) of the wiring 21 and a width (space width) between the wirings 21 of 30 μm (L / S = 30 μm / 30 μm), respectively. It is arranged to become. The wiring 21 is made of, for example, copper as a conductor material. The thickness of the wiring 21 is 12 μm to 18 μm, for example. The wiring 21 is covered with an insulating protective film 60 at the main part except for a part thereof. For the insulating protective film 60, for example, a solder resist having a thickness of 20 μm to 50 μm made of urethane resin, epoxy resin, or the like is used. The insulating protective film 60 can protect the wiring 21 from, for example, a short circuit due to adhesion of a metal foreign object or the like. In FIG. 1A1, the insulating protective film 60 is illustrated in a state of being floated on the wiring 21 in order to clearly show the structure of the wiring 21 and the like.

  The semiconductor device bonding bumps 31 formed on the second main surface S2 of the insulative substrate 10 are independently and dispersedly arranged on the second main surface S2. The bump 31 for joining a semiconductor device is made of, for example, copper as a conductor material. The bump 31 for joining a semiconductor device is formed in a rectangular shape having a height of 10 μm or more and a size of 40 μm × 40 μm, for example. As described above, the semiconductor device bonding bump 31 is electrically connected to the wiring 21 of the first main surface S <b> 1 through the via 12.

  The exposed surface of the wiring 21 that is not covered with the insulating protective film 60 and the surface of the bump 31 for bonding the semiconductor device are covered with plating thin films 72 and 73, respectively. The plated thin films 72 and 73 are made of, for example, tin (Sn) -based metal or gold (Au). In the case of the gold plated thin films 72 and 73, for example, the thickness can be 1.0 μm or less, preferably 0.2 μm to 0.5 μm. As a result, the exposed portion of the wiring 21 and the semiconductor device bonding bump 31 are protected.

  As described above, in the TAB tape according to this embodiment, the wiring 21 and the semiconductor device bonding bump 31 are formed on different surfaces of the insulating substrate 10. Thus, since the semiconductor device bonding bump 31 and the wiring 21 are formed physically separated from each other, the semiconductor device bonding bump 31 and the wiring 21 do not come into contact with each other and are short-circuited.

  The TAB tape according to the present embodiment is configured as a one-metal TAB tape having the wiring 21 on one surface (first main surface S1) of the insulating substrate 10 and the other surface (first surface) of the insulating substrate 10. The semiconductor device bonding bumps 31 are arranged on the two main surfaces S2) to form a two-metal structure. Thereby, compared with the conventional 1 metal TAB tape in which the wiring and the bumps for bonding the semiconductor device are formed on the same surface of the insulating substrate, the arrangement of the wiring 21 and the bumps 31 for bonding the semiconductor device can be afforded. The contact / short circuit between the bumps 31 for wiring and between the wirings 21 can be further suppressed.

  Further, since there is a margin in the arrangement of the wirings 21 and the semiconductor device bonding bumps 31, it is easy to achieve a fine pitch while suppressing contact / short-circuiting between the semiconductor device bonding bumps 31 and the wirings 21.

  Thus, for example, in the portion of the wiring 21, L / S = 30 μm / 30 μm or less, and the fine pitch between the semiconductor device bonding bumps 31 and between the semiconductor device bonding bumps 31 and the wiring 21 is 20 μm or less. A TAB tape can be easily obtained.

(2) Method for Mounting Semiconductor Device Next, a method for mounting a semiconductor device on a TAB tape according to an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a view showing a state in which a semiconductor device is mounted on a TAB tape according to an embodiment of the present invention, (a1) is a perspective view seen from the second main surface side of the insulating substrate, (a2) FIG. 4 is a perspective view of the insulating substrate as viewed from the first main surface side, (b) is a cross-sectional view showing a part of the AA cross section of (a2), and (c) is a cross-sectional view of B- of (a2). It is sectional drawing showing a part of B cross section.

  As shown in FIG. 2A1, when the semiconductor device 110 is mounted on the TAB tape, the second main surface S2 of the TAB tape, that is, the surface on which the semiconductor device bonding bumps 31 are formed faces upward. Then, the TAB tape is placed on the stage 200 of the semiconductor device mounting apparatus (not shown).

  On the other hand, as shown in FIG. 2A2, when the TAB tape is placed on the stage 200, the first main surface S1 side comes into contact with the stage 200. However, the semiconductor device bonding bumps 31 are not formed on the first main surface S1 side, and the semiconductor device bonding bumps 31 can be prevented from coming into contact with the stage 200 and being deformed.

  After the TAB tape is placed on the stage 200, the semiconductor device 110 is held above the TAB tape in the semiconductor device mounting apparatus with the surface having the bonding pad 120 made of, for example, aluminum facing down, and is opposed to each other. After positioning the semiconductor device bonding bumps 31 and the bonding pads 120, the semiconductor device bonding bumps 31 and the bonding pads 120 are brought into contact with each other. In this state, ultrasonic vibration is applied while applying pressure from one or both sides of the first main surface S1 side of the TAB tape or the surface side opposite to the bonding pad 120 of the semiconductor device 110. Thereby, as shown in FIGS. 2B and 2C, the semiconductor device bonding bumps 31 and the bonding pads 120 are bonded, and the semiconductor device 110 is mounted on the TAB tape.

(3) Manufacturing Method of Semiconductor Device Tape Carrier Next, a manufacturing method of a TAB tape as a semiconductor device tape carrier according to an embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a process diagram showing each process of the TAB tape manufacturing method according to the present embodiment in a sectional view on the same direction side as the AA section in FIG. FIG. 4 is a process diagram showing each process of the TAB tape manufacturing method according to the present embodiment in a sectional view on the same direction side as the BB section in FIG. In addition, each process shown by (a)-(m) of FIG. 3 respond | corresponds with each process shown by (a)-(m) of FIG.

  In the manufacturing method according to the present embodiment, as shown in FIGS. 3A and 4A, for example, a copper foil 20 as a metal thin film is formed on the first main surface S1, and the second main surface S2. It implements with respect to the insulated substrate 10 in which the copper foil 30 as a metal thin film was formed on it. The thicknesses of the copper foils 20 and 30 can be, for example, 12 μm to 18 μm, respectively. However, the copper foil 30 may have a thickness capable of forming a semiconductor device bonding bump 31 described later at a height of 10 μm or more. That's fine.

(Via formation process)
First, as shown in FIGS. 3B and 4B, a via hole 11 is formed in the insulating substrate 10 described above. That is, for example, a laser is irradiated from the first main surface S1 side of the insulating substrate 10 to penetrate the copper foil 20 and the insulating substrate 10, and the back surface of the copper foil 30 (the surface on the insulating substrate 10 side) is exposed. The via hole 11 is formed. As will be described later, semiconductor device bonding bumps 31 are formed mainly corresponding to the positions of the via holes 11.

  Next, as shown in FIG. 3C and FIG. 4C, the via hole 11 is filled with copper from the back surface side of the copper foil 30 toward the first main surface S1 side by, for example, copper plating. 12 is formed. As a result, the back surface of the copper foil 30 and the lower end of the via 12 are brought into close contact with each other. On the first main surface S1 side, the via 12 is filled up to the same height as the upper surface of the copper foil 20, and the side surface of the via 12 protruding from the surface of the insulating substrate 10 is penetrated by the laser. Fill with copper until the 20 side faces are in close contact.

(Wiring formation process)
Subsequently, the wiring 21 is formed on the first main surface S1. That is, as shown in FIGS. 3D and 4D, for example, a photosensitive dry film 40 is laminated on the copper foil 20 and the via 12 on the first main surface S1 side. Next, as shown in FIGS. 3 (e) and 4 (e), the photosensitive dry film 40 is exposed and developed to be opened, and a photosensitive film comprising a line portion (unopened portion) and a space portion (opening portion). The conductive dry film pattern 41 is formed. At this time, some of the line portions are arranged on the via 12. Using this photosensitive dry film pattern 41 as a mask, the copper foil 20 is patterned using, for example, an etching solution, and as shown in FIGS. 3 (f) and 4 (f), for example, a wiring of L / S = 30 μm / 30 μm 21 is formed. At this time, some of the wirings 21 are formed so as to partially include the protruding portions of the vias 12. After the wiring 21 is formed, the photosensitive dry film pattern 41 is removed as shown in FIGS. 3 (g) and 4 (g).

(Semiconductor device bonding bump formation process)
Subsequently, semiconductor device bonding bumps 31 are formed on the second main surface S2. That is, as shown in FIGS. 3 (h) and 4 (h), for example, a photosensitive dry film 50 is laminated on the copper foil 30 on the second main surface S2 side. Next, as shown in FIGS. 3 (i) and 4 (i), the photosensitive dry film 50 is exposed and developed to be opened to form a photosensitive dry film pattern 51. Using the photosensitive dry film pattern 51 as a mask, the copper foil 30 is patterned using, for example, an etching solution, and as shown in FIGS. 3 (j) and 4 (j), for example, the height is 10 μm or more and the dimensions are A bump 31 for bonding a semiconductor device having a rectangle of 40 μm × 40 μm is formed. At this time, the semiconductor device bonding bump 31 is mainly formed by forming the semiconductor device bonding bump 31 on the portion that is electrically connected to the wiring 21 of the first main surface S1, that is, on the via 12 formed earlier. Are arranged in a distributed manner independently on the second main surface S2. After the formation of the bump 31 for bonding the semiconductor device, the photosensitive dry film pattern 51 is removed as shown in FIGS. 3 (k) and 4 (k).

(Insulating protective film / plated thin film forming process)
Next, as shown in FIGS. 3L and 4L, an insulating protective film 60 is formed on the main portion of the wiring 21 by applying, for example, a solder resist. Then, as shown in FIGS. 3 (m) and 4 (m), the exposed surface of the wiring 21 and the surface of the bump 31 for bonding the semiconductor device are plated with gold, for example, a thickness of 1.0 μm or less, preferably 0. Plated thin films 72 and 73 of 2 μm to 0.5 μm are formed, respectively. In this way, for example, the plating thin films 72 and 73 are prevented so that the plating thin films 72 and 73 are brought into contact with each other and no contact / short circuit occurs between the semiconductor device bonding bumps 31 or between the semiconductor device bonding bumps 31 and the wiring 21. Is a very thin film as described above. As described above, the TAB tape according to this embodiment is manufactured.

  As described above, in this embodiment, the semiconductor device bonding bumps 31 are formed by, for example, the same process as the wiring 21, that is, by patterning the copper foil 30. Thus, by forming both the semiconductor device bonding bump 31 and the wiring 21 by a patterning method having excellent microfabrication, the positional accuracy of the semiconductor device bonding bump 31 with respect to the wiring 21 is improved, and the semiconductor device bonding is performed. The positional deviation of the bumps 31 can be suppressed, and a fine pitch can be easily achieved.

  In the prior art, wirings and semiconductor device bonding bumps are formed by different processes of patterning and metal plating, respectively. For this reason, when forming the wiring, it is necessary to consider the position tolerance when forming the bumps for bonding the semiconductor device, and it is difficult to obtain a high degree of positional accuracy. In particular, due to the problem of metal plating processing accuracy, there may be variations in the diameter and height of the formed semiconductor device bonding bumps. If the diameters of the semiconductor device bonding bumps vary, the intervals between the semiconductor device bonding bumps become uneven. Further, when the height of the bonding surface (top surface) of the bump for bonding the semiconductor device varies, bonding failure with the semiconductor device occurs.

  Further, when the semiconductor device bonding bump is formed by conventional metal plating or the like, the plating material spreads radially from the surface of the wiring, and a spherical semiconductor device bonding bump is formed. For this reason, even if a patterning technique with high microfabrication is used at the time of wiring formation, the wiring pitch takes into consideration the growth of the plating material laterally from the wiring side surface when plating bumps for bonding semiconductor devices. I had to.

  Further, when a semiconductor device bonding bump formed in a spherical shape by metal plating is bonded to a bonding pad of a semiconductor device, the top surface of the semiconductor device bonding bump is curved, so that the bonding with the bonding pad is curved. In some cases, bonding is caused at the apex, resulting in poor bonding due to a large bonding area.

  However, according to the present embodiment, the semiconductor device bonding bumps 31 are formed by patterning the copper foil 30 in the same manner as when the wirings 21 are formed, so that the fine workability is improved. Becomes substantially uniform. Thus, the semiconductor device bonding bumps 31 and the wirings 21 can be kept at a predetermined interval, and a short circuit due to contact between the respective members can be suppressed. Similarly, the heights of the bumps 31 for bonding the semiconductor device are also substantially uniform, and can be more reliably bonded to the bonding pad 120 of the semiconductor device 110.

  Further, unlike the case of using metal plating, the wiring pitch can be set without taking the lateral growth into consideration, and the fine pitch of the TAB tape is facilitated.

  Further, the top surface (bonding surface) of the bump 31 for bonding a semiconductor device, which is a bonding surface with the semiconductor device 110, is substantially flat, and a large bonding area can be obtained. Therefore, the bonding pad 120 of the semiconductor device 110 can be more reliably bonded.

(4) Effects According to One Embodiment According to the present embodiment, at least one or a plurality of effects described below can be obtained.

  According to the present embodiment, the semiconductor device bonding bump includes the insulating substrate 10 having the first main surface S1 on which the wiring 21 is formed and the second main surface S2 on which the plurality of semiconductor device bonding bumps 31 are formed. 31 are arranged in a distributed manner independently on the second main surface S2, and are electrically connected to the wiring 21 on the first main surface S1 through the vias 12 penetrating the insulating substrate 10. Thereby, short-circuiting between the semiconductor device bonding bumps 31 or between the semiconductor device bonding bumps 31 and the wiring 21 can be suppressed. Therefore, the fine pitch of the TAB tape can be easily achieved.

  In addition, according to the present embodiment, the wiring 21 and the semiconductor device bonding bumps 31 are arranged on each side of the insulating substrate 10 to form a two-metalized TAB tape. Thereby, there is a margin in the arrangement of the wirings 21 and the semiconductor device bonding bumps 31, and a short circuit between the semiconductor device bonding bumps 31 and the wirings 21 can be further suppressed. In addition, fine pitch can be easily achieved.

  In addition, according to the present embodiment, when the semiconductor device 110 is mounted on the TAB tape, the second main surface S2 on which the semiconductor device bonding bumps 31 are not formed exclusively contacts the stage 200 of the semiconductor device mounting device. It is. Therefore, deformation of the semiconductor device bonding bump 31 can be suppressed.

  According to the present embodiment, the wiring 21 and the semiconductor device bonding bump 31 are formed by patterning the copper foils 20 and 30 formed on the first main surface S1 and the second main surface S2, respectively. Yes. Thereby, the positional accuracy of the semiconductor device bonding bumps 31 with respect to the wiring 21 is improved, and the positional deviation of the semiconductor device bonding bumps 31 can be suppressed.

  In addition, according to the present embodiment, by forming the semiconductor device bonding bumps 31 by patterning the copper foil 30, the widths of the semiconductor device bonding bumps 31 are substantially uniform, A short circuit between the wirings 21 can be suppressed.

  Further, according to the present embodiment, by forming the semiconductor device bonding bumps 31 by patterning the copper foil 30, the heights of the respective semiconductor device bonding bumps 31 become substantially uniform, and the semiconductor device 110 is more reliably connected. Bonding with the bonding pad 120 is possible.

  Further, according to the present embodiment, by forming the semiconductor device bonding bump 31 by patterning the copper foil 30, the bonding surface (top surface) of the semiconductor device bonding bump 31 corresponding to the bonding surface with the semiconductor device 110 is substantially reduced. It becomes flat and can be more reliably bonded to the bonding pad 120 of the semiconductor device 110. Therefore, the mounting accuracy, stability, and reliability of the semiconductor device 110 can be improved.

  Further, according to this embodiment, the semiconductor device bonding bumps 31 and the wirings 21 are made of the same conductor material and are formed by the same process. Thereby, the material and manufacturing process of a TAB tape can be made common, the structure of a TAB tape can be simplified, and a manufacturing process can be simplified. Therefore, the material cost and manufacturing cost of the TAB tape can be reduced.

<Other embodiments>
As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, It can change variously in the range which does not deviate from the summary.

For example, in the above-described embodiment, the semiconductor device bonding bump 31 and the wiring 21 are made of copper. However, the invention is not limited to this, and the semiconductor device bonding bump 31 and the wiring 21 can be formed by a patterning method using the above-described etching solution or the like. Any other material may be used as long as it is a suitable material. In filling the vias 12, a material other than copper or a method other than plating may be used.

  In the above-described embodiment, the insulating substrate 10 is made of polyimide (PI) or the like, but is not limited thereto. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS). ), Polyamideimide (PAI), liquid crystal polymer (LCP), aramid, glass epoxy resin, or other organic resin.

  Further, in the above-described embodiment, the via hole 11 is formed by laser irradiation. However, etching using a chemical solution, punching by pressing, push-cutting by a pinnacle blade (including Thomson blade and engraving blade), and the like. Thus, the via hole 11 can be formed. Or some of these methods may be combined. When the via hole 11 is formed by punching, first, the copper foil 30 may be formed after the via hole 11 is provided by punching on the insulating substrate 10 on which only one of the copper foils, for example, only the copper foil 20 is formed.

  In the above-described embodiment, the pattern of the photosensitive dry films 40 and 50 is used as a mask when the semiconductor device bonding bumps 31 and the wirings 21 are formed. For example, a liquid photoresist or the like is applied. A mask may be formed. Further, for example, direct drawing may be performed by a laser beam or the like.

  In addition, not only combinations of wiring and semiconductor device bonding bumps on the same surface of an insulating substrate using different processes and different materials, but also when multiple types of conductor parts of a predetermined combination are formed, position accuracy, etc. If this problem appears, the present invention can be applied.

DESCRIPTION OF SYMBOLS 10 Insulating substrate 12 Via 21 Wiring 31 Bump for semiconductor device joining S1 1st main surface S2 2nd main surface

Claims (5)

An insulating substrate having a first main surface on which wiring is formed and a second main surface on which a plurality of semiconductor device bonding bumps are formed;
The semiconductor device bonding bumps are independently distributed on the second main surface, and are electrically connected to the wiring on the first main surface through vias penetrating the insulating substrate. A tape carrier for a semiconductor device. The wiring and the semiconductor device bonding bump are:
2. The tape carrier for a semiconductor device according to claim 1, wherein the metal thin film formed on the first main surface and the second main surface is formed by patterning. The semiconductor device tape carrier according to claim 1, wherein the semiconductor device bonding bumps have substantially uniform height and width. The semiconductor device tape carrier according to claim 1, wherein the semiconductor device bonding bump has a substantially flat bonding surface. 5. The semiconductor device tape carrier according to claim 1, wherein the semiconductor device bonding bump and the wiring on the first main surface are made of the same conductor material. 6.

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