JP2012113195A - Electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently secure a moving degree compensation period within one horizontal scan period.SOLUTION: An electro-optic device 100 includes a plurality of pixel circuits U which are disposed correspondingly to intersections of a plurality of data lines 16 which are divided into a plurality of blocks B, and a plurality of scan lines 120, a plurality of signal lines 18 which are disposed in one-to-one correspondence to the plurality of blocks B, a plurality of selectors MP which are disposed in one-to-one correspondence to the plurality of blocks B, and a drive circuit 20 which drives the pixel circuits U in a term of a horizontal scan period H. The horizontal scan period H includes a plurality of selection terms Ts (data output periods Pk) and a write period PWR. During the plurality of selection terms Ts and the write period PWR, the drive circuit controls current generation means in such a manner that a set current Is flows to a drive transistor TDR in each of the plurality of pixel circuits U corresponding to the scan line 120 which should be selected during the horizontal scan period H, thereby performing moving degree compensating operation on each of the drive transistors TDR over the plurality of selection terms Ts and the write period PWR.

Description

  The present invention relates to an electro-optical device and an electronic apparatus.

  In recent years, various electro-optical devices using electro-optical elements such as organic light-emitting diode (Organic Light Emitting Diode, hereinafter referred to as “OLED”) elements called organic EL (ElectroLuminescent) elements and light-emitting polymer elements have been proposed. As one of methods for driving such an electro-optical device, a multiplexer method is known (see, for example, Patent Document 1). In Patent Document 1, a plurality of data lines are divided into a plurality of blocks each having three lines, and a plurality of image signal lines corresponding to the data lines constituting the blocks are provided. In one horizontal scanning period, for each of the three data lines belonging to each block, R, G, and B signal voltages are sequentially supplied from the image signal line corresponding to the block.

  Each pixel of Patent Document 1 is disposed between a light emitting element that emits light with luminance corresponding to a driving current, a driving transistor that controls the driving current, a driving transistor and a data line, and a signal supplied to the scanning line. And a selection transistor whose ON / OFF is controlled accordingly. In Patent Document 1, the selection transistor of the pixel circuit corresponding to the scanning line to be selected in the one horizontal scanning period is turned off in a predetermined period before the signal writing period within one horizontal scanning period. After setting, the R, G, and B signal voltages VsigR, VsigG, and VsigB are distributed to the data lines. The signal voltage supplied to each data line is held by a parasitic capacitance associated with the data line. Then, in the subsequent signal writing period, the selection transistors of the pixel circuits corresponding to the scanning lines to be selected in the one horizontal scanning period are simultaneously turned on so that the signal voltage held in each data line Are simultaneously written in the pixel. As a result, a current corresponding to the signal voltage supplied to the data line corresponding to the pixel flows through the driving transistor of each pixel, and mobility compensation by negative feedback is performed.

JP 2008-304690 A

However, in the above-mentioned Patent Document 1, the mobility compensation operation is started all at once after waiting for completion of writing of the signal voltage to each data line, so the mobility compensation period within one horizontal scanning period is increased. There is a problem that it is difficult to ensure enough.
The present invention has been made in view of such circumstances, and an object thereof is to solve the problem of sufficiently securing a mobility compensation period within one horizontal scanning period.

  In order to solve the above problems, an electro-optical device (100) according to the present invention includes a plurality of data lines (16) divided into a plurality of blocks (B) in units of a plurality of lines, and a plurality of scanning lines ( 120), a plurality of pixel circuits (U) arranged corresponding to the respective intersections, a plurality of signal lines (18) provided in a one-to-one correspondence with the plurality of blocks, and a pair of the plurality of blocks. And a plurality of selection units (MP) for switching conduction and non-conduction between each data line belonging to the corresponding block and a signal line corresponding to the block, and a plurality of pixel circuits in a unit period ( And a driving circuit (20) that is driven in a cycle of one horizontal scanning period H), and each of the plurality of pixel circuits is provided on a path between the high-order power supply line (41) and the low-order power supply line (45). Driving transistor (TDR) connected in series and An element (E), a first capacitor element (C1) disposed between the gate and source of the driving transistor, a selection transistor (TSL) disposed between the gate of the driving transistor and the data line, Set current (Is) that branches from the side power supply line to the path different from the path to the light emitting element through the driving transistor and the node (ND) interposed between the driving transistor and the light emitting element. Current generating means (C2, 14) for generating, wherein the unit period includes a plurality of selection periods (Ts) and a writing period (PWR) after the plurality of selection periods, and a plurality of selection units In each of the plurality of selection periods, each of the data lines belonging to the block corresponding to the selection unit is sequentially selected and electrically connected to the signal line corresponding to the block. For a signal line, the block corresponding to the signal line The data potential (DT) corresponding to the specified gradation (D) of the pixel circuit corresponding to each intersection of each data line belonging to the pixel and the scanning line to be selected in the unit period is output in order, and Each of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period is set in an OFF state, and in the writing period, the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period In the plurality of selection periods and writing periods, a set current flows to each driving transistor of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period. Thus, by controlling the current generation means, the voltage across the first capacitor at the end of the writing period is set to a value reflecting the characteristics of the driving transistor.

  In the present invention, the driving circuit includes a current generating unit so that a set current flows in each driving transistor of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period in the plurality of selection periods and the writing period. By controlling, the mobility compensation operation of each driving transistor is performed over a plurality of selection periods and writing periods within a unit period (within one horizontal scanning period). That is, according to the present invention, the mobility compensation period within one horizontal scanning period can be sufficiently secured as compared with the conventional mode in which the mobility compensation operation is not performed in a plurality of selection periods. is there.

  As an aspect of the electro-optical device according to the invention, each selection unit simultaneously transmits each data line belonging to a block corresponding to the selection unit and a signal line corresponding to the block during the first selection period in the unit period. In such a mode, the potential of each data line belonging to the block may be set to the data potential output to the signal line corresponding to the block in the first selection period.

  Here, since a parasitic capacitance is interposed between the gate of the drive transistor of each pixel circuit and the data line corresponding to the pixel circuit, the gate of the drive transistor is connected to the data line under an electrically floating state. When the data potential is written, the gate potential of the driving transistor changes in conjunction with the potential of the data line. At this time, the source potential of the driving transistor also changes in conjunction with the gate potential. Accordingly, when the data potential is written to the data line in each of the selection periods described above, the value of the set current flowing through the pixel circuit corresponding to the data line also changes. As a result, the condition for mobility compensation changes. In the above-described aspect, each selection unit conducts each data line belonging to the block corresponding to the selection unit and the signal line corresponding to the block simultaneously in the first selection period within the unit period, The potential of each data line belonging to the block is set to the data potential output to the signal line corresponding to the block in the first selection period. That is, the amount of change in the set current flowing through each pixel circuit can be made uniform by aligning the amount of change in potential of each data line belonging to the block. Therefore, there is an advantage that the conditions for mobility compensation in the first selection period can be made uniform among the pixel circuits.

  Note that as the amount of change in the potential of the data line in each selection period increases, the amount of change in the set current flowing through the pixel circuit corresponding to the data line also increases, and the mobility compensation conditions vary greatly. In the above aspect, in the first selection period, the potential of each data line belonging to the block is higher than the initialization potential (data potential output to the signal line corresponding to the block in the first selection period). Therefore, as compared with the mode in which the potential of each data line is set to the initialization potential until the data potential is written to the data line, the data line in each of the second and subsequent selection periods is set. The amount of potential fluctuation can be suppressed. That is, there is also an advantage that it is possible to suppress a large change in mobility compensation conditions in each pixel circuit.

  As an aspect of the electro-optical device according to the invention, the unit period includes a set period (PS) before a plurality of selection periods, and the drive circuit sets the potential of each data line to the initialization potential ( VINI), and simultaneously setting the selection transistors of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period to the ON state, the gate potential of the driving transistor is set to the initialization potential. On the other hand, by controlling the current generation means so that a set current of a certain magnitude flows through the drive transistor, the voltage across the first capacitor element is set to a value necessary for the set current to flow through the drive transistor. It may be a mode set to.

  For example, in Patent Document 1 described above, the voltage between the gate and the source of the driving transistor immediately before the plurality of selection periods is set to the threshold voltage of the driving transistor. In Patent Document 1, the drive circuit causes a current to flow through the drive transistor while maintaining the gate potential of the drive transistor at a predetermined value in a period (compensation period) before a plurality of selection periods. The voltage between the gate and the source gradually approaches the threshold voltage, but as the voltage between the gate and the source of the driving transistor approaches the threshold voltage, the current flowing through the driving transistor becomes a small value, and the voltage between the gate and the source of the driving transistor The time change rate of the voltage is also very small. Therefore, a very long time is required until the value of the current flowing through the driving transistor is surely zero (until the voltage between the gate and the source of the driving transistor reliably reaches the threshold voltage). On the other hand, in the present invention, in the set period before the plurality of selection periods, the drive circuit sets the gate potential of the drive transistor to the initialization potential, and a set current having a constant magnitude is applied to the drive transistor. The voltage between the gate and source of the drive transistor (the voltage across the first capacitor element) is set to a value necessary for the set current to flow through the drive transistor by controlling the current generation means so that the current flows. To do. Accordingly, there is an advantage that the time length required for setting the gate-source voltage of the driving transistor immediately before a plurality of selection periods to a desired value can be significantly shortened as compared with Patent Document 1.

  As an aspect of the electro-optical device according to the invention, the current generation unit includes a second capacitor element (C2) including a first electrode (L1) and a second electrode (L2), and a feeder line (14). The first electrode is connected to the node, while the second electrode is connected to the power supply line, and the drive circuit outputs to the power supply line in the set period, the plurality of selection periods, and the writing period in each unit period. An aspect in which the potential is changed with time may be used. In this aspect, the set current has a value corresponding to the time change rate of the potential output to the feeder line. For example, if the potential output to the power supply line changes linearly at a constant rate of time change, the value of the set current is constant, and the voltage across the first capacitor element is the drive current of the set current. Is set to the value required to flow through. According to this aspect, there is an advantage that the voltage between the gate and the source of the driving transistor can be easily adjusted to a desired value.

  The electro-optical device according to the invention is used in various electronic apparatuses. A typical example of an electronic device is a device that uses a light-emitting device as a display device. Examples of the electronic apparatus according to the present invention include a personal computer and a mobile phone. However, the use of the light emitting device according to the present invention is not limited to image display. For example, the light emitting device of the present invention is also applied as an exposure device (optical head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light.

The present invention is also specified as a method of driving an electro-optical device with a period of a unit period. A driving method according to the present invention includes a plurality of data lines that are divided into a plurality of blocks in units of a plurality of lines, a plurality of pixel circuits that are arranged corresponding to respective intersections of the plurality of scanning lines, and a plurality of blocks And a plurality of signal lines provided in a one-to-one correspondence, and each of the plurality of pixel circuits includes a drive transistor and a light-emitting element connected in series between the high-side power supply line and the low-side power supply line And the first capacitor element disposed between the gate and the source of the drive transistor, the high-potential power line, the drive transistor, and the node interposed between the drive transistor and the light-emitting element, A method of driving an electro-optical device having a set period to generate a set current that branches and flows to a path different from the path to the path, the unit period being a plurality of selection periods And multiple Including a writing period after the selection period, and in a plurality of selection periods, each data line belonging to each block is sequentially selected and made conductive to the signal line corresponding to the block, while each signal line is By sequentially outputting the data potential corresponding to the specified gradation of the pixel circuit corresponding to each intersection of the data line belonging to the block corresponding to the signal line and the scanning line to be selected in the unit period, Data potential is written to the data line, and in the writing period, the data potential written to the data line corresponding to the pixel circuit is applied to each of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period. In the plurality of selection periods and writing periods, the current generation means is controlled so that a set current flows to each drive transistor of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period. And in, and sets the value that is characteristic of the driving transistor voltage is reflected across the first capacitive element at the end of the writing period.
The same effect as that of the electro-optical device according to the invention can be obtained by the above driving method.

1 is a block diagram of an electro-optical device according to an embodiment of the invention. FIG. It is a circuit diagram of a selection part. It is a circuit diagram of a pixel circuit. 3 is a timing chart illustrating an operation of a pixel circuit. It is a figure which shows operation | movement of the pixel circuit in an initialization period. It is a figure which shows operation | movement of the pixel circuit in a set period. It is a figure which shows operation | movement of the pixel circuit in a data output period. It is a figure which shows operation | movement of the pixel circuit in a data output period. It is a figure which shows operation | movement of the pixel circuit in the writing period. It is a figure which shows operation | movement of the pixel circuit in the light emission period. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention.

<A: Embodiment>
FIG. 1 is a block diagram illustrating a configuration of an electro-optical device 100 according to an embodiment of the present invention. The electro-optical device 100 is a device that is employed in various electronic devices as means for displaying an image. As shown in FIG. 1, the electro-optical device 100 includes an element unit 10 in which a plurality of pixel circuits U are arranged in a matrix. The element unit 10 includes m sets of wiring groups 12 extending in the X direction, m lamp power supply lines 14 extending in the X direction in pairs with the wiring groups 12, and a Y direction intersecting the X direction. 9n data lines 16 extending to (m and n are natural numbers) are formed. The plurality of pixel circuits U are arranged at the intersection of the wiring group 12 and the pair of the lamp power supply line 14 and the data line 16 and arranged in a matrix of m rows × 9n columns. In the present embodiment, the 9n data lines 16 are divided into n blocks B (B [1], B2,... B [n]) with 9 adjacent lines as a unit. However, the number of data lines 16 in each block B (unit of division of the data lines 16) is not limited to nine and can be set to an arbitrary number of two or more.

  As shown in FIG. 1, the electro-optical device 100 includes a drive circuit 20 that drives each pixel circuit U and n blocks B [1] to B [n] that are provided in a one-to-one correspondence. The signal lines 18 and the n blocks B [1] to B [n] are arranged in one-to-one correspondence, and the data lines 16 belonging to the corresponding block B and the signals corresponding to the block B are arranged. An n number of selection units MP (MP [1] to MP [n]) for switching between conduction and non-conduction with the line 18 and a control circuit 30 are further provided. As shown in FIG. 1, the drive circuit 20 includes a scanning line drive circuit 21, a signal line drive circuit 23, a potential generation circuit 25, and a data line initialization unit (not shown in FIG. 1) described later. Composed. The drive circuit 20 is distributed and mounted on a plurality of integrated circuits, for example. However, at least a part of the drive circuit 20 can be configured by a thin film transistor formed on the substrate together with the pixel circuit U.

  The control circuit 30 outputs a signal defining the operation of the electro-optical device 100 to the drive circuit 20 and each of the selection units MP [1] to MP [n]. In the present embodiment, the control circuit 30 outputs selection signals SEL1 to SEL9 that define the operations of the selection units MP [1] to MP [n] to the selection units MP [1] to MP [n]. Further, the control circuit 30 outputs a control signal (not shown) such as gradation data D indicating a designated gradation of each pixel circuit U and a clock signal to the signal line driving circuit 23. Further, the control circuit 30 also outputs a control signal (not shown) such as a clock signal to the scanning line driving circuit 21 and the potential generation circuit 25.

  The scanning line drive circuit 21 is means for sequentially selecting a plurality of pixel circuits U in units of rows in each of m horizontal scanning periods H (H [1] to H [m]) in each vertical scanning period. . The signal line driving circuit 23 generates n-phase grayscale signals VD [1] to VD [n] from the grayscale data D of each pixel circuit U output from the control circuit 30 and outputs them in parallel to the respective signal lines 18. To do. For example, the gradation signal VD [j] output to the signal line 18 corresponding to the j-th (1 ≦ j ≦ n) block B [j] is a data line for nine columns belonging to the block B [j]. 16 is a voltage signal in which the data potential DT corresponding to the gradation data D of each of the nine pixel circuits U corresponding to the intersections of 16 and the row selected by the scanning line driving circuit 21 is output in a time division manner.

  Each of the selection units MP [1] to MP [n] is a gradation output to the signal line 18 corresponding to the block B with respect to the nine data lines 16 belonging to the block B corresponding to the selection unit MP. It functions as a means for distributing the signal VD. FIG. 2 is a circuit diagram of the selection unit MP. In FIG. 2, only the j-th selection unit MP [j] corresponding to the j-th block B [j] is representatively illustrated, but the configuration of the other selection units MP is the same. As illustrated in FIG. 2, the selection unit MP [j] includes nine switches SW (SW_1 to SW_9) corresponding to the number of data lines 16 in the block B [j] corresponding to the selection unit MP [j]. including. The switch SW_k (k = 1 to 9) of the selection unit MP [j] is interposed between the k-th column data line 16 and the output end of the j-th column signal line 18 in the block B [j]. Thus, the electrical connection (conduction / non-conduction) between the two is controlled. The nine selection signals SEL1 to SEL9 are commonly supplied from the control circuit 30 to the n selection units MP [1] to Mp [n]. The selection signal SELk (k = 1 to 9) is supplied in common to the switch SW_k in each of the selection units MP [1] to MP [n] to control opening and closing.

  Returning to FIG. 1 again, the description will be continued. As shown in FIG. 1, the potential generation circuit 25 generates a high potential VELH of the power supply, a reset potential VELL, a low potential VCT of the power supply, a ramp potential Vrmp, and an initialization potential VINI. To do. The potential VELH is supplied to the power supply line 41 shown in FIG. The power supply line 41 is connected to each pixel circuit U in common. The potential VELL is supplied to the feed line 43 shown in FIG. The power supply line 43 is connected to each pixel circuit U in common. The potential VCT is supplied to the feeder line 45 shown in FIG. The power supply line 45 is connected to each pixel circuit U in common. The initialization potential VINI is supplied to the initialization line 47 shown in FIG. The potential generation circuit 25 individually outputs the lamp potential Vrmp to each lamp power supply line 14. Here, the lamp potential output to the lamp feed line 14 in the i-th row is denoted as Vrmp [i].

  FIG. 3 is a circuit diagram of the pixel circuit U. FIG. 3 representatively shows only one pixel circuit U located in the k-th column in the j-th block B [j] belonging to the i-th row (1 ≦ i ≦ m). . As shown in FIG. 3, the pixel circuit U includes a light emitting element E, a driving transistor TDR, a first capacitor element C1, a second capacitor element C2, a selection transistor TSL, and power supply switching transistors TH and TL. It is comprised including. As shown in FIG. 3, the wiring group 12 illustrated as one straight line in FIG. 1 includes a scanning line 120, a control line 122, and a control line 124. Each data line 16 is accompanied by a capacitor Cs.

  The drive transistor TDR and the light emitting element E are connected in series to a path between each of the feeder line 41 and the feeder line 43 and the feeder line 45. The light-emitting element E is an OLED element in which a light-emitting layer made of an organic EL material is interposed between an anode and a cathode facing each other, and emits light with a luminance corresponding to the value of the drive current generated by the drive transistor TDR. The cathode of the light emitting element E is connected to the feeder line 45.

  The drive transistor TDR is an N-channel thin film transistor, and generates a drive current having a current value corresponding to a voltage VGS (= VG−VS) which is a difference between the gate potential VG and the source potential VS. The source of the driving transistor TDR is connected to the anode of the light emitting element E. An N-channel transistor TH is disposed between the drain of the driving transistor TDR and the power supply line 41, and an N-channel transistor TL is disposed between the drain of the driving transistor TDR and the power supply line 43. . The gate of the transistor TH is connected to the control line 122, and on / off is controlled according to the control signal GVH [i] output to the control line 122. On the other hand, the gate of the transistor TL is connected to the control line 124, and on / off is controlled according to the control signal GVL [i] output to the control line 124. In the present embodiment, the transistor TH and the transistor TL operate in a complementary manner. More specifically, the transistor TL is turned off when the transistor TH is turned on, and the transistor TL is turned on when the transistor TH is turned off.

  A first capacitive element C1 is interposed between the gate and source of the driving transistor TDR. In addition, a node ND (corresponding to the source of the drive transistor TDR) interposed between the drive transistor TDR and the light emitting element E on the path connecting each of the feed line 41 and the feed line 43 and the feed line 45, and the i-th row The second capacitive element C2 is interposed between the lamp power supply line 14 and the second power supply line 14. The second capacitive element C2 includes a first electrode L1 connected to the node ND and a second electrode L2 connected to the i-th lamp power supply line. In the present embodiment, the second capacitor element C2 and the lamp power supply line 14 function as a current generating unit for generating a set current Is described later.

  A selection transistor TSL is disposed between the gate of the driving transistor TDR and the data line 16. For example, an N-channel transistor (thin film transistor) is preferably used as the selection transistor TSL. The gates of the selection transistors TSL of the n pixel circuits U belonging to the i-th row are commonly connected to the i-th row scanning line 120.

  The electro-optical device 100 according to the present embodiment further includes a data line initialization unit 50 for initializing the potential of each data line 16. As shown in FIG. 3, the data line initialization unit 50 is arranged between the 9n data lines 16 and the initialization line 47, and has a plurality (one to one) of the 9n data lines 16. 9n) initialization transistors Tin. An initialization signal GINI is commonly supplied to the gates of the 9n initialization transistors Tin.

  FIG. 4 is a timing chart illustrating the operation of the electro-optical device 100 according to the present embodiment. FIG. 4 illustrates only the i-th horizontal scanning period H [i], but each of the horizontal scanning periods H [1] to H [m] includes an initialization period PRS and an initialization period. It includes a set period PS after PRS, a data output period Pk after the set period PS, and a write period PWR after the data output period Pk. The period from the end of the i-th horizontal scanning period H [i] in a certain vertical scanning period to the start of the i-th horizontal scanning period H [i] in the next vertical scanning period is the light emission period PDR. Set as

  The scanning line driving circuit 21 in FIG. 1 generates scanning signals GWR [1] to GWR [m] and outputs them to each scanning line 120. As shown in FIG. 4, the scanning signal GWR [i] output to the i-th row scanning line 120 includes an initialization period PRS, a set period PS, and a writing period PWR in the horizontal scanning period H [i]. The active level (high level) is set at. Here, “the i-th row scanning line 120 is selected” means that the scanning signal GWR [i] is set to a high level in the writing period PWR in the horizontal scanning period H [i]. . The scanning line driving circuit 21 generates and outputs the control signals GVH [1] to GVH [m], the control signals GVL [1] to GVL [m], and the initialization signal GINI. The control signal GVH [i] is supplied to the control line 122 in the i-th row, and the control signal GVL [i] is supplied to the control line 124 in the i-th row. Further, the initialization signal GINI is supplied in common to the gates of the 9n initialization transistors Tin.

  In the data output period Pk within each horizontal scanning period H, the signal line driving circuit 23 in FIG. 1 is configured to each data line 16 belonging to the block B corresponding to the signal line 18 and the horizontal line for each signal line 18. A gradation signal VD for designating the designated gradation of the pixel circuit U corresponding to each intersection with the scanning line 120 to be selected in the scanning period H by time division is output. At this time, the selection units MP [1] to MP [n] sequentially select the data lines 16 belonging to the block B corresponding to the selection unit MP and make the data lines 16 corresponding to the block B conductive.

  As shown in FIG. 4, the data output period Pk in each horizontal scanning period H (H [1] to H [m]) is composed of a plurality (nine) of selection periods Ts1 to Ts9. Focusing on the j-th block B [j], the gradation signal VD [j] output to the signal line 18 corresponding to the block B [j] is represented by each horizontal scanning period H (H [1] to H [m]) in nine selection periods Ts1 to Ts9, 9 corresponding to each intersection between the scanning line 120 to be selected in the horizontal scanning period H and each data line 16 belonging to the block B [j]. The data potential DT (DT_1 to DT_9) corresponding to the gradation data D of each pixel circuit U is set in order. More specifically, the signal line corresponding to the block B [j] in the k-th (1 ≦ k ≦ 9) selection period Tsk in each horizontal scanning period H (H [1] to H [m]). The gradation signal VD [j] output to 18 corresponds to the intersection between the scanning line 120 to be selected in the horizontal scanning period H and the kth data line 16 in the block B [j]. That is, the data potential DT_k corresponding to the gradation data D of the pixel circuit U is set. The same applies to the gradation signal VD output to the other signal lines 18.

  As shown in FIG. 4, the selection signals SEL1 to SEL9 are sequentially set to the active level (high level) in the nine selection periods Ts1 to Ts9 in each horizontal scanning period H. In the present embodiment, in the first selection period Ts1, the selection signals SEL1 to SEL9 are simultaneously set to the high level, and details thereof will be described later. Assuming that k is a number other than 1, the selection signal SELk (k = 2 to 9) is set to a high level not only in the first selection period Ts1 but also in the kth selection period Tsk. The When the selection signal SELk transits to a high level in the selection period Tsk, the data potential DT_k set as the gradation signal VD [j] is transferred to the block B [j] via the switch SW_k of the selection unit MP [j]. That is, it is supplied to the data line 16 of the kth column. As described above, in the data output period Pk in each horizontal scanning period H, the potential of each data line 16 corresponds to the intersection of the scanning line 120 selected in the horizontal scanning period H and the data line 16. The data potential DT is set according to the gradation data D of the pixel circuit U.

  In the following, the operation of the pixel circuit U in the k-th column in the j-th block B [j] belonging to the i-th row is described as the initialization period PRS, the set period PS, the data output period Pk, and the writing Description will be made by dividing into a period PWR and a light emission period PDR. In the following description, k is a number other than 1.

(A) Initialization period PRS
As shown in FIG. 4, when the initialization period PRS starts, the drive circuit 20 (scan line drive circuit 21) sets the initialization signal GINI to an active level (high level). Therefore, as shown in FIG. 5, the initial transistor TIN is set to the ON state. Since each data line 16 is conducted to the initialization line 47 via the initialization transistor TIN in the on state, the potential of each data line 16 is set to the initialization potential VINI. At this time, the switches SW_1 to SW_9 of each selection unit MP [j] are set to the OFF state, so that each data line 16 in each block B and the signal line 18 corresponding to the block B are not conductive. It becomes.

  As shown in FIG. 4, the drive circuit 20 (scan line drive circuit 21) sets the scan signal GWR [i] and the control signal GVL [i] to an active level (high level), while the control signal GVH [ i] is set to an inactive level (low level). Therefore, as shown in FIG. 5, the selection transistor TSL and the transistor TL are set to the on state, while the transistor TH is set to the off state. As a result, the gate of the drive transistor TDR is electrically connected to the data line 16 via the selection transistor TSL in the on state, so that the potential VG of the gate of the drive transistor TDR is set to the initialization potential VINI. In addition, one electrode (drain) of the driving transistor TDR is electrically connected to the power supply line 43 through the transistor TL in the on state. In the present embodiment, the voltage difference between the potential VELL of the power supply line 43 and the initialization potential VINI is set to be sufficiently higher than the threshold voltage VTH of the drive transistor TDR, so that the drive transistor TDR is turned on. Therefore, the source potential VS of the drive transistor TDR is set to the potential VELL. That is, the voltage VGS between the gate and the source of the driving transistor TDR (the voltage between both ends of the first capacitive element C1) is initialized to the voltage difference (| VINI−VELL |) between the initialization potential VINI and the potential VELL. .

  Further, the potential VELL is set to such a value that the potential difference between the potential VELL and the potential VCT of the power supply line 45 is sufficiently lower than the light emission threshold voltage VTH_OLED of the light emitting element E. Status).

(B) Set Period As shown in FIG. 4, when the set period PS starts, the drive circuit 20 (scanning line drive circuit 21) sets the control signal GVH [i] to a high level, while the control signal GVL [i ] Is set to low level. Other signals are maintained at the same level as the initialization period PRS. Therefore, as shown in FIG. 6, the transistor TH is set to the on state, while the transistor TL is set to the off state. As a result, the current from the feed line 41 flows through the drive transistor TDR, and the potential VS of the source of the drive transistor TDR starts to rise. Since the gate potential VG of the driving transistor TDR is maintained at the initialization potential VINI, the voltage between the gate and the source of the driving transistor TDR gradually decreases. At this time, the drive circuit 20 (potential generation circuit 25) changes the lamp potential Vrmp [i] output to the lamp power supply line 14 in the i-th row with time, so that the power supply line 41 passes through the node ND. A set current Is of a predetermined magnitude is generated that branches and flows to a path different from the path to the light emitting element E. More specifically, it is as follows.

As shown in FIG. 4, when the horizontal scanning period H [i] starts, the potential generation circuit 25 changes the ramp potential Vrmp [i] output to the lamp feed line 14 in the i-th row from the reference potential Vref to the start potential VX ( > Vref). Then, the ramp potential Vrmp [i] is linearly decreased at the time change rate RX (RX = dVrmp / DT) from the start point to the end point of the horizontal scanning period H [i]. In the present embodiment, the potential generation circuit 25 linearly decreases the ramp potential Vrmp [i] so that the value of the ramp potential Vrmp [i] at the end point of the horizontal scanning period H [i] is equal to the reference potential Vref. Let When the capacitance of the second capacitive element C2 is denoted by Cp and the charge accumulated in the second capacitive element C2 is denoted by Q, the i-th row from the feeder line 41 through the node ND and the second capacitive element C2 in the set period PS. The set current Is flowing to the lamp power supply line 14 is expressed by the following equation (1).
Is = dQ / dt = Cp × dVrmp / dt = Cp × dRX / dt (1)

In the present embodiment, since the time change rate RX of the lamp potential Vrmp is constant, the value of the set current Is is constant. Therefore, in the set period PS, the voltage between the gate and the source of the drive transistor TDR gradually approaches the voltage VGS1 necessary for the constant set current Is to flow through the drive transistor TDR. As described above, the voltage between the gate and the source of each drive transistor TDR is set to the voltage VGS1 necessary for the constant set current Is to flow through the drive transistor TDR. In the present embodiment, the voltage VGS1 is expressed by the following equation (2).
VGS1 = VTH + Va (2)

  At the end of the set period PS, the voltage between the gate and the source of the drive transistor TDR is substantially equal to the voltage VGS1 required for the constant set current Is to flow through the drive transistor TDR. Is set to a potential VINI−VGS1 lower than the initialization potential VINI (gate potential VG) by the voltage VGS1. In the present embodiment, the potential difference (voltage between both ends of the light emitting element E) between the potential VINI-VGS1 and the potential VCT of the feeder line 45 is set to be lower than the light emission threshold voltage Vth_el of the light emitting element E. That is, the light emitting element E is in a non-light emitting state even in the set period PS.

(C) Data output period Pk
As shown in FIG. 4, when the data output period Pk starts, the drive circuit 20 (scan line drive circuit 21) sets the initialization signal GINI to a low level. Therefore, as shown in FIGS. 7 and 8, since the initial transistor TINI is set in the OFF state, each data line 16 and the initialization line 47 are in a non-conductive state. Further, as shown in FIG. 4, the drive circuit 20 (scan line drive circuit 21) sets the scan signal GWR [i] to a low level. Accordingly, as shown in FIGS. 7 and 8, the select transistor TSL is turned off, and the data line 16 is electrically floating. As described above, since the capacitance Cs is associated with each data line 16, the potential of each data line 16 is held at the initialization potential VINI until the data potential DT is written.

  As shown in FIG. 4, in the data output period Pk, the drive circuit 20 (potential generation circuit 25) applies the ramp potential Vrmp [i] to be output to the lamp feed line 14 in the i-th row in the same manner as in the set period PS. Since the voltage decreases linearly at the rate of change RX, the set current Is continues to flow in the path from the node ND to the lamp power supply line 14 in the i-th row via the second capacitive element C2. Here, as the mobility μ of the driving transistor TDR is increased, the value of the current flowing through the driving transistor TDR is increased, and the amount of increase in the source potential VS is also increased. Conversely, the smaller the mobility μ, the smaller the value of the current flowing through the drive transistor TDR. That is, as the mobility μ increases, the amount of decrease in the voltage between the gate and the source of the drive transistor TDR (negative feedback amount) increases. On the other hand, as the mobility μ decreases, the amount of decrease in the voltage between the gate and source (negative feedback amount). ) Becomes smaller. As a result, variations in mobility μ for each pixel circuit U are compensated.

  In the present embodiment, as shown in FIG. 4, in the first selection period Ts1 in the data output period Pk, the drive circuit (signal line drive circuit 23) has a signal line corresponding to the jth block B [j]. The value of the gradation signal VD [j] to be output to the level of the pixel circuit U corresponding to the intersection of the scanning line 120 of the i-th row and the data line 16 of the first column in the block B [j]. The data potential DT_1 corresponding to the key data D is set. In addition, the control circuit 30 sets the selection signals SEL1 to SEL9 to the high level all at once. As a result, the data lines 16 belonging to the block B [j] and the j-th signal line 18 corresponding to the block B [j] are simultaneously conducted. Therefore, as shown in FIG. 7, the potential of each data line 16 in the block B [j] changes from the initialization potential VINI to the data potential DT_1 (> VINI).

  Here, since a parasitic capacitance (not shown) is interposed between the gate of the driving transistor TDR and the data line 16, when the potential of the data line 16 changes from the initialization potential VINI to the data potential DT_1, the driving transistor TDR The gate potential VG changes in conjunction with the potential of the data line 16. At this time, since the source potential VS of the drive transistor TDR also changes in conjunction with the gate potential VG, the voltage across the second capacitor C2 changes, and the value of the set current Is changes. Thereby, the conditions for mobility compensation change. As described above, in the present embodiment, in the first selection period TS1, the data lines in the block B [j] and the signal line 18 corresponding to the block B [j] are made conductive at the same time, Since the potential of each data line 16 belonging to the block B [j] is set to the data potential DT_1, the change in potential of each data line 16 belonging to the block B [j] can be made uniform. That is, since the amount of change in the set current Is flowing through each pixel circuit U in the block B [j] can be made uniform, the conditions for mobility compensation in the first selection period Ts1 can be made uniform among the pixel circuits U. There is an advantage.

  Thereafter, when the k-th selection period Tsk in the data output period Pk starts, the drive circuit (signal line drive circuit 23) outputs the gradation signal VD [j output to the signal line 18 corresponding to the block B [j]. ] To the data potential DT_k corresponding to the gradation data D of the pixel circuit U corresponding to the intersection of the i-th scanning line 120 and the k-th data line 16 in the block B [j]. Set. At this time, since the control circuit 30 sets the selection signal SELk to a high level, the switch SW_k of the selection unit MP [j] is set to the on state, and the kth data line 16 in the block B [j]. And the signal line 18 corresponding to the block B [j] is conducted. Therefore, as shown in FIG. 8, the potential of the k-th data line 16 in the block B [j] changes from the potential DT_1 set in the first selection period TS1 to the potential DT_k. As a result, the value of the set current Is flowing through the pixel circuit U (the pixel circuit U located in the k-th column in the block B [j] belonging to the i-th row) also changes.

  Note that immediately before the kth selection period Tsk ends, the control circuit 30 sets the selection signal SELk to a low level. As a result, the switch SW_k is turned off, and the data line 16 in the kth column in the block B [j] is in an electrically floating state. As described above, since the data line 16 is accompanied by the capacitor Cs, the data potential DT_k written to the k-th data line 16 in the k-th selection period Tsk is held by the capacitor Cs. Condition.

  Here, as the amount of change in the potential of the data line 16 in each selection period Ts increases, the amount of change in the set current Is flowing through the pixel circuit U corresponding to the data line 16 also increases, and the mobility compensation conditions vary greatly. To do. As described above, in this embodiment, in the first selection period Ts1, the potential of each data line 16 belonging to the block B [j] is set to the potential DT_1 larger than the initialization potential VINI. In comparison with the mode in which the potential of 16 is set to the initialization potential VINI until the data potential DT is written to the data line 16, the variation of the potential of the data line 16 in each of the second and subsequent selection periods Ts. The amount can be suppressed. That is, according to the present embodiment, there is an advantage that the mobility compensation condition in each pixel circuit U can be suppressed from greatly fluctuating.

(D) Write period PWR
As shown in FIG. 4, when the writing period PWR starts, the drive circuit 20 (scan line drive circuit 21) sets the scan signal GWR [i] to a high level. Therefore, as shown in FIG. 9, since the selection transistor TSL is turned on, the gate of the driving transistor TDR is conducted to the kth data line 16 in the block B [j]. Thereby, the gate potential VG of the drive transistor TDR is set to the data potential DT_k, and the current Ids corresponding to the data potential DT_k flows through the drive transistor TDR. Since the current Ids flows through the driving transistor TDR, the source potential VS of the driving transistor TDR rises with time, so the voltage between the gate and source of the driving transistor TDR decreases with time.

  At this time, similarly to the set period PS and the data output period Pk, the drive circuit 20 (the potential generation circuit 25) linearly displays the lamp potential Vrmp [i] output to the lamp feed line 14 in the i-th row at a time change rate RX. Therefore, the set current Is continues to flow in a path from the node ND to the i-th row lamp power supply line 14 via the second capacitance element C2. As a result, the current Ids flowing through the driving transistor TDR branches into a set current Is flowing toward the second capacitor element C2 and a current Ic (Ids-Is) flowing toward the first capacitor element C1 at the node ND. The larger the value of the current Ids corresponding to the data potential DT_k, the larger the value of the current Ic flowing into the first capacitive element C1, resulting in an increase in the potential of the source of the driving transistor TDR (that is, the voltage between the gate and the source). (Decrease amount) increases.

Further, as described above, the larger the mobility μ of the driving transistor TDR, the larger the amount of decrease in the voltage between the gate and the source of the driving transistor TDR (negative feedback amount), while the smaller the mobility μ, the larger the mobility between the gate and source. The amount of voltage decrease (negative feedback amount) becomes smaller. As a result, variations in mobility μ for each pixel circuit U are compensated. Such a mobility compensation operation is performed over the data output period Pk and the writing period PWR, and the voltage between the gate and the source of the driving transistor TDR at the end point of the writing period PWR (the voltage between both ends of the first capacitor element C1). Is set to a value reflecting the data potential DT_k and the characteristics (mobility μ) of the driving transistor TDR. The gate-source voltage VGS2 of the driving transistor TDR at the end point of the writing period PWR is expressed by the following equation (3).
VGS2 = VGS1 + ΔV = VTH + Va + ΔV (3)
ΔV in Expression (3) is a value corresponding to the data potential DT_k and the characteristics (mobility μ) of the driving transistor TDR. Note that the source potential VS of the driving transistor TDR at the end point of the writing period PWR is set to a value such that the voltage across the light emitting element E is lower than the light emission threshold voltage Vth_el. Accordingly, the light emitting element E is in a non-light emitting state even in the writing period PWR.

(E) Light emission period PDR
As shown in FIG. 4, when the light emission period PDR starts, the drive circuit 20 (scan line drive circuit 21) sets the scan signal GWR [i] to a low level. Therefore, as shown in FIG. 10, the selection transistor TSL transitions to the off state, and the gate of the driving transistor TDR is in an electrically floating state. Further, since the drive circuit 20 (potential generation circuit 25) sets the lamp potential Vrmp [i] to be output to the lamp feed line 14 in the i-th row to a constant reference potential Vref, it can be understood from the equation (1). Thus, the value of the set current Is is zero.

At this time, the voltage between both ends of the first capacitive element C1 (the voltage between the gate and the source of the driving transistor TDR) is maintained at the voltage VGS2 at the end point of the writing period PWR, so that the current Iel corresponding to the voltage VGS2 Flows through the driving transistor TDR, and the source potential VS rises with time.
Since the gate of the drive transistor TDR is in an electrically floating state, the gate potential VG of the drive transistor TDR rises in conjunction with the source potential VS. The source potential VS of the drive transistor TDR gradually increases while the voltage between the gate and the source of the drive transistor TDR is maintained at the voltage VGS2 set at the end point of the write period PWR. When the voltage across the light emitting element E reaches the light emission threshold voltage Vth_el, the current Iel flows through the light emitting element E as a drive current. The light emitting element E emits light with luminance according to the drive current Iel.

Assuming that the drive transistor TDR operates in the saturation region, the drive current Iel is expressed in the form of the following equation (4). “Β” is a gain coefficient of the driving transistor TDR.
Iel = (β / 2) (VGS2−VTH) ² (4)
By substituting equation (3), equation (4) is transformed as follows.
Iel = (β / 2) (VTH + Va + ΔV−VTH) ²
= (Β / 2) (Va + ΔV) ²
That is, since the drive current Iel does not depend on the threshold voltage VTH of the drive transistor TDR, luminance unevenness due to variations in the threshold voltage VTH for each pixel circuit U is suppressed.

  As described above, the drive circuit 20 of the present embodiment should be selected in the horizontal scanning period H in the data output period Pk (a plurality of selection periods Ts) and the writing period PWR in one horizontal scanning period H. By controlling the charge amount of the second capacitor element C2 of each pixel circuit U so that the set current Is flows to each drive transistor TDR of each of the plurality of pixel circuits U corresponding to the scanning line 120, one horizontal scanning period H The mobility compensation operation of each drive transistor TDR is performed over the data output period Pk (a plurality of selection periods Ts) and the writing period PWR. That is, according to the present embodiment, the mobility compensation period within one horizontal scanning period is compared with the aspect in which the mobility compensation operation is not performed in the data output period Pk (a plurality of selection periods Ts) as in the prior art. Since it can be sufficiently ensured, there is an advantage that unevenness in luminance due to variations in mobility μ of the drive transistor TDR can be sufficiently suppressed.

<B: Modification>
The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible. Also, two or more of the modifications shown below can be combined.

(1) Modification 1
In the above-described embodiment, in the set period PS, the drive circuit 20 changes the lamp potential Vrmp [i] output to the lamp feed line 14 in the i-th row with time (that is, the charge of the second capacitor element C2). The set current Is is generated by changing the amount with time). However, the present invention is not limited to this, and a constant current for generating the set current Is is used instead of the second capacitor element C2 and the lamp feeder 14. The aspect in which a source is provided may be sufficient. In short, each pixel circuit U only needs to have a current generating means for generating the set current Is.

(2) Modification 2
In each of the above-described embodiments, the potential output to the lamp power supply line 14 decreases linearly at a constant time change rate RX. However, the present invention is not limited to this, and the potential output to the lamp power supply line 14 changes. The mode of is arbitrary. For example, the waveform of the potential output to the lamp power supply line 14 may be curved. In short, the potential output to the lamp power supply line 14 only needs to change with time so that the set current Is flows through the driving transistor TDR.

(3) Modification 3
In each of the above-described embodiments, in the initialization period PRS, the drive circuit 20 linearly decreases the lamp potential Vrmp [i] output to the lamp power supply line 14 at the time change rate RX. The potential of the lamp feeder 14 in the initialization period PRS is arbitrary. For example, in the initialization period PRS, the drive circuit 20 can also fix the potential output to the lamp power supply line 14 to a predetermined magnitude.

(4) Modification 4
The light emitting element E may be an OLED element, an inorganic light emitting diode, or an LED (Light Emitting Diode). In short, all elements that emit light in response to the supply of electric energy (application of electric field or supply of current) can be used as the light-emitting elements of the present invention.

<C: Application example>
Next, an electronic apparatus using the light emitting device according to the present invention will be described. FIG. 11 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 100 according to the embodiment described above as a display device. The personal computer 2000 includes an electro-optical device 100 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the electro-optical device 100 uses an OLED element as the light emitting element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 12 shows a configuration of a mobile phone that employs the electro-optical device 100 according to the embodiment described above as a display device. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 100. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled.

  FIG. 13 shows a configuration of a personal digital assistant (PDA) that employs the electro-optical device 100 according to the embodiment described above as a display device. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 10.

  The electronic apparatus to which the electro-optical device according to the present invention is applied includes, in addition to those shown in FIGS. 11 to 13, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, electronic paper, Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

DESCRIPTION OF SYMBOLS 10 ... Element part, 12 ... Wiring group, 14 ... Feed line, 16 ... Data line, 18 ... Signal line, 20 ... Drive circuit, 21 ... Scanning line drive circuit, 23 ... Data line drive Circuit, 25... Potential generation circuit, 30... Control circuit, 41, 43, 45 .. Feed line, 47... Initialization line, 50... Data line initialization unit, 100. ... Block, C1 ... First capacitor, C2 ... Second capacitor, E ... Light emitting element, GINI ... Initialization signal, GVH, GVL ... Control signal, GWR ... Scanning signal, MP ... Selection Part, ND ... node, SEL ... select signal, SW ... switch, TDR ... drive transistor, TSL ... select transistor, TIN ... initialization transistor, Vrmp ... lamp potential, U ... pixel circuit.

Claims (7)

A plurality of data lines that are divided into a plurality of blocks in units of a plurality of lines, and a plurality of pixel circuits that are arranged corresponding to each intersection of the plurality of scanning lines;
A plurality of signal lines provided in one-to-one correspondence with the plurality of blocks;
A plurality of selection units that are provided in one-to-one correspondence with the plurality of blocks, and that switch between conduction and non-conduction between each data line belonging to the corresponding block and the signal line corresponding to the block;
A drive circuit for driving the plurality of pixel circuits at a cycle of a unit period,
Each of the plurality of pixel circuits is
A driving transistor and a light emitting element connected in series to a path between the high-side power line and the low-side power line;
A first capacitive element disposed between a gate and a source of the driving transistor;
A selection transistor disposed between a gate and a data line of the driving transistor;
A set current that flows from the high-level power supply line to a path different from the path to the light emitting element through the driving transistor and a node interposed between the driving transistor and the light emitting element. Current generating means for generating,
The unit period includes a plurality of selection periods and a writing period after the plurality of selection periods,
Each of the plurality of selection units is
In the plurality of selection periods, each data line belonging to the block corresponding to the selection unit is sequentially selected to conduct to the signal line corresponding to the block,
The drive circuit is
In the plurality of selection periods, for each signal line, the pixel circuit corresponding to each intersection between each data line belonging to a block corresponding to the signal line and the scanning line to be selected in the unit period. A data potential corresponding to the specified gradation is output in order, and the selection transistor of each of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period is set to an off state,
In the writing period, the selection transistors of each of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period are simultaneously set to an on state,
In the plurality of selection periods and the writing period, the current generation unit is controlled so that the set current flows through the driving transistors of each of the plurality of pixel circuits corresponding to the scanning lines to be selected in the unit period. Thus, the voltage across the first capacitive element at the end of the writing period is set to a value reflecting the characteristics of the driving transistor.
An electro-optical device. Each of the selection units is
In the first selection period in the unit period, the data lines belonging to the block corresponding to the selection unit and the signal lines corresponding to the block are simultaneously conducted, so that The potential is set to the data potential output to the signal line corresponding to the block in the first selection period.
The electro-optical device according to claim 1. The unit period includes a set period before the plurality of selection periods,
The drive circuit is
In the set period, the potential of each data line is set to an initialization potential, and the selection transistors of each of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period are simultaneously turned on. By setting, the potential of the gate of the driving transistor is set to the initialization potential, while the current generating means is controlled so that the set current having a constant magnitude flows through the driving transistor, thereby The voltage across the capacitor is set to a value necessary for the set current to flow through the drive transistor;
The electro-optical device according to claim 2. The current generating means includes a second capacitive element including a first electrode and a second electrode, and a feeder line.
The first electrode is connected to the node while the second electrode is connected to the feeder;
The drive circuit is
From the start of the set period within the unit period to the end of the writing period, the potential output to the feeder line is changed over time.
The electro-optical device according to claim 3. From the start of the set period within the unit period to the end of the writing period, the potential output to the feeder line changes linearly.
The electro-optical device according to claim 4.   An electronic apparatus comprising the electro-optical device according to claim 1. A plurality of data lines that are divided into a plurality of blocks in units of a plurality of lines, and a plurality of pixel circuits that are arranged corresponding to each intersection of the plurality of scanning lines;
A plurality of signal lines provided in a one-to-one correspondence with the plurality of blocks,
Each of the plurality of pixel circuits is
A driving transistor and a light emitting element connected in series between the high-side power line and the low-side power line;
A first capacitive element disposed between a gate and a source of the driving transistor;
A set current that flows from the high-level power supply line to a path different from the path to the light emitting element through the driving transistor and a node interposed between the driving transistor and the light emitting element. A method of driving an electro-optical device comprising a current generation means at a cycle of a unit period,
The unit period includes a plurality of selection periods and a writing period after the plurality of selection periods,
In each of the plurality of selection periods, each data line belonging to each block is selected in order and made conductive to the signal line corresponding to the block, while each signal line belonging to the block corresponding to the signal line is connected to each signal line. By sequentially outputting the data potential corresponding to the designated gradation of the pixel circuit corresponding to each intersection between the data line and the scanning line to be selected in the unit period, the data potential is applied to each data line. writing,
In the writing period, the data potential written to the data line corresponding to the pixel circuit is supplied to each of the plurality of pixel circuits corresponding to the scanning line to be selected in the unit period,
In the plurality of selection periods and the writing period, the current generation unit is controlled so that the set current flows through the driving transistors of each of the plurality of pixel circuits corresponding to the scanning lines to be selected in the unit period. Thus, the voltage across the first capacitive element at the end of the writing period is set to a value reflecting the characteristics of the driving transistor.
A driving method for an electro-optical device.

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