JP2012110060A - Method for determining pwm control duty - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for determining a PWM control duty which can further reduce a noise level than techniques for slight variations in a communication frequency.SOLUTION: When slightly varying the duty of a PWM signal output to a drive circuit around a command value such that an average in a predetermined period matches the command value, a control IC 63 stores in a database 69 in a PC 68 data reflecting level measurements of noise components caused by actual supply to the PWM signal to the drive circuit along with modes of variation of the duty. By reference to such data stored in the database 69, the control IC 63 determines a mode of variation of the PWM duty to reduce a noise level of a frequency band to be suppressed in accordance with given operating environment and operating conditions.

Description

  The present invention relates to a method for determining a duty of PWM control for a drive control apparatus that controls switching of a load by outputting a PWM signal to a drive circuit.

One communication protocol used for wiring inside a vehicle is SbW (Safe by Wire). SbW is a protocol in which power supply and communication are performed using only two wires in order to be applied to a device that preferably has fewer wires, such as airbag control.
FIG. 14 shows a configuration in which one master (for example, an ECU for a vehicle) 1 and a plurality of slaves 2 (1 to 67) are connected in a line via a bus 3 (+, −). In addition, the switch 4 existing in each slave 2 is provided to disconnect the connection of the bus 3 to the slave 2 and to continue communication with only the normal slave 2 when a failure occurs in the subsequent slave 2. It has been.

  FIG. 15 shows voltage waveforms when the master 1 or the slave 2 drives the bus 3 when data is transmitted by communication using SbW. In SbW, the master 1 first supplies the operating power to each slave 2 by driving the bus 3 at the voltage level VLP in the power supply period (Power Phase). The data period following the power supply period (Data Phase) is a period in which the master 1 or slave 2 transmits 1-bit data, and the sum of both periods is defined as a 1-bit period (100% bit). ing. Further, the communication speed is determined by the length of this 1-bit period, and the communication speed may be dynamically changed in one system.

When the master 1 transmits data during the data period, the bus 3 is driven to one of the voltage levels VL0 and VL1. These voltage levels correspond to data “0, 1”, respectively. In the period in which the slave 2 transmits data, the master 1 drives the bus 3 to the voltage level VL0 in the data period. Note that the lengths of the power supply period and the data period are defined to be equal.
At this time, if the slave 2 does not drive the bus 3, the voltage level remains VL0 and data "0" is transmitted. When the slave 2 drives the bus 3 to VL1 whose voltage level is lower than VL0, data “1” is transmitted. When the slave 2 drives the bus 3 to VLS0 whose voltage level is lower than VL1, this means that an interrupt is generated for the master 1.

  FIG. 16 shows an example of data communication between the master 1 and the slave 2. The master 1 drives an SOF (Start Of Frame) indicating the start of communication by driving the bus 3 to VLP and VL0 at twice the length of one bit period (200% bit) at the communication rate at that time. Send. Each slave 2 recognizes the start of communication when the SOF is transmitted to the bus 3.

  Then, in order to specify the communication mode, the master 1 transmits two data bits of MSA and SEL, and thereafter, the slave 2 side transmits data. That is, Slot1_data and the subsequent CRC are data transmission periods of the master 1 (1), and CRC (Cyclic Redundancy Check) is an error detection code attached to Slot1_data. Thereafter, similarly, the other slaves 2 sequentially transmit Slot2_data, Slot3_data,... Slot_n_data. In the idle period when communication is not performed, the master 1 repeats a state in which the bus 3 is alternately driven to VLP and VL0.

As described above, SbW is a serial communication system that performs communication with the slave 2 while the master 1 supplies power during the power supply period through the two buses 3 (+, −).
Assuming that this communication system is applied to an airbag device mounted on a vehicle, a plurality of slaves 2 correspond to acceleration sensors arranged in each part of the vehicle. When any of the acceleration sensors detects an impact of an accident, a detection signal is transmitted from the slave 2 to the master 1. Then, the master 1 outputs an ignition command to an inflator of an airbag device (not shown) to generate gas and deploy the airbag.

As described above, in SbW, if the system is in operation, the master 1 continues to supply power to the slave 2 and drives the bus 3 even during the idle period. Accordingly, there is a problem that communication at a constant frequency is easily continued, and the power of the harmonic component having the frequency as a fundamental wave is increased to easily generate noise.
As a known technique for solving such a problem, for example, spread spectrum communication, frequency hopping applied to Bluetooth (registered trademark), such as frequency hopping, to disperse the power spectrum by changing the communication frequency, A technique for reducing the peak of a component that becomes noise is known.

In addition, since SbW itself is a technology that has not been widely spread, the applicant has not been able to find an appropriate prior art document to be presented.
Also, for example, in a system that performs switching control by outputting a PWM signal to a drive circuit that drives a load such as a motor, if the PWM duty is output constant, the harmonics of the PWM signal The same problem as in the case of the communication described above occurs for the components.

However, there are cases where the noise level cannot be sufficiently reduced only by introducing the above-described known technology.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a PWM control duty determination method capable of further reducing the noise level as compared with the technique of minutely changing the communication frequency. .

  According to the duty determination method of the PWM control of the present invention, the duty fluctuation means of the drive control device is configured such that the duty of the PWM signal output to the drive circuit is centered on the command value, and the average within a predetermined period matches the command value. Thus, the data reflecting the level measurement result of the noise component generated by applying the PWM signal to the drive circuit is stored in the measurement result storing means together with the duty variation mode. Then, referring to the data stored in the measurement result storage means, the PWM duty fluctuation mode is determined so as to reduce the noise level of the frequency band to be suppressed according to the given operating environment or operating condition. .

  That is, if the duty of the PWM signal is minutely varied as described above, the average of the duty within a predetermined period matches the command value, so that the drive control of the load is performed according to the command and the peak of noise generated by switching The level can be reduced and the noise frequency can be distributed. The measurement result storage means stores the noise generation result according to the PWM duty variation mode. By referring to the stored content, the measurement result storage means is responsive to the operating environment or operating condition given to the drive control device. Thus, the variation mode can be optimized so as to reduce the noise level of the frequency band to be suppressed.

Functional block diagram schematically showing the configuration of the master as a first reference example Functional block diagram showing the configuration of the frequency dispersion function unit built in the voltage driver An example of the state which changes a communication bit rate is shown, (a) is a figure which shows the relationship between the Load data value with respect to a counter, and a communication rate, (b) is a state transition diagram. Timing chart showing an example of operation of the frequency dispersion function unit The figure which shows the structure of the drive voltage / current adjustment part in a voltage driver inside Functional block diagram schematically showing the configuration of the slave The figure which shows the component which drives a bus to level VL1 or VLS0 in a communication driver / receiver. The figure which shows the voltage waveform in case a master or a slave drives a bus | bath when transmitting data by communication by SbW This is a second reference example and is a diagram for explaining the principle of minutely changing the bit rate. The figure which shows schematically the structure of the part which performs the fluctuation control of the bit rate The flowchart which shows the processing procedure in the fluctuation control section The figure which is one Example of this invention, and shows the apparatus which controls drive of the DC motor mounted in a vehicle The figure which shows notionally the setting process performed between control IC and a database The figure which shows the example of 1 structure of the communication system of a prior art Equivalent to FIG. The figure which shows an example of the data communication between a master and a slave

(First Reference Example)
Hereinafter, a first reference example will be described with reference to FIGS. The same parts as those in FIGS. 14 to 16 are denoted by the same reference numerals. FIG. 1 is a functional block diagram schematically showing a configuration of a master (communication device) 11 with a portion related to the gist as a center. The master 11 drives the bus 3 (BUS_A, BUS_B) by the CPU 12 controlling the voltage driver 13.
A voltage monitoring unit 14 for monitoring the drive level of the bus 3 is connected between the buses 3 (+) and 3 (−). The voltage monitoring unit 14 matches the data according to the monitoring result. Output to the circuit 15. The coincidence circuit 15 is also provided with data set by the CPU 12 writing to the set value register 16. The coincidence circuit 15 outputs a coincidence signal to the voltage driver 13 when the set value data coincides with the monitoring result data.

  FIG. 2 is a block diagram showing a configuration of the frequency dispersion function unit 17 built in the voltage driver 13. The frequency dispersion function unit 17 minutely changes the bit rate of communication, and includes a state transition sequencer 18, an adder / subtractor 19, a register 20, a counter 21, and a clock circuit 22. The clock circuit 22 supplies a clock signal clk having a frequency of 8 MHz, for example, to the counter 21. Control data L0_STATE is given to the state transition sequencer 18 by the CPU 12, and the state transition sequencer 18 performs the operation function of the adder / subtractor 19 each time a drive command from the counter 21 described later is counted by the value of the data L0_STATE. Outputs control signal PLUS / MINUS for switching to addition / subtraction.

  The adder / subtractor 19 is supplied with data L0_STEP corresponding to the amount of frequency dispersion from the CPU 12, and the data L0_STEP and the output data of the register 20 are supplied with a drive command from the counter 21 twice (VLP, Data Phase of Power Phase). VL0 or VL1) is added / subtracted each time it is output and output to the register 20. The output data of the register 20 is loaded into the counter 21. The counter 21 counts down the loaded data (Load data) with the clock signal clk, and outputs a drive command according to the count value.

FIG. 3 shows an example of a state in which the communication bit rate is changed by the frequency dispersion function unit 17. FIG. 3A shows the load data value (down count number by the clock signal clk) for the counter 21 and the communication rate. It is a table which shows the relationship. Assuming that the basic rate at which the variation is “0” is 80 kbps, if 50 clocks of the 8 MHz clock signal clk are counted, it becomes 1/2: 50% bit period of 1-bit transmission period. Then, the communication rate is varied up to ± 12% in increments of ± 4% with respect to this basic rate.
That is, when the load data is increased from “50” by “2” to “52”, “54”, “56”, the communication rate is −4%, −8%, −12% with respect to the basic rate. (Slower). Conversely, if the load data is decreased from “50” by “2” to “48”, “46”, “44”, the communication rate becomes + 4%, + 8%, + 12% with respect to the basic rate. (Gets faster).

  Therefore, FIG. 3B shows a state transition diagram. Starting from 50 clk: 0%, when the load data is decreased to 48 clk, 46 clk, and the minimum value 44 clk, the load data is changed to addition to 46 clk, Increase to 48 clk, 50 clk,. When the maximum value of 56 clk is reached, the subtraction starts from there and the data is reduced to the minimum value of 44 clk. By repeating the above state transitions cyclically, the communication rate is minutely changed up to ± 12% in increments of ± 4%.

  FIG. 4 is a timing chart showing an operation example of the frequency dispersion function unit 17. As shown in FIG. 4C, the change amount of the data loaded into the counter 21 is changed to + 8%, + 12%, + 8%, and + 4%. In this case, the adder / subtracter 19 performs subtraction for the first two communication waveforms, and the adder / subtractor 19 performs addition for the second two cycles. The communication waveform shown in FIG. 4A is not a waveform actually driven on the bus 3, but is shown as a rectangular wave for convenience of illustration.

  FIG. 5 shows the configuration of the drive voltage / current adjustment unit 23 inside the voltage driver 13. The drive voltage / current adjusting unit 23 is connected between a plurality of P-channel MOS transistors 24 (ac) connected in parallel between the power source V1 and the bus 3 (+), and between the bus 3 (−) and the ground. N channel MOS transistors 25 (a to c), a plurality of P channel MOS transistors 26 (a to c) connected in parallel between the power source V2 and the bus 3 (+), the bus 3 (−) and the ground A plurality of N-channel MOS transistors 27 (a to c) connected in between, a P-channel MOS transistor 28 and an N-channel MOS transistor 29 connected in series between the buses 3 (+) and 3 (−), etc. ing. The voltage of the power source V1 is set to about 14V, for example, and the voltage of the power source V2 is set to about 7V, for example.

  The gate signals for the MOS transistors 24 to 29 are given by a drive command from the frequency dispersion function unit 17 as a trigger. For the MOS transistors 24 to 27, selection circuits 30 (a, b), 31 is output. Further, a reference power supply VLM is connected to a common connection point (drain) of the MOS transistors 28 and 29, and a level variable DC power supply VL (+) is connected between the common connection point and the gates of the MOS transistors 28 and 29. ), VL (−) are connected to each other.

When the bus 3 is driven at the levels VLP and VL0, respectively, the drive voltage / current adjustment unit 23 sets ON and OFF of each MOS transistor as follows.
MOS transistor 24 25 26 27 28 29
VLP ON ON OFF OFF OFF OFF OFF
VL0 OFF OFF ON ON ON ON
When the bus 3 is driven at the level VLP, one or more MOS transistors 24a to 24c and 25a to 25c are turned on by the selection circuit 30. At this time, the level VLP is determined by the voltage of the power source V1 and how many of the MOS transistors 24a to 24c and 25a to 25c are turned on simultaneously. For example, when only the MOS transistors 24a and 25a are turned on and when all the MOS transistors 24a to 24c and 25a to 25c are turned on, the latter is equivalent to increasing the transistor size W equivalently. Thus, the current supply capability to the bus 3 is improved. In addition, since the ON resistance of the transistor also decreases, as a result, the voltage VLP further increases.

On the other hand, when the bus 3 is driven at the level VL0, one or more of the MOS transistors 26a to 26c and 27a to 27c are turned on by the selection circuit 31. Further, the MOS transistors 28 and 29 are set so that both are turned on when a gate voltage is applied by adjusting the voltages VL (+) and VL (−). At this time, when the threshold voltage of the MOS transistors 28 and 29 is VT, the level VL0 is
Bus 3 (+): VLM + VL (+) + VT
Bus 3 (-): VLM-VL (-)-VT
And the level VL0 is the difference between the two. VL0 = VL (+) + VL (−) + 2VT
It will be determined by.

  Also in this case, the level VL0 slightly fluctuates and the current supply capability to the bus 3 also changes depending on how many MOS transistors 26a to 26c and 27a to 27c are turned on. The selection of the number of transistors to be turned on by the selection circuits 30 and 31 may be changed, for example, every time the transistors are driven to each level, or may be changed within one drive period.

  FIG. 6 is a functional block diagram schematically showing the configuration on the slave (communication device) 41 side. A voltage monitoring circuit 42 is connected between the buses 3 (+) and 3 (−). The voltage monitoring circuit 42 monitors the voltage of the bus 3 driven by the master 11 to obtain information for the slave 41 to grasp the communication timing. The voltage monitoring circuit 42 includes a comparator for voltage level comparison. Has been. The voltage monitoring circuit 42 monitors whether the drive level of the bus 3 is normal and outputs the monitoring result to a CPU (microcomputer) 43.

  The voltage monitoring circuit 42 sets the data count voltage threshold VDC to a level slightly higher than VL0, and every time the rise of the voltage level of the bus 3 exceeds the threshold VDC, a one-shot pulse is set. Is output to the data counter 44. Further, the voltage monitoring circuit 42 sets the U / D switching signal output to the up / down counter 45 to the high level while the voltage level of the bus 3 is maintained at VLP. Then, when the master 11 stops driving the bus 3 in the power phase and the voltage level is lowered from the VLP by a predetermined value, the U / D switching signal is changed from high to low.

  The up / down counter 45 performs a counting operation based on the count clock signal output from the clock circuit 46 when the count enable signal (CE2) provided by the data counter 44 is active. An up-count operation is performed while the U / D switching signal is at a high level, and a down-count operation is performed when the U / D switching signal is at a low level. The U / D switching signal is also given to the communication driver / receiver 47.

The CPU 43 drives the bus 3 via the communication driver / receiver 47 to transmit data to the master 11 and receives data transmitted from the master 11 via the communication driver / receiver 47. The power transmitted by the master 11 in the power phase is smoothed by a power supply circuit (not shown) and supplied to each part of the slave 41 as an operating power supply.
Further, when the CPU 43 detects that the master 1 has transmitted SOF on the bus 3 via the communication driver / receiver 47, the CPU 43 activates the count enable signal (CE1) to be given to the data counter 44. Then, the data counter 44 starts counting pulses given by the voltage monitoring circuit 42, that is, counting the number of data transmitted on the bus 3 from the output time of the SOF. When the count value becomes a value corresponding to the start of the data transmission period of the slave 11, the count enable signal (CE2) given to the up / down counter 45 is made active.

When the enable signal CE2 becomes active and the U / D switching signal changes from high to low, the communication driver / receiver 47 starts driving the bus 3 according to transmission data given by the CPU 43. However, when data “0” is transmitted, the bus 3 is not driven as described above.
FIG. 7 shows components for driving the bus 3 to the level VL1 or VLS0 in the communication driver / receiver 47. A plurality of NMOS transistors 48a, 48b,..., 48n are connected in parallel between the bus 3 (+) and the power source V3. A gate signal is supplied to the gates of the transistors 48 via a selection circuit 49.

  Similar to the selection circuits 30 and 31 on the master 11 side, the selection circuit 49 selects how many MOS transistors 48 are turned on in response to a drive command given from the CPU 43. By the selection, when the slave 41 drives the bus 3 to the level VL1 or VLS0, the drive level is changed similarly to the master 11 side, and the current supply capability to the bus 3 is changed.

  Next, the operation of the first reference example will be described with reference to FIG. FIG. 8 shows communication waveforms on the bus 3 when the master 11 and the slave 41 drive the bus 3, respectively, by changing the drive level and the current supply capability. That is, the drive levels VLP and VL0 change for each drive period, and the fall of the level change and the slope of the rise change due to the change in the current supply capability. In addition, when the falling and rising slopes are changed more gently, the rapid change of the waveform at the drive level change point can be relaxed and rounded, so that the generation of harmonic components is suppressed.

  In practice, the change in the drive state is performed simultaneously with the minute fluctuation of the communication rate shown in FIG. 4, so the distribution state of the frequency spectrum generated according to the communication waveform simply fluctuates the communication rate. Compared to the case, it becomes more widespread. Therefore, the unnecessary radiation level generated with the communication is more relaxed when concentrated on a specific frequency, so that the peak of the level when viewed in the whole area can be reduced.

Here, the drive levels in SbW are set to the following voltage values, for example.
VLP: 12V, VL0: 5V, VL1: 3V, VLS0: 0V
For each level, an allowable range of, for example, about 0.5 V to 1.4 V is defined between the lower limit and the upper limit. Therefore, when driving each level, the master 11 and the slave 41 vary the level within the above-described allowable range.

As described above, according to the first reference example, the master 11 slightly changes the communication frequency during communication and changes the drive level of the bus 3 within an allowable range, thereby further suppressing the peak level of generated noise. can do. Further, since the master 11 changes the current drive capability when driving the bus 3 and changes the time required for level transition, the slope of the waveform when the signal level changes dynamically changes the signal frequency band. Can be further expanded, and the peak level of generated noise can be further suppressed. Furthermore, since the master 11 minutely varies the communication frequency according to the circulation pattern, the configuration necessary for minutely varying the frequency can be simplified.
In addition, the slave 41 also changes the drive level when driving the bus 3 during communication, and also changes the time required for level transition by changing the current drive capability, so the effect of suppressing the peak level of noise Can be further improved.

(Second reference example)
9 to 11 show a second reference example. The same reference numerals are given to the same parts as those in the first reference example, the description thereof is omitted, and different parts will be described below. In the first reference example, when the communication frequency is slightly changed, the data is cyclically changed with 12 bits as one cycle. However, in the second reference example, on the master side, a communication frame that is a group of bit data is unit. Manage the fluctuations as

  First, the principle will be described with reference to FIG. As shown in FIGS. 9 (a) and 9 (b), each communication frame is composed of a plurality of data bits, and the transmission time of the communication frame is relative to the initially set time according to the specifications of the communication protocol. The fluctuation tolerance is set. As an example, assuming that the variation tolerance is ± 10%, when the transmission period (bit rate) of each bit constituting one communication frame is varied, the total of the variations is within ± 10% of the above tolerance. Set to be.

  That is, for example, when the number of bits in one frame is “10”, only one of the bits does not change the transmission period, 5 bits can be changed to + 10%, and 4 bits can be changed to −10%. For example, the sum of the fluctuation amounts of one frame is + 10%. As in the first reference example, when the basic rate is 80 kbps, as shown in FIG. 9C, when the rate is changed by −10%, the rate determination counter as a 100% bit period is used. The data to be loaded may be “110”. The “sampling point” shown in FIG. 9C indicates the timing when it is assumed that the receiving side samples bit data near the center of one bit period for other general serial communication other than SbW. ing.

  FIG. 10 schematically shows a configuration of a portion that performs bit rate fluctuation control as described above. The variation control unit 51 includes a frame width control unit 52, a bit number control unit 53, and a bit rate control unit 54. The frame width control unit 52 includes a register 52a for determining the width of one communication frame, that is, the transmission time, and the bit number control unit 53 is a register for setting how many bits the frame has to be configured. 53a and a counter 53b for counting the number of transmissions of 1-bit data. The bit rate control unit 54 includes a register 54a for setting a communication rate and a counter 54b for counting the bit rate for each bit constituting the frame.

  That is, in the bit rate control unit 54, the number of clocks counted by the counter 54b and the number of clocks set in the register 54a are compared by a comparator (not shown). If they match, the 100% bit period is determined and a bit clock is generated. The bit clock is supplied to the counter 53 b of the bit number control unit 53. Further, in the bit rate control unit 54, the data in the register 54a of each bit is switched by a multiplexer or the like to be compared.

In the bit number control unit 53, if the counter 53b counts the number of output bit clocks and the count value matches the set value of the register 53a, one frame is completed.
FIG. 11 is a flowchart showing a processing procedure in the variation control unit 51, including the processing contents by hardware. First, when the width of one communication frame is set within the allowable range in the specification in the frame width control unit 52 (step S1), the number of bits transmitted in one frame is set in the register 53a of the bit number control unit 53 (step S1). S2). The process in step S2 may be automatically set based on the relationship between the frame width set in step S1 and the basic rate.

  Next, the bit rate control unit 54 writes and sets the bit rate (including fluctuation value) of the first transmission to the register 54a (step S3), and the count value of the counter 54b matches the data value of the register 54a. (Step S4: NO), the process proceeds to Step S5. If the count value of the counter 53b does not match the set value of the register 53a (YES) in the bit number control unit 53, the process returns to step S3, and the rate data of the next bit to be transmitted is set in the register 54a. Further, the processing in step S3 may also be automatically set based on the relationship between the frame width and the number of bits set in steps S1 and S2 and the basic rate.

  As described above, the processes of steps S3 to S5 are repeated. If the count value of the counter 53b matches the set value of the register 53a (NO) in step S5, the transmission process for one frame is completed. The method for changing the data voltage level is the same as in the first reference example.

  As described above, according to the second reference example, when the master determines the variation value of the transmission time within a permissible range for the communication frame that is a group of transmission data, the master determines the transmission time of the 1-bit period constituting the communication frame. The total of the variation values is varied so as to be within the variation value of the communication frame. Accordingly, the time fluctuation given for one bit period can be more diversified within the frame in units of communication frames, so that the peak of the noise level can be further reduced and the frequency of the noise component can be more dispersed. .

(Example)
12 and 13 show an embodiment of the present invention. In this embodiment, when the present invention is applied to a device that drives a DC motor by PWM control, a method of optimizing and setting the amount of fluctuation that the drive control device gives to the PWM duty is shown. FIG. 12 shows an apparatus for driving and controlling a DC motor mounted on a vehicle, for example. A control IC (drive control device, duty changing means) 63 is connected between power supply lines 62 (+) and 62 (−) connected to the positive and negative terminals of the battery 61 of the vehicle. A series circuit of a drive circuit 64 and a motor (load) 65 is connected, and a flywheel diode 66 is connected to the motor 65 in parallel.

  The control IC 63 receives a control signal given from an external ECU (Electronic Control Unit) 67 and outputs the drive signal as a PWM signal to the drive circuit 64 to control the drive of the motor 65. The drive circuit 64 includes a drive element such as a power MOSFET. Further, when the control IC 63 determines a predetermined command value according to the control signal given from the ECU 67 for the duty of the PWM signal, the command value is the same as the control shown in the first and second reference examples. To fluctuate.

  For example, if the determined duty command value is 70%, the command value is varied within a range of, for example, ± 5% (65% to 75%), and the duty of the PWM signal thus varied is changed. When averaged over a certain period, it is varied so as to coincide with the command value of 70%. As a result, the driving power of the motor 65 is equivalent to a PWM duty of 70%, and when the PWM duty is fixed at 70% and output, the noise peak generated by the harmonic component is reduced, and the noise is reduced. Can be dispersed.

  FIG. 13 conceptually shows a method for optimizing the variation mode of the duty given to the PWM signal for each product for the control IC 63 configured as described above. That is, when the variation mode of the duty given to the PWM signal is changed, the noise generation mode is changed accordingly. Therefore, a predetermined variation pattern is set in the control IC 63 and incorporated into the product, and noise generated when the motor 65 is actually driven is measured. The measurement result is stored in the personal computer (PC) 68.

A frequency dispersion value database (measurement result storage means) 69 is formed by sequentially storing measurement results in the PC 68 by changing the variation pattern. Then, with reference to the database 69, any variation depending on the use conditions, status, environment and load type of each product, manufacturing variation of the control IC 63, noise level and frequency components required to be suppressed for the product. You can see if the pattern is optimal for noise suppression.
Therefore, before shipping the control IC 63, the optimum pattern for changing the PWM duty according to the product is determined and written in the internal register 63R of the control IC 63 for setting. Then, the control IC 63 varies the PWM duty according to the variation pattern set in the internal register 63R.

  As described above, according to the present embodiment, the control IC 63 slightly fluctuates the duty of the PWM signal output to the drive circuit 64 so that the average within a predetermined period coincides with the command value with the command value as the center. In this case, the data reflecting the level measurement result of the noise component generated by actually applying the PWM signal to the drive circuit 64 is stored in the database 69 of the PC 68 together with the duty variation mode. Then, referring to the data stored in the database 69, the PWM duty variation mode by the control IC 63 so as to reduce the noise level of the frequency band to be suppressed according to the given operating environment, operating conditions, etc. To decide. Therefore, the duty variation mode can be optimized so as to reduce the noise level of the frequency band to be suppressed according to each product.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
As for the range in which the communication frequency is minutely changed, the reference frequency may be arbitrarily set within a range of about ± several% to several tens%. Further, the frequency variation is not limited to the circulation pattern, and may be varied in a random pattern.
In the master 11, only the level VLP may be changed.
In the slave 41, only one of the levels VL0, VL1, and VLS0 may be changed.
The configuration for changing the drive level or the configuration for changing the current driving capability may be provided in only one of the master and the slave. Further, only one of the drive level and the current drive capability may be changed.

In order to change the rising and falling slopes of the waveform accompanying the drive level transition, the drive time may be changed. That is, the time for actually driving the bus may be shortened, and the drive may be stopped for the remaining period to enter a high impedance state.
In the second reference example, when changing each bit rate, the absolute value of the fluctuation amount may be changed for each bit. Further, the total sum of these fluctuation amounts may be smaller than the allowable range set for the frame. Also, the variation value for the frame may be set smaller than the maximum allowable value in the specification.
Asynchronous communication is performed between the master and a plurality of slaves, not limited to SbW. The master supplies power to the bus, and the master or slave drives the bus to transfer 1-bit data on the bus. The present invention can be applied to any system that employs a protocol that performs communication for a continuous period including a period for outputting data to the network.

  In the drawing, 3 is a bus, 11 is a master (communication device), 13 is a voltage driver, 14 is a frequency dispersion function unit, 23 is a drive voltage / current adjustment unit, 41 is a slave (communication device), and 63 is a control IC (drive). 64, a drive circuit, 65 a DC motor (load), and 69 a frequency dispersion value database (measurement result storage means).

Claims (1)

The load is controlled by outputting a PWM (Pulse Width Modulation) signal to the drive circuit, and the duty of the PWM signal is averaged over a predetermined period centered on the duty command value determined for the PWM signal. In a method for setting a variation mode of the duty with respect to a drive control device including a duty variation unit that minutely varies so as to coincide with the command value,
The drive control device stores the data reflecting the level measurement result of the noise component generated by outputting the PWM signal to the drive circuit together with the duty variation mode by the duty variation unit in the measurement result storage unit,
By referring to the data stored in the measurement result storage means, it is given by the duty fluctuation means so as to reduce the noise level of the frequency band to be suppressed according to the given operating environment or operating condition. A duty determination method for PWM control, characterized by determining a variation mode of the duty.

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