JP2012195519A - Semiconductor element and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply provide a termination structure (junction termination structure) which does not significantly affect the reverse breakdown voltage of an SiC semiconductor device, even if the process conditions vary in the impurity addition process or the passivation film formation process.SOLUTION: The SiC semiconductor element has a junction termination structure consisting of a first conductivity type breakdown voltage sustention layer and a region of second conductivity type different from the first conductivity type having an infinite length, in the outer peripheral end of the element. The junction termination structure is formed so that the impurity concentration of the first conductivity type region is not uniform in the first direction, i.e. the layer direction, in a part of the junction termination structure but is modulated spatially from the outer peripheral end of the element as the inside end of the junction termination structure toward the outside end of the junction termination structure to decrease gradually.

Description

  The present invention relates to a semiconductor element and a method for manufacturing the semiconductor element, and more particularly to a semiconductor technology having a high voltage structure.

  Wide gap semiconductor materials such as silicon carbide (SiC) have various excellent characteristics such as about 10 times higher dielectric breakdown strength than silicon (Si), and high withstand voltage power with high reverse voltage resistance. It attracts attention as a material suitable for semiconductor devices. Power semiconductor devices are classified into unipolar elements such as Schottky diodes, MOSFETs, and JFETs, and bipolar elements such as pn diodes, bipolar transistors, IGBTs, and GTO thyristors, but SiC is more power than Si. A significant reduction in loss can be realized.

  As a conventional pn diode using SiC, for example, there is an element having a mesa structure as shown in FIG. In this pn diode, an n-type breakdown voltage maintaining layer 102 is formed on the other surface of an SiC single crystal n + type substrate 101 having a cathode electrode 105 formed on one surface, and a p-type is formed at the center of the n-type breakdown voltage maintaining layer 102. A charge injection layer 103 is formed. A p-type layer 151 for termination is formed on both sides of the p-type charge injection layer 103.

  Here, “termination” (junction termination) refers to various semiconductor structures provided around the pn junction in order to alleviate electric field concentration around the pn junction through which the current of the high breakdown voltage semiconductor element flows. It is. In the pn diode of FIG. 18, a pn junction for passing a current and a pn junction between a termination p-type layer 151 and an n-type breakdown voltage maintaining layer 102 for reducing electric field concentration are made of boron, aluminum, or the like. It is formed by ion implantation.

  Further, Patent Document 1 below discloses a technique in which an energization deterioration preventing layer that spatially separates the surface and the pn junction interface is formed on the mesa wall portion or the mesa wall portion and the mesa peripheral portion. In the structure shown in FIG. 19 corresponding to FIG. 3, the electric field relaxation layer 231 is formed in the mesa peripheral portion 210. This electric field relaxation layer 231 is formed by ion implantation of p-type impurities.

  By forming the electric field relaxation layer 231, when a reverse voltage is applied, a depletion layer spreads in a region where the electric field relaxation layer 231 is formed, and the breakdown voltage performance is further improved by this depletion layer. The electric field relaxation layer 231 is formed in an annular shape around the mesa. The electric field relaxation layer 231 is formed continuously from the p-type conductive layer 220. In the present specification, the invention related to the junction termination structure is described by taking a mesa diode as an example. However, the present invention is not limited to the mesa diode but may be a planar type. Although a pn junction diode will mainly be described as an example, it can also be applied to unipolar elements such as Schottky diodes and MOSFETs, and bipolar elements such as GTO thyristors and IGBTs.

  In one aspect of the electric field relaxation layer 231, the concentration of the p-type impurity is different, and the electric field relaxation layer 231 is composed of a plurality of annular layers that are continuous in the radial direction. In particular, a JTE (Junction Termination Extension) structure is preferable. An example of a specific structure of the electric field relaxation layer 231 is shown in FIG. In FIG. 19A, the electric field relaxation layer 231 is formed by a plurality of continuous annular p-type terminations 231a to 231c. The impurity concentrations in these p-type terminations 231a to 231c are different from each other. As an example, the impurity concentration is gradually decreased toward the outermost edge. The p-type terminations 231a to 231c may have substantially the same radial width, but may have different widths such as increasing the radial width of the inner p-type termination 231a as shown in FIG. Further, although the number of annular p-type terminations is three in the figure, the number may be further increased. In FIG. 19B, the electric field relaxation layer 231 is formed by a plurality of spaced annular p-type terminations 231d to 231g.

Japanese Patent Laying-Open No. 2005-259037

  In Patent Document 1, the electric field relaxation layer 231 is formed of a plurality of spaced annular p-type terminations 231d to 231g in order to increase the breakdown voltage in the mesa structure.

  However, Patent Document 1 states that “the impurity concentrations in these p-type terminations 231d to 231g may be the same or different from each other. The p-type terminations 231d to 231g are arranged in the inner p-type as shown in FIG. The width may be different from each other, for example, by increasing the radial width of the termination 231d.Although the number of annular p-type terminations is four in the figure, the number may be further increased. " However, an electrolytic relaxation layer is provided in order to increase the breakdown voltage in the mesa structure, and consideration is not given to variations in impurity concentration in the ion implantation and impurity diffusion processes in the p-type terminations 231d to 231g.

  However, in SiC, when activation annealing after ion implantation is performed, unlike Si and the like, the activation rate changes greatly due to slight variations in conditions of activation annealing and ion implantation, and p is the implanted layer. There is a problem that the impurity concentrations of the mold terminations 231d to 231g greatly vary, and the reverse breakdown voltage often becomes a low value different from the intended one. In addition, since a relatively high-density electric charge exists at the interface between the insulating film used for surface protection and SiC, this often breaks the balance of electric charges, and the reverse breakdown voltage as designed is often not obtained.

  The present invention solves the above-described problems. For example, in a SiC semiconductor structure, a new termination structure (junction termination structure) that does not significantly affect the reverse breakdown voltage even if there are variations in process conditions in the impurity addition step. The purpose is to provide. Another object of the present invention is to provide a SiC semiconductor manufacturing technique having a stable reverse breakdown voltage based on such a technique.

  According to one aspect of the present invention, a first conductivity type (for example, n-type) breakdown voltage maintaining layer and a second conductivity type (for example, a p-type) different from the first conductivity type having a finite length are provided at an outer peripheral end of the element. ) Region of the junction termination structure, and a part of the junction termination structure is not uniform with respect to the layer direction which is the first direction (not uniform) inside the junction termination region. The impurity concentration of the first conductivity type (for example, p-type) region is spatially modulated from the outer peripheral end of the element toward the outer end of the junction termination region (average viewed macroscopically) There is provided a SiC semiconductor device having a junction termination structure formed with a tendency that the impurity concentration gradually decreases.

  According to the SiC semiconductor device described above, the junction termination structure is formed such that the impurity concentration of the first conductivity type region is spatially modulated and the average impurity concentration viewed macroscopically tends to gradually decrease. Therefore, the electric field concentration on the surface and the bulk is suppressed as compared with the junction termination structure having a uniform impurity concentration. Therefore, it is possible to suppress a decrease in the reverse breakdown voltage of the semiconductor element that depends on the variation in impurity concentration.

  In the junction termination structure, a region having the same impurity concentration distribution of the second conductivity type in a depth direction which is a second direction intersecting the first direction is divided into a plurality of layers in the layer direction. In addition, it is preferable that the width of the divided region is formed with a tendency to narrow toward the outside of the junction termination region.

  A region having the same impurity concentration distribution of the second conductivity type in the depth direction is divided into a plurality of layers in the layer direction, and the width of the divided region tends to narrow toward the outside of the junction termination region. Therefore, it is possible to realize a junction termination structure formed with a simple structure and having a tendency that the average impurity concentration seen macroscopically decreases gradually.

  In the junction termination structure, a region in which the second conductivity type impurity concentration distribution is the same in the depth direction, which is the second direction intersecting the first direction, is divided into a plurality of layers in the layer direction. In addition, the distance between the divided regions may be formed with a tendency to expand toward the outside of the junction termination region. Even in this structure, it is possible to realize a junction termination structure formed with a simple structure and having a tendency that the average impurity concentration seen macroscopically gradually decreases.

In the junction termination structure, when the width of the region divided in the layer direction is L _Wj (j is a natural number and is numbered from the inside of the junction termination region), and the interval between the regions is L _Sj , L _{Wj + 1} / (L _{Wj + 1} + L _{Sj + 1} ) = A × L _Wj / (L _Wj + L _Sj ) (where A is a real number in the range of 0.1 to 0.9, preferably 0.5 to 0.8) It is preferable that the average impurity concentration is spatially modulated so as to hold.
By having this relationship, electric field concentration can be more effectively suppressed.

  In addition, the present invention provides a method for manufacturing an SiC semiconductor device according to any one of the above, wherein the method includes a step of collectively adding the second conductivity type impurity. It is. Accordingly, it is possible to reduce the number of steps required for adding the second conductivity type impurity.

  According to the present invention, a new termination structure (junction termination structure) that does not significantly affect the reverse breakdown voltage even if there are variations in process conditions in the impurity addition step and the formation of the surface protective film is obtained in the SiC semiconductor device. It is done. Moreover, based on such a technique, a SiC semiconductor element manufacturing technique having a stable reverse breakdown voltage can be provided.

It is structural sectional drawing which shows an example of the basic structure of a SiC high voltage | pressure-resistant semiconductor element. FIG. 2 is a diagram showing a relationship between a dose amount of an inner JTE structure and a reverse breakdown voltage (V) of a high breakdown voltage SiC semiconductor device in the structure shown in FIG. 1. FIG. 3 is a structural cross-sectional view showing a configuration example of a high voltage SiC semiconductor element according to the present embodiment, FIG. 3A is a diagram corresponding to FIG. 1A, and FIG. It is a figure which shows the structure of the principal part of (a). It is the figure which matched and showed the structure shown in FIG. 3, and the figure which looked at it from the upper side. It is a figure which shows the example of the spatial modulation structure by this Embodiment. It is a figure which shows the example of the spatial modulation structure by this Embodiment, and is a figure following FIG. 5A. 1 zone JTE, 1 zone JTE + 1R (ring), 1 zone JTE + 3R (Ls / Lw = 10/10 μm), 1 zone JTE + 5R (Ls / Lw = 10/10 μm), 2 zone JTE, 1 zone JTE + 5 SMR (spatial modulation ring: Ls It is a figure which shows the dose dependence of the p-type impurity of a reverse breakdown voltage in the case of / Lw = 6 / 14-8 / 12-10 / 10-12 / 8-14 / 6). It is a figure which shows an example of the manufacturing process for the case of 2 zone JTE + 3SMR (spatial modulation ring) of FIG. 5A (c) as an example. It is a figure which shows the creation process of a JTE area | region, and is a figure following FIG. FIG. 9 is a diagram illustrating a process following the process in FIG. 8. It is a figure following FIG. 8 which shows the manufacturing process of an electrode. 1 zone JTE structure) FIG. 11A) and an example of electric field distribution in 1 zone JTE + 3SMR (FIG. 11B: 1 zone JTE + 3SM in FIG. 5A (b)) structure. It is a figure which shows the position (distance from a mesa edge) dependence of the surface electric field in Fig.11 (a) and FIG.11 (b). It is a figure which shows the process of forming the spatial modulation structure of (2 ⁿ -1) by n times of ion implantation. It is a 4H-SiCPIN diode including the structure of FIG. 13, and shows the dose dependency of the reverse breakdown voltage on the innermost JTE when the total JTE width is 600 μm. It is a structural sectional view showing an example of a high voltage SiC semiconductor device according to the present embodiment. It is a semiconductor element which consists of SiC power MOSFET which is a 1st application example. It is sectional drawing which shows an example of a structure of a Schottky diode. It is a figure which shows the structure of the high voltage | pressure-resistant diode of mesa structure. It is a figure which shows the example which formed the electric field relaxation layer in the mesa peripheral part.

  Hereinafter, a semiconductor technology according to an embodiment of the present invention will be described using a high power device (hereinafter referred to as a high voltage SiC semiconductor device) using a high voltage SiC-pn junction as an example. In the following description, the p-type (first conductivity type) and the n-type (second conductivity type) will be described separately, but the same applies to structures in which p and n are reversed. In the following, a mesa structure is taken as an example, but a planar structure may be used.

FIG. 1 is a structural sectional view showing an example of a basic structure of a high voltage semiconductor device. FIG. 1A is a structural cross-sectional view showing an example of a high breakdown voltage SiC semiconductor element having a RESURF (surface electric field relaxation) region. As shown in FIG. 1A, a high breakdown voltage SiC semiconductor element having a JTE (RESURF) region includes a 4H—SiC n-type substrate 1 and an n ⁻ formed on one surface side (the upper surface side in the drawing). -SiC layer (first conductivity type withstand voltage maintaining layer, for example, 120 μm in thickness and n-type impurity concentration of 1.0 × 10 ¹⁴ cm ⁻³ as an example) 3 and an island shape formed thereon by mesa formation technology A diode element comprising the formed p ⁺ -SiC layer 5, the anode electrode 7 formed thereon, and the cathode electrode 11 formed on the other surface (the lower surface in the figure) of the n-type substrate 1. ing. Further, the p-SiC (first layer) extends from the outer peripheral end of the diode element, that is, the end of the mesa-shaped p ⁺ -SiC layer 5 to the surface region of the n ⁻ -SiC layer 3 from the end to a finite length. A first JTE (junction termination) region 12 of 2 conductivity type is formed. The p type impurity concentration of the p ⁺ -SiC layer 5 is, for example, about 10 ²⁰ cm ⁻³ . The p-type impurity concentration of the first JTE region 12 is, for example, about 10 ¹⁶ to 10 ¹⁷ cm ⁻³ . The n ⁻ -SiC layer 3 is covered with an insulating film such as SiO _2, and a polyimide 15 that opens the anode electrode 7 is formed thereon.

In the semiconductor element shown in FIG. 1B, in addition to the structure shown in FIG. 1A, a second JTE (junction termination: third) having a higher impurity concentration in the first JTE (junction termination) region 12b. It has a two-zone JTE structure in which a conductive region) region 12a is formed. The p-type impurity concentration of the second JTE (junction termination) region 12a is, for example, about 10 ¹⁷ cm ⁻³ .
It should be noted that the parameters such as the impurity concentration are merely examples, and can be arbitrarily selected within a practicable range.

  FIG. 2 is a diagram showing the relationship between the dose amount of the inner JTE structure and the reverse breakdown voltage (V) of the high breakdown voltage SiC semiconductor element in the structure shown in FIG. As can be seen from FIG. 2, the high breakdown voltage SiC semiconductor element having the two-zone JTE structure has a slightly higher breakdown voltage than the one-zone JTE structure high breakdown voltage SiC semiconductor element, and a high reverse in a wide dose range. It can be seen that the directional breakdown voltage is shown. As described above, by forming two JTE structures, the dose dependency of the reverse breakdown voltage is reduced. However, since two JTEs having different impurity concentrations are produced, the cost is increased and the process is also complicated. .

  FIG. 3 is a structural cross-sectional view showing a configuration example of the high voltage SiC semiconductor element according to the present embodiment, FIG. 3A is a diagram corresponding to FIG. 1A, and FIG. These are figures which show the structure of the principal part of Fig.3 (a). The parameters (thickness, dose, etc.) of each layer are basically the same as those in FIG. The JTE 12 in FIG. 1A corresponds to the connection termination of the one-zone JTE 13 + SMR (spatial modulation) structure 21 in FIG.

The structure shown in FIG. 3A is formed in the n ⁻ -SiC layer 3 (breakdown voltage maintaining layer) in addition to the structure shown in FIG. 1A, and is formed at the end of the JTE 13 on the direction side away from the anode 7. The spatial modulation structure 21 is formed so as to tend to decrease in the effective impurity concentration of the p-type impurity toward the direction away from the end of the p ⁺ -SiC layer 5. A junction termination structure is formed by the JTE 13 and the spatial modulation structure 21.

As shown in FIG. 3B, as an example of the spatial modulation structure 21, a p-type having the same impurity concentration as the p-type impurity concentration of JTE13 and divided into a plurality (three in the figure) in the layer direction. Impurity regions 21a, 21b, and 21c are provided. More specifically, the p-type impurity concentration distribution in the depth direction of JTE 13 and the p-type impurity concentration distribution in the depth direction of p-type impurity regions 21a, 21b, and 21c are the same. In this spatial modulation structure 21, the effective impurity concentration in the spatial modulation structure is separated in the layer direction from the end of the p ⁺ -SiC layer 5 by changing the distance Ls between the regions and the width Lw of the region. A slope can be formed that becomes lower as Therefore, the electric field concentration at the end of the junction termination structure formed by the JTE 13 and the spatial modulation structure 21 can be suppressed.

  3A, as in FIG. 1A, the total distance from the mesa edge to the edge of the p-type impurity region 21c (the edge of the junction termination structure) is 600 μm. In FIG. 3A, the total distance of the junction termination structure of JTE13 + spatial modulation structure 21 corresponds to the distance of JTE12 in FIG.

FIG. 4 is a view showing the structure shown in FIG. 3 and the view of the structure as viewed from above. As shown in FIG. 4, the first to third p-type impurity regions 21a, 21b, and 21c are located radially away from the outer peripheral edge of the p ⁺ -SiC layer 5 of the high voltage SiC semiconductor element. It is formed as a band-like region (ring) having a concentric rectangular shape as a whole. Therefore, electric field concentration at the time of applying a high voltage to the pn junction can be suppressed at any position in a concentric rectangular (for example, square) region radially away from the p ⁺ -SiC layer 5.

  5A and 5B are diagrams showing examples of the junction termination structure having the spatial modulation structure according to the present embodiment. FIG. 5A (a) shows a basic structure in which first to third p-type impurity regions 21a, 21b, and 21c are formed in order from the end of the JTE 13 in the layer direction. The distance Ls1 between the end and the inner peripheral end on the opposite side of the first p-type impurity region 21a is 10 μm, the width Lw1 of the first p-type impurity region 21a is 10 μm, and the outer periphery of the first p-type impurity region 21a The distance Ls2 between the end and the inner peripheral end on the opposite side of the second p-type impurity region 21b is also 10 μm, the width Lw2 of the second p-type impurity region 21b is also 10 μm, and the second p-type impurity region 21b. The distance Ls3 between the outer peripheral end of the second p-type impurity region 21c and the inner peripheral end on the opposite side of the third p-type impurity region 21c is also 10 μm, and the width Lw3 of the third p-type impurity region 21c is also 10 μm. This structure is referred to as 1 zone JTE + 3R (ring). The depth from the p-type impurity regions 21a to 21c is the same as the depth of the JTE structure, but is not limited to this.

  In FIG. 5A (b), for example, Ls1 / Lw1-Ls2 / Lw2-Ls3 / Lw3 is 5 / 10-10 / 10-15 / 10. In other words, the interval (Ls) between the p-type impurity regions becomes longer in the direction away from the end of the JTE 13. Needless to say, the interval Ls is not limited to the above numerical value as long as it is formed in the direction in which the width of the p-type impurity region is effectively increased. Conversely, the interval (Ls) between the p-type impurity regions may be fixed, and the width (Lw) of the p-type impurity region may be reduced toward the outside. This structure is called 1 zone JTE + 3SMR (spatial modulation ring).

  In FIG. 5A (c), the structure of the spatial modulation ring is the same as that of FIG. 5A (b), but the spatial modulation structure 21 is provided for the JTE 13b outside the two-zone JTE structure shown in FIG. 3B. It has been. This structure is called 2-zone JTE + 3SMR (spatial modulation ring).

  5A (d), a similar spatial modulation structure 23 is formed for the first JTE 13a of the two-zone JTE + 3SMR (spatial modulation ring) of FIG. 5A (c). This structure is called 2-zone JTE + 2 × 3 SMR (spatial modulation ring).

  Basically, from FIG. 5A (a) to FIG. 5A (d), the effect of spatial modulation increases, and the dependence of the reverse breakdown voltage on the impurity concentration tends to decrease.

  The structure shown in FIG. 5B (e) is an example of the structure of the spatial modulation 2-zone JTE. In the structure shown in FIG. 5A (d), no SMR (spatial modulation ring) is provided outside the outer JTE 13b. is there. In this way, it is possible to provide three spatial modulation rings 23 outside the inner JTE 13a and inside the outer JTE 13b, so that no ring is provided on the outermost periphery.

  The structure shown in FIG. 5B (f) is an example of the structure of the spatial modulation 2-zone JTE. Among the structures shown in FIG. 5A (d), there are four spatial modulations outside the inner JTE 13a and inside the outer JTE 13b. A ring 23 is provided, and no SMR (spatial modulation ring) is provided on the outer side (outermost circumference) of the outer JTE 13b.

  In the structures shown in FIGS. 5A to 5D, the potential of the ring-shaped portion on the outermost periphery is floating (floating), so the potential fluctuates during high-speed switching, and the effect of reducing the electric field concentration is not sufficient. there is a possibility. Compared to this, in the structure shown in FIGS. 5B and 5F, by eliminating the outermost ring-shaped portion, it is possible to eliminate the floating portion of the potential, and to reduce the electric field concentration. There is an advantage that it can be obtained sufficiently.

The above structure is an example, and the dimensions of Ls and Lw, the number of spatially modulated island-shaped (annular) p-type impurity regions (three in the figure), and the like are arbitrary.
The widths of the p-type impurity regions 21a, 21b, 21c,... Divided in the layer direction are set to L _Wj (j is a natural number and numbered from the inside of the junction termination region), and the p-type impurity regions 21a, 21b, 21c _,. When the interval is L _{S j} , L _{Wj + 1} / (L _{Wj + 1} + L _{Sj + 1} ) = A × L _Wj / (L _Wj + L _Sj ) (where A is 0.1 to 0.9 It is preferable that the average impurity concentration is spatially modulated so that a relationship of a real number in the range, preferably 0.5 to 0.8 is satisfied.

  FIG. 6 shows 1 zone JTE, 1 zone JTE + 1R (ring), 1 zone JTE + 3R (ring: Ls / Lw = 10/10 μm), 1 zone JTE + 5R (ring: Ls / Lw = 10/10 μm), 2 zone JTE (3 : 2) Dosing dependence of reverse breakdown voltage on p-type impurities in the case of 1 zone JTE + 5SMR (spatial modulation ring: Ls / Lw = 6 / 14-8 / 12-10 / 10-12 / 12 / 8-14 / 6) It is a figure which shows sex. From this figure, it can be seen that as the latter structure is formed, the region where the dose dependency of the p-type impurity of the reverse breakdown voltage is small increases. In particular, in the case of 1 zone JTE + 5 SMR (spatial modulation ring) in spite of being 1 zone JTE, the region where the dose dependence of the p-type impurity of the reverse breakdown voltage is smaller than that in the case of 2 zone JTE becomes wide. It is noted that even when the junction termination is formed with one kind of impurity concentration, the performance is improved as compared with the case where the junction termination is formed with two kinds of impurity concentrations. Compared with 1 zone JTE + 5R (ring), in the case of 1 zone JTE + 5 SMR (spatial modulation ring), the region where the dose dependency of the p-type impurity of the reverse breakdown voltage is small is increased. That is, it can be seen that even with a simple structure (small number of steps), by providing the spatial modulation structure, it is possible to expand a region where the dose dependency of the p-type impurity of the reverse breakdown voltage is small.

  The manufacturing process of the high voltage SiC semiconductor element according to the present embodiment will be described below. FIG. 7 to FIG. 10 are diagrams showing an example of the manufacturing process, taking as an example the case of a spatial modulation structure composed of two-zone JTE + 3 SMR (spatial modulation ring) in FIG. 5A (c).

First, the process of creating the inclined mesa structure will be described. As shown in FIG. 7A, first, an n ⁻ -SiC layer 3 is epitaxially grown on a 4H—SiC n-type substrate 1. Next, the p ⁺ high concentration layer 5 is formed on the n ⁻ -SiC layer 3 by an epitaxial growth method. The p ⁺ high concentration layer 5 may be formed by Al ion implantation. Next, as shown in FIG. 7B, a film P1 made of SiO ₂ having a thickness of 2 μm is deposited on the n ⁻ -SiC layer 3 by, for example, a plasma enhanced (PE) CVD method. Patterning is performed using a lithography technique. As shown in FIG. 7C, for example, by etching the film P1 made of SiO ₂ using the resist M1 as a mask by an isotropic wet etching method using BHF (HF buffer solution), the side surfaces are formed. An inclined SiO ₂ mask M2 having a tapered shape is formed. Next, as shown in FIG. 7 (d), by using a reactive SiO ₂ mask M2 and reactive ion etching (RIE) method using a reactive gas such as CF ₄ , CHF ₃ , Cl ₂ , p ⁺ The high-concentration layer (contact layer) 5 and the n ⁻ -SiC layer 3 are partially removed in the thickness direction, and the inclined SiO ₂ mask M2 is transferred to SiC to form an inclined mesa structure (5a). The remaining inclined SiO ₂ mask M2 is removed by HF (hydrofluoric acid).

Next, the JTE region creation process will be described with reference to FIG. As shown in FIG. 8A, a film P2 made of SiO ₂ is deposited by 2 μm on the structure of FIG. 7D by PECVD, and a resist mask M3 is formed using a photolithography technique. The resist mask M3 is a mask that opens up to a region separated from the mesa structure by a certain distance. As shown in FIG. 8 (b), by isotropic wet etching using a BHF (buffered solution of HF), processing the film P2 made of SiO _2, made of SiO ₂ that took over the shape of the resist mask M3 A mask M4 opened to form a JTE region is formed. Next, as shown in FIG. 8C, a p-type impurity is added to the region 13 by, for example, Al ⁺ ion implantation to form a JTE region. The impurity addition step is not limited to the ion implantation method, and can be performed by a known method such as an impurity diffusion method (the same applies hereinafter).

Next, patterning is performed with a photoresist, and the mask M4 made of SiO ₂ formed outside the JTE region 13 is processed to form openings for forming three p-type conductive regions. A resist mask M5 that protects the inner region is formed. As shown in FIG. 8E, the resist mask M5 is used to form openings for forming a plurality of p-type conductive regions made of SiO ₂ for forming a spatial modulation structure made of a p-type conductive region. A mask M6 is formed. This opening also serves as an opening for forming the first JTE region 13 a and the second JTE region 13 b from the JTE region 13 by opening the outer region of the JTE region 13. As shown in FIG. 8F, the p-type impurity is added to the p-type conductive region and the second JTE region 13b by adding a p-type impurity to the opening region of the mask M6, for example, by ion implantation of Al ^+. can do. Here, the addition amount (doping amount) of the impurity is added so as to be, for example, 2: 1 in the first JTE region 13a and the second JTE region 13b. In FIG. 8G, the mask M6 is removed by HF.

FIG. 9 is a diagram showing a step following FIG. First, as shown in FIG. 9A, a photoresist M7 is applied to the entire surface. Next, as shown in FIG. 9B, a carbon cap M71 is manufactured by performing heat treatment at 750 ° C. for 15 minutes in an Ar atmosphere using RTA (Rapid Thermal Annealing). As shown in FIG. 9C, the p-type impurity is activated by activation annealing at 1700 ° C. for 20 minutes by an induction heating method. Next, the carbon cap M71 is removed by sacrificial oxidation at 1150 ° C. for 3 hours. Next, for example, a passivation film having a thickness of 34 nm is formed by N ₂ O oxynitridation at 1300 ° C. for 5 hours.

Next, as shown in FIG. 10A, a photoresist is applied, and a resist mask M8 is formed by performing patterning for opening the mesa region 5a. Next, the passivation film (SiO ₂ ) in the opening region is removed by BHF using the resist mask M8. As shown in FIG. 10B, Ti / Al / Ni (20 nm / 100 nm / 50 nm) is vapor-deposited, and the anode electrode 7a in contact with the mesa region 5a is formed by lift-off using the resist mask M8. . Next, as shown in FIG. 10 (c), after depositing Ni to the back side of the substrate 1 to a thickness of 100 nm, the back side of the substrate 1 is subjected to heat treatment at 1000 ° C. for 2 minutes in an Ar atmosphere by the RTA method. Can be formed. As shown in FIG. 10 (d), an Al layer 25 is deposited on the entire surface side, and then a photoresist is applied on the entire surface, followed by patterning to leave the Al film 25 on the Ti / Al / Ni electrode 7a. As a result, a photoresist mask M9 is formed. Next, as shown in FIG. 10E, using a photoresist mask M9, a phosphoric acid etchant (H ₃ PO ₄ : CH ₃ COOH: HNO ₃ = 12.5: 1: 0.15) is used. After the Al layer 25 is etched at 60 ° C., the photoresist mask M9 is removed, whereby the anode electrode 7 in which the Al electrode 25a is laminated on the Ti / Al / Ni electrode 7 is formed.

As shown in FIG. 10 (f), a polyimide film M10 is applied to the substrate surface in order to improve insulation, and an opening is provided on the anode electrode 7 by photolithography. Next, by the RTA method, a temperature increase to 140 ° C., a heat retention to 140 ° C. for 30 minutes, a temperature increase to 350 ° C., a heat retention to 350 ° C. for 60 minutes and a cooling step are included in an N ₂ atmosphere Heat treatment is performed. Thereby, the polyimide film M10 is cured, and a PiN diode made of SiC is completed.

  The structure produced by the above process is a SiC-PiN diode having a spatial modulation structure composed of the p-type conductive region of the 2-zone JTE + 3SMR (spatial modulation structure) of FIG. 5A (c).

  When manufacturing the SiC-PiN diode having the spatial modulation structure shown in FIG. 5A (b), the impurity addition process is performed once by opening the JTE region and the spatial modulation region from FIG. 8 (a). Just do it.

  Further, when manufacturing the SiC-PiN diode having the spatial modulation structure of FIG. 5A (d), the spatial modulation is applied to the mask M4 when the first JTE region 13a is formed in the process of FIG. 8B. A process such as forming an opening for forming a region may be performed.

FIG. 11 (color drawing) shows a 1-zone JTE structure (structure of FIG. 11 (a) and FIG. 1 (a)) and a 2-zone JTE + 3SMR (FIG. 11 (b): spatial modulation of FIG. 5A (c)) structure. It is a figure which shows the example of an electric field distribution in. FIG. 12 is a diagram showing the dependency of the position of the surface electric field in FIG. 11A and FIG. 11B (the length from the mesa edge to the JTE edge is 600 μm). As described above, for example, the n ⁻ -SiC layer (voltage block layer) 3 has a doping amount of 1.0 × 10 ¹⁴ cm ⁻² and a thickness of 120 μm. Further, the reverse voltage applied between the electrodes is 11 kV, and the dose amount of JTE13 is 8.5 × 10 ¹² cm ⁻² . In contrast to the one-zone JTE structure of FIG. 11 (a), FIG. 11 (b) shows the electric field distribution in the case of a spatial modulation structure with one-zone JTE + 3SMR (spatial modulation ring) as shown in FIG. 5A (c). ing.

  FIGS. 12A and 12B are diagrams corresponding to FIGS. 11A and 11B and showing the distance dependence of the surface electric field. As shown in FIGS. 11A and 12A, in the one-zone JTE structure, a high surface electric field is observed in the vicinity of the edge of JTE 13, and it can be seen that electric field concentration occurs. In contrast, as shown in FIGS. 11 (b) and 12 (b), in the spatial modulation structure using 1 zone JTE structure + 3SMR (spatial modulation ring), the surface electric field in the vicinity of the edge of JTE 13 (distance 600 μm). It can be seen that the concentration is suppressed and the surface electric field in the range of distance of 500 to 600 μm is dispersed in a plurality of peaks. The maximum surface electric field is also reduced from 2.4 MV / cm to 1.8 MV / cm. Thus, it is clear that the concentration of the surface electric field at the JTE edge is suppressed by providing the spatial modulation structure.

  As described above, according to the semiconductor technology according to the present embodiment, the junction termination including the JTE region and the spatial modulation structure can be formed by a simple process. Further, the high breakdown voltage SiC semiconductor device is designed to have a high breakdown voltage, and the reverse breakdown voltage variation with respect to the impurity concentration (including the activation rate) and the fixed charge variation at the insulating film / SiC interface in the impurity addition process when forming the JTE region Can be greatly suppressed. Therefore, there is a great advantage that the margin in the manufacturing process can be greatly improved.

Next, a high voltage SiC semiconductor device according to a second embodiment of the present invention will be described. FIG. 13 is a diagram illustrating a process of forming a (2 ⁿ −1) spatial modulation structure by ⁿ ion implantations. An example in the case of n = 1 has a structure as shown in FIG. 5A (b).

  Here, an example in the case of n = 2 is shown (an example of 3 zone JTE + 3 × 5 SMR (spatial modulation structure)). In the structure shown in FIG. 13 (a), a mesa structure (not shown) as shown in FIG. 7 (d) is provided on the left side of FIG. 13 (a), and from there, on the right side of FIG. 13 (a). A junction termination structure is formed. At this time, first, a mask M11 is formed which covers the region where the third JTE and the third spatial modulation structure are to be formed, and which covers the region where the p-type conductive region is to be formed in the second spatial modulation region. . Using this mask M11, p-type impurities are added. Next, as shown in FIG. 13B, a mask M12 is formed to open the first to third p-type conductive region formation regions for forming the first to third spatial modulation structures. To do. The interval between the p-type impurity regions of the first to third spatial modulation structures and the width of the p-type impurity region are, for example, 6 / 14-8 / 12-10 / 10-12 / 12 / 8-14 / 6 μm. Next, a second impurity addition is performed. The ratio of the first impurity addition amount (dose amount) to the second impurity addition amount (dose amount) for the second time is 2: 1.

  FIG. 13 (c) is a diagram showing the position dependency of the effective dose amount in the first to third JTE structures and the spatial modulation structure formed as described above. As shown in FIG. 13C, the dose amount in the junction termination structure as a total is 3 (JTE1): 2 (JTE2): 1 (JTE3) in order from the mesa structure side, and the relationship between JTE1 and JTE2 In the first spatial modulation structure formed in JTE1 of the junction, the second spatial modulation structure formed in JTE2 of the junction between JTE2 and JTE3, and the third spatial modulation structure formed in JTE3 , The dose is designed to be tilted and connected to the next JTE. This can suppress surface and bulk electric field concentration due to a large change in dose at the junction termination. Even if there is a spatial variation in the impurity addition amount (in consideration of the activation rate), the total junction termination structure has little influence on the shape with a tilted dose, so the impurity addition amount Can be reduced, the impurity addition process can be given a margin, and fluctuations in the reverse breakdown voltage can be suppressed.

  FIG. 14 is a diagram showing the dose dependency of the reverse breakdown voltage on the innermost JTE when the total JTE width is 600 μm in the 4H-SiCPIN diode including the structure of FIG. In FIG. 14, 1 zone JTE, 1 zone JTE + 1R, 1 zone JTE + 3R, 1 zone JTE + 5R, 2 zone JTE (dose amount = 3: 2), 1 zone JTE + 5 SMR (spatial modulation structure), 3 zone JTE + 3 The dependence on x5 SMR (spatial modulation: this structure is the structure shown in FIG. 13B) is shown. The 5SMR is 6 / 14-8 / 12/10 / 10-12 / 12 / 8-14 / 6 μm as described above. In this case, the effective dose ratio is 0.7, 0.6, 0.5, 0.4, and 0.3. When the spatial modulation structure is not provided, the relationship between the space between the p-type conductive regions and the width of the p-type conductive region is 10/10 μm.

  As shown in FIG. 14, in the case of 3 zone JTE + 3 × 5 SMR (spatial modulation structure) according to the present embodiment, it is the same as the case of 2 zone JTE in that two impurity introduction steps are required. In addition, fluctuations in the reverse breakdown voltage are suppressed over a wide dose range, which shows that this structure is extremely effective.

  Thus, even when the total width of the JTE is the same as 600 μm, it can be seen that the three-zone JTE + 5 SMR (spatial modulation structure) suppresses the variation in the reverse breakdown voltage due to the dose.

Next, a high voltage SiC semiconductor element according to a third embodiment of the present invention will be described. FIG. 15 is a structural cross-sectional view showing an example of a high voltage SiC semiconductor device according to the present embodiment.
As shown in FIG. 15, the SiC semiconductor device according to the present embodiment includes a p-type conductive region 21a, a second p-type conductive region 21b, and a third p-type conductive region 21c. The impurity concentration in the type conduction region is constant and the interval Ls is also constant, and the ring of the first p-type conduction region 21a, the second p-type conduction region 21b, and the third p-type conduction region 21c The width Lw is made smaller in the layer direction away from the JTE 13. Even in such a structure, since the p-type impurity concentration tends to decrease in the layer direction away from the JTE 13, a dose gradient can be effectively formed.
According to FIG. 15, since the slope can be formed by one ion implantation, there is an advantage that the process is simplified.

  Next, application examples of the high voltage SiC semiconductor element according to each embodiment of the present invention will be described. In each of the above embodiments, a pn junction type diode has been described as an example. However, the present invention can be applied to other semiconductor elements.

First, the semiconductor element which consists of SiC power MOSFET which is a 1st application example is demonstrated. A semiconductor element made of a SiC power MOSFET is connected to a large number (for example, 1000 × 1000 elements) of SiC-MOSFETs formed in a region of about 10 μm × 10 μm. In such a SiC power-MOSFET, by providing the outermost MOSFET with the spatial modulation structure as described above, the dose dependency of the reverse breakdown voltage can be suppressed, and element breakdown or the like hardly occurs. A structural cross-sectional view of such a SiC-MOSFET is shown in FIG. The SiC-MOSFET shown in FIG. 16 includes a 4H—SiC n-type substrate 1 and an n ⁻ -SiC layer (thickness 30 μm, n-type impurity concentration 2.0 ×) formed on one side (the front side in the figure). 10 ¹⁵ cm ⁻³ ) 3, a source and gate structure formed on the upper surface side thereof, and a drain electrode 11 formed on the other surface (lower surface in the drawing) of the n-type substrate 1. Source and gate ^structure, n - and p-type conductivity region 61 formed in a region near the surface of the SiC layer ^3, n - and -SiC layer insulating film 75 made of SiO ₂ formed on the surface of 3, insulation A gate electrode 77 formed on the film 75, and a source electrode 73 formed in contact with the high-concentration n ⁺ p ⁺ junction structures 63 and 65 formed in the p-type conductive region 61. Yes.

  The gate electrode 77 functions as a current control structure that controls the current between the source and the drain. Here, a JTE 67 made of a p-type conductive layer is formed outside the p-type conductive region 61 as a connection termination structure, and an SMR (spatial modulation structure) as shown in FIG. 5A or FIG. 71 (in this case, three p-type conductive layers 71a, 71b, 71c, for example, Ls1 / Lw1-Ls2 / Lw2-Ls3 / Lw3 is 5 / 10-10 / 10-15 / 10 Spatial modulation structure) is formed. By providing such an SMR (Spatial Modulation Structure) outside the outer edge transistor, the dose dependence of the reverse breakdown voltage of the outer edge transistor is suppressed, so that the stable reverse is less likely to depend on variations in impurity concentration. The characteristics of a power transistor having a directional breakdown voltage can be obtained.

Next, a second application example will be described. FIG. 17 is a cross-sectional view showing an example of the configuration of a Schottky diode made of SiC. As shown in FIG. 17, the Schottky diode according to this application example has a large-area structure, and is a 4H—SiC n-type substrate 1 and n ⁻ −SiC formed on one side (the front side in the drawing). Layer (for example, thickness 30 μm, n-type impurity concentration 2.0 × 10 ¹⁵ cm ⁻³ ) 3, Schottky electrode (Ti / Ni) 81 formed on the upper surface side, and other n-type substrate 1 And an ohmic electrode 11 formed on one surface (the lower surface in the figure). A p-type conductive region is formed in the n ⁻ SiC layer 3 on both sides of the Schottky electrode (Ti / Ni) 81 to form a JTE region 83. Here, on the outside of the JTE region 83, for example, there are three p-type conductive layers SMR (spatial modulation structure) 85 (in this case, 85a, 85b, 85c shown in either FIG. 5A or FIG. 5B, For example, Ls1 / Lw1-Ls2 / Lw2-Ls3 / Lw3 is 5 / 10-10 / 10-15 / 10 μm). By providing such an SMR (spatial modulation structure), the dose dependency of the reverse breakdown voltage of the Schottky diode can be suppressed, and stable diode characteristics can be obtained. In addition, it can be applied to avalanche photodiodes and the like. Of course, such a JTE + spatial modulation structure may be provided in a SiC JFET, IGBT, bipolar transistor, or the like.

  In the above-described embodiment, the configuration and the like illustrated in the accompanying drawings are not limited to these, and can be appropriately changed within a range in which the effect of the present invention is exhibited. In addition, various modifications can be made without departing from the scope of the object of the present invention. For example, in the above embodiment, a mesa structure is taken as an example, but a planar semiconductor element may be used.

  In the above embodiment, an example is shown in which the present invention is applied to a SiC semiconductor element. However, the suppression of electric field concentration on the surface by providing a spatial modulation structure can also be applied to other high-voltage semiconductor elements. Is possible.

  The present invention is applicable to a high breakdown voltage SiC semiconductor element. It can also be used for semiconductor elements such as GaN.

DESCRIPTION OF SYMBOLS 1 ... 4H-SiC n-type substrate, 3 ... n ^- SiC layer (pressure | voltage resistant maintenance layer), 5 ... p ^<+>- SiC layer, 7 ... Anode electrode, 11 ... Cathode electrode, 12 ... Conventional JTE (junction termination) area | region , 13 ... 1st JTE region, 13a ... 2nd JTE region, 15 ... Polyimide, 21 ... SMR (spatial modulation structure), 21a, 21b, 21c ... p-type impurity region, 73 ... Source electrode, 75 ... Insulating film , 77... Gate electrode, 81... Schottky electrode.

Claims (5)

A SiC semiconductor device comprising a junction termination structure comprising a first conductivity type withstand voltage maintaining layer and a second conductivity type region different from the first conductivity type having a finite length at an outer peripheral end of the device,
In a part of the junction termination structure, with respect to the layer direction that is a first direction, the inner end of the junction termination region and from the outer peripheral end of the element toward the outer end of the junction termination region, the first An SiC semiconductor device having a junction termination structure formed so that the impurity concentration of one conductivity type region is spatially modulated and the impurity concentration tends to gradually decrease. In the junction termination structure,
A region having the same impurity concentration distribution of the second conductivity type in the depth direction, which is the second direction intersecting the first direction, is divided into a plurality in the layer direction, and the division 2. The SiC semiconductor device according to claim 1, wherein the width of the formed region is formed with a tendency to narrow toward the outside of the junction termination region. In the junction termination structure,
A region having the same impurity concentration distribution of the second conductivity type in the depth direction, which is the second direction intersecting the first direction, is divided into a plurality in the layer direction, and the division 2. The SiC semiconductor device according to claim 1, wherein an interval between the formed regions has a tendency to expand toward an outside of the junction termination region. In the above junction termination structure,
When the width of the region divided in the layer direction is L _Wj (j is a natural number and numbered from the inside of the junction termination region), and the region interval is L _Sj , L _{Wj + 1} / (L _{Wj + 1} + L _{Sj + 1} ) = A × L _Wj / (L _Wj + L _Sj ) (where A is a real number in the range of 0.1 to 0.9, preferably 0.5 to 0.8). 4. The SiC semiconductor element according to claim 2, wherein the SiC semiconductor element is spatially modulated. It is a manufacturing method of the SiC semiconductor device according to any one of claims 1 to 4,
A method of manufacturing a SiC semiconductor device, comprising: adding the second conductivity type impurities in a lump.

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