JP2012191038A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that allows reduction in charges at an interface between one insulating film and the other insulating film formed on the one insulating film in a simple configuration while suppressing an increase in manufacturing cost.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: (a) preparing a substrate composed of a SiC semiconductor; (b) forming, on a surface of the substrate, a recess structure and a guard ring layer under the recess structure so as to surround an element region of the substrate; (c) forming a first insulating film so as to cover the guard ring layer; (d) forming a second insulating film composed of a material different from the first insulating film so as to cover the first insulating film; and (e) irradiating the second insulating film with ions having a charge opposite to that of ions accumulated on the first insulating film before the step (d), in the step (d), or after the step (d).

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a manufacturing method for achieving both improvement in breakdown voltage characteristics of a power semiconductor device and reduction in manufacturing cost of an element.

  In order to save energy in power electronics devices such as inverters, it is necessary to reduce loss of switching elements (IGBT: Insulated Gate Bipolar Transistor, MOSFET: Metal Oxide Semiconductor-Field Effect Transistor, etc.).

  The loss is determined by the so-called ON resistance of the element. Developments using new semiconductor materials such as SiC are underway to reduce the ON resistance.

  On the other hand, improvement of the breakdown voltage characteristics of the element is necessary for high power control.

  An electric field concentration tends to occur at the end of the electrode of the switching element, and an impurity layer (hereinafter referred to as a GR (Guard Ring) layer) is included in the semiconductor layer at a position in contact with the end of the electrode in order to reduce the electric field concentration. Is formed.

  Further, in order to reduce the electric field concentration generated at the end portion of the GR layer in the direction toward the inside of the semiconductor layer, the surface of the semiconductor layer outside the GR layer may be in contact with or separated from the GR layer. An impurity layer (hereinafter referred to as a JTE (Junction Termination Extension) layer) is formed.

  Patent Document 1 discloses a method for manufacturing a silicon carbide Schottky barrier diode having uniform characteristics in order to reduce the defect level on the SiC surface and ensure a breakdown voltage. In Patent Document 1, a groove is formed in the GR layer and the JTE layer to reduce the leakage current and ensure the withstand voltage.

International Publication No. 2009/116444 JP-A-8-255919 JP 9-45631 A

  In the prior art, the impurity concentration of the JTE layer is set smaller than that of the GR layer. By making the impurity concentration of the JTE layer smaller than that of the GR layer, the electric field strength at the outer periphery of the element can be reduced and the breakdown voltage is improved. In order to realize the above GR / JTE structure, two types of injection conditions are required. A wide band gap semiconductor such as SiC is used to realize a high breakdown voltage device.

  On the other hand, in order to position the substrate in the process, it is necessary to form an alignment mark, and the alignment mark is often arranged on the outer peripheral side of the substrate. The alignment mark is necessary for positioning the substrate in each process. In particular, in the case of a SiC material, the alignment mark needs to have a structure that can withstand high-temperature annealing, and is therefore a digging structure (groove).

  Here, when the GR / JTE structure is a digging structure (groove), it is possible to perform alignment mark formation and GR / JTE structure formation with the same mask.

  Note that the termination structure can be formed with a single mask by making the termination structure only the structure of the GR layer and making the process of forming the alignment mark and the process of forming the GR layer in common.

  A semiconductor device manufactured by the above method will be described. In this semiconductor device, only the GR layer is formed in its termination structure, and impurities are implanted into the dug structure (recess structure) at one concentration. The recess structure is produced by etching during the alignment mark forming process.

  Here, in the case of a SiC device, the implanted impurities are activated with little diffusion. Therefore, a high concentration impurity layer is formed in the very vicinity of the recess structure.

  The impurity concentration of the GR layer formed using one mask is formed at a relatively high concentration in order to ensure the breakdown voltage characteristics of the element. For this reason, when a high voltage is applied to the cathode, the depletion layer of the impurity layer is little stretched and a high electric field is likely to be generated.

  In particular, a strong electric field is generated at the corner of the bottom surface of the recess, and when the dielectric breakdown strength of the polyimide film is exceeded, dielectric breakdown is caused. In the recess structure, it has been hardly known that dielectric breakdown occurs due to electric field concentration.

  On the other hand, when the termination structure is covered with an insulating film such as polyimide, charges may accumulate on the surface of the insulating film. This electric charge fluctuates the electric field strength in the recess portion, which causes the dielectric breakdown of polyimide.

  In particular, when the device is incorporated in a module for power conversion, it is necessary to cover the element with another insulating film. In this process, charges accumulate on the surface of the insulating film such as polyimide, and the withstand voltage is reduced. It was a cause of lowering.

  In order to prevent dielectric breakdown as described above, it is necessary to suppress electric field concentration, and charge at the interface between the insulating film and another insulating film (resin film, etc.) formed above the insulating film is reduced. There is a need to. By reducing the charge, not only the breakdown voltage is reduced due to charge accumulation, but also the breakdown can be suppressed even when the GR layer is formed in a recess structure.

  There is Patent Literature 2 as a prior example for preventing a decrease in dielectric strength voltage. In Patent Document 2, the charge generated in the interface between the semiconductor substrate and the insulating film or in the insulating film is changed to a predetermined amount. Specifically, there is a problem that charged particles are allowed to pass through in order to set a predetermined amount of electric charge existing at the interface between the semiconductor layer and the insulating film, and that a vacuum apparatus is required for the implementation. .

  Moreover, there is Patent Document 3 as a prior example in which charging is not performed by ion irradiation. In Patent Document 3, ion implantation is performed on a semiconductor substrate in order to prevent variations in the charge amount of the semiconductor substrate, and an ion implantation apparatus using an extraction electrode for accelerating ions must be used. There was also a problem of not becoming.

  The present invention has been made in order to solve the above-described problems, and suppresses an increase in manufacturing cost, and with a simple configuration, charges at the interface between the insulating film and the insulating film formed on the upper portion thereof. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of reducing the above.

  A method for manufacturing a semiconductor device according to the present invention includes: (a) a step of preparing a substrate using a SiC semiconductor; and (b) a recess structure and a surface of the surface layer portion of the substrate so as to surround an element region of the substrate. Forming a guard ring layer under the recess structure; (c) forming a first insulating film covering the guard ring layer; and (d) covering the first insulating film, A step of forming a second insulating film made of a material different from that of the first insulating film, and (e) ions having a charge opposite to the charge accumulated on the first insulating film, before the step (d), or Irradiating in the step (d) or after the step (d).

  According to the method for manufacturing a semiconductor device of the present invention, (a) a step of preparing a substrate using an SiC semiconductor, and (b) a recess structure so as to surround an element region of the substrate in a surface layer portion of the substrate. And a step of forming a guard ring layer under the recess structure, (c) a step of covering the guard ring layer and forming a first insulating film, and (d) covering the first insulating film, A step of forming a second insulating film made of a material different from that of the first insulating film, and (e) ions having a charge opposite to the charge accumulated on the first insulating film, before the step (d), or The step of irradiating in the step (d) or after the step (d) reduces charges accumulated at the interface between the first insulating film and the second insulating film, and is generated in the guard ring layer. The electric field strength to be reduced can be reduced. Therefore, the withstand voltage of the semiconductor device can be improved.

FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; FIG. 6 is a diagram illustrating a manufacturing process of the manufacturing method of the semiconductor device according to the first embodiment; It is sectional drawing of the Schottky diode concerning the premise technique of this invention.

<A. Embodiment 1>
FIG. 14 shows a termination structure in which a GR layer is formed in a semiconductor device as a prerequisite technology of the present invention. The alignment marks formed on the outer periphery of the substrate are not shown in FIG.

  As shown in FIG. 14, n-type epitaxial layer 2 is formed on the surface layer portion of n + substrate 1, and metal layer 6 is disposed on the back surface of n + substrate 1. A recess structure 100 is formed on the n-type epitaxial layer 2, and a GR layer 3 is formed in the recess structure 100. A metal layer 5 is formed on the n-type epitaxial layer 2 so as to cover a part of the recess structure 100, and a surface electrode 7 is further formed on the metal layer 5. A first insulating film 8 is formed so as to cover a part of the surface electrode 7 and the n-type epitaxial layer 2.

  As the termination structure, only the GR layer 3 is formed, and impurities are implanted into the dug structure (of the recess structure 100) at one concentration. The recess structure 100 is manufactured simultaneously with the alignment mark by etching during an alignment mark forming process (not shown).

  When the termination structure is covered with the first insulating film 8 such as polyimide, charges are accumulated outside the termination structure. Therefore, the electric field strength in the recess portion fluctuated, and polyimide caused a dielectric breakdown.

  In particular, when the device is incorporated in a module for power conversion, it is necessary to cover the element with another insulating film. In that process, charges accumulate on the surface of the first insulating film 8 such as polyimide, This was a cause of lowering the withstand voltage.

  In order to prevent the dielectric breakdown as described above, it is necessary to suppress the electric field concentration, and the first insulating film 8 and another second insulating film (resin film or the like) formed on the first insulating film 8 are formed. It is necessary to reduce the charge at the interface with the

  The following embodiments show a method for manufacturing a semiconductor device that solves the above-described problems.

<A-1. Manufacturing method>
1 to 13 show a manufacturing process of a semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 1, an n + substrate 1 made of a silicon surface 4H—SiC is prepared. Next, a low-concentration n-type epitaxial layer 2 having an impurity concentration of about 5 × 10 ¹⁵ cm ⁻³ is formed on the surface of the n + substrate 1.

  Next, the surface of the n-type epitaxial layer 2 is sacrificial oxidized to form a thermal oxide film 10 (protective film) on the opposite surface of the n + substrate 1 (FIG. 2). The thermal oxide film 10 formed on this surface functions as a process protective film. Further, as will be described later, by removing the thermal oxide film 10 immediately before the metal layer 5 is formed, the surface of the n-type epitaxial layer 2 after the removal is chemically stable with good reproducibility, and a good Schottky junction is formed. Enable.

Next, after applying a resist to the SiC substrate, exposing, developing, and patterning, a recess structure 100 (digging structure) is formed by RIE (Reactive Ion Etching) in the terminal portion and the alignment mark forming portion (FIG. 3). By performing RIE dry etching using SF ₆ gas, a tapered recess structure 100 can be formed. By forming the recess structure 100, the withstand voltage of the semiconductor device is improved.

  Next, a termination structure is formed in the n-type epitaxial layer 2. Since the electric field concentration is likely to occur at the end portion of the Schottky electrode, the termination structure is formed so as to relax the electric field concentration and stably secure a breakdown voltage exceeding kV. In the SiC substrate, the GR layer 3 is formed so as to surround the element region formed in the surface layer portion of the substrate. For example, in this termination structure, Al ions are implanted to form the p-type GR layer 3 (FIG. 4). When implanting Al ions, the same resist mask as in FIG. 3 is used. B ions which are p-type impurities may be implanted instead of Al ions.

  Subsequently, the resist mask is removed, and annealing (heat treatment) is performed to activate Al ions. Annealing is performed by flowing an inert gas and heating in an annealing furnace.

  Next, a metal layer 6 that is a first metal layer is formed by sputtering. The material of the first metal layer may be Ni or the like, and is formed on the back side of the substrate on which the recess is not formed. By performing annealing after forming the film and silicidation, the contact resistance between the metal layer 6 and the SiC substrate can be reduced. Next, a Ti film as a second metal layer is vapor-deposited on the substrate on which the recess is formed, the metal layer 5 is provided, a resist is applied, exposed and developed to form a resist mask, and then the metal layer 5 is covered. Wet etching with acid etc. and patterning. A heat treatment is performed to form a Schottky junction with desired characteristics (FIG. 5). By using Ti as the Schottky bonding material, desired forward characteristics can be obtained, and a processing process such as wet etching described later is facilitated. The material of the metal layer 5 may be Mo other than Ti.

  Next, the process until the surface electrode 7 is formed on the metal layer 5 will be described. For example, a metal layer such as Al is formed by sputtering, a resist is applied, exposed and developed, wet etching such as hot phosphoric acid is performed from the resist opening to remove the resist mask (FIG. 6), and the surface electrode 7 is formed. Form.

  Next, the process until the first insulating film 8 and the back electrode 9 are formed will be described.

  After forming the surface electrode 7, a first insulating film 8 (first insulating film) such as polyimide is applied on the n-type epitaxial layer 2 and the surface electrode 7. After the resist is applied, exposed and developed, etching is performed, followed by baking (FIG. 7). The first insulating film 8 is formed so as to cover the GR layer 3.

  Next, the back electrode 9 is formed on the back surface of the n + substrate 1 (FIG. 8).

  Next, a resin film 11 (for example, a silicon resin), which is a second insulating film, is applied on the first insulating film 8 with a predetermined thickness. However, here, it is assumed that the resin film 11 having a thickness of about several μm (for example, 2 to 5 μm) is applied once during the process of forming the resin film 11. FIG. 9 shows a state in which positive charges are charged at the interface between the first insulating film 8 and the resin film 11 as the second insulating film due to frictional charging when the resin film 11 is applied.

  As the material of the resin film 11, a silicon-based polymer material (for example, silicon resin) is used. As the resin film 11, a film made of a material different from that of the first insulating film 8 can be used. The first insulating film 8 is an organic polymer material such as polyimide, whereas the resin film 11 is a silicon polymer material, and the resin film 11 is easily positively charged from the charging column.

  When positive charges are charged at the interface between the first insulating film 8 and the resin film 11, negative ions 12, which are reverse charges, can be irradiated in the atmosphere in order to remove the positive charges. Here, the charge removal includes not only that the electric charges are completely removed but also a case where a part of the electric charges is removed.

  The negative ions 12 are irradiated onto the resin film 11 using an ion generator. Irradiation conditions of the ion generator are set so that the positive charge disappears at the interface between the first insulating film 8 and the resin film 11 (FIG. 10). The ion generator can easily control the amount of charge, and can suppress an increase in manufacturing cost.

  When the charge accumulated at the interface between the first insulating film 8 and the resin film 11 is a negative charge, positive ions that are opposite charges are irradiated. In the first embodiment, a case where negative ions 12 are irradiated will be described.

  The ion generator for negative ions 12 is a device that can generate only negative ions 12 by applying a negative high voltage to the needle electrode and the ground surface in the atmosphere to generate corona discharge. Note that the irradiation of the negative ions 12 is completed in about several minutes (FIG. 11).

  The resin film 11 has a low viscosity immediately after being applied by a dispenser or the like, and the negative ions 12 on the resin film 11 and the positive ions at the interface between the first insulating film 8 and the resin film 11 are the surface of the first insulating film 8. And creeping due to air adhering to the surface of the resin film 11 and moisture in the air.

  A leak current flows through the resin film 11 through voids (bubbles) present in the resin film 11. The amount of positive charges (ions) at the interface between the first insulating film 8 and the resin film 11 and the minus charges (ions) on the upper surface of the resin film 11 is reduced and the charge is eliminated. FIG. 12 shows a state where static electricity is generated due to leakage current.

  In the present invention, since the static electricity is removed by using the leak current, it is not necessary for the irradiated ions to pass through the resin film 11, and the energy of the irradiated ions can be kept small. Also, the device configuration can be made simpler.

  Although it is necessary to set the irradiation amount of the negative ions 12 by measuring the charge of the resin film 11, it is difficult to directly measure the charge amount on the resin film 11. Therefore, the surface potential meter is moved closer to the top of the substrate, and the surface potential on the resin film 11 is measured in a non-contact manner.

  The surface electrometer can measure the potential in a non-contact manner, but the measurement range increases when the distance from the object to be measured is increased. Although there are differences depending on the surface potential meter, the entire surface of the 4-inch wafer can be measured at a time by separating the distance from the resin film 11 by about 20 mm.

  One of the surface electrometer measurement methods uses a piezo element. The piezoelectric element to which the electrode is attached is attached to a tuning fork (U-shaped metal plate), an AC voltage is applied to the piezoelectric element and vibrated, and the first insulating film 8 is charged on the surface of the measurement electrode attached to the piezoelectric element. The induced displacement current and displacement voltage are induced, and the displacement voltage is measured to measure the surface potential of the resin film 11.

  Immediately after the negative ion irradiation, negative ions on the resin film 11 cause a negative potential in the surface potential measurement. However, positive ions at the interface between the first insulating film 8 and the resin film 11 and negative ions on the upper surface of the resin film 11 are used. However, as the charge removal proceeds due to leakage, the potential gradually increases. However, the potential rise has a time delay with respect to the negative ion irradiation, and the potential is measured at the time when the time change is lost. When this potential becomes zero, the negative ion irradiation is terminated. If the surface potential of the resin film 11 is negative, the upper surface of the resin film 11 is negatively charged. However, if the potential becomes zero by the surface potential meter, the charge removal in the resin film 11 is completed. End irradiation.

  Next, FIG. 13 shows a state where the potential on the resin film 11 has become zero.

  When the formation process that has been interrupted is resumed after the neutralization is completed, even if the resin film 11 is applied so as to be thick, no new charge is generated. By baking the resin film 11 after reaching a predetermined thickness, the viscosity of the resin film 11 is increased, micro defects are reduced, and insulation can be secured.

  In this embodiment, the negative ions 12 are irradiated in the middle of the resin film 11 application step. However, the negative ions 12 may be irradiated in advance before the resin film 11 application step. The negative ion 12 may be irradiated after the resin film 11 coating step.

  In the above description, the negative ion 12 is irradiated and the ion irradiation is terminated when the potential becomes zero. However, when the negative ion 12 is excessively irradiated and the potential becomes negative, the metal layer 5 is irradiated. An electric field is generated due to negative charges between the first insulating film 8 and the first insulating film 8. However, if this electric field is a potential difference that does not exceed the dielectric breakdown strength of the first insulating film 8, problems such as discharge do not occur.

<A-2. Effect>
According to the first embodiment of the present invention, in the method of manufacturing a semiconductor device, (a) a step of preparing an n + substrate 1 and an n-type epitaxial layer 2 using a SiC semiconductor, and (b) a surface layer of the n + substrate 1. In the partial n-type epitaxial layer 2, a step of forming a recess structure and a GR layer 3 below the recess structure so as to surround the element region, and (c) forming a first insulating film 8 covering the GR layer 3. A step, (d) forming a resin film 11 as a second insulating film made of a material different from the first insulating film so as to cover the first insulating film 8, and (e) accumulating on the first insulating film 8. The first insulating film 8 and the resin film 11 by irradiating ions having a charge opposite to the charge to be performed before the step (d), during the step (d), or after the step (d). The charge accumulated at the interface with the substrate can be reduced and generated in the GR layer 3 It is possible to reduce the field strength. Therefore, the withstand voltage of the semiconductor device can be improved.

  Further, since the first insulating film 8 and the resin film 11 are not charged, the electric field strength in the insulating film can be reduced when a high voltage is applied to the Schottky diode. Therefore, the breakdown voltage of the Schottky electrode and the cathode electrode is improved.

  In addition, according to the first embodiment of the present invention, in the method for manufacturing a semiconductor device, the step (b) is a step of forming the GR layer 3 in the recess structure 100 formed on the n-type epitaxial layer 2. Thus, the withstand voltage of the semiconductor device can be further improved.

  Further, according to the first embodiment of the present invention, in the method for manufacturing a semiconductor device, the step (d) includes the step of temporarily interrupting the formation of the resin film 11 with a predetermined thickness, thereby forming the resin film 11. The step (e) is a step of irradiating ions having a charge opposite to the charge accumulated on the first insulating film 8 during the interruption of the step (d). The leaked charge leaks and is neutralized. Then, after the charge removal is completed, the interrupted process is resumed, and when the resin film 11 is applied to increase the thickness, no new charge is generated.

  In the embodiment of the present invention, the material, material, conditions for implementation, etc. of each component are also described, but these are examples and are not limited to those described.

  1 n + substrate, 2 n-type epitaxial layer, 3 GR layer, 5, 6 metal layer, 7 surface electrode, 8 first insulating film, 9 back electrode, 10 thermal oxide film, 11 resin film, 12 negative ion, 100 recess structure .

Claims (3)

(A) preparing a substrate using a SiC semiconductor;
(B) forming a recess structure and a guard ring layer under the recess structure so as to surround an element region of the substrate in a surface layer portion of the substrate;
(C) forming a first insulating film so as to cover the guard ring layer;
(D) forming a second insulating film made of a material different from the first insulating film so as to cover the first insulating film;
(E) irradiating ions having a charge opposite to the charge accumulated on the first insulating film before the step (d), during the step (d), or after the step (d); Comprising
A method for manufacturing a semiconductor device. The first insulating film in the step (c) is an insulating film made of an organic polymer material, and the second insulating film in the step (d) is an insulating film made of a silicon-based polymer material. Is a membrane,
A method for manufacturing a semiconductor device according to claim 1. The step (d) includes a step of temporarily interrupting the formation of the second insulating film with a predetermined thickness,
The step (e) is a step of irradiating ions having a charge opposite to the charge accumulated on the first insulating film during the interruption of the step (d).
A method for manufacturing a semiconductor device according to claim 1.

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