JP2012187776A - Information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To turn off a power supply using a hardware timer, even when powered off from a sleep state at a high speed start-up setting, by solving the problem that an electric power is increased at a sleep mode, if the hardware timer operated even in failure of software uses a power supply for supplying the electrical power at the sleep mode.SOLUTION: An information processing apparatus has a first timer circuit which is powered on at the sleep mode, and a second timer circuit which is powered off at the sleep mode.

Description

  The present invention relates to an information processing apparatus.

  In recent years, as functions of MFPs (multifunction peripheral devices) have increased, programs have become more complex. Therefore, when the power is turned on, a large amount of program data is read from a recording medium such as a hard disk (HDD), written to the internal memory, and various initialization settings are performed, which takes time to start. In order to solve these problems, a fast startup method has been proposed that keeps the internal memory state after startup even when the power switch is OFF, thereby speeding up startup when the power switch is ON. Yes. For example, normal startup is performed when the power switch is turned on for the first time, and the power supply of the circuit including the internal memory is held when the power switch is turned off, so that the startup at the next startup can be accelerated.

  On the other hand, shutdown processing is performed when the power switch is turned off in order to prevent a failure of the HDD due to power interruption during writing processing to the HDD or to cancel a job being processed by the MFP. In this case, after the shutdown process is performed, a process for shutting off the power is performed. In addition, a configuration has been proposed in which the power is turned off by hardware in preparation for a case where the power cannot be turned off because the shutdown process is not normally performed due to a software abnormality. For example, in the invention described in Patent Document 1, a hardware timer is activated when the power is turned off, and the power is turned off after a predetermined time has elapsed. (Patent Document 1).

JP-A-6-282361

  When entering the sleep state, which saves power in the fast startup setting state, when the power switch is turned off, it is necessary to start up the CPU once and set the power OFF in the fast startup. At this time, if the timer circuit is configured with a power supply that is not used during sleep, it is necessary to supply power to the timer circuit and charge it when returning from sleep, and the power switch cannot be turned off to set the trigger for starting the timer. . Further, if the timer circuit is configured with a power source used during sleep, power consumption is consumed. In particular, when a long-time timer is configured with a low voltage, there is a problem that the power during sleep increases.

Therefore, in the present invention, in the information processing apparatus having a plurality of timer circuits that start when the power switch is turned off and shut off the power circuit after a predetermined time has passed,
The first timer circuit is constituted by an information processing apparatus characterized in that the power is cut off during the power saving mode, and the second timer circuit is supplied with power during the power saving mode.

  Further, the second timer circuit is enabled when the power switch is turned off in the power saving mode.

  Further, the information processing apparatus has a setting of a fast start mode, and the second timer circuit is enabled when the power switch is turned off when the power saving mode and the fast start mode are set. .

  Further, the first timer circuit has a longer time setting than the second timer circuit.

  Further, the first timer circuit is supplied with a higher voltage than the second timer circuit.

  According to the present invention, the power can be shut off by the hardware timer even when the power is turned off from the sleep state of the fast startup setting without greatly increasing the power during sleep.

It is a block diagram which shows a system configuration. 2 is a block diagram showing a configuration of an MFP 102. FIG. 3 is a block diagram showing a configuration of a control unit 201. FIG. It is a figure which shows the structure of an electric power supply state and electric power supply control. It is a flowchart which shows the flow of the process at the time of power-ON. It is a flowchart which shows the flow of a process at the time of a power supply OFF. It is a time chart which shows power supply control.

  FIG. 1 is a block diagram showing the system configuration of this embodiment.

  101 is a PC. Reference numeral 102 denotes an MFP (multifunction peripheral device). A network 103 connects the PC 101 and the MFP 102 and transmits data such as image data. Note that the connection between the PC 101 and the MFP 102 may be a local connection.

  FIG. 2 is a block diagram showing the configuration of the MFP 102.

  A control unit 201 controls each component 202-205 of the MFP 102. Details of the control unit 201 will be described later with reference to FIG. An operation unit 202 includes a display unit and an input unit. The display unit provides an operation screen of the MFP 102 to the user, and accepts various operations on the MFP 102 from the user through the input unit. The operation unit 202 also includes a switch for shifting between a power saving state or a sleep state and a standby state. A reading unit 203 converts the original into read image data and inputs the image data to the control unit 201. Reference numeral 204 denotes a printing unit that executes image formation on output paper based on image data that has been subjected to image processing by the control unit 201. Reference numeral 206 denotes a power supply unit that supplies power to the components 201 to 204 of the MFP 102.

  FIG. 3 is a block diagram showing the configuration of the control unit 201.

  Reference numeral 301 denotes a CPU, which controls each configuration 202-205 of the MFP 102 and each configuration 302-309 of the MFP control unit 201 based on a program developed in the RAM 303. A ROM 302 stores a boot program executed by the CPU 301 and the like. Reference numeral 303 denotes a RAM, and an OS and application programs executed by the CPU 301 are expanded from the HDD 304. Reference numeral 304 denotes an HDD, which stores an OS and application programs executed by the CPU 301. Reference numeral 305 denotes an image processor that executes various types of image processing on image data stored in the image memory 306. An image memory 306 temporarily holds image data input from the reading unit 203 or the network IF or FAX IF. A network IF 307 inputs and outputs image data and the like from an external device such as the PC 101. Reference numeral 308 denotes a FAX IF that inputs and outputs FAX data through a public line (not shown). A power supply control unit 309 switches the power supply state from the power supply unit 205 to each of the components 201-204 of the MFP 102 and each of the components 301-307 of the control unit 201.

  FIG. 4 is a diagram showing a power supply state for each component of the power supply unit 205, a power supply control for each component of the CPU 301 and the power control unit 309, and a signal control configuration. A thick solid arrow indicates power supply, and a dotted arrow indicates power supply control.

  Reference numeral 401 denotes an AC power supply that supplies power to the sub power supply 402. The AC power supply 401 supplies power to the main power supply 403 via the relay switch 406. A sub power source 402 supplies power to each component of the power control unit 309, the FAX incoming circuit 506, the network response circuit 507, and the RAM 303 via the power switch 404 and the relay switch 405. In this embodiment, the output voltage of the sub power supply 402 is 3.3V.

The power switch 404 can be switched ON / OFF by the user, and the SW_MON signal is output to the trigger control unit 501 in accordance with the ON / OFF of the power switch 404. The relay switch 405 is switched ON / OFF according to the RELAY_ON signal of the trigger control unit 501. The relay switch 405 is for controlling the power to perform a predetermined shutdown process without immediately turning off the power of the information processing apparatus when the power switch 404 is turned off.

  A main power source 403 supplies power to the reading unit 203, the printing unit 204, the CPU 301 of the control unit 201, and other necessary circuits. In this embodiment, the output voltage of the main power supply is 12V, and it is converted to a necessary voltage such as 3.3V or 5V by a DC / DC converter (not shown) or the like, and power is supplied to each circuit.

  The relay switch 406 is switched ON / OFF mainly by the RMT_MSW signal output from the main power supply control 409 in accordance with the RMT_SYS signal of the trigger control unit 501. The main power supply 403 may also supply power to each of the components 201-205 of the MFP 102 and each of the components 301-307 of the control unit 201 via a relay switch (not shown).

  Reference numeral 407 denotes a timer A, which is supplied with power from the sub power supply 402, receives the SW_MON signal output from the power switch 404, and outputs a TIM_A signal. The timer A407 is a CR timer circuit that uses charging / discharging of the capacitor. The timer is activated when the power switch 404 is turned OFF, and outputs a TIM_A signal after a predetermined time has elapsed (about 10 seconds in this embodiment).

  A timer B 408 is supplied with power from the main power supply 403, receives the SW_MON signal output from the power switch 404, and outputs a TIM_B signal. The timer B408 is a CR timer circuit that uses charging / discharging of the capacitor. The timer is activated when the power switch 404 is turned off, and outputs a TIM_B signal after a predetermined time has elapsed (about 90 seconds in this embodiment).

  Reference numeral 409 denotes main power control, which outputs an RMT_MSW signal in response to input of an RMT_SYS signal, a TIM_A signal, and a TIM_B signal, and controls the relay switch 406 to turn on / off the main power source 403.

  Reference numeral 501 denotes a trigger control unit that detects each signal input from the CPU 301, the operation unit 202, the network IF 307, the FAX IF 308, and the power switch 404. Then, the relay switches 405, 406, 503, and 504 are turned ON / OFF by outputting the RELAY_ON signal, the RMT_SYS signal, and the RMT_NETFAX signal. Reference numeral 502 denotes an LED control circuit, which can control ON / OFF and blinking of the LED 505. The blinking control is performed by a hardware circuit so as to repeat ON and OFF every 0.5 seconds, for example.

  The CPU 301 controls the trigger control unit 501 by the CPU_CNT signal and receives the status signal STS of the trigger control unit 501.

  Reference numeral 506 denotes a FAX receiving circuit that detects a FAX incoming call from a public line.

  A network response circuit 507 responds to an inquiry via the network or detects that a print job has been input.

  As described above, since the timer B408 is composed of a 12V power source, it is easy to configure a relatively long 90-second timer. In addition, the timer A407 is a timer with a short time of 10 seconds configured from a 3.3V power supply, and thus can be configured without relatively increasing power consumption.

  The detailed processing flow of the present embodiment will be described with reference to the flowcharts of FIGS.

  FIG. 5 is a flowchart showing the start-up and sleep states when the MFP 201 is powered on.

  When the power switch 404 is turned on in S501, it is determined in S502 whether the fast startup setting is turned on. The high-speed startup setting can be set to ON / OFF in advance by an operation unit (not shown), and the control and state when the power switch is OFF will be described later with reference to FIG.

  If the fast activation setting is not turned on in S502, the sub power supply 402 is supplied to the trigger control unit 501 and the like in S503 as normal activation. Here, the LED 505 is turned on, and the power of the FAX incoming circuit 506 and the network response circuit 507 is also turned on. In S504, the RMT_SYS signal is controlled from the trigger control unit 501, and the relay switch 406 is turned on to turn on the main power supply 403. In S505, the CPU 301 is activated. In S506, the CPU 301 reads a program from the HDD 304 and writes it to the RAM 303 to perform various settings and enter a standby state (standby mode).

  If the fast startup setting is ON in S502, the power supply of the sub power supply 402 remains supplied, and the FAX incoming circuit 506 and the network response are controlled by controlling the RMT_NETFAX signal from the trigger control unit 501. The power of the circuit 507 is turned on. Next, in S508, the RMT_SYS signal is controlled from the trigger control unit 501, and the main power supply 403 is turned on by turning on the relay switch 406. The CPU is activated in S509, and the CPU 301 reads the data previously stored in the RAM 303 in S510, and enters a standby state. Here, when the CPU 301 reads data from the RAM 303, it is possible to shift to the standby state at a higher speed than reading from the normally activated HDD 304.

  Next, in S511, it is determined whether or not to shift to sleep. The sleep transition is determined based on whether the sleep (power) button of the operation unit 202 has been pressed or whether a predetermined time has elapsed since standby. When it is determined in S511 that the sleep is shifted, the sleep shift control in S512 is performed. After performing the sleep transition control in S512, the main power supply in S514 is turned off to enter the power saving mode (sleep mode) in which only the sub power supply 402 is turned on. In this sleep state, the LED 505 is lit and data is retained in the RAM 303.

  In S514, it is determined whether to return from sleep. As a condition for returning from sleep, there is a case where a sleep (power) button of the operation unit 202 is pressed or a job such as network print / fax reception print is accepted. If it is determined in S514 that the sleep is restored, the trigger control unit 501 controls the RMT_SYS signal in S515, and the relay switch 406 is turned on to turn on the main power supply 403. In S516, the CPU is activated, and data is read from the RAM 303 in S517, so that the standby state is again entered.

  Next, a flow when the power switch 404 is turned off will be described with reference to FIG. In the MFP 201 in the power-on state, when the power switch 404 is turned off in S601, it is determined whether or not it is in a sleep state in S602. If the main power supply 403 is not in the sleep state, the timer B timer (90 seconds) is started by the SW_MON signal in S603. Here, when not in the sleep state, it is a standby state or a job execution state such as printing. If the job is being executed in S604, the job is canceled and a predetermined process required for shutting down the power is shut down. During standby, only predetermined processing required when the power is turned off is performed as shutdown processing. If the timer B has not expired during the shutdown process in S605, the process continues until the shutdown process ends in S606. When the shutdown process is completed, the RMT_SYS signal is output from the trigger control unit in S607, whereby the RMT_MSW is output from the main power supply control 409, the relay switch 406 is controlled, and the main power supply 403 is turned off. The normal shutdown process is completed within 90 seconds, but when timer B expires in S605 (90 seconds have elapsed), RMT_MSW is forcibly output from the main power supply control 409 by the TIM_B signal even during the shutdown process. Turn off the main power supply 403.

  After the main power supply 403 is turned off in S607, the RELAY_ON signal is output from the trigger control unit 501 in S608, and the relay switch 405 is controlled to turn off the power supply from the sub power supply.

  Next, in the case of the sleep state in S602, it is further determined in S609 whether or not the fast startup setting is ON. If the fast startup setting is ON in S609, the timer A timer (10 seconds) is started by the SW_MON signal in S610. In S611, the RMT_SYS signal is controlled from the trigger control unit 501, and the main power supply 403 is turned on by turning on the relay switch 406. In S612, the CPU is activated. Further, in S610, a fast startup OFF process is performed. Here, the process is almost equivalent to the transition to the normal sleep mode, but the FAX receiving circuit 506 and the network response circuit 507 are further turned off so that FAX reception and network print data reception cannot be performed. . If the timer A has not expired during the fast startup OFF setting process in S614, it continues until the fast startup OFF setting ends in S615. Further, when the fast startup OFF setting is completed, the RMT_SYS signal is output from the trigger control unit in S616, whereby the RMT_MSW is output from the main power supply control 409, the relay switch 406 is controlled, and the main power supply 403 is turned off. This fast startup OFF setting is usually completed within 10 seconds. When the timer A expires in S614 (10 seconds have elapsed), RMT_MSW is forcibly output from the main power supply control 409 by the TIM_A signal and the main power supply 403 is turned off even if the fast startup OFF is being set.

  In S609, if the fast startup setting is not ON, the main power supply 403 is also OFF. In S617, the RELAY_ON signal is output from the trigger control unit 501 and the relay switch 405 is controlled. Turn off the power supply from.

  FIG. 7 shows a time chart of power control. FIG. 7A shows power ON / OFF control in the normal mode, and FIG. 7B shows power ON / OFF control in the fast start mode. A solid line represents a process when the shutdown process is normally completed. The dotted line indicates the control when the timer expires without completing the shutdown process. For example, in FIG. 7A, when the shutdown process is completed, the RMT_MSW signal is also set to L level by turning the RMT_SYS signal to L level, and the main power supply is turned off. Furthermore, the trigger control power supply (sub power supply) is also turned OFF by setting the RELAY_ON signal to the L level. When the shutdown process is not completed, the timer B expires, TIM_B becomes L level, and RMT_MSW becomes L level, thereby turning off the main power.

  In FIG. 7 (b), when the shutdown process is completed, the MT_SYS signal is set to L level, the RMT_MSW signal is also set to L level, and the main power supply is turned off. When the shutdown process is not completed, the timer A expires, TIM_A becomes L level, and RMT_MSW becomes L level, thereby turning off the main power.

  Thus, even when the shutdown process does not operate normally, the main power supply can be reliably turned off by the two hardware timers.

101 PC
102 MFP

Claims (5)

In an information processing device that has a plurality of timer circuits that start when the power switch is turned off and shut off the power circuit after a predetermined time has passed,
An information processing apparatus, wherein the first timer circuit is supplied with power in the power saving mode, and the second timer circuit is cut off in power saving mode. 2. The information processing apparatus according to claim 1, wherein when the power switch is turned off in the power saving mode, only the first timer circuit is enabled. The information processing apparatus has a setting of a fast startup mode, and when the power switch is turned off when the power saving mode and the fast startup mode are set, only the first timer circuit is enabled. Item 4. The information processing apparatus according to Item 1. The information processing apparatus according to claim 1, wherein the first timer circuit has a shorter time setting than the second timer circuit. The information processing apparatus according to claim 1, wherein the first timer circuit is supplied with a voltage lower than that of the second timer circuit.