JP2012185904A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase change memory capable of highly reliable operations.SOLUTION: A semiconductor device comprises a memory array having structure in which memory cells are stacked, the memory cells including memory layers using chalcogenide material and diodes, and initialization conditions and rewrite conditions are changed according to the layer in which the selected memory cell is positioned. The initialization conditions and the rewrite conditions (herein, reset conditions) are changed according to an operation by selecting a current mirror circuit according to the operation and by a control mechanism of reset current in a voltage select circuit and the current mirror circuit.

Description

  The present invention relates to a semiconductor device, and more particularly to a memory device including a memory cell composed of elements that can differ in resistance value in accordance with memory information, and in particular, stores information using a state change of a chalcogenide material, The present invention relates to a technique effective when applied to a storage device including a phase change memory using a memory cell that detects a difference and discriminates information.

  As a technique studied by the present inventors, for example, the following techniques are conceivable in a semiconductor device including a phase change memory. The memory element uses a chalcogenide material (or phase change material) such as Ge—Sb—Te system or Ag—In—Sb—Te system containing at least antimony (Sb) and tellurium (Te) as a material of the recording layer. Yes. The selection element uses a diode. Thus, the characteristics of a phase change memory using a chalcogenide material and a diode are described in Non-Patent Document 1, for example.

  FIG. 2 is a diagram showing the relationship between the pulse width and temperature necessary for the phase change of the resistive memory element using the phase change material. When the storage information ‘0’ is written in the storage element, as shown in FIG. 2, a reset pulse is applied so that the element is heated to the melting point Ta or higher of the chalcogenide material and then rapidly cooled. By setting the cooling time t1 to a short value, for example, about 1 ns, the chalcogenide material becomes a high-resistance amorphous state.

  On the contrary, when the memory information '1' is written, by applying a set pulse that keeps the memory element in a temperature region lower than the melting point Ta and higher than the crystallization temperature Tx equal to or higher than the glass transition point. The chalcogenide material is in a low resistance polycrystalline state. The time t2 required for crystallization varies depending on the composition of the chalcogenide material. The temperature of the element shown in FIG. 2 depends on Joule heat generated by the memory element itself and thermal diffusion to the surroundings.

  Patent Document 1 describes memory cell characteristics and read conditions of a semiconductor memory device having an array structure in which memory cells having a ferroelectric layer are stacked via an insulating layer. Specifically, since the thermal history of the memory cell varies from layer to layer, the electrical characteristics of the memory cell vary depending on the formed layer. In order to reliably read out such a memory cell, a method is described in which the reference voltage is changed according to the layer including the accessed memory cell. Patent Document 2 describes memory cell characteristics of a semiconductor memory device having an array structure in which memory cells made of a chalcogenide material are stacked. That is, it is stated that the chalcogenide material has characteristics that are easily affected by the step of forming the stacked arrangement. Patent Document 3 describes a memory array structure of a stacked magnetic memory. Specifically, a method is described in which the wiring structure, the contact structure, and the like are changed for each layer in order to prevent the writing characteristics from changing for each layer.

Japanese Patent No. 2003-060171 Japanese Patent No. 2007-501519 Japanese Patent No. 2004-266220

"IEE, International Solid-State Circuits Conference, Digest of Technical Papers" (USA), 2007, p. 472-473

  Prior to the present application, the inventors of the present application examined high integration of a phase change memory using a recording layer made of a chalcogenide material and a diode. In particular, when three-dimensionalization by stacking memory arrays was examined, the following two problems were found.

  The first problem is that the thermal history of the memory cell differs from layer to layer, which may cause a difference in the electrical characteristics of the memory cell. Specifically, the heat load is higher in the lower memory array. For this reason, the resistance value after manufacture is expected to be lower in the lower memory array. In a phase change memory, a so-called initialization operation is generally performed in which a higher voltage or a larger current than that in a normal rewrite operation is applied to lower the resistance value. If the bias in this initialization operation is set to a value that matches the upper memory array that requires a higher voltage or larger current, the memory cells located in the lower layer with the lower resistance value will be overstressed, and the recording layer There is a risk that the electrical characteristics of the battery deteriorate. Therefore, it is desirable to adjust the voltage or current in the initialization operation depending on the layer in which the memory cell to be initialized is formed.

  The second problem is that the resistance value after the normal rewrite operation may vary due to the difference in the electrical characteristics of the memory cell caused by the same thermal history as the first problem. In the memory having the ferroelectric layer described in Patent Document 1 described above, that is, the ferroelectric memory, information is stored by applying an electric field to the ferroelectric to change the direction of spontaneous polarization. As a method for compensating for the difference in the electrical characteristics of the memory cell generated between the formed layers, it is conceivable to change the rewrite voltage for each layer. However, this method is not preferable because it is necessary to provide a voltage control circuit for changing the rewrite voltage for each layer and, in addition to the increase in the transistor size, the chip area is increased. Therefore, the difference in electrical characteristics generated in the memory cell after the rewrite operation has to be compensated by adjusting the read condition (here, the reference voltage) as described in Patent Document 1.

  On the other hand, in the phase change memory cell, it is expected that characteristic deterioration such as disturb and endurance will be caused by the difference in the state after rewriting. In order to avoid such a problem, if the operating condition is set in accordance with the lower memory array that requires a higher voltage or a larger current in the reset operation for setting the high resistance state, the upper layer having a relatively high resistance value Excessive stress is applied to the memory cells located in the memory array. As a result, the resistance value after reset becomes higher than necessary, and there is a possibility that the reverse rewriting operation cannot be performed. On the other hand, if the bias in the reset operation is set to a value necessary for the upper memory array, the energy given to the memory cell located in the lower layer having a relatively low resistance value is insufficient, so that a desired resistance value is obtained. There is a risk that it will not change. However, in consideration of chip area suppression, when a readout circuit common to each layer is formed on a silicon substrate, the cell resistance in the reset state must be a certain value or more in order to realize a reliable readout operation. I must. Therefore, a reset operation is desired so that the memory cells located in any memory array have the same resistance value.

  The third problem is that the yield may vary depending on the layer in which the memory cells are formed due to the influence of the thermal load described so far. That is, in the conventional chip architecture, when a layer with a low yield exists, the entire chip is determined to be defective, and the chip is discarded. In such an inspection method, the number of chips acquired per wafer is reduced, resulting in an increase in bit cost. In order to reduce the bit cost, it is desired to have an architecture in which a non-defective product is determined on a layer-by-layer basis, and if there is at least one layer with a high yield, the chip can be regarded as non-defective and shipped.

  Therefore, in view of such problems and the like, an object of the present invention is to perform an initialization operation and a write operation in a phase change memory having a memory array having a structure in which memory cells are stacked, depending on the layer in which the memory cells are formed. By adjusting the driving voltage or driving current, the memory cell is controlled to have a desired resistance value without impairing the electrical characteristics of the chalcogenide material. Further, the performance of the memory cell is evaluated in units of layers, and if there is even one layer with a high yield, a memory array configuration in which only that layer can be used is provided. The above object and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A first memory cell having a first memory element, which is provided in the first layer and in which stored information is written by current, and a second layer formed above the first layer, in which stored information is written by current. A second memory cell having a second storage element and a first address for outputting a first layer selection signal for selecting the first layer or a second layer selection signal for selecting the second layer; A decoder; supplying a first current to the first memory cell when writing first storage information to the first memory cell; and writing the first storage information to the second memory cell. A rewrite driver for supplying a second current having a magnitude different from that of the first current, the rewrite driver in response to the first layer selection signal and the second layer selection signal. 1 current and the second current And controlling the magnitude.

  Alternatively, the first bit line provided in the first layer, the second bit line provided in the second layer formed above the first layer, and the first bit line and the second bit line intersect. A first word line, a second word line, a first memory element provided at an intersection of the first bit line and the first word line, to which memory information is written by a current, and the first word line to the first word line A first memory cell having a first rectifying element for flowing current in a direction to reach the first bit line via a storage element; and provided at an intersection of the first bit line and the second word line; A second storage element in which stored information is written by a current; and a second rectifying element for causing a current to flow from the second word line to the first bit line via the second storage element. A second memory cell; the second bit line; A third memory element that is provided at an intersection of one word line and writes stored information by a current; and for passing a current from the first word line to the second bit line via the third memory element A third memory cell having a third rectifying element; a fourth memory element provided at an intersection of the second bit line and the second word line; and storage information is written by a current; A fourth memory cell having a fourth rectifying element for passing a current in a direction to reach the second bit line via the fourth memory element, and initializes the first or second memory cell. In this case, the first voltage is supplied to the first or second memory cell, and when the third or fourth memory cell is initialized, the third or fourth memory cell is different from the first voltage. A second voltage is supplied

  Alternatively, the first memory cell that is provided in the first layer and has a first memory element that writes the stored information by current and the second layer that is formed above the first layer, and the stored information is written by current. A second memory cell having a second memory element and a first address signal for selecting either the first layer or the second layer for selecting the other of the first layer or the second layer An address conversion circuit for converting to a second address signal, a multiplexer for selecting one of the first address signal and the second address signal output from the address conversion circuit, and the multiplexer selected And a first address decoder for generating a first layer selection signal for selecting the first layer or a second layer selection signal for selecting the second layer according to a signal. To.

  A brief description of the effects obtained by typical inventions among the inventions disclosed in the present application can realize a phase change memory with high reliability.

In the semiconductor device of Embodiment 1 of this invention, it is a figure which shows the structural example of the principal part circuit block of the phase change memory contained in it. It is a figure which shows the relationship between pulse width and temperature required for the phase change of the resistive element using a phase change material. FIG. 2 is a diagram showing a memory array configuration example in the circuit book shown in FIG. 1 in the semiconductor device according to the first embodiment of the present invention; FIG. 4 is a diagram showing a cross-section of stacked memory cells included in the memory array shown in FIG. 3 in the semiconductor device according to the first embodiment of the present invention. In the semiconductor device of Embodiment 1 of this invention, it is a figure which shows the memory map of the phase change memory as described in FIG. FIG. 6 is a diagram showing an example of a page configuration shown in FIG. 5 in the semiconductor device according to the first embodiment of the present invention. In the semiconductor device of Embodiment 1 of this invention, it is a figure which shows the example of allocation of a column address. FIG. 6 is a diagram showing an example of row address assignment in the semiconductor device of the first embodiment of the present invention. FIG. 2 is a diagram showing an example of a detailed configuration of a sense amplifier circuit in FIG. 1 included in the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a detailed configuration of a rewrite driver in FIG. 1 included in the semiconductor device according to the first embodiment of the present invention. FIG. 11 is a diagram illustrating a relationship between a memory layer to be reset and a reset current in the rewrite driver illustrated in FIG. 10 in the semiconductor device according to the first embodiment of the present invention. In the semiconductor device of Embodiment 1 of this invention, it is a figure which shows the setting for every operation | movement of the array voltage VARY. FIG. 6 is a diagram showing an example of an initialization operation of a phase change memory included in the semiconductor device according to the first embodiment of the present invention. FIG. 14 is a diagram showing an example of an internal operation in the initialization operation of the phase change memory shown in FIG. 13 in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a diagram showing an example of a write operation of a phase change memory included in the semiconductor device according to the first embodiment of the present invention. FIG. 16 is a diagram showing an example of an internal operation in a write operation of the phase change memory shown in FIG. 15 in the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a diagram showing an example of a read operation of a phase change memory included in the semiconductor device according to the first embodiment of the present invention. FIG. 18 is a diagram showing an example of an internal operation in a read operation of the phase change memory shown in FIG. 17 in the semiconductor device according to the first embodiment of the present invention. In the semiconductor device of Embodiment 2 of this invention, it is a figure which shows the example of a detailed structure of the rewriting driver in FIG. 1 contained in it. FIG. 20 is a diagram illustrating a relationship between a memory layer to be reset and a reset current in the rewrite driver illustrated in FIG. 19 in the semiconductor device according to the second embodiment of the present invention. In the semiconductor device of Embodiment 3 of this invention, it is a figure which shows the structural example of the principal part circuit block of the phase change memory contained in it. FIG. 22 is a diagram showing a configuration example of an address conversion circuit in the circuit book shown in FIG. 21 in the semiconductor device according to the third embodiment of the present invention. FIG. 23 is a diagram showing an address conversion table in the address conversion circuit shown in FIG. 22 in the semiconductor device according to the third embodiment of the present invention; FIG. 23 is a diagram showing the function of the multiplexer shown in FIG. 22 in the semiconductor device according to the third embodiment of the present invention. In the semiconductor device of Embodiment 4 of this invention, it is a figure which shows the flowchart in the read-out operation | movement for confirming the availability of each memory layer of the phase change memory contained in it. In the semiconductor device of Embodiment 4 of this invention, it is a figure which shows the modification of the read-out operation | movement of the phase change memory contained in it. In the semiconductor device of Embodiment 4 of this invention, it is a figure which shows the example of a response | compatibility with an input command and a chip | tip internal signal. In the semiconductor device of Embodiment 4 of this invention, it is a figure which shows the example of device ID read-out operation | movement of the phase change memory contained in it. In the semiconductor device of Embodiment 4 of this invention, it is a figure which shows the example of the content of device ID. In the semiconductor device of Embodiment 5 of this invention, it is a figure which shows the example of a structure of the principal part block. In the semiconductor device of Embodiment 6 of this invention, it is a figure which shows another example of the structure of the principal part block. In the semiconductor device of Embodiment 7 of this invention, it is a figure which shows the example of a detailed structure of the rewriting driver in FIG. 1 contained in it. FIG. 33 is a diagram showing a relationship between a memory layer to be reset and a reset current in the rewrite driver shown in FIG. 32 in the semiconductor device according to the seventh embodiment of the present invention. FIG. 23 is a diagram showing an example of an internal operation in a write operation of the phase change memory shown in FIG. 22 in the semiconductor device of the seventh embodiment of the present invention. In the semiconductor device of Embodiment 8 of this invention, it is a figure which shows the structural example of the principal part circuit block of the phase change memory contained in it. FIG. 36 is a diagram showing the setting of the array voltage VARY and the function of the voltage selection circuit shown in FIG. 35 by retreating to the semiconductor device according to the eighth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). .

  Note that, in the embodiment, a MOS (Metal Oxide Semiconductor) transistor is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor). In the drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding an arrow symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

(Embodiment 1)
The present embodiment provides a phase change memory capable of changing the initialization condition and the rewrite condition in accordance with the layer in which the selected memory cell is located.

First, a phase change memory according to the present invention will be described with reference to FIGS. The phase change memory according to the present invention has a structure in which a memory layer composed of a recording layer made of a chalcogenide material and a cell selection diode is stacked via an insulating layer.
<< Overall structure of stacked phase change memory >>
FIG. 1 is a circuit block diagram showing a configuration example of a main part of a phase change memory in the semiconductor device according to the first embodiment of the present invention. In the figure, as an example, a configuration in the case of 8 Gbit composed of 2 Gbit memory planes PL0 to PL3 is shown. Each memory plane includes a memory array MA, a sense amplifier, and a rewrite driver (S / A & Write Drive).
er), a column selection gate (Y-Gating), a column decoder YDEC, a first row decoder XDEC1, a second row decoder XDEC2, and a third row decoder XDEC3. As described above, the memory array MA has a configuration in which memory cells including a recording layer made of a chalcogenide material and a cell selection diode are arranged in a three-dimensional matrix. The sense amplifier and the rewrite driver are circuit blocks that read out stored information from the memory array and write stored information into the memory array. The column selection gate (Y-Gating) is connected to the sense amplifier and the rewrite driver via 16896 {= (2 ¹⁴ +2 ⁹ ) −1} data line pairs D [16895: 0], and is connected to the plane data bus. It is a circuit block that is connected to an input / output line buffer group and a latch circuit group (I / OB Buffers & Latches) via the PDBUS and exchanges stored information.

The operation of each decoder will be described below with a focus on the memory plane PL0. The column decoder YDEC is a circuit block for selecting a gate to be activated in a column selection gate that connects the above-described sense amplifier and rewrite driver with an input / output line buffer group and a latch circuit group. The first to third row decoders XDEC1 to XDEC3 are circuit blocks for selecting a memory cell to be activated. The first row decoder uses 4095 (= 2 ¹ ) in accordance with the internal address PA0 [23:12] distributed for the memory plane PL0.
² -1) word lines WL [4095: 0] by selecting one from a circuit block to be activated. The second row decoder selects one of the eight bit line selection lines BS [7: 0] according to the internal address PA0 [26:24] distributed for the memory plane PL0, and activates it. This is a circuit block. The third row decoder selects a pair from the four pairs of layer selection lines (LS7T, LS7B) to (LS0T, LS0B) according to the internal address PA0 [28:27] distributed for the memory plane PL0. This is a circuit block to be activated.

  The array voltage VARY is a voltage supplied from the outside of the phase change memory PCM to the first row decoder XDEC1 and the rewrite driver WD. Here, the array voltage is controlled as shown in FIG. That is, when performing the initialization operation, the voltage is set to any one of V0 to V3 so that the voltage is optimal for each layer, and when performing the read or rewrite operation, the VDD is always set regardless of the layer. And then supplied to the first row decoder XDEC1 and the rewrite driver.

  Here, the array voltage VARY is characterized in that an optimum initialization voltage is supplied for each layer in the initialization operation.

  As described above, the array voltage VARY controlled for each layer is supplied to the first row decoder XDEC1, so that the memory has an optimum voltage for each layer according to the resistance value that varies for each layer due to the difference in electrical characteristics. Cell initialization operation can be performed. Here, the voltage used for initialization can be generated by providing a power generation circuit inside as shown in a seventh embodiment described later. However, since it is sufficient to perform the initialization operation only once in a test at the time of shipment, it can be supplied from the outside without providing a power generation circuit inside. By supplying power from the outside, it is possible to prevent an increase in chip area due to the internal power supply circuit.

  In addition, the array voltage controlled for each layer is supplied to the rewrite driver WD, so that the amount of current Iint flowing in the memory cell during the initialization operation can be controlled to an appropriate value, and the initialization operation can be performed with higher accuracy. It becomes.

Next, the peripheral circuit block will be described. Each of the storage information, command signal, and address signal handled by the phase change memory according to the present invention is sent from the input / output line IO [7: 0] to the global buffer or the output driver (Output Driver).
). The global buffer is controlled by a control signal group CTL1. The stored information is further transferred between the global buffer or the output driver and the input / output line buffer group and the latch circuit group (I / O Buffers & Latches).
Transfer is performed via the corresponding global bus GBUS1 or global bus GBUS2. I / O line buffer group and latch circuit group (I / O Buffers & Latc
hes) is controlled by the control signal group CTL2. The command signal is transferred from the global buffer (Global Buffer) to the command register and control logic circuit (Command Resister & Control Logic) via the chip internal bus IBUS. The address signal IA [30: 0] is also transferred to the address buffer group and the latch group via the IBUS. Specifically, the address signal IA [11: 0] is transferred to the column address buffer group and the latch group (Y-Buffers & Latches). The address signal IA [30:12] is transferred to the row address buffer group and the latch group (X-Buffers & Latches).

Command register and control logic (Command Resister & Con
trol Logic) further includes a row address buffer group and a latch group (X-B).
The control signal groups CTL1 to CTL4 are distributed to the respective blocks of the phase change memory in accordance with the memory plane selection signal PS [3: 0] output from the buffers & Latches) and a plurality of control signals. Specifically, the plurality of control signals are a command latch start signal CLE, an address latch start signal ALE, a chip start signal CEB, a read start signal REB, a write start signal WEB, a write protection signal WPB, and a ready / busy signal RBB. It is. The command latch activation signal CLE is a signal for activating the command register that temporarily stores the command signal. The address / latch activation signal ALE is a signal for activating the aforementioned address buffer group and latch group for temporarily storing the address signal. The chip activation signal CEB is a signal for selecting a phase change memory chip. The read activation signal REB is a signal for activating the above-described output driver and outputting stored information while generating a column address within the chip. The write activation signal WEB is a signal for receiving storage information, a command signal, and an address signal. The write protection signal WPB is a signal for preventing an accidental write operation when the power is turned on. The ready / busy signal RBB is a signal for notifying whether the internal state of the chip is in the middle of a read operation or a write operation.

  The column address buffer group and the latch group (Y-Buffers & Latches) send the address signal IA [11: 0] to the memory plane according to the control signal group CTL3 and the memory plane selection signal PS [3: 0]. This is a circuit block for transferring to PL0 to PL3. For example, when the memory plane control signal PS0 is activated, the internal address signal PA0 [11: 0] is activated. By selectively distributing the internal address signal to the activated memory plane, the power consumption required for driving the signal line can be suppressed.

The row address buffer group and the latch group (X-Buffers & Latches) transfer the address signal IA [30:12] to the memory planes PL0 to PL3 in response to the memory plane selection signal PS [3: 0]. This is a circuit block. Similarly to the internal address signal PA0 [11: 0], the transfer destination memory plane is selected by the memory plane control signals PS0 to PS3 generated according to the internal address signal PA [30:29].
<Configuration of memory array>
FIG. 3 is a diagram showing a detailed configuration example of the memory array MA shown in FIG. By configuring the memory array MA as shown in the figure, it is possible to improve the degree of integration of the memory cells by the structure in which the memory layer using the chalcogenide material and the memory cells configured by the diodes are stacked. The details will be described below.

A unit of a memory cell accessed by one read operation or write operation is hereinafter referred to as a page. The memory array MA of FIG. 3 has 131072 (= 2 ¹⁷ ) pages. Each page is composed of a main area of 2 kbytes and a spare area of 64 bytes, and the total of these pages is 2112 kbytes. The memory array MA having such characteristics will be described in detail below.

The memory array MA includes 16896 (= 2 ¹⁴ +2 ⁹ ) sub memory arrays SM0 to SM16895, a first multiplexer group MUXB1, and a second multiplexer group MUXB2. Each of the sub memory arrays SM0 to SM16895 includes, for example, 4096 (= 2 ¹² ) word lines WL0 to WL4095 (= WL (2 ¹² −1)) and eight local memory arrays SM0. The stacked memory cell groups MB00 to MB (2 ¹² -1) 7 are arranged at the intersections of the bit line pairs (LB001 to LB004) to (LB071 to LB074). Each of the stacked memory cell groups MB00 to MB (2 ¹² -1) 7 includes a phase change resistance element R having a function of a recording layer using a chalcogenide material, a memory cell selecting diode D, a corresponding bit line, The memory cells MC1 to MC4 are connected in series with the word line.

The first multiplexer group MUXB1 is composed of multiplexer groups MB10 to MB116895 corresponding to 16896 (= 2 ¹⁴ +2 ⁹ ) sub memory arrays SM0 to SM16895. Each of the multiplexer groups MB10 to MB116895 selects one of the four local bit lines LB001 to LB004 according to the memory layer selection signal LS [3: 0], for example, like the multiplexer MUX10 in the multiplexer group MB10. Thus, the circuit is connected to the bit BL00.

The second multiplexer group MUXB2 includes multiplexers MUX20 to MUX216895 corresponding to 16896 (= 2 ¹⁴ +2 ⁹ ) sub memory arrays SM0 to SM16895. Each of the multiplexers MUX20 to MUX216895 selects one of the eight local bit lines BL00 to BL07 in accordance with the bit line selection signal BS [7: 0] as in the multiplexer MUX20, for example, and outputs the common data line CD0. It is a circuit connected to.

FIG. 3 also shows a sense amplifier and a rewrite driver (S / A & Write Driver). The sense amplifier and rewrite driver (S / A & Write Driver) are configured by read / write circuits RW0 to RW16895 corresponding to 16896 (= 2 ¹⁴ +2 ⁹ ) sub memory arrays SM0 to SM16895. Each of the read / write circuits RW0 to RW16895 is arranged between the common data line CD0 and the data line pair D0T / B, for example, like the read / write circuit RW0. The read / write circuit RW0 includes a sense amplifier SA and a rewrite driver WD.

In FIG. 3, in the stacked memory cell groups MB00 to MB (2 ¹² −1) 7, bit lines are provided for the memory cells MC1 to MC4 of the first layer to the memory cells MC4 of the fourth layer for each memory cell. The word lines are collectively short-circuited by the same wiring from memory cells MC1 to MC4. Contrary to this embodiment, this configuration can realize the same configuration even if a word line is provided for each memory cell and bit lines are collectively provided by the same wiring. However, since the plurality of word lines are respectively connected to the selection circuit in the row decoder XDEC1, a PMOS having a large area is connected to each of the word lines. Therefore, this embodiment, which can suppress the number of PMOSs by collecting a plurality of word lines, is more effective in suppressing an increase in circuit area.

FIG. 4 shows a cross-sectional structure of the stacked memory cell group and the first multiplexer group shown in FIG. In the figure, as an example, a stacked memory cell group MB00 to MB (2 ¹² −1) 0 and a multiplexer MUX10 connected to the local bit line pairs LB001 to LB004 are shown. The stacked memory cell group according to the present embodiment is characterized in that four memory cells MC1 to MC4 shown in FIG. 3 are stacked.

The stacked memory cell groups MB00 to MB (2 ¹² −1) 0 and the multiplexer MUX10 are formed in a P well region 101 formed on the P type silicon substrate 100. Reference numeral 103 denotes a polysilicon layer serving as a gate electrode of an NMOS transistor included in the multiplexer MUX10. Symbols in parentheses are memory layer selection signals LS [3: 0]. Reference numeral 104 denotes an N + diffusion layer region that becomes a source electrode or a drain electrode of the NMOS transistor. Reference numeral 105 denotes an oxide for element isolation for cutting off current between the transistors.

  Reference numerals 201 to 204 denote first to fourth tungsten layers to be the local bit lines LB001 to LB004. 211 to 214 are fifth to eighth tungsten layers to be word lines. The word line is shared in the stacked memory cell group like WL0, and the fifth to eighth tungsten layers are short-circuited at positions not shown on the paper surface. These first to eighth tungsten layers are separated from each other by an interphase insulating film 600.

  Reference numeral 301 denotes a first contact for connecting the first tungsten layer and the N + diffusion layer. Reference numeral 302 denotes a second contact for connecting the second tungsten layer and the first tungsten layer. Reference numeral 303 denotes a third contact for connecting the third tungsten layer and the second tungsten layer. Reference numeral 304 denotes a fourth contact for connecting the fourth tungsten layer and the third tungsten layer.

The memory cell is, for example, between the tungsten layer (201 in this case) serving as the local bit line LB001 and the tungsten layer (211 in this case) serving as the word line WL0, like the memory cell MC1 in the stacked memory cell group MB00. , Formed in a columnar shape. 400 is a P layer of a PN diode, 401 is an N layer of a PN diode, and 402 is a chalcogenide material layer. Reference numeral 500 denotes a ninth tungsten layer serving as a buffer layer between the PN diode and the chalcogenide material layer, and reference numeral 501 denotes a tenth tungsten layer serving as a buffer layer between the chalcogenide material layer and the local bit line. Here, the memory cell includes a selection transistor and a chalcogenide material layer, and a configuration in which a word line is connected to the gate of the selection transistor is also possible. However, the configuration having the diode and the chalcogenide material layer as in this embodiment can further improve the degree of integration of the memory cells.
<< Memory map >>
Next, a memory map of the phase change memory according to the present embodiment will be described. FIG. 5 is a diagram showing an outline of this memory map. Each of the memory planes PL0 to PL3 is characterized in that it includes four main blocks (Main block 0, Main block 4, Main block 8, and Main block 12) as in the memory plane PL0, for example. These main blocks correspond to stacked memory arrays. For example, main block 0 is a first layer memory array main block 4 is a second layer memory array, main block 8 is a third layer memory array, The memory block 12 is a fourth layer memory array. Each of the main blocks (Main block 0 to Main block 15) is composed of 512 blocks (Block 0 to Block 511) like the main block 0, for example. Further, each of the blocks (Block 0 to Block 511) is composed of 64 pages (Page 0 to Page 63) like the block 0.

FIG. 6 is a diagram showing the page configuration shown in FIG. The page is composed of a main area of 2048 (= 2 ¹¹ ) bytes and a spare area of 64 (= 2 ⁸ ) bytes. The main area is further composed of four areas of 512 bytes (A area to D area, or first sector to fourth sector). The spare area is composed of four 16-byte areas (E area to H area, or fifth sector to eighth sector). Storage information is written in the main area, and a 1-bit error correction code is written in the spare area. According to such a page configuration, the memory array shown in FIG. 3 is composed of 16896 (= 2 ¹⁴ +2 ⁹ ) sub memory arrays. The sense amplifier and rewrite driver (S / A & Write Driver) are composed of 16896 (= 2 ¹⁴ +2 ⁹ ) pairs of sense amplifiers and rewrite drivers.

FIG. 7 is a diagram showing column address assignment. The main area is specified by column addresses 0 to 2047. The spare area is specified by column addresses 2048 to 2111. These column addresses are generated by the address signal IA [11: 0] shown in FIG. Therefore, as will be described in detail later, the storage information of 16896 (= 2 ¹⁴ +2 ⁹ ) bits read out from the memory array MA at one time is temporarily stored in the sense amplifier, and corresponds to the data line selection line DS [211: 0]. 1 byte at a time from the column gate (Y-Gating). On the other hand, the stored information is stored in the rewrite driver 1 byte at a time via the column gate (Y-Gating), and written to the memory array MA at once when 16896 (= 2 ¹⁴ +2 ⁹ ) bits are aligned.

FIG. 8 is a diagram showing row address assignment. The row address is generated by the address signal IA [30:12] shown in FIG. A memory plane selection signal PS [3: 0] is generated by the address signal IA [30:29]. A memory layer selection signal LS [3: 0] is generated by the address signal IA [28:27]. Word lines WL0 to WL (2 ¹² -1) and bit line selection lines BS [7: 0] for selecting a page are generated by an address signal IA [26:12].
<< Configuration of sense amplifier and rewrite driver >>
Hereinafter, a specific configuration example of the sense amplifier and the rewrite driver (S / A & Write Driver) will be described. FIG. 9 shows a read / write circuit RW0 as an example. First, the sense amplifier SA has a known circuit configuration including a precharge circuit PCC, a cross-coupled latch amplifier CCL, and a transmission gate RG.

  The precharge circuit PCC is composed of three NMOS transistors and is activated when the data line equalize signal DLEQ is driven to the boosted voltage VPP higher than the power supply voltage VDD during standby, and the data line pair D0T and D0B is used as a reference. It is driven to the voltage VDR (here, for example, VDD / 2).

  The cross-coupled line latch amplifier CCL is composed of two PMOS transistors and two NMOS transistors. During standby, the common source lines CSP and CSN are driven to the same precharge voltage (here, the reference voltage VDR) as the data line pair D0T and D0B. On the other hand, when a signal corresponding to information stored in the selected memory cell is generated in the data line D0T in the read operation, the common source line CSP is driven to the power supply voltage VDD and the common source line CSN is driven to the ground voltage VSS. As a result, the minute signal generated in the data line pair D0T and D0B is amplified.

  The transmission gate RG is composed of two NMOS transistors inserted between the cross-coupled sense latch and the memory cell array. In the read operation, the transmission gate activation signals RGE1 and RGE2 are activated by being driven to the boosted voltage VPP, and the common data line CD0 and the reference voltage VREF (here, for example, VDD / 2), the cross-coupled latch amplifier, And the signal read from the selected memory cell is transferred to the cross-coupled sense latch. The data line equalize signal DLEQ, common source lines CSP and CSN, and transmission gate activation signals RGE1 and RGE2 are components of the control signal group CTL4.

  FIG. 10 shows the configuration of the rewrite driver WD0. This rewrite driver is characterized in that the current Irst flowing through the memory cell at the time of reset is controlled according to the memory layer selection signals LS1B to LS3B, and the rewrite conditions are changed for each layer. This configuration makes it possible to control the resistance value to a desired value for each layer in accordance with the difference in the electrical characteristics of each layer in the reset operation that puts the memory cell in a high resistance state, and a highly reliable phase change. A memory can be realized.

  The basic configuration of this rewrite driver is three current mirror circuits composed of NMOS transistors MN70, MN71, MN72, and MN73, and has the following two features. The first feature is that the current mirror circuit is activated according to the operation. The second feature is that the voltage value of the supplied array voltage VARY is controlled according to the operation mode.

  First, the configuration of the current mirror circuit will be described. The first current mirror circuit is composed of a combination of transistors MN70 and MN73. PMOS transistors MP700 and MP701 are inserted in series between the transistor MN70 and the array voltage VARY. A bias voltage VBIAS0 is input to the gate of the transistor MP700. A signal obtained by inverting the initialization start signal INT_EN by the inverter circuit IV700 is input to the gate of the transistor MP701. With such a configuration, the memory cell current Icell applied through the common data line CD0 is set to a value Iint necessary for the initialization operation.

  As described above, the first current mirror circuit is characterized in that the initialization current of the memory cell is controlled regardless of the memory layer selection signals LS1B to LS3B. This is because, in initialization, the initialization voltage can be controlled for each layer by controlling the array voltage VARY, and the initialization operation can be performed under optimum conditions. Therefore, it is possible to reduce the circuit area by not providing a circuit that performs control for each layer according to the memory layer selection signal.

  The second current mirror circuit is configured by a combination of transistors MN71 and MN73. PMOS transistors MP710 and MP711 are inserted in series between the transistor MN71 and the array voltage VARY. A bias voltage VBIAS1 is input to the gate of the transistor MP710. The output signal of the two-input NAND circuit ND70 to which the set activation signal SET_EN and the data line D0T are input is input to the gate of the transistor MP711. With this configuration, the memory cell current Icell applied via the common data line CD0 is controlled to a value Iset necessary for the set operation when the memory cell is brought into a low resistance state, that is, when the storage information “1” is written. .

  As described above, the second current mirror circuit is characterized in that the set current Iset of the memory cell is controlled without depending on the memory layer selection signals LS1B to LS3B, as in the first current mirror circuit. This is because the reset resistor is controlled to an appropriate value by a third current mirror circuit, which will be described later, so that it is not necessary to perform control for each layer in accordance with the memory layer selection signal in the set operation. . Therefore, the circuit configuration is simplified and the circuit area can be reduced.

  However, in the first current mirror circuit and the second current mirror circuit described above, a circuit for controlling each layer may be provided.

  The third current mirror circuit is configured by a combination of transistors MN72 and MN73. Between the transistor MN72 and the array voltage VARY, PMOS transistors MP720, MP722, MP723, MP724, and MP721 are inserted in series and parallel. Here, the gate width of the transistors connected in parallel is set larger in the order of the transistors MP720, MP722, MP723, and MP724. The ground voltage VSS is input to the gate of the transistor MP720. Further, inverted signals LS1B to LS3B of the memory layer selection signals LS1T to LS3T are input to the gates of the transistors MP722, MP723, and MP724, respectively. Further, the output signal of the two-input NAND circuit ND71 to which the reset activation signal RST_EN and the data line D0B are input is input to the gate of the transistor MP721. With such a configuration, the memory cell current Icell applied through the common data line CD0 is selected as shown in FIG. 11 when the memory cell is put into a high resistance state, that is, when the storage information “0” is written. It is controlled to a value Irst corresponding to the memory layer. Specifically, when a write operation is performed on a memory cell in the first memory layer (lowermost layer), the reset current Irst is set to Irst0 when the transistor MP720 is turned on. When a write operation is performed on a memory cell in the second memory layer, the reset current Irst is set to (m + 1) × Irst0 by turning on the transistors MP720 and MP722. When a write operation is performed on a memory cell in the third memory layer, the transistors MP720 and MP723 are turned on, so that the reset current Irst is set to (k + 1) × Irst0. When a write operation is performed on a memory cell in the fourth (uppermost layer) memory layer, the reset current Irst is set to (j + 1) × Irst0 when the transistors MP720 and MP724 are turned on. Here, the coefficients m, k, and j are set to have a relationship of m <k <j. Therefore, by applying a larger current to the upper memory array and performing the reset operation, the resistance value of the memory cell in each layer can be reliably controlled to a desired resistance value. Note that the reset current Irst is set to be larger than the set current Iset. Each of the initialization activation signal INIT_EN, the set activation signal SET_EN, and the reset activation signal RST_EN is a component of the control signal group CTL4.

  As described above, the third current mirror circuit is characterized in that transistors MP720, 722, 723, and 724 having different gate widths are connected in parallel and a transistor to be turned on is selected according to a memory layer selection signal. With such a configuration, it is possible to supply an optimum reset current to each layer.

  Note that the transistor MP720 is in a conductive state and may be removed. However, the provision of the transistor MP720 has an advantage that a current serving as a base when the reset operation of the first memory layer is performed can be designed.

  Next, the voltage value of the array voltage VARY supplied to the rewrite driver WD and the first row decoder XDEC1 will be described. FIG. 12 shows the setting of the array voltage VARY for each operation. In the case of the initialization operation, the array voltage VARY having a value corresponding to the memory layer in which the selected cell is located is applied.

Specifically, when the memory cell in the first memory layer (lowermost layer) is initialized, the array voltage VARY is supplied as the first voltage V0. Similarly, when the memory cells in the second memory layer are initialized, the array voltage VARY is supplied as the second voltage V1 higher than the first voltage V0, and the memory cells in the third memory layer are initialized. Is supplied as the third voltage V2 higher than the second voltage V1, and when the memory cell in the fourth memory layer (the highest level) is initialized, the fourth voltage higher than the third voltage V2 is supplied. Voltage V3. The above voltages have the following relationship.
VDD ≧ V3>V2>V1> V0 (Formula 1)
In this way, by supplying the optimum voltage for each layer and performing the initialization operation, it becomes possible to prevent deterioration of electrical characteristics caused by excessive stress applied to the memory layer, and reliable phase change A memory can be realized.

In the read operation or the rewrite operation, the array voltage VARY is set to the power supply voltage VDD. This is because the array voltage is supplied from the outside of the phase change memory PCM and no voltage generation circuit is provided inside. However, in the read operation, since the state of the memory cell is not rewritten, it is not necessary to control the array voltage VARY. Further, in the rewrite operation, the reset operation and the set operation can be performed under the optimum conditions by the rewrite driver shown in FIG. 10, so that the array voltage control shown in FIG. Optimal conditions can be provided.
<< Initialization action >>
The operation of the phase change memory according to the present embodiment described so far will be described below. FIG. 13 shows an example of the initialization operation. The command latch start signal CLE that is at the ground voltage VSS is driven to a high level, and the chip start signal CEB and the address latch start signal ALE that are at a high level are driven to a low level. Thereafter, when the first initialization command signal IN1 is input via the input / output line I / Ox (x = 0 to 7), the first initialization command signal IN1 is phased by the rising edge of the write activation signal WEB. Captured in change memory chip. Next, the command latch activation signal CLE that is at the high level is driven to the low level, and the address latch activation signal ALE that is at the low level are driven to the high level, respectively. Enter the row address. Here, since the column address is from 0 to 2111 as shown in FIG. 7, 12 bits are required. On the other hand, since there are only eight I / O pins for inputting an address as shown in FIG. 1, a 12-bit column address is sequentially input in two steps (CA1, CA2). Similarly, since the row address requires 19 bits as shown in FIG. 8, these are inputted in order in three times (RA1, RA2, RA3). These addresses are taken into the phase change memory chip by the rising edge of the write activation signal WEB, and the addresses are sequentially decoded inside the chip. Further, the address latch start signal ALE that is at the high level is driven to the low level and the command latch start signal CLE that is at the low level are driven to the high level, respectively, and the second initialization command signal IN2 is input to the input / output line I / Ox (x = 0 to 7). The second initialization command signal IN2 is taken into the phase change memory chip by the rising edge of the write activation signal WEB, and an initialization operation is performed. In the initialization operation, the ready / busy signal RBB that is at a high level is driven to a low level.

FIG. 14 is a diagram showing an example of the internal operation of the chip in the initialization operation of the phase change memory according to the present embodiment. This figure shows operation waveforms when the memory cell MC1 in the lowermost layer of the stacked memory cell group MB00 is initialized in the sub memory arrays SMA0 to SMA16895 included in the memory array MA shown in FIG. . In order to simplify the explanation, the operation waveforms of the first multiplexer group MUXB1 and the second multiplexer group MUXB2 are omitted, but the memory layer selection is performed according to the second initialization command IN2 shown in FIG. When the signal LS0 and the bit line selection signal BS0 are activated, the local bit lines LS001, LS101,..., LS1689501 and the common data lines CD0, CD1,. Next, when the initialization start signal INIT_EN at the ground voltage VSS is driven to the power supply voltage VDD and the word line WL0 at the ground voltage VSS is driven to the first array voltage V0, the corresponding local bit line An initialization current Iint is applied to LB001, LB101,..., LB1688951, and an initialization operation is performed. It can be easily understood from FIG. 12 that the array voltage applied to the word line is any one of V0 to V3 depending on the memory layer to which the selected memory cell belongs. .
<< Write operation >>
FIG. 15 shows an example of the write operation. The command latch activation signal CLE that is at the low level is driven to a high level, and the chip activation signal CEB and the address latch activation signal ALE that are at a high level are driven to a low level. Thereafter, when the first write command signal PRG1 is input via the input / output line I / Ox (x = 0 to 7), the first write command signal PRG1 is changed to the phase change memory by the rising edge of the write activation signal WEB.・ Incorporated into the chip. Next, the command latch activation signal CLE that is at the high level is driven to the low level, and the address latch activation signal ALE that is at the low level are driven to the high level, respectively. The row address is divided into three times (RA1, RA2, RA3) and input in order, twice (CA1, CA2). These addresses are taken into the phase change memory chip by the rising edge of the write activation signal WEB, and the addresses are sequentially decoded inside the chip. Further, the address latch activation signal ALE which is at the high level is driven to the low level, and the storage information Din (N) to Din (M) is transferred to the input / output lines I / Ox (x = 0 to 7). Input through. Subsequently, the low-level command latch activation signal CLE is driven to a high level, and the second rewrite command signal PRG2 is input to the input / output line I / Ox (x = 0 to 7). The second initialization command signal PRG2 is taken into the phase change memory chip by the rising edge of the write activation signal WEB, and a rewrite operation is performed. In the rewriting operation, the ready / busy signal RBB that is at a high level is driven to a low level. After the rewrite operation is completed, the ready / busy signal RBB that is at the low level is driven to the high level, and then the state read command signal RDS is input. The state read command signal RDS is taken into the chip at the rising edge of the write activation signal WEB. Furthermore, the state RIO0 after writing is output from the input / output line I / Ox (x = 0 to 7) in synchronization with the read activation signal RDB.

FIG. 16 is a diagram showing an example of the chip internal operation in the rewrite operation of the phase change memory according to the present embodiment. In the figure, in sub memory arrays SMA0 to SMA16895 included in memory array MA shown in FIG. 3, there are shown operation waveforms when storage information is written to memory cell MC1 in the lowest layer of stacked memory cell group MB00. Yes. In response to the second rewrite command PRG2 shown in FIG. 15, the data line equalize signal DLEQ having the boosted voltage VPP is driven to the ground voltage VSS, and the common source lines CSP and CSN having the reference voltage VDR are supplied with power. By being driven to the voltage VDD and the ground voltage VSS, respectively, the stored information input via the data lines D0T to D16895T is temporarily stored in the sense amplifier SA in the read / write circuits RW0 to RW16895. In order to simplify the description, the operation waveforms of the first multiplexer group MUXB1 and the second multiplexer group MUXB2 are omitted, but the memory layer selection signal LS0 and the bit line selection signal BS0 are activated. Thus, the local bit lines LS001, LS101,..., LS1688951 and the common data lines CD0, CD1,. Subsequently, when the reset activation signal RST_EN and the set activation signal SET_EN are respectively driven to the power supply voltage VDD and the word line WL0 that is at the ground voltage VSS is driven to the array voltage VARY (here, the power supply voltage VDD), In accordance with the stored information stored in the corresponding sense amplifier, the reset current Irst or the set current Iset is applied to the local bit lines LB001, LB101,. Note that the pulse width of the set activation signal SET_EN is set larger than that of the reset activation signal RST_EN so that the memory layer can be sufficiently crystallized to reduce its resistance value. Finally, the common source line CSP having the power supply voltage VDD and the common source line CSN having the ground voltage VSS are driven to the reference voltage VDR, respectively, and the data line equalize signal DLEQ having the ground voltage VSS is boosted. Driving to the voltage VPP returns to the standby state.
<< Read operation >>
FIG. 17 shows an example of a read operation. The command latch activation signal CLE that is at the low level is driven to a high level, and the chip activation signal CEB and the address latch activation signal ALE that are at a high level are driven to a low level. Thereafter, when the first read command signal RD1 is input via the input / output line I / Ox (x = 0 to 7), the first read command signal RD1 is changed to the phase change memory by the rising edge of the write activation signal WEB.・ Incorporated into the chip. Next, the command latch activation signal CLE that is at the high level is driven to the low level, and the address latch activation signal ALE that is at the low level are driven to the high level, respectively. The row address is divided into three times (RA1, RA2, RA3) and input in order, twice (CA1, CA2). These addresses are taken into the phase change memory chip by the rising edge of the write activation signal WEB, and the addresses are sequentially decoded inside the chip. Further, the address latch start signal ALE that is at a high level is driven to a low level and the command latch start signal CLE that is at a low level is driven to a high level, respectively, and the second read command signal RD2 is driven. Are input to the input / output line I / Ox (x = 0 to 7). The second read command signal RD2 is taken into the phase change memory chip by the rising edge of the write activation signal WEB, and a read operation is performed. In the read operation, the ready / busy signal RBB that is at a high level is driven to a low level. The storage information read from the memory array is transferred inside the chip and the ready / busy signal RBB, which is at the low level, is driven to the high level, and then is synchronized with the rising edge of the read activation signal REB. It is output in the order of Dout (N) to Dout (M).

  FIG. 18 is a diagram showing an example of the chip internal operation in the read operation of the phase change memory according to the present embodiment. In the figure, in sub memory arrays SMA0 to SMA16895 included in memory array MA shown in FIG. 3, operation waveforms in the case of reading storage information from memory cell MC1 in the lowest layer of stacked memory cell group MB00 are shown. Yes. In order to simplify the description, the operation waveforms of the first multiplexer group MUXB1 and the second multiplexer group MUXB2 are omitted, but in response to the second read command RD2 shown in FIG. By activating LS0 and bit line selection signal BS0, local bit lines LS001, LS101,..., LS1689501 and common data lines CD0, CD1,. Next, the transmission gate activation signal RGE1 at the ground voltage VSS is driven to the boosted voltage VPP, and each of the local bit lines LS001, LS101,..., LS1688951 is driven to the ground voltage VSS. Further, the data line equalize signal DLEQ at the boosted voltage VPP is driven to the ground voltage VSS, and the transmission gate activation signal RGE2 at the ground voltage VSS is driven to the boosted voltage VPP, respectively, so that the data lines D0B, D1B,. Is driven to the reference voltage VREF. Subsequently, by driving the word line at the ground voltage VSS to the array voltage VARY (here, the power supply voltage VDD), the local bit line and the data line are driven to a voltage corresponding to the stored information. For example, when the memory cell on the local bit line LB001 stores information “1” and is in a low resistance state, the local bit line LB001 and the data line D0T are charged. On the other hand, as in the memory cell on the local bit line LB101, information "0" is stored, and when in the high resistance state, the local bit line LB101 and the data line D1T are substantially held at the ground voltage VSS. Is done. Thereafter, as in the case of the local bit line LB001 and the data line D0T from which the storage information “1” is read, the common source line CSP having the reference voltage VDR at the timing when these voltages exceed the reference voltage VREF, The CSN is driven to the power supply voltage VDD and the ground voltage VSS, respectively, and the read signal is amplified. Further, the common data lines CD0, CD1,..., CD16895 are driven by driving the word line WL0 having the power supply voltage VDD to the ground voltage VSS and the transmission gate activation signals RGE1 and RGE2 having the boosted voltage VPP to the ground voltage VSS. And the data lines D0T, D1T,..., D16895T, thereby avoiding data destruction due to excessive voltage application. Finally, the common source line CSP having the power supply voltage VDD and the common source line CSN having the ground voltage VSS are driven to the reference voltage VDR, respectively, and the data line equalize signal DLEQ having the boost voltage VPP is grounded. Driving to the voltage VSS returns to the standby state.

  With the above configuration and operation, the following two effects can be obtained. As shown in FIG. 4, the first effect is to improve the degree of integration of the phase change memory chip by using a structure in which a memory cell using a chalcogenide material and a memory cell composed of a diode are stacked. There is in point that can. The second effect is that the initialization condition and the rewrite condition are changed according to the layer in which the selected memory cell is located. Specifically, as shown in FIG. 10, the current mirror circuit is selected according to the operation, and the initialization condition and rewriting are performed by the voltage setting and the control mechanism of the reset current Irst in the current mirror circuit shown in FIG. Conditions (here, reset conditions) can be changed according to the operation. With such a mechanism, it is possible to prevent deterioration in electrical characteristics caused by application of excessive stress to the memory layer in the initialization operation. In addition, the resistance value can be controlled to a desired value in the reset operation for setting the memory cell in the high resistance state. Therefore, a highly reliable phase change memory can be realized.

Note that although the case where four layers of memory cells are stacked has been described in this embodiment mode, the number of stacked layers is not limited to this, and may be two layers or eight layers. In this case as well, the same effect can be obtained by controlling the operating conditions in accordance with the selected memory layer.
(Embodiment 2)
In the second embodiment, another configuration of the rewrite driver WD shown in FIG. 10 will be described. FIG. 19 shows a configuration example of the rewrite driver WD in the present embodiment. The difference between this rewriting circuit and the rewriting circuit shown in FIG. 10 is that the PMOS transistors MP722, MP723, and MP724 are replaced with transistors MP725 and MP726. The gate width of these transistors is a one-to-one-to-two dimension in the order of the transistors MP720, MP725, and MP726.

A signal LS13B obtained by inverting the output signal of the two-input NAND circuit ND720 to which the memory layer selection signals LS1B and LS3B are input by the inverter circuit IV720 is input to the gate of the transistor MP725. A signal LS23B obtained by inverting the output signal of the two-input NAND circuit ND721, to which the memory layer selection signals LS2B and LS3B are input, by the inverter circuit IV721 is input to the gate of the transistor MP726. With such a configuration, a four-stage reset current Irst as shown in FIG. 20 is generated using three transistors. If the logic circuit portion is shared by a plurality of rewrite circuits, the number of transistors in the rewrite driver is reduced, and the area of the rewrite driver WD can be suppressed.
(Embodiment 3)
In the third embodiment, another configuration example of the phase change memory PCM shown in FIG. 1 will be described. FIG. 21 shows a configuration example of the phase change memory PCM in the present embodiment. The feature of this phase change memory PCM is that only a memory layer determined to be non-defective is used by determining whether each memory layer is non-defective or defective. In order to realize such a function, there is a feature in that an address conversion circuit AE is added to the configuration shown in FIG. The address conversion circuit AE converts the internal address IA [28:27] into the internal address CA [28:27] and transfers it to the row address buffer group and the latch group (X-Buffers & Latches).

  FIG. 22 shows a configuration example of the address conversion circuit AE shown in FIG. The address conversion circuit AE includes an address conversion logic circuit AEL and a multiplexer MUX. The address conversion circuit is set to an arbitrary logic using a fuse or the like. This logic differs depending on the combination of the memory layers determined to be non-defective, and for example, a function as shown in FIG. 23 is realized. Its function is described below.

  The first function is to generate an address for selecting one of the first layer to the fourth layer, since there is one non-defective memory layer. In this case, the internal address IA [28:27] to be input is defined as 00. The address conversion logic circuit AEL converts the internal address IA [28:27] into any one of 00, 01, 10, and 11 according to the memory layer determined to be non-defective.

  The second function is that there are two memory layers determined as non-defective, and an address for selecting any one of the first to fourth layers is generated. In this case, the internal address IA [28:27] to be input is defined as 00 or 01. The address conversion logic circuit AEL converts the internal address IA [28:27] into six combinations according to the memory layer determined to be non-defective.

  The third function is to generate three addresses from which the non-defective products are determined, and to select one of the three layers from the first layer to the fourth layer. In this case, the internal address IA [28:27] to be input is defined as one of 00, 01, and 10. The address conversion logic circuit AEL converts the internal address IA [28:27] into four combinations according to the non-defective memory layer.

  The fourth function is that the non-defective memory layers are four layers and an address for selecting one of the first to fourth layers is generated. In this case, the internal address IA [28:27] to be input is defined as one of 00, 01, 10, and 11. The internal address IA [28:27] is output as it is as the internal address EA [28:27].

The multiplexer MUX outputs either the internal address IA [28:27] or the internal EA [28:27] as the internal address CA [28:27] according to the control signal group CTL4. As shown in FIG. 24, the control signal group CTL4 includes an initialization mode signal INIT, a test mode signal TEST, and a normal operation mode signal NORM. The initialization mode signal INIT is activated by the first and second initialization command signals IN1 and IN2 as shown in FIG. As shown in FIGS. 15 and 17, the normal operation mode signal NORM includes the first and second rewrite command signals PRG1 and PRG2, and the first and second read command signals RD1.
, Activated by RD2. The test mode signal TEST is the first and second rewrite command signals PRG1 and PRG2 and the first and second read command signals RD1 and RD2 shown in FIGS. It is activated by inputting the second rewrite command signals TPRG1 and TPRG2 and the first and second read command signals TRD1 and TRD2. With the above operation mode signals, in the initialization mode and the test mode, the internal address IA [28:27] is selected and output to the internal address CA [28:27]. In the normal operation mode, the internal address EA [28:27] converted by the address conversion logic circuit AEL is selected and output to the internal address CA [28:27].

The following effects can be obtained by the configuration and operation of the address conversion circuit AE as described above. That is, as shown in FIG. 23, by converting the internal address IA [28:27] to the internal address EA [28:27], when performing the initialization operation, the write operation, and the read operation test, By selecting all the memory layers and performing a desired operation, it is possible to identify non-defective products or defective products in units of memory layers. In addition, by setting the address conversion logic circuit AEL for each chip according to the characteristic determination for each memory layer, a so-called partial product chip capable of performing memory operation by selecting only a memory layer with good characteristics is realized. can do. Such a partial product can improve the number of chips acquired per wafer and reduce the bit cost.
(Embodiment 4)
In the present embodiment, a means for confirming usable memory layers in the partial product chip described in the third embodiment will be described. The feature of this means is that, in the page configuration shown in FIG. 7, information on whether or not the memory layer including the corresponding page can be used is written in the spare area of an arbitrary page before shipping the chip. It is in. More specifically, as shown in FIG. 5, in the memory plane PL0, the first and second blocks of the main blocks Main block 0, Main block 4, Main block 8, Main block 12 in the first block Block 0, Block 2048, Block 4096, and Block 6144 are displayed. Information on whether or not the memory layer is usable is written in the memory cell selected by the column address 2049 in the spare area of the pages Page 0 and Page 1. The spare area is not necessarily configured by the same memory as the main block, and may be configured by another nonvolatile memory.

  In the following, it is assumed that the corresponding memory layer can be used when the storage information is “FFh” and cannot be used when the storage information is other than “FFh”.

  FIG. 25 shows a flowchart in a read operation for confirming whether or not the memory layer can be used. First, the memory layer availability confirmation command signal RLS1 is input. Next, an address signal corresponding to the column address 2049 and a row address signal for selecting the aforementioned page shown in FIG. 8 are input. Further, the memory layer usability confirmation command signal RLS2 is input to read storage information in a desired spare area. Here, if the corresponding memory layer is usable, the stored information “FFh” is transferred to a so-called host-side device such as a memory controller or a central processing unit CPU connected outside the phase change memory chip. Be notified. On the other hand, when the corresponding memory layer is unusable, information other than the stored information “FFh” is a so-called host side such as a memory controller or a central processing unit CPU connected outside the phase change memory chip. The device is notified. Information notified in this way is recorded in the unusable memory layer management table (Invalid Layer Table) by the host-side device. Such an operation is repeated while advancing the memory layer address one layer at a time to create an unusable memory layer management table.

  FIG. 26 shows a read operation portion in the flowchart shown in FIG. The operation principle is the same as the read operation shown in FIG. The first and second command signals are replaced from the read command signals RD1 and RD2 shown in FIG. 17 with memory layer availability confirmation command signals RLS1 and RLS2. Another feature is that only the storage information of the column address 2049 in the first page or the subsequent page is read out.

  FIG. 27 is a diagram showing another function of the multiplexer shown in FIG. The function of the multiplexer according to the present embodiment is expanded by the memory layer confirmation mode signal RLS generated from the first and second memory layer availability confirmation command signals RLS1 and RLS2. That is, when the memory layer confirmation mode signal RLS is activated, the internal address IA [28:27] is selected and output to the internal address CA [28:27]. The memory layer confirmation mode signal RLS newly added in the present embodiment is a component of the control signal group CTL4.

  With the above configuration and operation, the following effects can be obtained. That is, by reading the storage information in the spare area of each memory layer using the first and second memory layer availability confirmation command signals RLS1 and RLS2, it is possible to determine which memory layer the host side device can use. I can understand. Therefore, it becomes easy to construct a system by combining phase change memory chips of various capacities or to add phase change memory chips.

The method for confirming whether or not the memory layer can be used is not limited to this, and there are various methods. For example, a device ID table may be provided in the phase change memory chip to store information regarding the memory plane capacity. FIG. 28 is a timing chart of a device ID read operation, and FIG. 29 shows a device ID table. The device ID read operation shown in FIG. 28 is based on the read operation shown in FIG. 17, and the device IDs shown in FIG. 29 are sequentially read by the device ID read command signal RID. The chip user (here, the host-side device) can grasp the effective chip capacity of the phase change memory and the address signal to be input from the memory plane capacity.
(Embodiment 5)
In this embodiment, a phase change memory module formed using a plurality of phase change memory chips described in the third to fourth embodiments will be described. FIG. 30 shows a configuration of the phase change memory module PM according to the present embodiment. In the figure, as an example, a configuration using four phase change memory chips PCM0 to PCM3 and a nonvolatile memory control chip NVCTL is shown.

The nonvolatile memory control chip NVCTL has the unusable memory layer management table (Invalid Layer Table) described in the third to fourth embodiments. Also, it has a wear leveling function for leveling the number of rewrites in each memory cell, and a garbage collection function for collecting free areas scattered in the memory space. The phase change memory chips PCM0 to PCM3 have the address conversion circuit AE shown in FIGS. The address conversion circuit AE converts the input address signal into an internal address signal for selecting a usable memory layer. The nonvolatile memory control chip NVCTL and the phase change memory chips PCM0 to PCM3 are connected by an input / output line I / O. The nonvolatile memory control chip NVCTL is connected to the host device via the system bus SBUS. With such a configuration, it is possible to construct a large-capacity storage device that combines phase change memory chips of various capacities.
(Embodiment 6)
In the present embodiment, another configuration of a phase change memory module formed using the plurality of phase change memory chips described will be described. FIG. 31 shows a configuration of the phase change memory module PM according to the present embodiment. In the figure, as an example, a configuration using four phase change memory chips PCM0 to PCM3 and a nonvolatile memory control chip NVCTL is shown. Here, it is assumed that the four phase change memory chips PCM0 to PCM3 do not have the address conversion circuit as described in the third to fourth embodiments.

The difference from the phase change memory module shown in FIG. 30 is that the nonvolatile memory control chip NVCTL has an address generation circuit block AG having an address conversion function as shown in FIG. The non-volatile memory control chip NVCTL performs a read operation for checking the availability of the memory layer shown in FIGS. 18 and 19 each time the power is turned on, and builds an unusable memory layer management table (Invalid Layer Table) To do. By consolidating the address conversion function in the nonvolatile memory control chip NVCTL, it is possible to reduce the chip area of the phase change memory chips PCM0 to PCM3.
(Embodiment 7)
In this embodiment, another example of the semiconductor device of Embodiment 1 will be described. In the present embodiment, the control signal group CTL4 shown in FIG. 1 further includes four types of reset activation signals RST_EN0 to RST_EN3, and selects these reset activation signals according to the memory layer to which the stored information is written. There is a feature.

  FIG. 32 shows another configuration example of the rewrite driver in FIG. The characteristic of the figure is activated by performing an AND logic operation of the reset activation signals RST_EN0 to RST_EN3 and the memory layer selection signals LS [3: 0] using the NAND circuits ND730 to ND733 and the inverter circuits IV730 to 733. The reset activation signal corresponding to the selected memory layer selection signal is selected. The output signals of the inverter circuits IV730 to 733, which are the results of the AND logic operation, are respectively input to the four-input NOR circuit NR730, and the reset activation signal generated by inverting the output signal by the inverter circuit IV734 is input to the NAND circuit ND71. Entered.

  FIG. 34 is a diagram showing an example of the chip internal operation in the rewrite operation of the phase change memory in the semiconductor device shown in FIG. In the figure, in sub memory arrays SMA0 to SMA16895 included in memory array MA shown in FIG. 3, there are shown operation waveforms when storage information is written to memory cell MC1 in the lowest layer of stacked memory cell group MB00. Yes. The pulse width of the reset activation signal RST_EN [3: 0] is set to increase in the order of the reset activation signal RST_EN3 to RST_EN0. These pulses are selected in the rewrite driver shown in FIG. Here, since the memory layer to which the stored information is written is the lowest layer, when the memory layer selection signal LS0 is activated, the reset activation signal RST_EN0 having a large pulse width is selected as shown in FIG. . By this reset activation signal RST_EN0, a reset operation is performed according to the stored information.

With the above configuration and operation, the following effects can be obtained. That is, the resistance of the recording layer can be increased to a desired value by increasing the current drive time in the reset operation for the memory cell located in the lower layer having a relatively low resistance value. Further, like the rewrite driver shown in FIG. 32, the reset operation can be performed more reliably by combining with the adjustment function of the applied current.
(Embodiment 8)
In the present embodiment, another configuration of the phase change memory chip described so far will be described. FIG. 35 shows a configuration based on the phase change memory chip shown in FIG. There are the following three features.

  The first feature is that a plurality of voltages V [3: 0] are generated inside the chip using the internal voltage generation circuit VGEN. The internal voltage generation circuit VGEN generates a plurality of these voltages from the power supply voltage VDD and the ground voltage VSS. By supplying the power supply voltage VDD to the logic circuit and supplying a plurality of voltages to the memory array, the operation of the logic circuit and driving of the plurality of voltages can be stabilized.

  A second feature is that each of the generated power supply lines of the voltage V [3: 0] is drawn to the pads PAD_V0 to PAD_V3. With such a configuration, it becomes easy to measure whether or not a desired voltage can be generated inside the chip.

  A third feature is that a voltage selection circuit VSEL is provided in the memory planes PL0 to PL3. The voltage selection circuit VSEL selects a value corresponding to the initialization activation signal INIT_EN and the memory layer selection signal LS [3: 0], which are components of the control signal group CTL4, and outputs it as the array voltage VARY. The array voltage VARY controlled to an appropriate value is supplied to the word line WL via the first row decoder XDEC1, and is also supplied to the rewrite driver WD. By such voltage control, it is possible to perform the initialization operation of the memory cell with an optimum voltage for each layer according to the resistance value that varies for each layer due to the difference in electrical characteristics.

  Specifically, the array voltage VARY is set as shown in FIG. When the memory cells in the first memory layer (lowermost layer) are initialized, the memory layer selection signal LS0 is activated (in this case, driven to the power supply voltage VDD), so that the array voltage VARY becomes the first. The voltage V0 is driven. When the memory cells in the second memory layer are initialized, the memory layer selection signal LS1 is activated (in this case, driven to the power supply voltage VDD), so that the array voltage VARY becomes higher than the first voltage V0. Is driven to the second voltage V1. When the memory cells in the third memory layer are initialized, the memory layer selection signal LS2 is activated (in this case, driven to the power supply voltage VDD), so that the array voltage VARY becomes higher than the second voltage V1. Is also driven to a third voltage V2. When initializing the memory cell in the fourth memory layer (topmost layer), the memory layer selection signal LS3 is activated (in this case, driven to the power supply voltage VDD), so that the array voltage VARY becomes the third voltage. Is driven to a fourth voltage V3, which is higher than the voltage V2. The above voltages satisfy the relationship of (Equation 1) described above.

  In this way, by supplying the optimum voltage for each layer and performing the initialization operation, it becomes possible to prevent deterioration of the electrical characteristics caused by the application of excessive stress to the memory layer, and highly reliable phase change A memory can be realized.

  Note that when the initialization activation signal INIT_EN is in an inactive state (in this case, driven to the ground voltage VSS), the phase change memory according to the present invention performs a read operation or a rewrite operation. In such a case, the array voltage VARY is set to the power supply voltage VDD regardless of the state of the memory layer selection signals LS [3: 0]. The array voltage VARY can be supplied from the outside. This is because it is sufficient to perform the initialization operation once in a test at the time of shipment, and it is sufficient to supply a voltage necessary for the initialization by a test at the time of shipment. It is also possible to provide a dedicated pin for the array voltage VARY to supply the array voltage according to the memory layer. However, since the desired initialization operation can be performed only by adjusting the value of the power supply voltage VDD, the operation of this embodiment can be realized by adjusting the voltage applied to the power supply voltage VDD pin. In this case, since the number of pins can be suppressed, the area of the memory chip can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the memory cells to be stacked are not limited to four layers, and may be less or more (for example, two layers or eight layers). On the other hand, the array voltage in the initialization operation is not limited to a setting that becomes higher as the upper layer, but other settings are possible depending on the characteristics of the memory cell. For example, if the resistance value of the upper memory cell tends to be lower for some reason, such as the variation in processing dimension becomes larger in the upper memory cell, the array voltage may be set to be lower in the upper layer. Is possible. Similarly, the reset current Irst in the reset operation can be set smaller as the upper layer. In addition, the width of the reset activation signal RST_EN in the reset operation can be set to be smaller as the upper layer. Furthermore, not only the reset operation but also the set-up operation can optimize the same rewrite conditions depending on the electrical characteristics of the memory cell. The present invention is not limited to a single memory chip, but can be applied to an on-chip memory interface. The concept of the present invention is not limited to phase change memory, but can be applied to various semiconductor memories such as flash memory, dynamic random access memory, static random access memory, magnetoresistive random access memory, etc. It is also possible to do.

  The semiconductor device of the present invention prevents excessive stress on the recording layer and avoids deterioration of electrical characteristics by adjusting the initialization operation condition and the reset operation condition according to the layer in which the memory cell to be accessed is located. Is. As the capacity of a semiconductor memory increases, the memory array is three-dimensionalized by stacking. Further, as the number of stacked memory cells increases, the difference in thermal history between the memory cells increases, so that the difference in electrical characteristics of the memory array increases. However, according to the present invention, since the operating conditions can be optimized for each layer, it is suitable for a highly reliable technology of a semiconductor device having a future stacked memory array.

PCM, PCM0 to PCM3 phase change memory,
PL0 to PL3 Memory plane MA Memory array YDEC Column decoder XDEC1, XDEC2, XDEC3 Row decoder,
D [16895: 0], D0T / B to D16895T / B data line pairs,
IA [30: 0] address signal,
PA0 [28:27], PA0 [26:24], PA0 [23:12], CA [28: 2
7], EA [28:27] Internal address signal,
WL [4095: 0] word line,
BS [7: 0] bit line selection line,
LS7T, LS7B) to (LS0T, LS0B) selection line,
CTL1 to CTL4 control signal group,
INITV [3: 0] Initialization voltage,
VARY, V0, V1, V2, V3 array voltage,
IO [7: 0] I / O line,
CLE command latch start signal,
ALE address latch start signal,
CEB chip activation signal,
REB read start signal,
WEB write start signal,
WPB write protection signal,
RBB ready / busy signal,
PS [3: 0] Memory plane selection signal,
SM0 to SM16895 sub memory array,
MUXB1, MUXB2, MB10 to MB116895 multiplexer group,
MB00 to MB (2 ¹² -1) 7 stacked memory cell group,
R phase change resistance element,
D a diode for selecting a memory cell,
MC1 to MC4 memory cells,
MUX, MUX10 to MUX17, MUX20 to MUX216895 multiplexer,
LB001 to LB004 local bit lines,
BL00 to BL1168957 bits,
CD0 to CD116895 common data line,
RW0 to RW16895 read / write circuit,
SA sense amplifier,
WD rewrite driver,
100 P-type silicon substrate,
101 P-well region,
103 polysilicon layer,
104 N + diffusion layer region,
105 oxide for element isolation,
201-204, 211-214, 500-501 tungsten layer,
600 interphase insulating film,
301, 302, 303, 304 contact,
P layer of 400 PN diode,
401 N layer of PN diode,
402 chalcogenide material layer,
SA sense amplifier,
PCC precharge circuit,
CCL cross-coupled latch amplifier,
RG transmission gate,
DLEQ data line equalize signal,
CSP, CSN common source line,
RGE1, RGE2 transmission gate activation signal,
VDD supply voltage,
VPP boost voltage,
VDR reference voltage,
VSS ground voltage,
VREF reference voltage,
VBIAS0, VBIAS1 bias voltage,
MN70, MN71, MN72, MN73 NMOS transistors,
MP700, MP701, MP710, MP711, MP710, MP722, MP723, MP724, MP725, MP726 PMOS transistor,
INT_EN initialization start signal,
IV700, IV730-733 inverter circuit,
Icell, Iint, Iset, Irst Memory cell current,
SET_EN set activation signal,
ND70, ND71, ND720, ND721, ND730-ND733 two-input NAND circuit,
INIT_EN initialization start signal,
SET_EN set activation signal,
RST_EN, RST_EN0 to RST_EN3 Reset start signal,
IN1, IN2 initialization command signal,
CA1, CA2 column address,
RA1, RA2, RA3 row address,
PRG1, PRG2 write command signal,
RD1, RD2 read command signal,
IV720, IV721 inverter circuit,
AE address conversion circuit,
AEL address conversion logic circuit,
INIT initialization mode signal,
TEST test mode signal,
NORM Normal operation mode signal,
RLS1, RLS2 memory layer availability confirmation command signal,
RLS memory layer confirmation mode signal,
RID device ID read command signal,
NVCTL nonvolatile memory control chip,
SBUS system bus,
NR730 four-input NOR circuit,
PAD_V0 to PAD_V3 Pad VGEN Chip internal power generation circuit VSEL Voltage selection circuit.

Claims (6)

A first memory cell that is provided in the first layer and has a first memory element that writes memory information by current;
A second memory cell provided in a second layer formed above the first layer and having a second memory element for writing stored information by current;
Address conversion circuit for converting a first address signal for selecting either the first layer or the second layer into a second address signal for selecting the other of the first layer or the second layer When,
A multiplexer for selecting one of the first address signal and the second address signal output from the address conversion circuit;
A first address decoder for generating a first layer selection signal for selecting the first layer or a second layer selection signal for selecting the second layer according to a signal selected by the multiplexer; A featured semiconductor device. The semiconductor device according to claim 1,
The multiplexer selects the second address signal when either the first layer or the second layer is not usable and the other of the first layer or the second layer is usable. A semiconductor device. The semiconductor device according to claim 1,
A non-volatile memory;
Information about whether or not the first layer and the second layer are usable is written in the memory. The semiconductor device according to claim 1,
A first bit line provided in the first layer and connected to the first memory cell;
A second bit line provided in the second layer and connected to the second memory cell;
And a first word line connected to the first memory cell and the second memory cell, the first memory cell passing through the first memory element from the first word line. A first rectifier for flowing current in a direction to the bit line;
The second memory cell further includes a second rectifying element for causing a current to flow from the first word line to the second bit line via the second memory element. . The semiconductor device according to claim 1,
The semiconductor device, wherein the first memory element and the second memory element are phase change elements. A plurality of memory cells each having a phase change memory;
A word driver that supplies a reset pulse to each of the plurality of
Each of the plurality of memory cells is stacked on each other,
2. The semiconductor device according to claim 1, wherein the word driver supplies a reset pulse having a wider pulse width to a memory cell located in a lower layer among the plurality of memory cells.

Images