JP2012160992A - Clock synchronous serial communication device and communication control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce communication overheads generated at the time of specification of a slave device to be targeted for communication when a master device and a plurality of slave devices perform serial data communication.SOLUTION: A clock synchronous serial communication device comprises: a master device which adjusts a frequency of a clock signal and outputs the clock signal whose frequency is adjusted and a data signal; and a plurality of slave devices which receive the data signal and the clock signal outputted from the master device, and measure the frequency of the received clock signal. The plurality of slave devices respectively hold the frequency for identification, and hold or discard the data signal outputted from the master device according to whether or not the measured frequency and the frequency for identification are matched with each other.

Description

  The present invention relates to a clock synchronous serial communication device and a communication control method thereof, and more particularly to a clock synchronous serial communication device in which a plurality of slave devices are connected to a master device and a communication control method thereof.

  In recent years, in a communication system, cases where one master device and a plurality of slave devices perform serial data communication are increasing. Generally, when a communication system has a plurality of slave devices, a selection signal for selecting a slave device is transmitted during data communication. However, with the complexity of the system, the number of slave devices to be connected has increased, and the selection of slave devices has become complicated.

  In such a situation, a connection error on the hardware occurs or a phenomenon occurs in which each other enters a waiting state during communication and affects the operation of the system. Therefore, it is desired to realize a stable operation and an efficient connection method between a master device and a plurality of slave devices.

  The technique described in Patent Document 1 realizes a serial data transfer apparatus that minimizes the number of signals used for serial data transfer and does not increase the number of signal lines even if the number of devices that transfer data increases.

  FIG. 7 is a configuration explanatory diagram of the serial data transfer device described in Patent Document 1. In FIG.

  In FIG. 7, 1 is a master serial interface circuit that operates in the master mode, and 2 to 5 are slave serial interface circuits that operate in the slave mode. The clock output for serial data transfer output from the CLK terminal of the master serial interface circuit 1 is input to the clock input terminals CLK of the slave serial interface circuits 2 to 5, respectively. The DATA terminal of the master serial interface circuit 1 is connected to the DATA terminals of the slave serial interface circuits 2 to 5 to input / output serial data signals.

  The data format of the serial data signal input / output at the DATA terminal has the following configuration, and the data length is matched between the master serial interface circuit 1 and the slave serial interface circuits 2 to 5 in advance.

  (1) Start signal, (2) Device selection signal, (3) I / O signal, (4) Address signal, (5) Data signal

  Here, the start signal (1) is for storing the data signal in the shift register for the data length with the signal as a cue when waiting for data reception on the slave side or the master side. The device selection signal (2) is information for designating individual numbers so that the slave device can be selected. The I / O signal (3) is information for indicating whether to write data to the slave side or to read data on the slave side. The address signal (4) is an address corresponding to the memory address on the slave side. The data signal (5) is data information for the slave address. The devices on the slave side, that is, the slave serial interface circuits 2 to 5 individually have device selection numbers. In the state where the slave side receives the start signal, data is stored in the shift register with the start signal as a cue, and only the data of the device having the number matching the device selection signal is valid.

JP 2008-040575 A (FIG. 1)

  The following analysis was made by the present inventors.

  In the technique described in Patent Document 1, a serial data signal having a communication data format including a device selection signal is used. At this time, each time the master device (master serial interface circuit 1 in FIG. 7) performs one data communication, the device selection signal of the slave device (slave serial interface circuits 2 to 5 in FIG. 7) is a DATA terminal. Need to send from. Therefore, there is a problem that overhead during communication occurs and the speed of serial data communication decreases.

  Accordingly, when serial data communication is performed between a master device and a plurality of slave devices, it is a problem to reduce communication overhead that occurs when a slave device to be communicated is specified.

The clock synchronous serial communication device according to the first aspect of the present invention is:
A master device that adjusts the frequency of the clock signal and outputs a clock signal and a data signal with the adjusted frequency,
A plurality of slave devices that receive the clock signal and data signal output from the master device and measure the frequency of the received clock signal,
Each of the plurality of slave devices holds an identification frequency, and holds or discards a data signal output from the master device depending on whether the measured frequency matches the identification frequency. .

The communication control method according to the second aspect of the present invention is:
The master device adjusts the frequency of the clock signal and outputs the clock signal and the data signal with the adjusted frequency;
A plurality of slave devices each holding a frequency for identification, receiving the clock signal and data signal output from the master device, and measuring the frequency of the received clock signal;
The plurality of slave devices holding or discarding the data signal output from the master device according to whether the measured frequency matches the identification frequency.

  According to the clock synchronous serial communication device and the communication control method thereof according to the present invention, when a master device and a plurality of slave devices perform serial data communication, it is possible to reduce communication overhead that occurs when a slave device to be communicated is specified. Can do.

It is a block diagram which shows the structure of the clock synchronous serial communication apparatus which concerns on embodiment. It is a block diagram which shows the structure of the communication operation determination part of the clock synchronous serial communication apparatus which concerns on embodiment. It is a flowchart which shows operation | movement of the communication operation determination part of the clock synchronous serial communication apparatus which concerns on embodiment. It is a state transition diagram of a slave device having a communication operation determination unit of the clock synchronous serial communication device according to the embodiment. It is a serial data format in the communication operation example in the embodiment. It is a flowchart which shows operation | movement of a master device at the time of communicating with the slave device which has a communication operation determination part of the clock synchronous serial communication apparatus which concerns on embodiment. 10 is a block diagram showing a configuration of a serial data transfer device described in Patent Document 1. FIG.

  First, the outline of the present invention will be described. Note that the reference numerals of the drawings attached to this summary are merely examples for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  Referring to FIG. 1, the present invention relates to a clock synchronous serial communication apparatus (300). In a system in which a master device (301) and a plurality of slave devices (302 to 304) perform serial data communication, a slave device (302 To 304) each have a communication operation determination unit (202 to 204). The communication operation determination unit (202 to 204) measures the communication clock frequency between the master device (301) and the slave device (302 to 304). According to the measured frequency, a slave device to be communicated is specified.

  According to the present invention, by designating the slave device to be communicated by the clock frequency, the communication overhead generated when the slave device to be communicated is designated can be reduced, and the serial data communication can be speeded up.

  Referring to FIG. 1, the clock synchronous serial communication device (300) adjusts the frequency of the clock signal and outputs the clock signal and the data signal with the adjusted frequency, and the master device (301) that is output from the master device. A plurality of slave devices (302 to 304) that receive the clock signal (CLK) and the data signal (DATA) and measure the frequency of the received clock signal, and each of the plurality of slave devices (302 to 304) Preferably, the identification frequency is held, and the data signal output from the master device (301) is preferably held or discarded depending on whether the measured frequency matches the identification frequency.

  The plurality of slave devices (302 to 304) hold the data signal output from the master device (301) when the measured frequency and the identification frequency match, and when the frequency does not match. Preferably discards the data signal output from the master device (301).

  Further, referring to FIG. 4, each of the plurality of slave devices (302 to 304) holds the maximum frequency of the clock signal output from the master device (301) and holds the data signal output from the master device (301). The first state (S0) to be performed and the second state (S1) to discard the data signal output from the master device, and the first frequency when the measured frequency matches the identification frequency When the state transitions to the state (S0) and the measured frequency matches the maximum frequency, the first state (S0) or the second state (S1) is maintained, otherwise the second state You may make it change to a state (S1).

  The master device (301) has a clock signal that matches either the identification frequency held by each of the plurality of slave devices (302 to 304) or the maximum frequency of the clock signal output by the master device (301). It is preferable to adjust the frequency.

  Referring to FIG. 2, each of the plurality of slave devices (302 to 304) includes an edge detection unit (402) that detects an edge of the clock signal (CLK) output from the master device (301), and an edge detection unit (402). ) By using a notification indicating that an edge has been detected as a trigger, a period measuring unit (403) that measures a period until the next edge of the clock signal output from the master device (301) is detected, and a period measuring unit The frequency of the clock signal (CLK) output from the master device (301) is obtained based on the period measured in (403), and the obtained frequency and the frequency for identification or the maximum of the clock signal output from the master device (301) are obtained. It is preferable to include a frequency comparison unit (406) that compares the frequency.

  According to the clock synchronous serial communication device of the present invention, when a master device and a plurality of slave devices perform serial data communication, it is possible to reduce communication overhead that occurs when a slave device to be communicated is designated.

(Embodiment)
A clock synchronous serial communication device according to an embodiment will be described with reference to the drawings. FIG. 1 is a block diagram illustrating an example of the configuration of the clock synchronous serial communication device according to the present embodiment.

  Referring to FIG. 1, a clock synchronous serial communication apparatus 300 includes a master device 301 and slave devices 302 to 304.

  The slave devices 302 to 304 have communication operation determination units 202 to 204, respectively.

  The master device 301 outputs a serial clock signal CLK to the slave devices 302 to 304, and the slave devices 302 to 304 receive the clock signal CLK as a serial clock. Further, the master device 301 performs data communication (transmission / reception) with the slave devices 302 to 304 using the serial data signal DATA.

  FIG. 2 is a block diagram illustrating a configuration of the communication operation determination unit 202 provided in the slave device 302 of the clock synchronous serial communication device 300 according to the present embodiment. Note that the configuration of the communication operation determination units 203 and 204 is the same as the configuration of the communication operation determination unit 202, and thus illustration is omitted.

  Referring to FIG. 2, the communication operation determination unit 202 includes an edge detection unit 402, a period measurement unit 403, an identification frequency holding unit 404, a maximum communication frequency holding unit 405, and a frequency comparison unit 406.

  The edge detection unit 402 receives the serial clock signal CLK output from the master device 301 and detects a rising (or falling) edge of the serial clock signal CLK. When detecting the clock edge, the edge detection unit 402 notifies the period measurement unit 403 that the clock edge has been detected.

  The period measurement unit 403 starts time measurement based on the notification from the edge detection unit 402 (trigger), and outputs the period until the notification from the edge detection unit 402 is received again to the frequency comparison unit 406.

  The identification frequency holding unit 404 holds a unique communication frequency (identification frequency) for identifying that it is designated as a communication target from the master device 301, and outputs the held frequency to the frequency comparison unit 406.

  The maximum communication frequency holding unit 405 holds the maximum communication clock frequency output from the master device, and outputs the held frequency to the frequency comparison unit 406.

  The frequency comparison unit 406 receives a period corresponding to the clock edge interval output from the period measurement unit 403, an identification frequency held by the identification frequency holding unit 404, and a maximum communication frequency held by the maximum communication frequency holding unit 405. And Further, the frequency comparison unit 406 calculates a frequency from the period output from the period measurement unit 403, determines a match with the identification frequency, and outputs a determination result to the slave device 302 having the communication operation determination unit 202.

  FIG. 3 is a flowchart showing the operation of the communication operation determination unit 202. With reference to FIG. 3, the operation of the communication operation determination unit 202 shown in FIG. 2 will be described.

  The edge detection unit 402 determines whether the rising (or falling) edge of the serial clock signal CLK output from the master device 301 has been detected (step S501). If the edge of the serial clock signal CLK is detected (Yes in step S501), the edge detecting unit 402 proceeds to step S502, and if not detected (No in step S501), the edge detecting unit 402 returns to step S501 and clocks. Edge detection is performed.

  When the period measurement unit 403 detects the edge of the serial clock signal CLK (Yes in step S501), the period measurement unit 403 starts time measurement and the period until the edge detection unit 402 detects the edge of the serial clock signal CLK again. Is held (step S502).

  The edge detection unit 402 determines whether or not the rising (or falling) edge of the next serial clock signal CLK output from the master device 301 has been detected (step S503). If the edge of the serial clock signal CLK is detected (Yes in step S503), the edge detecting unit 402 proceeds to step S504, and if not detected (No in step S503), the edge detecting unit 402 returns to step S503 and clocks. Edge detection is performed.

  The frequency comparison unit 406 calculates a frequency from the period measured by the period measurement unit 403 and compares whether the value held by the identification frequency holding unit 404 or the value held by the maximum communication frequency holding unit 405 matches. (Step S504). If the frequency matches the identification frequency, the process proceeds to step S505. If the frequency matches the maximum communication frequency, the process proceeds to step S506. Otherwise, the process proceeds to step S507.

  If the value matches the value held by the identification frequency holding unit 404, it is determined to be in the “reception permitted” state, and the process ends (step S505).

  On the other hand, when the value matches the value held by the maximum communication frequency holding unit 405, it is determined that the state is the “hold” state, and the process ends (step S506).

  If it does not match either the value held by the identification frequency holding unit 404 or the value held by the maximum communication frequency holding unit 405, it is determined that the state is “reception prohibited” and the process is terminated (step S507). ).

  FIG. 4 is a state transition diagram of the slave devices 302 to 304 having the communication operation determination unit 202. Referring to FIG. 4, each of the slave devices 302 to 304 has a “reception permitted” state (S0) and a “reception prohibited” state (S1).

  As illustrated in FIG. 4, the slave devices 302 to 304 including the communication operation determination units 202 to 204 hold or discard received data according to the determination results of the communication operation determination units 202 to 204. The operation of the slave device 302 will be described below, but the operation of the slave devices 303 and 304 is the same.

  If the determination result of the communication operation determination unit 202 is “reception permitted”, the slave device 302 holds the received data (step S704).

  On the other hand, if the determination result of the communication operation determination unit 202 is “reception prohibited”, the slave device 302 discards the received data (step S702).

  When the determination result of the communication operation determination unit 202 is “pending”, the determination result of the previous communication operation determination unit 202 that is finally determined as “reception permitted” or “reception prohibited” is taken over. . That is, when it is finally determined “reception permitted”, the received data is retained (step S701), and when it is finally determined “reception prohibited”, the received data is discarded (step S703).

  FIG. 1 shows a case where three slave devices 302 to 304 are connected to a master device 301 as an example. A specific example of the communication operation in the present embodiment will be described with reference to FIG.

  The communication clock frequency set in FIG. 1 is as follows. The maximum communication clock frequency that can be output by the master device 301 is 10 MHz. The identification frequency of each slave device 302 to 304 is 8 MHz for the slave device 302, 7 MHz for the slave device 303, and 6 MHz for the slave device 304. Furthermore, the maximum communication frequency holding unit 405 of each slave device 302 to 304 is 10 MHz, the identification frequency holding unit 404 of the slave device 302 is 8 MHz, the identification frequency holding unit 404 of the slave device 303 is 7 MHz, and the slave device 304 is identified. It is assumed that 6 MHz is set in each frequency holding unit 404. The master device 301 outputs data based on the serial data format shown in FIG.

  FIG. 6 is a flowchart illustrating an example of the operation of the master device 301 when communicating with the slave devices 302 to 304 having the communication operation determination units 202 to 204 according to the present embodiment. Here, the operations of the master device 301 and the slave devices 302 to 304 will be described by taking as an example a case where 4-byte data communication is performed from the master device 301 to the slave devices 302 to 304.

  The master device 301 sets the communication clock to 8 MHz (step S901).

  The master device 301 transfers the first byte data to the slave devices 302 to 304 (step S902).

  The master device 301 sets the communication clock to 10 MHz that is the maximum communication frequency (step S903).

  The master device 301 transfers the second byte data to the slave devices 302 to 304 (step S904).

  The master device 301 transfers the third byte data to the slave devices 302 to 304 (step S905).

  The master device 301 transfers the fourth byte data to the slave devices 302 to 304 (step S906).

  Next, the operation of the slave device 302 will be described with reference to FIG.

  The slave device 302 receives the first byte data, and simultaneously measures the edge interval of the serial clock signal CLK output from the master device 301 by the communication operation determination unit 202 of the slave device 302 (steps S501 to S503). It is determined whether or not the obtained frequency matches the identification frequency or the maximum communication frequency (step S504).

  Since the communication operation determination unit 202 of the slave device 302 compares the frequency (step S504) and is determined to be in the “reception permitted” state (step S505), the slave device 302 receives the received data (first byte data). Hold.

  The slave device 302 receives the second byte data, and simultaneously measures the edge interval of the serial clock signal CLK output from the master device 301 by the communication operation determination unit 202 of the slave device 302 (steps S501 to S503). It is determined whether or not the obtained frequency matches the identification frequency or the maximum communication frequency (step S504).

  As a result of comparing the frequencies (step S504) by the communication operation determination unit 202 of the slave device 302, it is determined to be in the “pending” state (step S506), so the slave device 302 holds the received data (second byte data). To do.

  As the operation of the slave device 302 at the time of receiving the data of the third byte and the fourth byte, the slave device 302 holds the received data similarly to the operation at the time of receiving data of the second byte.

  Next, the operation of the slave device 303 will be described.

  The slave device 303 receives the first byte data, and simultaneously measures the edge interval of the serial clock signal CLK output from the master device 301 by the communication operation determination unit 202 of the slave device 303 (steps S501 to S503). It is determined whether or not the obtained frequency matches the identification frequency or the maximum communication frequency (step S504).

  Since the communication operation determination unit 202 of the slave device 303 compares the frequency (step S504) and is determined to be in the “reception prohibited” state (step S507), the slave device 303 receives the reception data (first byte data). Discard.

  The slave device 303 receives the second byte data, and simultaneously measures the edge interval of the serial clock signal CLK output from the master device 301 by the communication operation determination unit 202 of the slave device 303 (steps S501 to S503). It is determined whether or not the obtained frequency matches the identification frequency or the maximum communication frequency (step S504).

  As a result of comparing the frequencies (step S504) by the communication operation determination unit 202 of the slave device 303 (step S506), the slave device 303 discards the received data (second byte data) because it is determined to be in the “pending” state (step S506). To do.

  As an operation of the slave device 303 at the time of receiving the data of the third byte and the fourth byte, the slave device 303 discards the received data similarly to the operation at the time of receiving the data of the second byte.

  The operation of the slave device 304 is the same as that of the slave device 303.

  In this embodiment, by designating the slave device to be communicated by the clock frequency, the communication overhead generated when the slave device to be communicated in the technique described in Patent Document 1 can be reduced, and serial data communication Can be speeded up.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 Master serial interface circuit 2-5 Slave serial interface circuit 202-204 Communication operation determination part 300 Clock synchronous serial communication apparatus 301 Master device 302-304 Slave device 402 Edge detection part 403 Period measurement part 404 Identification frequency holding | maintenance part 405 Maximum communication frequency Holding unit 406 Frequency comparison unit CLK Serial clock signal DATA Serial data signal S0, S1 state

Claims (10)

A master device that adjusts the frequency of the clock signal and outputs a clock signal and a data signal with the adjusted frequency,
A plurality of slave devices that receive the clock signal and data signal output from the master device and measure the frequency of the received clock signal,
Each of the plurality of slave devices holds an identification frequency, and holds or discards a data signal output from the master device depending on whether the measured frequency matches the identification frequency. A clock-synchronous serial communication device.   Each of the plurality of slave devices holds the data signal output from the master device when the measured frequency matches the identification frequency, and the data output from the master device when the frequency does not match. 2. The clock synchronous serial communication device according to claim 1, wherein the signal is discarded.   Each of the plurality of slave devices holds a maximum frequency of a clock signal output from the master device, a first state holding a data signal output from the master device, and a data signal output from the master device. A second state to be discarded, and when the measured frequency and the identification frequency match, transition to the first state, and when the measured frequency and the maximum frequency match, 3. The clock synchronous serial communication device according to claim 1, wherein the first state or the second state is maintained, and transition to the second state is performed in other cases.   The master device adjusts the frequency of the clock signal so as to match either the identification frequency held by each of the plurality of slave devices or the maximum frequency of the clock signal output from the master device. The clock synchronous serial communication device according to any one of claims 1 to 3. Each of the plurality of slave devices is
An edge detection unit for detecting an edge of the clock signal output from the master device;
A period measurement unit that measures a period until a next edge of a clock signal output from the master device is detected, using a notification indicating that an edge is detected by the edge detection unit as a trigger;
Based on the period measured by the period measurement unit, the frequency of the clock signal output from the master device is obtained, and the obtained frequency is compared with the identification frequency or the maximum frequency of the clock signal output from the master device. 5. The clock synchronous serial communication device according to claim 1, further comprising a comparison unit. The master device adjusts the frequency of the clock signal and outputs the clock signal and the data signal with the adjusted frequency;
A plurality of slave devices each holding a frequency for identification, receiving the clock signal and data signal output from the master device, and measuring the frequency of the received clock signal;
A step of holding or discarding a data signal output from the master device according to whether or not the measured frequency and the identification frequency match, the plurality of slave devices. Communication control method. A step of holding the data signal output from the master device when the plurality of slave devices match the measured frequency and the identification frequency;
The communication control method according to claim 6, further comprising a step of discarding the data signal output from the master device when they do not match. The plurality of slave devices, when the measured frequency and the identification frequency match, a transition to a first state in which the data signal output from the master device is held;
When the measured frequency matches the maximum frequency of the clock signal output from the master device, maintaining the first state or the second state in which the data signal output from the master device is discarded;
The communication control method according to claim 6, further comprising a step of transitioning to the second state in cases other than these.   Adjusting the frequency of the clock signal so that the master device matches either the identification frequency held by each of the plurality of slave devices or the maximum frequency of the clock signal output by the master device. The communication control method according to any one of claims 6 to 8, wherein The plurality of slave devices detecting edges of a clock signal output from the master device;
Triggering a notification indicating that an edge has been detected as a trigger, measuring a period until the next edge of the clock signal output from the master device is detected, and
Obtaining a frequency of a clock signal output from the master device based on a measured period;
The communication control method according to claim 6, further comprising a step of comparing the obtained frequency with a frequency for identification or a maximum frequency of a clock signal output from the master device. .

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