JP2012160019A - Information processor and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve an information processor and a control method for controlling the generation timing of a power-down signal and a reset signal without using a controller which supports the output of a power-down signal.SOLUTION: An EC 120 includes: a power-down signal LPC PD# generation function and a reset signal LPC Reset# generation function. In warm reset, the power-down signal LPC PD# and the reset signal LPC Reset# are set to an active state by the EC 120 under the control of a BIOS. When an operation state is restored, the power-down signal LPC PD# and the reset signal LPC Reset# are set to an inactive state under the control of the EC 120.

Description

  Embodiments described herein relate generally to an information processing apparatus such as a personal computer and a control method applied to the apparatus.

  In recent years, information processing apparatuses such as personal computers use various types of buses such as a peripheral component interconnect (PCI) bus and a low pin count (LPC) bus. Depending on the bus standard, not only a signal group that needs to be supported as standard, but also some optional signals that need to be supported only when necessary. For example, in the LPC bus standard, a power down signal is defined as one of the option signals. The power down signal is a signal used to instruct peripheral devices on the LPC bus to prepare for power off. For example, a peripheral device that needs to execute a predetermined process before being powered off requires input of a power-down signal.

  Typically, the LPC bus is used for interconnection between the controller (chipset) and peripheral devices. However, the number of controllers having an option signal output function such as a power down signal is limited to some products at present, and many controllers do not support the output of a power down signal.

  In a system configuration that uses a controller that does not support the output of a power-down signal, it is difficult to properly operate the functions of peripheral devices that require the input of the power-down signal. For this reason, in a computer equipped with a controller that does not support output of a power-down signal, such peripheral devices are not supported.

  In a system configuration that uses a chipset that does not support power-down signal output, control the generation timing of the power-down signal separately from the chipset so that peripheral devices that require power-down signal input can be supported. A new function has been disclosed (see, for example, Patent Document 1).

JP 2010-262659 A

  However, in Patent Document 1, the power down signal is asserted / deasserted by using a power saving state transition request signal issued from the south bridge to the embedded controller as a trigger. Therefore, if the information processing apparatus is not shifted to the power saving state, peripheral devices that require the input of a power down signal cannot be supported, for example, during a warm reset.

  An object of the present invention is to provide an information processing apparatus and a control method capable of controlling the generation timing of a power-down signal and a reset signal without using a controller that supports output of the power-down signal.

  According to the embodiment, the information processing apparatus executes a non-volatile memory that stores a system program that generates a reset request signal in response to receiving a reset operation request from the operating system, and the operating system and the system program. Connected to the peripheral device via a bus including at least a data line, and in response to receiving the reset request signal from the system program, a power-down signal and a reset signal are activated for the peripheral device. And a controller that sets the power-down signal to an inactive state when detecting an inactive state of the reset signal after resetting the peripheral device.

  Further, according to the embodiment, the control method controls the operation of an information processing apparatus including a peripheral device connected to a bus including at least a data line and a controller that controls the peripheral device via the bus. A power down signal and a reset signal are set to an active state in response to receiving a request for a reset operation from the operating system, the controller detects an inactive state of the reset signal, and the reset signal When the inactive state is detected, the power down signal is set to the inactive state.

1 is a perspective view showing an appearance of an information processing apparatus according to an embodiment of the present invention. 2 is an exemplary block diagram showing the system configuration of the information processing apparatus of the embodiment. FIG. 6 is a timing chart for explaining a reset signal control operation executed by the information processing apparatus of the embodiment. 6 is an exemplary flowchart illustrating a procedure of a warm reset process which is executed by the information processing apparatus of the embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the configuration of an information processing apparatus according to an embodiment of the present invention will be described with reference to FIG. This information processing apparatus is realized as, for example, a battery-driven portable notebook personal computer 10. FIG. 1 is a perspective view of the computer 10 viewed from the front side with the display unit opened. The computer 10 includes a computer main body 11 and a display unit 12. The display unit 12 incorporates a display device composed of an LCD 16 (Liquid Crystal Display).

  The display unit 12 is supported by the computer main body 11 and rotates between an open position where the upper surface of the computer main body 11 is exposed to the computer main body 11 and a closed position where the upper surface of the computer main body 11 is covered by the display unit 12. Mounted freely. The computer main body 11 has a thin box-shaped housing, and a keyboard 13, a touch pad 15, and a power button 14 for powering on / off the computer 10 are disposed on the upper surface of the computer main body 11.

  The computer 10 has an operation state and a power saving state. The power saving state is a state in which almost all devices other than a specific device such as a main memory are turned off.

  FIG. 2 shows the system configuration of the computer 10. The computer 10 is connected to a CPU 111, a north bridge 112, a main memory 113, a graphics controller 114, a south bridge 115, a hard disk drive (HDD) 116, an I / O device 117 connected to the PCI bus, a BIOS-ROM 118, and an LPC bus. LPC device 119, embedded controller (EC) 120, power supply circuit 121, and the like.

  The CPU 111 is a processor that controls the operation of each component of the computer 10. The CPU 111 executes various software loaded from the HDD 116 to the main memory 113, such as an operating system (OS) and application programs. The CPU 111 also executes a BIOS (basic input output system) stored in the BIOS-ROM 118 which is a nonvolatile memory. The BIOS is a system program for hardware control.

  The BIOS has a function for executing the warm reset function of the computer 10 and is connected without causing the system state of the computer 10 to transition in cooperation with the embedded controller (EC) 120. Perform device reset processing. The BIOS also has a function of controlling the generation timing of the power down signal LPC PD # and the reset signal LPC Reset # required by the LPC device 119 in cooperation with the embedded controller (EC) 120.

  The power down signal LPC PD # indicates that the LPC device 119 should be prepared for power off. The power down signal LPC PD # is a low active signal. A reset signal LPC Reset # indicates reset of the LPC device 119. The reset signal LPC Reset # is a low active signal.

  The north bridge 112 is a bridge device that connects the local bus of the CPU 111 and the south bridge 115. The north bridge 112 also has a function of executing communication with the graphics controller 114. Further, the north bridge 112 also includes a memory controller that controls the main memory 113. The graphics controller 114 is a display controller that controls the LCD 16 used as a display monitor of the computer 10.

  The south bridge 115 is connected to a Peripheral Component Interconnect (PCI) bus and a Low Pin Count (LPC) bus. The LPC bus includes at least a data line and a reset signal line. The data line is composed of a 4-bit command / address / data signal line. The LPC bus further includes a frame signal line. The command / address / data signal line is a bus for transmitting multiplexed commands, addresses and data. The frame signal line is used for transmission of a frame signal for indicating the start and end of a bus cycle. The reset signal line is used to transmit a reset signal LPC Reset # for resetting the LPC device 119. The reset signal LPC Reset # is a low active signal.

  The south bridge 115 functions as a controller for controlling the LPC device 119 on the LPC bus. An LPC host controller 201 is provided in the south bridge 115. The LPC host controller 201 is configured to execute communication with the LPC device 119 via the LPC bus. The power down signal LPC PD # described above is an LPC bus option signal. In the present embodiment, a controller that does not support the output of the power down signal LPC PD # is used as the south bridge 115. That is, the LPC host controller 201 does not have a function of outputting the power down signal LPC PD #. Therefore, the LPC bus connecting the south bridge 115 and the LPC device 119 does not include the power down signal LPC PD #.

  The LPC device 119 is a device that requires input of the power-down signal LPC PD #, and executes a predetermined preparation process to prepare for power-off when the power-down signal LPC PD # is set to an active state. I can do it. As the LPC device 119, for example, a TPM (Trusted Platform Module) device for executing a security function is used. In this case, the LPC device 119 performs processing for encrypting predetermined data, processing for managing a key used for data encryption, and the like. When the power-down signal LPC PD # is set to the active state, the LPC device 119 executes a predetermined preparation process for preparing for power-off. In the preparation process, a process for stopping the internal operation of the LPC device 119 is executed. In the preparation process, for example, a process of saving internal data in, for example, a nonvolatile memory provided in the LPC device 119 may be executed. Thereby, even when the system state enters a power saving state such as the suspend state, it is possible to prevent the loss of necessary internal data (for example, a key or the like). Of course, the LPC device 119 that requires the input of the power down signal LPC PD # is not limited to the TPM device, and is configured to execute some processing in response to the power down signal LPC PD # from the host. Any device can be used.

  In the present embodiment, in order to support an LPC device 119 having an input pin for inputting a power down signal LPC PD #, that is, an LPC device 119 that requires input of the power down signal LPC PD #, The controller (EC) 120 has a function of controlling the generation of the power down signal LPC PD #.

  Further, in the present embodiment, a function for controlling the generation of the reset signal LPC Reset # is provided in the embedded controller (EC) 120 in order to cope with the warm reset.

  The LPC device 119 includes an input / output pin for inputting / outputting a command / address / data signal in a time division manner, an input pin for inputting a frame signal, an input pin for inputting a reset signal LPC Reset #, and a power down signal. An input pin for inputting LPC PD # is provided. Input / output pins and input pins for inputting a frame signal are connected to the south bridge 115 via the LPC bus. On the other hand, input pins for inputting the power down signal LPC PD # and the reset signal LPC Reset # are connected to the embedded controller (EC) 120 via the power down signal LPC PD # line and the reset signal LPC Reset # line, respectively. Has been.

  The embedded controller (EC) 120 is a controller including a function for executing power management of the computer, and is realized as a one-chip microcomputer incorporating a keyboard controller function for controlling the keyboard (KB) 13 and the touch pad 15. Yes. The EC 120 cooperates with the power supply circuit 121 to turn on / off the computer 10 in accordance with the operation of the power button switch 14 by the user. The power supply circuit 121 generates a system power supply to be supplied to each component of the computer 10 by using an external power supply supplied via the battery 122 built in the computer main body 11 or the AC adapter 123.

  The EC 120 is connected to the south bridge 115 via, for example, the above-described LPC bus. The EC 120 includes a power down signal generation unit 301 and a reset signal generation unit 302. The power down signal generator 301 is a circuit that drives the power down signal LPC PD # line to set the power down signal LPC PD # to an active state / inactive state. The reset signal generator 302 is a circuit that drives the reset signal LPC Reset # line to set the reset signal LPC Reset # to an active state / inactive state. The EC 120 has a register group that can be accessed by the CPU 111, and can communicate with the BIOS via the register group.

  Here, an outline of the warm reset function of the computer 10 will be described. The warm reset function is to reset peripheral devices such as the LPC device 119 while maintaining the system state of the computer 10 in the operating state. Compared to a cold reset and a cold start in which the power of the computer 10 is turned off, the warm reset omits checking of hardware such as a memory and the input information is not initialized, so that the startup is performed quickly.

  When receiving the warm reset request transmitted from the OS, the BIOS transmits a warm reset request command to the south bridge 115 to cause the south bridge 115 to prepare for the warm reset. The south bridge 115 executes a predetermined preparation process.

  At the same time, the BIOS sets the power down signal LPC PD # to the active state via the south bridge 115 and the EC 120 so that the LPC device 119 can be safely powered off. Thereafter, in order to reset the LPC device 119, the reset signal LPC Reset # is set to the active state.

  FIG. 3 is a timing chart illustrating a reset signal control operation executed by the information processing apparatus according to the embodiment. The warm reset process executed by the computer 10 will be described with reference to the timing chart of FIG.

  FIG. 3 shows a timing sequence when a warm reset is instructed. In FIG. 3, the symbol # added to the right of the signal name indicates that the signal is negative logic (low active). In the following description, assert means that a signal is set to an active state, and deassertion means that a signal is set to an inactive state.

First, the procedure until the LPC device 119 is powered off from the normal operation state will be described.
(1) The BIOS receives a warm reset request from the OS at the timing of T1, and transmits a power down signal generation command to the EC 120.
(2) The EC 120 asserts the power down signal LPC PD # for the LPC device 119 at the timing of T2 (LPC PD # = low level).
(3) When receiving the warm reset request command from the BIOS at the timing of T3, the LPC host controller 201 asserts a reset signal LPC Reset # (SB) signal to the EC 201 (reset signal LPC Reset # (SB) = Low level).

  (4) The EC 201 asserts the reset signal LPC Reset # (EC) signal to the LPC device 119 at the timing of T4 (reset signal LPC Reset # (EC) = low level). When the power down signal LPC PD # and the reset signal LPC Reset # signal are both set to a low level, the LPC device 119 is powered off.

Next, the procedure will be described until the LPC device 119 is raised from the power-off state to the normal operation state again.
(5) The EC 201 detects deassertion of the reset signal LPC Reset # (SB) signal at the timing of T5.
(6) The EC 201 deasserts the power down signal LPC PD # to the LPC device 119 at the timing of T6.
(7) The EC 201 deasserts the reset signal LPC Reset # (EC) signal to the LPC device 119 at the timing of T7.
FIG. 4 is a flowchart for explaining the procedure of the warm reset process executed by the information processing apparatus of the embodiment. With reference to the flowchart of FIG. 4, the procedure of the control process executed during the warm reset process will be described.

  First, when a warm reset request event occurs due to a user operation or the like, the OS transmits a warm reset request to the BIOS, and the BIOS transmits a power down signal generation command to the EC 120 to the EC 201 (at T1 in FIG. 3). Corresponding to timing) (step S11). Thereafter, the EC 201 asserts a power down signal LPC PD # to the LPC device 119. (Corresponding to the timing of T2 in FIG. 3) (step S12).

  Next, when receiving a warm reset request command from the BIOS, the LPC host controller 201 asserts a reset signal LPC Reset # (SB) to the EC 120 (corresponding to the timing of T3 in FIG. 3) (step S13). Next, the EC 120 asserts a reset signal LPC Reset # (EC) to the LPC device 119 (corresponding to the timing of T4 in FIG. 3) (step S14).

  Next, the EC 120 detects deassertion of the reset signal LPC Reset # (SB) (corresponding to the timing of T5 in FIG. 3) (step S15). The EC 120 deasserts the power down signal LPC PD # to the LPC device 119 (corresponding to the timing of T6 in FIG. 3) (step S16). The EC 120 deasserts the reset signal LPC Reset # (EC) to the LPC device 119 (corresponding to the timing of T7 in FIG. 3) (step S17).

  As described above, in the present embodiment, the EC 120 is provided with the function of generating the power down signal LPC PD # and the reset signal LPC Reset #, so that the warm reset can be performed without using a controller that supports the output of the power down signal. It can correspond to.

  Note that the timing for deasserting the reset signal LPC Reset # (EC) and the reset signal LPC Reset # (SB) is shifted, but there is sufficient time until the BIOS starts operating after the reset and the LPC device operates. The warm reset process will not be hindered.

  In the present embodiment, the control of the power down signal LPC PD # of the LPC bus has been described. However, the power down signal generation control function of the present embodiment is applied to an arbitrary bus in which the power down signal is defined as an option signal. It can be applied to.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 10 ... Information processing apparatus, 111 ... CPU, 115 ... South bridge, 119 ... LPC device, 120 ... EC.

Claims (7)

A non-volatile memory for storing a system program for generating a reset request signal in response to receiving a reset operation request from the operating system;
A processor for executing the operating system and the system program;
A power-down signal and a reset signal are connected to the peripheral device via a bus including at least a data line and a reset signal line, and to the peripheral device in response to the reset request signal from a system program executed by the processor A controller that switches between an active state and an inactive state;
An information processing apparatus.   2. The information processing according to claim 1, wherein the peripheral device includes a first input pin for inputting the power-down signal, and the first input pin is connected to the controller via a first signal line. apparatus.   The information processing apparatus according to claim 1, wherein the peripheral device includes a second input pin for inputting the reset signal, and the second input pin is connected to the controller via a second signal line.   The information processing apparatus according to claim 1, wherein the reset request is a reset request that does not change an operation state of the information processing apparatus.   The information processing apparatus according to claim 1, wherein the power-down signal is a signal for notifying the peripheral device that the power-off signal should be prepared.   The information processing apparatus according to claim 1, wherein the reset signal is a signal for notifying the peripheral device of an operation stop. A control method for controlling an operation of an information processing apparatus including a peripheral device connected to a bus including at least a data line, and a controller for controlling the peripheral device via the bus,
In response to receiving the reset operation request from the operating system, the power down signal and the reset signal are set to the active state.
Detecting an inactive state of the reset signal by the controller;
A control method for setting the power down signal to an inactive state when an inactive state of the reset signal is detected.

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