JP2012027199A - Optical semiconductor device and method for driving the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical semiconductor device having excellent high-frequency characteristics, and to provide a method for driving the same.SOLUTION: The optical semiconductor device includes: a first optical waveguide 18a which is a part of an intrinsic semiconductor layer 14; a second optical waveguide 18b formed in the first side of the first optical waveguide; first impurity regions 19 and 20 of a first conductive type formed in the second side of the first optical waveguide; a second impurity region 21 of a second conductive type formed in the first side of the first optical waveguide; a third impurity region 22 of the first conductive type formed in the second side of the second optical waveguide; fourth impurity regions 23 and 24 of the second conductive type formed in the first side of the second optical waveguide; a first capacitor 32a having a first lower electrode which is a part of the second impurity region, and a first upper electrode 30a; a fifth impurity region 25 of the second conductive type formed in the lower part of the first upper electrode; a second capacitor 32b having a second lower electrode which is a part of the fourth impurity regions, and a second upper electrode 30b; and a sixth impurity region 26 of the first conductive type formed in the lower part of the second upper electrode.

Description

  The present invention relates to an optical semiconductor device and a driving method thereof.

  Recently, optical phase shifters and Mach-Zehnder type optical modulators using silicon materials have been proposed (Non-Patent Documents 1 to 4).

  The Mach-Zehnder type optical modulator is an optical modulator that turns light on and off according to interference conditions when the light is split into two and multiplexed again.

  In the proposed technique, a P-type semiconductor layer is provided on one side of an I-type optical waveguide, and an N-type semiconductor layer is provided on the other side of the I-type optical waveguide, and a PIN structure is provided. (PIN diode) is used.

  When a forward bias is applied to such a PIN structure, carriers are injected into the optical waveguide. When carriers are injected into the optical waveguide, a carrier plasma effect occurs in the optical waveguide, and the refractive index of light in the optical waveguide changes. When the refractive index of light in the optical waveguide changes, the wavelength of the light traveling through the optical waveguide changes, so that the phase of the light can be changed in the course of traveling through the optical waveguide.

S.J.Spector et al., “CMOS-compatible dual-output silicon modulator for analog signal processing”, Optics Express, Vol. 16, No. 15, pp. 11027-11031 (2008) William M. J. Green et al., “Ultra-compact, low RF power, 10 Gb / s silicon Mach-Zehnder modulator”, Optics Express, Vol. 15, No. 25, pp. 17106-17113 (2007) F. Gan et al., “Compact, Low-Power, High-Speed Silicon Electro-Optic Modulator”, Conference on Laser and Electro-optics 2007, CTuQ6 (2007) S.J.Spector et al., “Compact Carrier Injection Based Mach-Zehnder Modulator in Silicon”, OSA / IPNRA 2007, ITuE5 (2007)

  However, in the proposed technology, since the capacitance of the PIN diode is relatively large, the CR time constant is large, and it is not always possible to obtain good high frequency characteristics.

  An object of the present invention is to provide an optical semiconductor device having good high-frequency characteristics and a method for manufacturing the same.

  According to one aspect of the embodiment, an intrinsic semiconductor layer formed on a substrate, a first optical waveguide that is a part of the semiconductor layer, and another part of the semiconductor layer, A second optical waveguide formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide; and a second optical waveguide opposite to the first side of the first optical waveguide. A first impurity region formed in the semiconductor layer on the side and doped with an impurity of a first conductivity type; and formed in the semiconductor layer on the first side of the first optical waveguide; A second impurity region into which a second conductivity type impurity opposite to the first impurity region is introduced, and the semiconductor layer on the second side of the second optical waveguide, wherein the first conductivity type impurity is introduced, A third impurity region connected to the second impurity region, and the second optical waveguide A fourth impurity region formed in the semiconductor layer on the first side and doped with an impurity of a second conductivity type; a first lower electrode which is a part of the second impurity region; and at least the first A first capacitor having a first insulating film formed on the lower electrode and a first upper electrode formed on the first insulating film; and a region under the first upper electrode. A fifth impurity region formed in a part of the semiconductor layer and doped with a second conductivity type impurity; a second lower electrode which is a part of the fourth impurity region; and at least the second A second capacitor having a second insulating film formed on the lower electrode and a second upper electrode formed on the second insulating film; and a region under the second upper electrode. Formed in the semiconductor layer in the first portion and introduced with a first conductivity type impurity An optical semiconductor device is provided having 6 an impurity region of.

  According to another aspect of the embodiment, an intrinsic semiconductor layer formed on a substrate, a first optical waveguide that is a part of the semiconductor layer, and another part of the semiconductor layer, A second optical waveguide formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide; and a second optical waveguide opposite to the first side of the first optical waveguide. A first impurity region formed in the semiconductor layer on the first side and doped with an impurity of a first conductivity type; and formed in the semiconductor layer on the first side of the first optical waveguide, A second impurity region doped with an impurity of a second conductivity type opposite to the mold and the semiconductor layer on the second side of the second optical waveguide, and the impurity of the first conductivity type is introduced; , A third impurity region connected to the second impurity region, and the front of the second optical waveguide A fourth impurity region formed in the semiconductor layer on the first side and doped with an impurity of a second conductivity type; a first lower electrode which is a part of the first impurity region; and at least the first A first capacitor having a first insulating film formed on the first lower electrode; a first upper electrode formed on the first insulating film; and the first capacitor of the first lower electrode. A fifth impurity region formed in the semiconductor layer on the second side and doped with a first conductivity type impurity at an impurity concentration lower than that of the first impurity region; and a part of the fourth impurity region. A second capacitor having a second lower electrode, at least a second insulating film formed on the second lower electrode, and a second upper electrode formed on the second insulating film; Forming the semiconductor layer on the first side of the second lower electrode. Is, the optical semiconductor device is provided having a sixth impurity region of the fourth of the second conductivity type with a lower impurity concentration than the impurity regions of the impurity is introduced.

  According to still another aspect of the embodiment, an intrinsic semiconductor semiconductor layer formed on a substrate; a first optical waveguide that is part of the semiconductor layer; and another part of the semiconductor layer; A second optical waveguide formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide; and a second optical waveguide opposite to the first side of the first optical waveguide; A first impurity region formed in the semiconductor layer on the second side and doped with an impurity of a first conductivity type; formed in the semiconductor layer on the first side of the first optical waveguide; A second impurity region doped with an impurity of a second conductivity type opposite to the conductivity type; and formed in the semiconductor layer on the second side of the second optical waveguide, wherein the impurity of the first conductivity type is introduced A third impurity region connected to the second impurity region; and the second optical waveguide A fourth impurity region formed in the semiconductor layer on the first side and doped with an impurity of a second conductivity type; a first lower electrode that is part of the second impurity region; and at least the A first capacitor having a first insulating film formed on the first lower electrode and a first upper electrode formed on the first insulating film; below the first upper electrode A fifth impurity region formed in the semiconductor layer in a part of the region and doped with an impurity of the second conductivity type; a second lower electrode which is a part of the fourth impurity region; and at least the first A second capacitor having a second insulating film formed on the second lower electrode and a second upper electrode formed on the second insulating film; a region below the second upper electrode Formed in the semiconductor layer in a part of the first conductivity type impurity introduced The sixth impurity region, the first electrode connected to the first impurity region on the second side of the fifth impurity region, the second impurity region and the third impurity A method for driving an optical semiconductor device, comprising: a second electrode connected to a region; and a third electrode connected to the fourth impurity region on the first side of the sixth impurity region. , Connecting the first electrode to a first potential, connecting the third electrode to a second potential lower than the first potential, and lowering the first upper electrode below the first potential. , Connected to a third potential higher than the second potential, and connected the second upper electrode to a fourth potential lower than the third potential and higher than the second potential, Apply an input signal that changes within a range below the fourth potential and above the fourth potential to the second electrode An optical semiconductor device driving method is provided.

  According to still another aspect of the embodiment, an intrinsic semiconductor layer formed on a substrate, a first optical waveguide that is a part of the semiconductor layer, and another part of the semiconductor layer, A second optical waveguide formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide; and a second optical waveguide opposite to the first side of the first optical waveguide. A first impurity region formed in the semiconductor layer on the second side and doped with an impurity of a first conductivity type; and formed in the semiconductor layer on the first side of the first optical waveguide; A second impurity region into which an impurity of a second conductivity type opposite to the conductivity type is introduced, and the semiconductor layer on the second side of the second optical waveguide are formed, and the impurity of the first conductivity type is introduced. A third impurity region connected to the second impurity region, and the second optical waveguide A fourth impurity region formed in the semiconductor layer on the first side and doped with a second conductivity type impurity; a first lower electrode which is a part of the first impurity region; and at least the A first capacitor having a first insulating film formed on the first lower electrode; a first upper electrode formed on the first insulating film; and the first capacitor on the first lower electrode. A fifth impurity region formed in the semiconductor layer on the second side and doped with an impurity of the first conductivity type at an impurity concentration lower than that of the first impurity region; and a part of the fourth impurity region. A second capacitor having a second lower electrode, at least a second insulating film formed on the second lower electrode, and a second upper electrode formed on the second insulating film And the semiconductor layer on the first side of the second lower electrode And a sixth impurity region formed and doped with an impurity of a second conductivity type at an impurity concentration lower than that of the fourth impurity region, wherein the first electrode is connected to the first electrode. The third electrode is connected to a second potential lower than the first potential, the first upper electrode is connected to a third potential, and the second upper electrode is connected to the second potential. 4 is provided, and an input signal that changes within a range equal to or lower than the first potential and equal to or higher than the second potential is applied to the second electrode. Is done.

  According to the disclosed optical semiconductor device and the manufacturing method thereof, the first optical waveguide that is a part of the semiconductor layer of the intrinsic semiconductor, the second optical waveguide formed on the first side of the first optical waveguide, Is provided. The first impurity region of the first conductivity type is formed in the semiconductor layer on the second side of the first optical waveguide, and the second conductivity type is formed in the semiconductor layer on the first side of the first optical waveguide. The second impurity region is formed. A first lower electrode that is a part of the first impurity region; a first insulating film formed on the first lower electrode; and a first upper electrode formed on the first insulating film; Thus, a first capacitor is formed. A third impurity region of the first conductivity type is formed in the semiconductor layer on the second side of the second optical waveguide, and the second conductivity type is formed in the semiconductor layer on the first side of the first optical waveguide. The fourth impurity region is formed. A second lower electrode which is a part of the fourth impurity region; a second insulating film formed on the second lower electrode; and a second upper electrode formed on the second insulating film; Thus, a second capacitor is formed. The fifth impurity region of the second conductivity type is formed in the semiconductor layer in the region below the first upper electrode of the first capacitor, and a voltage is applied to the first upper electrode of the first capacitor. At this time, an inversion layer is formed in the fifth impurity region, and the fifth impurity region becomes a resistance layer. The sixth impurity region of the first conductivity type is formed in the semiconductor layer in the region below the second upper electrode of the second capacitor, and a voltage is applied to the second upper electrode of the second capacitor. At this time, an inversion layer is formed in the sixth impurity region, and the sixth impurity region becomes a resistance layer. For this reason, a capacitor and a resistor can be directly connected to each PIN structure without performing wiring. Therefore, it is possible to provide an optical semiconductor device with good high frequency characteristics.

It is sectional drawing which shows the optical semiconductor device by 1st Embodiment. 1 is a plan view showing an optical semiconductor device according to a first embodiment. It is the top view which expanded and showed a part of optical semiconductor device by 1st Embodiment. It is a perspective view (the 1) which shows the optical semiconductor device by 1st Embodiment. It is a perspective view (the 2) which shows the optical semiconductor device by 1st Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. FIG. 9 is a process cross-sectional view (part 2) illustrating the method for manufacturing the optical semiconductor device according to the first embodiment; It is process sectional drawing (the 3) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. FIG. 11 is a process cross-sectional view (part 4) illustrating the method for manufacturing the optical semiconductor device according to the first embodiment; It is process sectional drawing (the 5) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. It is process sectional drawing (the 7) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. It is process sectional drawing (the 8) which shows the manufacturing method of the optical semiconductor device by 1st Embodiment. It is sectional drawing which shows the optical semiconductor device by 2nd Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the optical semiconductor device by 2nd Embodiment. It is process sectional drawing (the 2) which shows the manufacturing method of the optical semiconductor device by 2nd Embodiment. It is sectional drawing which shows the optical semiconductor device by the modification of 2nd Embodiment. It is a figure which shows an equivalent circuit.

  FIG. 18A is a diagram illustrating an equivalent circuit of a Mach-Zehnder type optical modulator having two PIN structures.

  Since the capacitance of the PIN diode is relatively large, the CR time constant is relatively large, and good high frequency characteristics cannot always be obtained.

  In order to improve the high frequency characteristics, it is conceivable to add a capacitor or a resistor as shown in FIG. 18B (see Non-Patent Document 3).

  However, when a capacitor or a resistor is simply added, the parasitic capacitance increases due to the wiring for connecting the capacitor and the resistor, and it is difficult to obtain good high-frequency characteristics.

[First Embodiment]
The optical semiconductor device according to the first embodiment, the manufacturing method thereof, and the driving method thereof will be described with reference to FIGS.

(Optical semiconductor device)
First, the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 1 is a sectional view of the optical semiconductor device according to the present embodiment. FIG. 2 is a plan view of the optical semiconductor device according to the present embodiment. FIG. 3 is an enlarged plan view showing a part of the optical semiconductor device according to the present embodiment. FIG. 4 is a perspective view showing the optical semiconductor device according to the present embodiment. FIG. 1 corresponds to a cross section taken along the line AA ′ of FIGS. 2 and 3.

  In the present embodiment, a Mach-Zehnder type optical modulator will be described as an example of an optical semiconductor device, but the present invention is not limited to the optical modulator, and can be applied to various optical semiconductor devices.

  A semiconductor layer 14 is formed on the semiconductor substrate 10 via an insulating film 12. Here, for example, an SOI substrate in which a silicon layer 14 is formed on a silicon substrate 10 via a buried oxide film 12 is used. The thickness of the insulating film 12 is, for example, about 2 to 3 μm. Since the thickness of the insulating film 12 is set to be sufficiently thick, the capacitance between the semiconductor substrate 10 and the semiconductor layer 14 is suppressed to be sufficiently small.

  The semiconductor layer 14 is processed into a rib shape as shown in FIG. 1, thereby forming a plurality of optical waveguides 18 a to 18 f as shown in FIG. 2. The portions (rib portions) where the thickness of the semiconductor layer 14 is thick become optical waveguides 18a to 18f.

  The height of the optical waveguides (arm waveguides) 18a and 18b, that is, the vertical dimension of the optical waveguides 18a and 18b in FIG. 1 is, for example, about 250 nm. The width of the optical waveguides 18a and 18b, that is, the dimension of the optical waveguides 18a and 18b in FIG. The thickness of the thinned portion of the semiconductor layer 14 is, for example, about 50 nm. The optical waveguides 18a and 18b extend in the left-right direction in FIG. The height and width of the optical waveguides 18c to 18f are set similarly to the optical waveguides 18a and 18b.

  The incident optical waveguides 18 c and 18 d are connected to the optical demultiplexer 11 provided on the semiconductor substrate 10. Incident light (modulated light) is branched into two by the optical demultiplexer 11 and output from two output ports of the optical demultiplexer 11. As the modulated light, for example, continuous light (CW: Continuous Wave) is used.

  The two output ports of the optical demultiplexer 11 are connected to the input ports of the waveguides 18a and 18b, respectively. Output ports of the waveguides 18 a and 18 b are connected to the optical multiplexer 13.

  The optical multiplexer 13 multiplexes the light provided from the waveguides 18a and 18b and outputs it to the output optical waveguides 18e and 18f. For example, an optical coupler having a branching ratio of 50:50 can be used as the optical multiplexer 13. The optical multiplexer 13 can output modulation signals to the optical waveguides 18e and 18f in a complementary manner.

  The lengths of the arms of the optical waveguides 18a and 18b, that is, the dimensions of the optical waveguides 18a and 18b in the left-right direction in FIG. 2 are, for example, about 1 mm. Dopant impurities are not introduced into the optical waveguides 18a to 18f. The optical waveguides 18a to 18f are formed of intrinsic semiconductors, that is, I (Intrinsic) type semiconductors.

P-type impurity regions (P ⁺ impurity regions) 19 and 20 are formed in the semiconductor layer 14 on one side of the optical waveguide 18a, that is, on the left side in FIG. The impurity regions 19 and 20 are formed in parallel with the optical waveguide 18a. The impurity regions 19 and 20 are formed in regions excluding a predetermined region where the N-type impurity region 25 is formed. The impurity region 19 and the impurity region 20 are formed at a predetermined interval. The distance between the impurity region 19 and the impurity region 20 is, for example, about 200 nm.

An N-type impurity region (N ⁺ impurity region) 21 is formed in the semiconductor layer 14 on the other side of the optical waveguide 18a, that is, on the right side in FIG.

  The semiconductor layer 14 in the region between the P-type impurity region 20 and the N-type impurity region 21 is an intrinsic semiconductor region 14a.

  The P-type impurity regions 19 and 20, the I-type optical waveguide 18a, and the N-type impurity region 21 form a PIN structure (PIN diode) 16a.

  An N-type impurity region 25 is formed between the P-type impurity region 19 and the P-type impurity region 20. The impurity region 25 functions as a resistance layer by forming an inversion layer when a predetermined voltage is applied to the upper electrode 30a of the capacitor 32a. The dimension of the impurity region 25 in the left-right direction in FIG. 1 is about 200 nm, for example. The impurity region 25 is formed in parallel with the optical waveguide 18a.

  The resistance value of the resistance layer 25 when a predetermined voltage is applied to the upper electrode 30a of the capacitor 32a is, for example, about 100 to 500Ω.

  Since the current flowing through the PIN structure 16a is about 10 μA per 1 μm of the optical waveguide length, there is no particular problem even with the electric resistance obtained by forming the inversion layer.

  Since the current flowing through the inversion layer has saturation characteristics with respect to voltage, the differential resistance of the resistance layer is set to about 10 to 100 times the differential resistance of the PIN diode 16a by appropriately setting the channel length of the inversion layer. Is possible.

  The resistance value of the resistance layer 25 is not limited to 100 to 500Ω. The resistance value of the resistance layer 25 can be appropriately set so as to obtain a desired high frequency characteristic. The resistance value of the resistance layer 25 can be adjusted by appropriately setting the concentration of the N-type dopant impurity introduced into the impurity region 25, the voltage value applied to the upper electrode 30a of the capacitor 32a, and the like.

  On the impurity regions 19 and 20 and the impurity region 25, an upper electrode 30a is formed via an insulating film (dielectric film) 28. The insulating film 28 is made of, for example, a silicon oxide film. The thickness of the insulating film 28 is, for example, about 3 to 10 nm. Here, the film thickness of the insulating film 28 is, for example, about 3 nm. The upper electrode 30a is formed of, for example, a polysilicon film into which a P-type dopant impurity is introduced. The upper electrode 30a is formed in parallel with the optical waveguide 18a. The dimension of the upper electrode 30a in the left-right direction in FIG. 1 is about 600 nm, for example. The dimension in the left-right direction on the paper surface of the region where the upper electrode 30a and the impurity region 20a overlap is about 500 nm, for example.

  A capacitor (MOS capacitor) 32a is formed by the lower electrode, which is part of the impurity region 20, the insulating film (dielectric film) 28, and the upper electrode 30a. The capacitance of the capacitor 32a is preferably about 1/10 to 1/100 of the capacitance of the PIN diode 16a. Here, the capacitance of the capacitor 32a is, for example, about 0.1 to 0.5 pF.

  Note that the capacitance of the capacitor 32a is not limited to 0.1 to 0.5 pF. What is necessary is just to set the electrostatic capacitance of the capacitor 32a suitably so that a desired high frequency characteristic may be acquired. The capacitance of the capacitor 32a can be adjusted by appropriately setting the facing area between the impurity region 20 and the upper electrode 30a, the thickness of the dielectric film 28, the material, and the like.

  Further, here, a case where a part of the impurity region 19 and the upper electrode 30a overlap is described as an example, but a part of the impurity region 19 and the upper electrode 30a may not overlap.

  The capacitor 32a is for reducing the CR time constant of the PIN structure 16a. In order to reduce the CR time constant of the PIN structure 16a, it is preferable to connect the capacitor 32a directly to the impurity region 20 serving as the anode. For this reason, in this embodiment, a part of the impurity region 20 also serves as the lower electrode of the capacitor 32a, and a part of the impurity region 20 and a part of the upper electrode 30a of the capacitor 32a overlap each other.

  Since the conductivity type of impurity region 25 is opposite to the conductivity type of impurity regions 19 and 20, impurity region 25 is in a very high resistance state when no bias is applied to upper electrode 30a of capacitor 32a. . In this embodiment, by applying a predetermined bias voltage to the upper electrode 30a of the capacitor 32a, an inversion layer is formed in the impurity region 25, and the resistance value of the impurity region 25 is set to a desired resistance value. It is preferable that the impurity region 25 is located in a region below the upper electrode 30a so that an inversion layer is formed in the impurity region 25 when a predetermined bias voltage is applied to the upper electrode 30a of the capacitor 32a.

  In order to achieve miniaturization, it is preferable to set the size of the upper electrode 30a in the left-right direction in FIG. 1 to be relatively small. The position of the center line in the longitudinal direction of the impurity region 25 is set to the position of the center line in the longitudinal direction of the upper electrode 30a of the capacitor 32a in order to sufficiently secure the capacitance of the capacitor 32a while miniaturizing. It is located on the left side in FIG.

A P-type impurity region (P ⁺ impurity region) 22 is formed in the semiconductor layer 14 on one side of the optical waveguide 18b, that is, on the left side in FIG. The impurity region 22 is formed in parallel with the optical waveguide 18b.

N-type impurity regions (N ⁺ impurity regions) 23 and 24 are formed on the semiconductor layer 14 on the other side of the optical waveguide 18b, that is, on the right side in FIG. The impurity regions 23 and 24 are formed in regions excluding a predetermined region where the P-type impurity region 26 is formed. The impurity region 23 and the impurity region 24 are formed at a predetermined interval. The distance between the impurity region 23 and the impurity region 24 is, for example, about 200 nm.

  The semiconductor layer 14 in the region between the P-type impurity region 22 and the N-type impurity region 23 is an intrinsic semiconductor region 14b.

  The P-type impurity region 22, the I-type optical waveguide 18b, and the N-type impurity regions 23 and 24 form a PIN structure (PIN diode) 16b.

  A P-type impurity region 26 is formed between the N-type impurity region 23 and the N-type impurity region 24. The impurity region 26 functions as a resistance layer by forming an inversion layer when a predetermined voltage is applied to the upper electrode 30b of the capacitor 32b. The dimension of the impurity region 26 in the left-right direction in FIG. 1 is about 200 nm, for example. The impurity region 26 is formed in parallel with the optical waveguide 18b.

  The resistance value of the resistance layer 26 when a predetermined voltage is applied to the upper electrode 30b of the capacitor 32b is, for example, about 100 to 500Ω.

  Since the current flowing through the PIN structure 16b is about 10 μA per 1 μm of the optical waveguide length, there is no particular problem even with the electric resistance obtained by forming the inversion layer.

  Since the current flowing through the inversion layer has saturation characteristics with respect to voltage, the differential resistance of the resistance layer is set to about 10 to 100 times the differential resistance of the PIN diode 16b by appropriately setting the channel length of the inversion layer. Is possible.

  The resistance value of the resistance layer 26 is not limited to 100 to 500Ω. The resistance value of the resistance layer 26 can be appropriately set so as to obtain a desired high frequency characteristic. The resistance value of the resistance layer 26 can be adjusted by appropriately setting the concentration of the N-type dopant impurity introduced into the impurity region 26, the voltage value applied to the upper electrode 30b of the capacitor 32b, and the like.

  An upper electrode 30 b is formed on the impurity regions 23 and 24 and the impurity region 26 with an insulating film 28 interposed therebetween. The upper electrode 30b is formed of, for example, a polysilicon film into which an N-type dopant impurity is introduced. The upper electrode 30b is formed in parallel with the optical waveguide 18b. The dimension of the upper electrode 30b in the left-right direction in FIG. 1 is about 600 nm, for example. The dimension in the left-right direction of the drawing of the region where the upper electrode 30b and the impurity region 23 overlap is about 500 nm, for example.

  A capacitor 32b is formed by the lower electrode, which is part of the impurity region 23, the insulating film 28, and the upper electrode 30b. The capacitance of the capacitor 32b is preferably about 1/10 to 1/100 of the capacitance of the PIN diode 16b. Here, the capacitance of the capacitor 32b is, for example, about 0.1 to 0.5 pF.

  Note that the capacitance of the capacitor 32b is not limited to 0.1 to 0.5 pF. What is necessary is just to set the electrostatic capacitance of the capacitor 32b suitably so that a desired high frequency characteristic may be acquired. The capacitance of the capacitor 32b can be adjusted by appropriately setting the facing area between the impurity region 23 and the upper electrode 30b, the thickness of the dielectric film 28, the material, and the like.

  Further, here, a case where a part of the impurity region 24 and the upper electrode 30b overlap is described as an example, but a part of the impurity region 24 and the upper electrode 30b may not overlap.

  The capacitor 32b is for reducing the CR time constant of the PIN structure 16b. In order to reduce the CR time constant of the PIN structure 16b, it is preferable to connect the capacitor 32b directly to the impurity region 23 serving as a cathode. For this reason, in this embodiment, a part of the impurity region 23 also serves as the lower electrode of the capacitor 32b, and a part of the impurity region 23 and a part of the upper electrode 30b of the capacitor 32b overlap each other.

  Since the conductivity type of impurity region 26 is opposite to the conductivity type of impurity regions 23 and 24, impurity region 26 is in a very high resistance state when no bias is applied to upper electrode 30b of capacitor 32b. . In the present embodiment, an inversion layer is formed in the impurity region 26 by applying a predetermined bias voltage to the upper electrode 30b of the capacitor 32b, and the resistance value of the impurity region 26 is set to a desired resistance value. It is preferable that the impurity region 26 is located in a lower region of the upper electrode 30b so that an inversion layer is formed in the impurity region 26 when a predetermined bias voltage is applied to the upper electrode 30b of the capacitor 32b.

  In order to achieve miniaturization, it is preferable to set the size of the upper electrode 30b in the horizontal direction in FIG. 1 to be relatively small. The position of the center line in the longitudinal direction of the impurity region 26 is set to the position of the center line in the longitudinal direction of the upper electrode 30b of the capacitor 32b in order to sufficiently secure the capacitance of the capacitor 32b while miniaturization is achieved. It is located on the right side in FIG.

  On the semiconductor layer 14 on which the capacitors 32a and 32b are formed, for example, an interlayer insulating film 34 of a silicon oxide film is formed. The film thickness of the interlayer insulating film 34 is, for example, about 1 μm.

  In the interlayer insulating film 34, openings 36a and 36b reaching the upper electrodes 30a and 30b of the capacitors 32a and 32b, openings 36c and 36d reaching the impurity regions 19 and 24, and openings reaching the impurity regions 21 and 22, respectively. A portion 36e is formed.

  For example, a silicide film 38 of nickel silicide is formed on the bottom surfaces of the contact holes 36a to 36e.

  In the openings 36a to 36e where the silicide film 38 is formed and on the interlayer insulating film 34, for example, an adhesion layer 40 formed by a laminated film of a Ti film and a TiN film is formed.

  For example, aluminum wiring layers (electrodes) 42a to 42e are formed in the openings 36a to 36e in which the adhesion layer 40 is formed and on the interlayer insulating film 34, respectively. The wiring layer 42a is connected to the upper electrode 30a of the capacitor 32a. The wiring layer 42b is connected to the upper electrode 30b of the capacitor 32b. The wiring layer 42 c is connected to the impurity region 19. The wiring layer 42 d is connected to the impurity region 24. The wiring layer 42 e is connected to the impurity regions 21 and 22.

  Thus, the optical semiconductor device according to the present embodiment is formed.

(Operation of optical semiconductor device (1))
Next, the operation (part 1) of the optical semiconductor device according to the present embodiment will be explained.

  Here, the wiring layer 42a is a first DC bias line, the wiring layer 42b is a second DC bias line, the wiring layer 42c is a power supply line, the wiring layer 42d is a ground line, and the wiring layer 42e is a signal line. An example of this will be described.

As shown in FIG. 4, the power supply line 42c is connected to the power supply voltage _Vdd , for example. The power supply voltage V _dd is, for example, 2.4V.

  The ground line 42d is connected to, for example, the ground (GND, 0V).

The first DC bias line 42a is connected to the first bias voltage _Vbias1 , for example. The first bias voltage _{V bias1} is lower than the power supply voltage _{V dd,} higher than the second bias voltage _{V bias2} applied to the second DC bias line 42b. The first bias voltage V _bias1 applied to the first bias line 42a has an inversion layer formed in the impurity region 25 located below the upper electrode 30a of the capacitor 32a, and the impurity region 25 has a desired resistance value. It is set to be a resistive layer having. The first bias voltage V _bias1 is 2 V, for example. When such a bias voltage V _bias1 is applied, an inversion layer is formed in the impurity region 25 located below the upper electrode 30a of the capacitor 32a, and the impurity region 25 can function as a resistance layer having a desired resistance value.

The second DC bias line 42b is connected to the second bias voltage _Vbias2 , for example. The second bias voltage _{V bias2} is lower than the first bias voltage _{V bias1,} higher than the potential of ground (GND). Here, the second bias voltage V _{bias2 is set} to 0.4 V, for example. The second bias voltage V _bias2 applied to the second bias line 42b is such that an inversion layer is formed in the impurity region 26 located below the upper electrode 30b of the capacitor 32b, and the impurity region 26 has a desired resistance value. It is set to be a resistive layer having.

  In the present embodiment, not only the capacitors 32a and 32b but also the resistance layers 25 and 26 are connected to the PIN structures 16a and 16b in order to ensure the balance of the circuit. That is, when the capacitor 32a is simply connected in series with the anode of the PIN diode 16a, the balance of the circuit is lost and desired electrical characteristics cannot be obtained. Further, when the capacitor 32b is simply connected in series with the cathode of the PIN diode 16b, the balance of the circuit is lost and desired electrical characteristics cannot be obtained. In order to ensure the balance of the circuit, it is preferable to connect not only the capacitors 32a and 32b but also an electrical resistance. For this reason, in this embodiment, not only the capacitors 32a and 32b but also the resistance layers 25 and 26 are formed.

The bias voltage V _bias1 is not limited to 2V. Upon application of a bias voltage _{V bias1,} so that a desired resistance value in the impurity region 25 is obtained, it may be set as appropriate bias voltage _{V bias1.}

Also, the bias voltage V _bias2 is not limited to 0.4V. Upon application of a bias voltage _{V bias2,} as desired resistance value in the impurity region 26 is obtained, it may be set as appropriate bias voltage _{V bias2.}

An input signal voltage V _signal is applied to the signal line 42e.

As the input signal voltage V _signal , for example, a high frequency (RF) radio signal is used.

For example, the input signal voltage V _signal is obtained by superimposing a ± 0.5 V AC component on a 1.2 V DC component.

When the data of the input signal is 1, that is, when the input signal is at the “H (High)” level, the input signal voltage V _signal is, for example, about 1.7V. When the power supply voltage V _dd is, for example, 2.4 V and the input signal voltage V _signal is, for example, 1.7 V, the potential difference between the impurity region 24 and the impurity region 22 is 1.7 V. When the voltage drop generated in the resistance layer 26 is about 0.85V, for example, a forward bias of about 0.85V is applied to the PIN structure 16b. Since a sufficiently large forward bias is applied to the PIN structure 16b, sufficient carriers (electrons and holes) are injected into the optical waveguide 18b. When carriers are injected into the optical waveguide 18b, the refractive index of light decreases in the optical waveguide 18b due to the carrier plasma effect, and the phase of the optical signal traveling through the optical waveguide 18b shifts in the first direction. Therefore, when the input signal is at the “H” level, the phase of the optical signal traveling through the optical waveguide 18b is shifted in the first direction. On the other hand, the potential difference between the impurity region 21 and the impurity region 19 is, for example, 0.7V. When the voltage drop generated in the resistance layer 25 is about 0.2V, for example, a forward bias of about 0.5V is applied to the PIN structure 16a. Since the forward bias applied to the PIN structure 16a is relatively small, sufficient carriers are not injected into the optical waveguide 18a, and the carrier plasma effect generated in the optical waveguide 18a is reduced. Therefore, when the input signal is at the “H” level, the refractive index increases in the optical waveguide 18a, and the phase of the optical signal traveling through the optical waveguide 18a is the first phase shift direction in the optical waveguide 18b. Shift in a second direction opposite the direction.

When the data of the input signal is 0, that is, when the input signal is at “L (Low)” level, the input signal voltage V _signal is about 0.7V, for example. When the power supply voltage V _dd is, for example, 2.4 V and the input signal voltage V _signal is, for example, 0.7 V, the potential difference between the impurity region 21 and the impurity region 19 is 1.7 V. When the voltage drop generated in the resistance layer 25 is about 0.85V, for example, a forward bias of about 0.85V is applied to the PIN structure 16a. Since a sufficiently large forward bias is applied to the PIN structure 16a, sufficient carriers are injected into the optical waveguide 18a. When carriers are injected into the optical waveguide 18a, the refractive index of light in the optical waveguide 18a decreases due to the carrier plasma effect, and the phase of the optical signal traveling through the optical waveguide 18a shifts in the first direction. Therefore, when the input signal is at the “L” level, the phase of the optical signal traveling through the optical waveguide 18a is shifted in the first direction. On the other hand, the potential difference between the impurity region 22 and the impurity region 24 is, for example, 0.7V. When the voltage drop generated in the resistance layer 26 is about 0.2V, for example, a forward bias of about 0.5V is applied to the PIN structure 16b. Since the forward bias applied to the PIN structure 16b is small, sufficient carriers are not injected into the optical waveguide 18b, and the carrier plasma effect generated in the optical waveguide 18b is reduced. Therefore, when the input signal is at the “L” level, the refractive index increases in the optical waveguide 18b, and the phase of the optical signal traveling through the optical waveguide 18b is the first phase shift direction in the optical waveguide 18a. Shift in a second direction opposite the direction.

  As described above, the phase shift direction of the optical signal traveling through the optical waveguide 18a and the phase shift direction of the optical signal traveling through the optical waveguide 18b are opposite to each other. In comparison, the arm length is halved.

The AC component of the input signal voltage V _signal is not limited to ± 0.5V. What is necessary is just to set the magnitude _| size of the alternating current component of input signal voltage _Vsignal suitably so that a desired phase shift amount may be obtained.

(Operation of optical semiconductor device (part 2))
Next, the operation (part 2) of the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 5 is a perspective view (part 2) of the optical semiconductor device according to the present embodiment.

  Here, the wiring layer 42c is a first DC bias line, the wiring layer 42d is a second DC bias line, the wiring layer 42a is a power supply line, the wiring layer 42d is a ground line, and the wiring layer 42e is a signal line. An example of this will be described.

The power supply line 42a is connected to the power supply voltage _Vdd , for example. The power supply voltage V _dd is lower than the first bias voltage V _{bias1 and} higher than the potential of the ground (GND, 0 V). The power supply voltage V _dd is set to 1.6 V, for example.

The ground line 42b is connected to the ground, for example. The ground potential is lower than the power supply voltage V _{dd and} higher than the second bias voltage V _bias2 .

The first DC bias line 42c is connected to the first bias voltage _Vbias1 , for example. The first bias voltage V _bias1 is higher than the power supply voltage V _dd . The first bias voltage _Vbias1 applied to the first DC bias line 42c is such that an inversion layer is formed in the impurity region 25 located below the upper electrode 30a of the capacitor 32a, and the impurity region 25 has a desired resistance value. It is set to be a resistance layer having The first bias voltage V _bias1 is 2 V, for example. When such a first bias voltage V _bias1 is applied, an inversion layer is formed in the impurity region 25 located below the upper electrode 30a of the capacitor 32a, and the impurity region 25 functions as a resistance layer having a desired resistance value. Can do.

The second DC bias line 42d is connected to the second bias voltage _Vbias2 , for example. The second bias voltage V _bias2 is lower than the ground potential. The second bias voltage V _bias2 applied to the second DC bias line 42d has an inversion layer formed in the impurity region 26 located below the upper electrode 30b of the capacitor 32b, and the impurity region 26 has a desired resistance value. It is set to be a resistance layer having The second bias voltage V _bias2 is set to, for example, −0.4V. When such a second bias voltage V _bias2 is applied, an inversion layer is formed in the impurity region 26 located below the upper electrode 30b of the capacitor 32b, and the impurity region 26 functions as a resistance layer having a desired resistance value. Can do.

The bias voltage V _bias1 is not limited to 2V. Upon application of a bias voltage _{V bias1,} so that a desired resistance value in the impurity region 25 is obtained, it may be set as appropriate bias voltage _{V bias1.}

Further, the bias voltage V _bias2 is not limited to −0.4V. Upon application of a bias voltage _{V bias2,} as desired resistance value in the impurity region 26 is obtained, it may be set as appropriate bias voltage _{V bias2.}

An input signal voltage V _signal is applied to the signal line 42e.

As a circuit for applying the input signal voltage V _signal to the signal line 42e, for example, a CMOS inverter circuit 68 having a PMOS transistor Tr1 and an NMOS transistor Tr2 as shown in FIG. 4 is used.

The data signal _{V in} input to the CMOS inverter 68, for example, a logic signal of radio frequency (RF) is used.

When the data of the input data signal _{V in} is 1, i.e., the input signal voltage _{V signal} at the time of the input data signal is "H (High)" level is, for example, about 0V. When the first bias voltage V _bias1 is, for example, 2V and the input signal voltage V _signal is, for example, 0V, the potential difference between the impurity region 19 and the impurity region 21 is 2V. When the voltage drop generated in the resistance layer 25 is, for example, about 1.15V, a forward bias of, for example, about 0.85V is applied to the PIN structure 16a. Since a sufficiently large forward bias is applied to the PIN structure 16a, carriers are injected into the optical waveguide 18a. When carriers are injected into the optical waveguide 18a, the refractive index of light in the optical waveguide 18a decreases due to the carrier plasma effect, and the phase of the optical signal traveling through the optical waveguide 18a shifts in the first direction. Therefore, when the input signal is at the “H” level, the phase of the optical signal traveling through the optical waveguide 18a is shifted in the first direction. On the other hand, when the second bias voltage V _bias2 is −0.4V, for example, the potential difference between the impurity region 22 and the impurity region 24 is 0.4V. When the voltage drop generated in the resistance layer 26 is about 0.1V, for example, a forward bias of about 0.3V is applied to the PIN structure 16b. Since the forward bias applied to the PIN structure 16b is small, sufficient carriers are not injected into the optical waveguide 18b, and the carrier plasma effect generated in the optical waveguide 18b is reduced. Accordingly, when the input data signal is at the “H” level, the refractive index increases in the optical waveguide 18b, and the phase of the optical signal traveling through the optical waveguide 18b is the first phase shift direction in the optical waveguide 18a. Shift in a second direction opposite to the direction of.

When the data of the input data signal is 0, that is, when the input data signal is at the “L (Low)” level, the input signal voltage V _signal is about 1.6 V, for example. When the second bias voltage V _bias is −0.4 V, for example, and the input signal voltage V _signal is 1.6 V, for example, the potential difference between the impurity region 22 and the impurity region 24 is 2 V. When the voltage drop generated in the resistance layer 26 is, for example, about 1.15V, a forward bias of, for example, about 0.85V is applied to the PIN structure 16b. Since a sufficiently large forward bias is applied to the PIN structure 16b, the number of carriers injected into the optical waveguide 18b increases. When carriers are injected into the optical waveguide 18b, the refractive index of light decreases in the optical waveguide 18b due to the carrier plasma effect, and the phase of the optical signal traveling through the optical waveguide 18b shifts in the first direction. Therefore, when the input signal is at the “L” level, the phase of the optical signal traveling through the optical waveguide 18b is shifted in the first direction. On the other hand, the potential difference between the impurity region 19 and the impurity region 21 is, for example, 0.4V. When the voltage drop generated in the resistance layer 25 is about 0.1V, for example, a forward bias of about 0.3V is applied to the PIN structure 16a. Since the forward bias applied to the PIN structure 16a is small, carriers injected into the optical waveguide 18a are reduced, and the carrier plasma effect generated in the optical waveguide 18a is reduced. Therefore, when the input signal is at the “L” level, the refractive index increases in the optical waveguide 18a, and the phase of the optical signal traveling through the optical waveguide 18a is the first phase shift direction in the optical waveguide 18b. Shift in a second direction opposite the direction.

  As described above, the phase shift direction of the optical signal traveling through the optical waveguide 18a and the phase shift direction of the optical signal traveling through the optical waveguide 18b are opposite to each other. In comparison, the arm length is halved.

Note that the input signal voltage V _signal is not limited to the above. The input signal voltage V _signal may be appropriately set so that a desired phase shift amount can be obtained.

  In the optical semiconductor device according to the present embodiment, a capacitor 32a is formed by a part of the impurity region 20 forming the anode of the PIN structure 16a, the insulating film 28, and the upper electrode 30a. A capacitor 32b is formed by a part of the impurity region 23 forming the cathode of the PIN structure 16b, the insulating film 28, and the upper electrode 30b. In the optical semiconductor device according to the present embodiment, the resistance layer is formed by the impurity regions 25 and 26 formed in the regions below the upper electrodes 30a and 32b of the capacitors 32a and 32b, respectively. Therefore, in the present embodiment, the capacitors 32a and 32b and the resistance layers 25 and 26 can be connected to the PIN structures 16a and 16b without performing wiring. Therefore, according to the present embodiment, an optical semiconductor device with good high-frequency characteristics can be provided.

(Manufacturing method of optical semiconductor device)
Next, the method for fabricating the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. 6 to 13 are process cross-sectional views illustrating the method of manufacturing the optical semiconductor device according to the present embodiment.

  First, an SOI (Silicon On Insulator) 15 in which a semiconductor layer 14 is formed on a semiconductor substrate 10 via an insulating film (buried oxide film) 12 is prepared (see FIG. 6A). For example, a silicon substrate is used as the semiconductor substrate 10. As the insulating film 12, for example, a silicon oxide film having a film thickness of about 2 to 3 μm is formed. As the semiconductor layer 14, an I (Intrinsic) type, ie, intrinsic semiconductor silicon layer 14 is formed. The thickness of the silicon layer 14 is, for example, about 250 nm.

  Next, a photoresist film 44 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 44 is patterned into a planar shape of the optical waveguides 18a to 18f (see FIG. 2) by using a photolithography technique.

  Next, the semiconductor layer 14 is anisotropically etched using the photoresist film 44 as a mask. At this time, the semiconductor layer 14 is etched until the thickness of the portion of the semiconductor layer 14 not covered with the photoresist film 44 becomes, for example, about 50 nm.

  In this way, rib-type optical waveguides 18a to 18f are formed (see FIGS. 2 and 6B).

  The width of the optical waveguides 18a and 18b, that is, the dimension in the horizontal direction of the optical waveguides 18a and 18b in FIG. 6B is, for example, about 500 nm. The height of the optical waveguides 18a and 18b, that is, the vertical dimension of the optical waveguides 18a and 18b in FIG. 6B is about 250 nm, for example. The optical waveguides 18a and 18b are formed so as to extend in the direction perpendicular to the paper surface in FIG. The thickness of the semiconductor layer 14 excluding the optical waveguides 18a and 18b is, for example, about 50 nm. The width and height of the optical waveguides 18c to 18f are the same as those of the optical waveguides 18a and 18b.

  Thereafter, the photoresist film 44 is removed by, for example, ashing.

  Next, a photoresist film 46 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 46 is patterned using a photolithography technique. As a result, openings 48 a to 48 c for forming the P-type impurity regions 19, 20 and 22 are formed in the photoresist film 46.

Next, by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 46 as a mask, the P-type impurity regions (P ⁺ -type impurity regions) 19, 20, 22 are formed. Form. (See FIG. 7 (a)). The ion implantation conditions are as follows. For example, boron is used as the P-type dopant impurity. The impurity concentration in the P-type impurity regions 19, 20, 22 is, for example, about 1 × 10 ¹⁹ cm ⁻³ . The impurity region 20 is formed in the semiconductor layer 14 on one side of the optical waveguide 18a so as to be parallel to the optical waveguide 18a. The impurity region 19 is formed to be parallel to the optical waveguide 18a with a predetermined interval from the impurity region 20. The dimension between the impurity region 19 and the impurity region 20 is, for example, about 200 nm. The impurity region 22 is formed in the semiconductor layer 14 on one side of the optical waveguide 18b so as to be parallel to the optical waveguide 18b.

  Thereafter, the photoresist film 46 is removed by, for example, ashing.

  Next, a photoresist film 50 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 50 is patterned using a photolithography technique. As a result, openings 52 a, 52 b, 52 c for forming the impurity regions 21, 23, 24 are formed in the photoresist film 50.

Next, N-type impurity regions (N ⁺ -type impurity regions) 21, 23, 24 are formed by introducing N-type dopant impurities into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 50 as a mask. It forms (refer FIG.7 (b)). The ion implantation conditions are as follows. For example, phosphorus is used as the N-type dopant impurity. The impurity concentration in the impurity regions 21, 23, 24 is about 1 × 10 ¹⁹ cm ⁻³ . The impurity region 21 is formed in the semiconductor layer 14 on the other side of the optical waveguide 18a so as to be parallel to the optical waveguide 18a. The impurity region 23 is formed in the semiconductor layer 14 on the other side of the optical waveguide 18b so as to be parallel to the optical waveguide 18b. The impurity region 24 is formed so as to be parallel to the optical waveguide 18b at a predetermined interval from the impurity region 23. The dimension between the impurity region 23 and the impurity region 24 is, for example, about 200 nm.

  Thereafter, the photoresist film 50 is removed by, for example, ashing.

  Next, a photoresist film 54 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 54 is patterned using a photolithography technique. Thereby, an opening 55 for forming the impurity region 26 is formed in the photoresist film 54.

Next, a P-type impurity region (resistance layer) 26 is formed by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 54 as a mask (FIG. 8A). )reference). The ion implantation conditions are as follows. For example, boron is used as the dopant impurity. The impurity concentration in the impurity region 26 is, for example, about 5 × 10 ¹⁷ cm ⁻³ . The impurity region 26 is formed between the impurity region 23 and the impurity region 24 so as to be parallel to the optical waveguide 18b. The dimension of the impurity region 26 in the left-right direction in FIG. 8A is about 200 nm, for example.

  Thereafter, the photoresist film 54 is removed by, for example, ashing.

  Next, a photoresist film 56 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 56 is patterned using a photolithography technique. Thereby, an opening 57 for forming the impurity region 25 is formed in the photoresist film 56.

Next, an N-type impurity region (resistance layer) 25 is formed by introducing an N-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 56 as a mask (FIG. 8B). )reference). The ion implantation conditions are as follows. For example, phosphorus is used as the dopant impurity. The impurity concentration in the impurity region 25 is, for example, about 5 × 10 ¹⁷ cm ⁻³ . The impurity region 25 is formed between the impurity region 19 and the impurity region 20 so as to be parallel to the optical waveguide 18a. The dimension of the impurity region 25 in the left-right direction in FIG. 8B is about 200 nm, for example.

  Thereafter, the photoresist film 56 is removed by, for example, ashing.

  Next, as shown in FIG. 9A, an insulating film 28 made of a silicon oxide film is formed by, eg, thermal oxidation. The film forming temperature is about 900 ° C., for example. The thickness of the insulating film 28 is, for example, about 3 to 10 nm. Here, the film thickness of the insulating film 28 is, for example, about 3 nm.

  Next, a polysilicon film 30 is formed by, for example, a CVD (Chemical Vapor Deposition) method (see FIG. 9B). The film thickness of the polysilicon film 30 is, eg, about 150 nm.

  Next, a photoresist film 58 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 58 is patterned by using a photolithography technique. Thereby, an opening 60 for introducing a P-type dopant impurity into the polysilicon film 30 is formed in the photoresist film 58.

Next, using the photoresist film 58 as a mask, a P-type dopant impurity is introduced into the polysilicon film 30 by, eg, ion implantation (see FIG. 10A). For example, boron is used as the dopant impurity. Thus, part of the polysilicon film 30 becomes a P-type polysilicon film 30a. The impurity concentration in the P-type polysilicon film 30a is, for example, about 1 × 10 ²⁰ cm ⁻³ .

  Next, a photoresist film 62 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 62 is patterned using a photolithography technique. As a result, an opening 64 for introducing an N-type dopant impurity into the polysilicon film 30 is formed in the photoresist film 62.

Next, using the photoresist film 62 as a mask, an N-type dopant impurity is introduced into the polysilicon film 30 by, eg, ion implantation (see FIG. 10B). For example, phosphorus is used as the dopant impurity. Thus, a part of the polysilicon film 30 becomes an N-type polysilicon film 30b. The impurity concentration in the N-type polysilicon film 30b is, for example, about 1 × 10 ²⁰ cm ⁻³ .

  Next, a photoresist film 66 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 66 is patterned into a planar shape of the upper electrodes 30a and 32b of the capacitors 32a and 32b by using a photolithography technique.

  Next, the polysilicon film 30 is anisotropically etched using the photoresist film 66 as a mask (see FIG. 11A). As a result, an upper electrode 30a made of P-type polysilicon and an upper electrode 30b made of N-type polysilicon are formed. The upper electrodes 30a and 30b are formed in parallel with the optical waveguides 18a and 18b, respectively.

  Thereafter, the photoresist film 66 is removed by, for example, ashing.

  Thus, a capacitor 32a having a lower electrode, which is a part of the impurity region 20, the insulating film 28, and the upper electrode 30a is formed. The size of the region where the upper electrode 30a of the capacitor 32a and the impurity region 20 overlap is about 500 nm, for example, in the left-right direction in FIG.

  In addition, a capacitor 32b having a lower electrode that is a part of the impurity region 23, an insulating film 28, and an upper electrode 30b is formed. The dimension of the region where the upper electrode 30b of the capacitor 32b and the impurity region 23 overlap is about 500 nm, for example, in the left-right direction in FIG.

  Next, as shown in FIG. 11B, a silicon oxide interlayer insulating film 34 having a thickness of about 1 μm is formed on the entire surface by, eg, CVD.

  Next, the openings 36a and 36b reaching the upper electrodes 30a and 30b of the capacitors 32a and 32b, the openings 36c and 36d reaching the impurity regions 19 and 24, respectively, and the impurity regions 21 and 22 using the photolithography technique. The reaching opening 36e is formed in the interlayer insulating film 34 (see FIG. 12A). The openings 36a to 36e are formed in parallel with the optical waveguides 18a and 18b, respectively.

  Next, a nickel film (not shown) is formed on the entire surface by, eg, sputtering.

  Next, the nickel film and the semiconductor layer 14 are reacted by performing heat treatment. As a result, nickel in the nickel film and silicon in the semiconductor layer 14 react to form a silicide film 38 of nickel silicide.

  Next, the unreacted nickel film is removed by, for example, wet etching. Thus, silicide films 38 are respectively formed on the bottom surfaces of the openings 36a to 36e (see FIG. 12B).

  Next, a Ti film having a thickness of 2 nm is formed on the entire surface by, eg, sputtering.

  Next, a 2 nm-thick TiN film is formed on the entire surface by, eg, sputtering. Thus, the adhesion layer 40 formed by the laminated film of the Ti film and the TiN film is formed in the openings 36 a to 36 e and on the interlayer insulating film 34.

  Next, an aluminum film having a thickness of 200 nm is formed on the entire surface by, eg, sputtering.

  Next, the aluminum film and the adhesion layer 40 are patterned using a photolithography technique. Thus, for example, aluminum wiring layers (electrodes) 42a to 42e are formed in the openings 36a to 36e and on the interlayer insulating film 34 (see FIG. 13).

  Thus, the optical semiconductor device according to the present embodiment is formed.

[Second Embodiment]
The optical semiconductor device and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. The same components as those of the optical semiconductor device according to the first embodiment shown in FIGS. 1 to 13 are denoted by the same reference numerals, and description thereof is omitted or simplified.

(Optical semiconductor device)
First, the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 14 is a sectional view of the optical semiconductor device according to the present embodiment.

  The optical semiconductor device according to the present embodiment is mainly characterized in that the resistance layer 25a is formed of a P-type impurity region and the resistance layer 26a is formed of an N-type impurity region.

As shown in FIG. 14, between the P-type impurity region (P ⁺ impurity region) 19 and the P-type impurity region (P ⁺ impurity region) 20, a P-type dopant impurity is introduced at a low concentration. Impurity region (P ^- impurity region) 25a is formed. The concentration of the P-type dopant impurity in the impurity region 25 a is set lower than the concentration of the P-type dopant impurity in the impurity regions 19 and 20. Therefore, the carrier concentration in the impurity region 25 a is lower than the carrier concentration in the impurity regions 19 and 20.

Between the N-type impurity region (N ⁺ impurity region) 23 and the N-type impurity region (N ⁺ impurity region) 24, an impurity region (N ⁻ impurity region) into which an N-type dopant impurity is introduced at a low concentration ) 26a is formed. The concentration of the N-type dopant impurity in the impurity region 26 a is set lower than the concentration of the N-type dopant impurity in the impurity regions 23 and 24. Therefore, the carrier concentration in the impurity region 26 a is lower than the carrier concentration in the impurity regions 23 and 24.

  The resistance value in the impurity region 25a is, for example, about 100 to 500Ω.

  The resistance value in the impurity region 26a is, for example, about 100 to 500Ω.

For example, boron is used as the P-type dopant impurity introduced into the impurity regions 19 and 20. The concentration of the P-type dopant impurity in the impurity regions 19 and 20 is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

For example, boron is used as the P-type dopant impurity to be introduced into the impurity region 25a. The concentration of the P-type dopant impurity in the impurity region 25a is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

For example, phosphorus is used as the N-type dopant impurity to be introduced into the impurity regions 23 and 24. The concentration of the N-type dopant impurity in the impurity regions 23 and 24 is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

For example, phosphorus is used as the N-type dopant impurity to be introduced into the impurity region 26a. The concentration of the N-type dopant impurity in the impurity region 26a is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

  Note that the concentration of the dopant impurity in the impurity region 25a is not limited to the above. It can be set as appropriate so that a desired electrical resistance can be obtained in the impurity region 25a.

  The concentration of the dopant impurity in the impurity region 26a is not limited to the above. It can be set as appropriate so that a desired electric resistance can be obtained in the impurity region 26a.

  Further, the resistance value of the impurity region 25a is not limited to 100 to 500Ω. What is necessary is just to set the resistance value of the impurity region 25a suitably so that a desired high frequency characteristic may be acquired.

  Further, the resistance value of the impurity region 26a is not limited to 100 to 500Ω. What is necessary is just to set the resistance value of the impurity region 26a suitably so that a desired high frequency characteristic may be acquired.

  In the present embodiment, since a P-type impurity region is used as the resistance layer 25a, it is not necessary to apply a bias voltage for forming an inversion layer in the resistance layer 25a to the upper electrode 30a of the capacitor 32a. For this reason, you may electrically short-circuit the wiring layer 42a and the wiring layer 42c.

  In the present embodiment, since an N-type impurity region is used as the resistance layer 26a, it is not necessary to apply a bias voltage for forming an inversion layer in the resistance layer 26a to the upper electrode 30b of the capacitor 32b. For this reason, the wiring layer 42b and the wiring layer 42d may be electrically short-circuited.

  In this case, the signal voltage is applied to the wiring layer 42e. A logic signal is used as a signal applied to the wiring layer 42e. The amplitude of the signal voltage applied to the wiring layer 42e is, for example, not more than the magnitude of the power supply voltage.

  Thus, the resistance layer 25a may be formed of a P-type impurity region, and the resistance layer 26a may be formed of an N-type impurity region.

(Manufacturing method of optical semiconductor device)
Next, the method for fabricating the optical semiconductor device according to the present embodiment will be explained with reference to FIGS. 15 and 16 are process cross-sectional views illustrating the method for manufacturing the optical semiconductor device according to the present embodiment.

  First, from the step of preparing the SOI substrate 16 to the step of forming the N-type impurity regions 21, 23, 24, the optical semiconductor device according to the first embodiment shown in FIGS. 6A to 7B is manufactured. Since it is the same as the method, description is abbreviate | omitted.

  Next, a photoresist film 54 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 54 is patterned using a photolithography technique. Thereby, an opening 55 for forming the impurity region 26 a is formed in the photoresist film 54.

Next, an N-type impurity region (N ^- impurity region, resistance layer) 26a is formed by introducing an N-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 54 as a mask. (See FIG. 15 (a)). The ion implantation conditions are as follows. For example, phosphorus is used as the dopant impurity. The impurity concentration of the N-type impurity region 26a is, for example, about 1 × 10 ¹⁷ cm ⁻³ . The concentration of the N-type dopant impurity introduced into the N-type impurity region 26 a is set lower than the concentration of the N-type dopant impurity introduced into the N-type impurity regions 23 and 24. The carrier concentration of the N-type impurity region 26 a is set lower than the carrier concentration of the N-type impurity regions 23 and 24. The impurity region 26a is formed between the impurity region 23 and the impurity region 24 so as to be parallel to the optical waveguide 18b. The dimension of the impurity region 26a in the left-right direction in FIG. 15A is, for example, about 200 nm.

  Thereafter, the photoresist film 54 is removed by, for example, ashing.

  Next, a photoresist film 56 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 56 is patterned using a photolithography technique. Thus, an opening 57 for forming the impurity region 25a is formed in the photoresist film 56.

Next, a P-type impurity region (P ^- impurity region, resistance layer) 25a is formed by introducing a P-type dopant impurity into the semiconductor layer 14 using, for example, an ion implantation method using the photoresist film 56 as a mask. (See FIG. 15 (b)). The ion implantation conditions are as follows. For example, boron is used as the dopant impurity. The impurity concentration of the P-type impurity region 25a is, for example, about 1 × 10 ¹⁷ cm ⁻³ . The concentration of the P-type dopant impurity introduced into the P-type impurity region 25a is set lower than the concentration of the P-type dopant impurity introduced into the P-type impurity regions 19 and 20. The carrier concentration of the P-type impurity region 25a is set lower than the carrier concentration of the P-type impurity regions 19 and 20. The impurity region 25a is formed between the impurity region 19 and the impurity region 20 so as to be parallel to the optical waveguide 18a. The dimension of the impurity region 25a in the left-right direction in FIG. 15B is about 200 nm, for example.

  Thereafter, the photoresist film 56 is removed by, for example, ashing.

  The subsequent manufacturing method of the optical semiconductor device is the same as the manufacturing method of the optical semiconductor device according to the first embodiment shown in FIGS.

  Thus, the optical semiconductor device according to the present embodiment is manufactured (see FIG. 16).

(Modification)
Next, a modification of the optical semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 17 is a cross-sectional view showing an optical semiconductor device according to this modification.

  The optical semiconductor device according to this modification is mainly characterized in that the resistance layers 25a and 26a are located outside the regions below the upper electrodes 30a and 30b of the capacitors 32a and 32b.

  As shown in FIG. 17, the resistance layer 25a is located outside the region below the upper electrode 30a of the capacitor 32a.

  In addition, the resistance layer 26 a is located outside the region below the upper electrode 30 of the capacitor 32.

  When the resistance layer 25a is arranged between the capacitor 32a and the impurity region 20, good high frequency characteristics cannot be obtained.

  Therefore, when the impurity region 25a is positioned outside the region below the upper electrode 30a of the capacitor 32a, it is not positioned between the capacitor 32a and the impurity region 20, but between the capacitor 32a and the impurity region 19. preferable.

  Therefore, in the present embodiment, the resistance layer 25a is formed on the left side in FIG. 17, that is, on the impurity region 19 side with respect to the upper electrode 30a of the capacitor 32a.

  In addition, when the resistance layer 26a is disposed between the capacitor 32b and the impurity region 23, good high frequency characteristics cannot be obtained.

  Therefore, when the impurity region 26a is located outside the region below the upper electrode 30b of the capacitor 32b, it is not between the capacitor 32b and the impurity region 23 but between the capacitor 32b and the impurity region 24. preferable.

  Therefore, in the present embodiment, the resistance layer 26a is formed on the right side of FIG. 17, that is, on the impurity region 24 side with respect to the upper electrode 30b of the capacitor 32b.

  As described above, the impurity regions 25a and 26a may be arranged outside the regions below the upper electrodes 30a and 30b of the capacitors 32a and 32b.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the above embodiment, the case where a silicon layer is used as the material of the semiconductor layer 14 has been described as an example, but the semiconductor layer 14 is not limited to the silicon layer. For example, an indirect transition type semiconductor layer such as a germanium layer may be used as the semiconductor layer 14.

  In the above embodiment, a silicon oxide film is used as the insulating film 28. However, the insulating film 28 is not limited to a silicon oxide film. For example, an Hf oxide film or the like may be used as the insulating film 28. Further, as the insulating film 28, a silicon nitride film or the like may be used.

  Moreover, although the said embodiment demonstrated to the example the case where the optical waveguides 18a-18f were processed into a rib type, it is not limited to this, You may process the optical waveguides 18a-18f into another shape. .

  In the above embodiment, the case where the optical semiconductor device is operated as an optical modulator has been described as an example. However, the optical semiconductor device is not limited to the optical modulator, and may be operated as an optical switch.

  Regarding the above embodiment, the following additional notes are disclosed.

(Appendix 1)
An intrinsic semiconductor layer formed on a substrate;
A first optical waveguide that is part of the semiconductor layer;
A second optical waveguide that is another part of the semiconductor layer and is formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide;
A first impurity region formed in the semiconductor layer on the second side opposite to the first side of the first optical waveguide and doped with a first conductivity type impurity;
A second impurity region formed in the semiconductor layer on the first side of the first optical waveguide and introduced with an impurity of a second conductivity type opposite to the first conductivity type;
A third impurity region formed in the semiconductor layer on the second side of the second optical waveguide, introduced with a first conductivity type impurity, and connected to the second impurity region;
A fourth impurity region formed in the semiconductor layer on the first side of the second optical waveguide and doped with a second conductivity type impurity;
A first lower electrode which is a part of the second impurity region; a first insulating film formed on at least the first lower electrode; and a first formed on the first insulating film. A first capacitor having a plurality of upper electrodes;
A fifth impurity region formed in the semiconductor layer in a part of the lower region of the first upper electrode and introduced with a second conductivity type impurity;
A second lower electrode which is a part of the fourth impurity region; a second insulating film formed on at least the second lower electrode; and a second insulating film formed on the second insulating film. A second capacitor having a top electrode of
An optical semiconductor device comprising: a sixth impurity region formed in the semiconductor layer in a part of a lower region of the second upper electrode and doped with a first conductivity type impurity.

(Appendix 2)
An intrinsic semiconductor layer formed on a substrate;
A first optical waveguide that is part of the semiconductor layer;
A second optical waveguide that is another part of the semiconductor layer and is formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide;
A first impurity region formed in the semiconductor layer on the second side opposite to the first side of the first optical waveguide and doped with a first conductivity type impurity;
A second impurity region formed in the semiconductor layer on the first side of the first optical waveguide and introduced with an impurity of a second conductivity type opposite to the first conductivity type;
A third impurity region formed in the semiconductor layer on the second side of the second optical waveguide, introduced with a first conductivity type impurity, and connected to the second impurity region;
A fourth impurity region formed in the semiconductor layer on the first side of the second optical waveguide and doped with a second conductivity type impurity;
A first lower electrode which is a part of the first impurity region; at least a first insulating film formed on the first lower electrode; and a first insulating film formed on the first insulating film. A first capacitor having a plurality of upper electrodes;
A fifth impurity region formed in the semiconductor layer on the second side of the first lower electrode and doped with an impurity of a first conductivity type at a lower impurity concentration than the first impurity region;
A second lower electrode which is a part of the fourth impurity region; a second insulating film formed on at least the second lower electrode; and a second insulating film formed on the second insulating film. A second capacitor having a top electrode of
And a sixth impurity region formed in the semiconductor layer on the first side of the second lower electrode and doped with an impurity of a second conductivity type at an impurity concentration lower than that of the fourth impurity region. An optical semiconductor device.

(Appendix 3)
The optical semiconductor device according to claim 1 or 2,
The first upper electrode, the second upper electrode, the fifth impurity region, and the sixth impurity region are formed in parallel with the first optical waveguide and the second optical waveguide. An optical semiconductor device characterized by comprising:

(Appendix 4)
The optical semiconductor device according to any one of claims 1 to 3,
The optical semiconductor device, wherein the semiconductor layer is a silicon layer or a germanium layer.

(Appendix 5)
An intrinsic semiconductor layer formed on the substrate; a first optical waveguide that is part of the semiconductor layer; and another part of the semiconductor layer that is a first side of the first optical waveguide. A second optical waveguide formed parallel to the first optical waveguide; and formed on the semiconductor layer on the second side opposite to the first side of the first optical waveguide; A first impurity region doped with an impurity of a first conductivity type; an impurity of a second conductivity type formed in the semiconductor layer on the first side of the first optical waveguide and opposite to the first conductivity type A second impurity region into which is introduced; and formed in the semiconductor layer on the second side of the second optical waveguide, wherein a first conductivity type impurity is introduced and connected to the second impurity region. A third impurity region; and the semiconductor on the first side of the second optical waveguide A fourth impurity region doped with an impurity of the second conductivity type; a first lower electrode which is a part of the second impurity region; and at least formed on the first lower electrode. A first capacitor having a first insulating film and a first upper electrode formed on the first insulating film; the semiconductor layer in a part of a lower region of the first upper electrode; A fifth impurity region formed and doped with an impurity of the second conductivity type; a second lower electrode which is a part of the fourth impurity region; and at least formed on the second lower electrode A second capacitor having a second insulating film and a second upper electrode formed on the second insulating film; formed on the semiconductor layer in a part of a lower region of the second upper electrode; A sixth impurity region doped with an impurity of the first conductivity type; A first electrode connected to the first impurity region on the second side of the impurity region; a second electrode connected to the second impurity region and the third impurity region; And a third electrode connected to the fourth impurity region on the first side of the sixth impurity region.
Connecting the first electrode to a first potential, connecting the third electrode to a second potential lower than the first potential, and lowering the first upper electrode below the first potential; A third potential higher than the second potential, the second upper electrode connected to a fourth potential lower than the third potential and higher than the second potential, and the third potential; Hereinafter, an input signal that changes in a range equal to or higher than the fourth potential is applied to the second electrode.

(Appendix 6)
An intrinsic semiconductor layer formed on the substrate; a first optical waveguide that is part of the semiconductor layer; and another part of the semiconductor layer that is a first side of the first optical waveguide. A second optical waveguide formed so as to be parallel to the first optical waveguide, and the semiconductor layer on the second side opposite to the first side of the first optical waveguide, A first impurity region doped with a first conductivity type impurity and a second conductivity type impurity formed in the semiconductor layer on the first side of the first optical waveguide and opposite to the first conductivity type; Is formed in the semiconductor layer on the second side of the second optical waveguide, the first conductivity type impurity is introduced, and is connected to the second impurity region. A third impurity region and the semiconductor on the first side of the second optical waveguide A fourth impurity region doped with an impurity of a second conductivity type, a first lower electrode that is a part of the first impurity region, and at least formed on the first lower electrode. A first capacitor having a first insulating film and a first upper electrode formed on the first insulating film; and the semiconductor layer on the second side of the first lower electrode. A fifth impurity region formed and doped with an impurity of a first conductivity type at an impurity concentration lower than that of the first impurity region; a second lower electrode that is a part of the fourth impurity region; and at least A second capacitor having a second insulating film formed on the second lower electrode; a second upper electrode formed on the second insulating film; and a second capacitor formed on the second lower electrode. The fourth impurity region formed in the semiconductor layer on the first side; Ri a sixth driving method for an optical semiconductor device having an impurity region of an impurity of the second conductivity type is introduced at a low impurity concentration,
Connecting the first electrode to a first potential, connecting the third electrode to a second potential lower than the first potential, connecting the first upper electrode to a third potential; The second upper electrode is connected to a fourth potential, and an input signal that changes within a range equal to or lower than the first potential and equal to or higher than the second potential is applied to the second electrode. Driving method of optical semiconductor device.

(Appendix 7)
By etching the intrinsic semiconductor layer formed on the substrate, a first optical waveguide is formed in a part of the semiconductor layer, and other than the semiconductor layer on the first side of the first optical waveguide. Forming a second optical waveguide in parallel with the first optical waveguide in a part of
By introducing a first conductivity type impurity into a region excluding the first predetermined region of the semiconductor layer on the second side opposite to the first side of the first optical waveguide, Forming a first impurity region, and introducing a first conductivity type impurity into the semiconductor layer on the second side of the second optical waveguide, thereby forming a second impurity region;
A third impurity region is formed by introducing an impurity of a second conductivity type into the semiconductor layer on the first side of the first optical waveguide, and the first impurity of the second optical waveguide is formed. A step of forming a fourth impurity region by introducing a second conductivity type impurity into a region of the semiconductor layer on the side excluding the second predetermined region;
Forming a fifth impurity region by introducing a second conductivity type impurity into the semiconductor layer in the first predetermined region;
Forming a sixth impurity region by introducing a first conductivity type impurity into the semiconductor layer in the second predetermined region;
Forming a first upper electrode on the first impurity region and the fifth impurity region via a first insulating film, thereby forming a first lower electrode which is a part of the first impurity region; A first capacitor having the first insulating film and the first upper electrode is formed, and a second insulating film is disposed on the fourth impurity region and the sixth impurity region via the second insulating film. By forming a second upper electrode, a second capacitor having a second lower electrode that is a part of the fourth impurity region, the second insulating film, and the second upper electrode And a method of manufacturing an optical semiconductor device.

(Appendix 8)
By etching the intrinsic semiconductor layer formed on the substrate, a first optical waveguide is formed in a part of the semiconductor layer, and other than the semiconductor layer on the first side of the first optical waveguide. Forming a second optical waveguide in parallel with the first optical waveguide in a part of
By introducing a first conductivity type impurity into a region excluding the first predetermined region of the semiconductor layer on the second side opposite to the first side of the first optical waveguide, Forming a first impurity region, and introducing a first conductivity type impurity into the semiconductor layer on the second side of the second optical waveguide, thereby forming a second impurity region;
A third impurity region is formed by introducing an impurity of a second conductivity type into the semiconductor layer on the first side of the first optical waveguide, and the first impurity of the second optical waveguide is formed. A step of forming a fourth impurity region by introducing a second conductivity type impurity into a region of the semiconductor layer on the side excluding the second predetermined region;
Forming a fifth impurity region having an impurity concentration lower than that of the first impurity region by introducing a first conductivity type impurity into the semiconductor layer in the first predetermined region;
Forming a sixth impurity region having an impurity concentration lower than that of the fourth impurity region by introducing a second conductivity type impurity into the semiconductor layer in the second predetermined region;
A first upper electrode is formed on the first impurity region on the first side of the fifth impurity region with a first insulating film interposed therebetween, whereby a part of the first impurity region is formed. Forming a first capacitor having a first lower electrode, the first insulating film, and the first upper electrode; and forming the fourth capacitor on the second side of the sixth impurity region. By forming a second upper electrode over the impurity region via a second insulating film, a second lower electrode which is a part of the fourth impurity region, the second insulating film, Forming a second capacitor having a second upper electrode. A method for manufacturing an optical semiconductor device, comprising:

(Appendix 9)
In the manufacturing method of the optical semiconductor device according to claim 7 or 8,
In the step of forming the fifth impurity region, the fifth impurity region is formed in parallel with the first optical waveguide,
In the step of forming the sixth impurity region, the sixth impurity region is formed in parallel with the second optical waveguide,
In the step of forming the first capacitor and the second capacitor, the first upper electrode is formed so as to be parallel to the first optical waveguide, and the second upper electrode is formed as the second light guide. An optical semiconductor device manufacturing method, wherein the optical semiconductor device is formed in parallel with a waveguide.

(Appendix 10)
In the manufacturing method of the optical semiconductor device according to any one of claims 7 to 9,
The method for manufacturing an optical semiconductor device, wherein the semiconductor layer is a silicon layer or a germanium layer.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, silicon substrate 12 ... Insulating film, buried insulating film 14 ... Semiconductor layer, silicon layers 14a, 14b ... I-type semiconductor 15 ... SOI substrates 16a, 16b ... PIN structure, PIN diodes 18a-18f ... Optical waveguide 19 ... P-type impurity region 20 ... P-type impurity region 21 ... N-type impurity region 22 ... P-type impurity region 23 ... N-type impurity region 24 ... N-type impurity region 25 ... N-type impurity region 25a ... P-type impurity region 26 ... P-type Impurity region 26a ... N-type impurity region 28 ... insulating film 30 ... polysilicon film 30a ... P-type polysilicon film, upper electrode 30b ... N-type polysilicon film, upper electrodes 32a, 30b ... capacitor 34 ... interlayer insulating film 36a ... 36e ... opening 38 ... silicide film 40 ... adhesion layers 42a to 42e ... wiring layer, electrode 44 ... photoresist film 46 ... photoresist Film 48a-48c ... opening 50 ... photoresist film 52a-52c ... opening 54 ... photoresist film 55 ... opening 56 ... photoresist film 57 ... opening 58 ... photoresist film 60 ... opening 62 ... photoresist Film 64 ... opening 66 ... photoresist film

Claims (6)

An intrinsic semiconductor layer formed on a substrate;
A first optical waveguide that is part of the semiconductor layer;
A second optical waveguide that is another part of the semiconductor layer and is formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide;
A first impurity region formed in the semiconductor layer on the second side opposite to the first side of the first optical waveguide and doped with a first conductivity type impurity;
A second impurity region formed in the semiconductor layer on the first side of the first optical waveguide and introduced with an impurity of a second conductivity type opposite to the first conductivity type;
A third impurity region formed in the semiconductor layer on the second side of the second optical waveguide, introduced with a first conductivity type impurity, and connected to the second impurity region;
A fourth impurity region formed in the semiconductor layer on the first side of the second optical waveguide and doped with a second conductivity type impurity;
A first lower electrode which is a part of the second impurity region; a first insulating film formed on at least the first lower electrode; and a first formed on the first insulating film. A first capacitor having a plurality of upper electrodes;
A fifth impurity region formed in the semiconductor layer in a part of the lower region of the first upper electrode and introduced with a second conductivity type impurity;
A second lower electrode which is a part of the fourth impurity region; a second insulating film formed on at least the second lower electrode; and a second insulating film formed on the second insulating film. A second capacitor having a top electrode of
An optical semiconductor device comprising: a sixth impurity region formed in the semiconductor layer in a part of a lower region of the second upper electrode and doped with a first conductivity type impurity. An intrinsic semiconductor layer formed on a substrate;
A first optical waveguide that is part of the semiconductor layer;
A second optical waveguide that is another part of the semiconductor layer and is formed on the first side of the first optical waveguide so as to be parallel to the first optical waveguide;
A first impurity region formed in the semiconductor layer on the second side opposite to the first side of the first optical waveguide and doped with a first conductivity type impurity;
A second impurity region formed in the semiconductor layer on the first side of the first optical waveguide and introduced with an impurity of a second conductivity type opposite to the first conductivity type;
A third impurity region formed in the semiconductor layer on the second side of the second optical waveguide, introduced with a first conductivity type impurity, and connected to the second impurity region;
A fourth impurity region formed in the semiconductor layer on the first side of the second optical waveguide and doped with a second conductivity type impurity;
A first lower electrode which is a part of the first impurity region; at least a first insulating film formed on the first lower electrode; and a first insulating film formed on the first insulating film. A first capacitor having a plurality of upper electrodes;
A fifth impurity region formed in the semiconductor layer on the second side of the first lower electrode and doped with an impurity of a first conductivity type at a lower impurity concentration than the first impurity region;
A second lower electrode which is a part of the fourth impurity region; a second insulating film formed on at least the second lower electrode; and a second insulating film formed on the second insulating film. A second capacitor having a top electrode of
And a sixth impurity region formed in the semiconductor layer on the first side of the second lower electrode and doped with an impurity of a second conductivity type at an impurity concentration lower than that of the fourth impurity region. An optical semiconductor device. The optical semiconductor device according to claim 1 or 2,
The first upper electrode, the second upper electrode, the fifth impurity region, and the sixth impurity region are formed in parallel with the first optical waveguide and the second optical waveguide. An optical semiconductor device characterized by comprising: The optical semiconductor device according to any one of claims 1 to 3,
The optical semiconductor device, wherein the semiconductor layer is a silicon layer or a germanium layer. An intrinsic semiconductor layer formed on the substrate; a first optical waveguide that is part of the semiconductor layer; and another part of the semiconductor layer that is a first side of the first optical waveguide. A second optical waveguide formed parallel to the first optical waveguide; and formed on the semiconductor layer on the second side opposite to the first side of the first optical waveguide; A first impurity region doped with an impurity of a first conductivity type; an impurity of a second conductivity type formed in the semiconductor layer on the first side of the first optical waveguide and opposite to the first conductivity type A second impurity region into which is introduced; and formed in the semiconductor layer on the second side of the second optical waveguide, wherein a first conductivity type impurity is introduced and connected to the second impurity region. A third impurity region; and the semiconductor on the first side of the second optical waveguide A fourth impurity region doped with an impurity of the second conductivity type; a first lower electrode which is a part of the second impurity region; and at least formed on the first lower electrode. A first capacitor having a first insulating film and a first upper electrode formed on the first insulating film; the semiconductor layer in a part of a lower region of the first upper electrode; A fifth impurity region formed and doped with an impurity of the second conductivity type; a second lower electrode which is a part of the fourth impurity region; and at least formed on the second lower electrode A second capacitor having a second insulating film and a second upper electrode formed on the second insulating film; formed on the semiconductor layer in a part of a lower region of the second upper electrode; A sixth impurity region doped with an impurity of the first conductivity type; A first electrode connected to the first impurity region on the second side of the impurity region; a second electrode connected to the second impurity region and the third impurity region; And a third electrode connected to the fourth impurity region on the first side of the sixth impurity region.
Connecting the first electrode to a first potential, connecting the third electrode to a second potential lower than the first potential, and lowering the first upper electrode below the first potential; A third potential higher than the second potential, a second upper electrode connected to a fourth potential lower than the third potential and higher than the second potential, and an input signal A method for driving an optical semiconductor device, comprising: applying to the second electrode. An intrinsic semiconductor layer formed on the substrate; a first optical waveguide that is part of the semiconductor layer; and another part of the semiconductor layer that is a first side of the first optical waveguide. A second optical waveguide formed so as to be parallel to the first optical waveguide, and the semiconductor layer on the second side opposite to the first side of the first optical waveguide, A first impurity region doped with a first conductivity type impurity and a second conductivity type impurity formed in the semiconductor layer on the first side of the first optical waveguide and opposite to the first conductivity type; Is formed in the semiconductor layer on the second side of the second optical waveguide, the first conductivity type impurity is introduced, and is connected to the second impurity region. A third impurity region and the semiconductor on the first side of the second optical waveguide A fourth impurity region doped with an impurity of a second conductivity type, a first lower electrode that is a part of the first impurity region, and at least formed on the first lower electrode. A first capacitor having a first insulating film and a first upper electrode formed on the first insulating film; and the semiconductor layer on the second side of the first lower electrode. A fifth impurity region formed and doped with an impurity of a first conductivity type at an impurity concentration lower than that of the first impurity region; a second lower electrode that is a part of the fourth impurity region; and at least A second capacitor having a second insulating film formed on the second lower electrode; a second upper electrode formed on the second insulating film; and a second capacitor formed on the second lower electrode. The fourth impurity region formed in the semiconductor layer on the first side; Ri a sixth driving method for an optical semiconductor device having an impurity region of an impurity of the second conductivity type is introduced at a low impurity concentration,
Connecting the first electrode to a first potential, connecting the third electrode to a second potential lower than the first potential, connecting the first upper electrode to a third potential; A method for driving an optical semiconductor device, comprising: connecting the second upper electrode to a fourth potential; and applying an input signal to the second electrode.

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