JP2012002995A - 3d image display system and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accomplish stable image displaying with a high AC drive frequency, restraint on luminance abnormality due to an error attributable to a difference in characteristics of a pixel circuit and stable 3D image displaying in the minimum necessary data transfer bandwidth.SOLUTION: An inverting circuit 101, a DAC 102 and a source driver 103 simultaneously supply in succession, within one horizontal scanning period, a positively polarized image signal and a negatively polarized image signal obtained from one of an image signal for the right eye and an image signal for the left eye to each of two row signal lines D1 and D2 of each set, switch over between the positively polarized image signal and the negatively polarized image signal in every one frame period, and supply the positively polarized image signal and the negatively polarized image signal, switched over in every one frame period, to each of the two row signal lines, wherein each pixel 105 has two signal holding capacitances and, after holding an image signal voltage in each, alternately reads it out in every 1/2 frame period to supply it to a pixel electrode.

Description

  The present invention relates to a stereoscopic video display system and a liquid crystal display device, and more particularly, to a stereoscopic video display system for stereoscopic viewing using glasses and an active matrix liquid crystal display device suitable for a projection type liquid crystal display used therefor.

  FIG. 8 is a cross-sectional view showing the structure of one pixel of an example of a conventional liquid crystal display device. As shown in the figure, the pixel cell 10 has a structure in which a pixel electrode 14, a liquid crystal layer 13, a transparent common electrode 12, and a glass 11 are laminated on a silicon substrate 15 on which a pixel circuit 16 is formed. The liquid crystal layer 13 is sandwiched between the transparent common electrode 12 and the pixel electrode 14. The pixel circuit 16 is formed in the silicon substrate 15 and includes column signal lines, row scanning line input lines, and output lines to the pixel electrodes 14.

  In the pixel cell 10 having such a structure, the polarization of light passing through the liquid crystal layer 13 is rotated by the liquid crystal layer 13, and the degree of the rotation depends on the voltage asserted to the liquid crystal layer 13. The ability to rotate polarized light is used to modulate the intensity of reflected light as follows.

  Incident light 1 is previously polarized by polarizing plate 2a. The polarized light passes through the glass 11, the transparent common electrode 12, and the liquid crystal layer 13, enters the pixel electrode 14, is reflected there, and passes through the liquid crystal layer 13 again. The polarized light is rotated by an amount depending on the voltage asserted between the pixel electrode 14 and the transparent common electrode 12 while passing through the liquid crystal layer 13 twice.

  Next, the polarized light that has passed through the liquid crystal layer 13 passes through the transparent common electrode 12 and the glass 11, and only light having a designated polarization direction passes through the polarizing plate 2b. Therefore, the intensity of the light passing through the polarizing plate 2b depends on the degree of polarization rotation caused by the liquid crystal layer 13, and the degree of rotation is similarly the voltage asserted between the pixel electrode 14 and the transparent common electrode 12. Dependent.

  FIG. 9 shows an equivalent circuit diagram of one pixel of an example of a conventional liquid crystal display element. As shown in the figure, the pixel circuit 16 is connected to a field effect transistor (FET) Q1 whose gate is connected to the row scanning line W and whose drain is connected to the column signal line D, and to the source of the FET Q1. It comprises a signal holding capacitor C1 ′. The signal holding capacitor C1 'is connected to the pixel electrode 14 (pixel electrode 14 in FIG. 8) of the liquid crystal element LC. The liquid crystal element LC is configured such that a fixed voltage Vcom is applied to the common electrode 12 (transparent common electrode 12 in FIG. 8).

  In the pixel circuit 16, the column signal line D is asserted to a voltage necessary for holding. Next, when the row scanning line W is asserted to the on voltage, the FET Q1 is turned on, and the voltage asserted to the column signal line D is held in the signal holding capacitor C1 ′ through the drain and source of the FET Q1. . The voltage held in the signal holding capacitor C1 'is various voltages according to the video signal. Since the signal holding capacitor C1 'is connected to the pixel electrode 14, the pixel electrode 14 is driven by the voltage held in the signal holding capacitor C1'. Thereby, the liquid crystal element C has a light modulation rate of the liquid crystal layer 13 due to a potential difference between the drive voltage applied to the pixel electrode 14 from the signal holding capacitor C1 ′ and the fixed voltage Vcom applied to the transparent common electrode 12. It is controlled and displays an image according to the drive voltage.

  FIG. 10 shows a basic configuration diagram of an example of a conventional liquid crystal display device. In the figure, a liquid crystal display device 4 is an active matrix liquid crystal display device including a source driver 5, a gate driver 6, and a pixel unit 7. The pixel unit 7 includes a plurality of pixels 8 arranged in a two-dimensional matrix. Each pixel 8 has the configuration shown in FIGS.

In the liquid crystal display device 4, input data (PHM: voltage value) is input to the source driver 5. The source driver 5 asserts each column signal line with the sequentially input voltage. In synchronization with the asserting timing, the gate driver 6 sequentially applies voltages for turning on the switching elements (corresponding to the FET Q1 in FIG. 9) in the plurality of pixels 8 arranged in each row of the pixel unit 7 for each row. Assert. As a result, the data input from the source driver 5 is held in the signal holding capacitors (corresponding to C1 ′ in FIG. 9) arranged in each pixel 8.
The data held in the signal holding capacitor drives the pixel electrode 14 of each pixel 8.

  The gate driver 6 includes a shift register 61 and a level shifter 62. The shift register 61 outputs to the level shifter 62 a selection signal for sequentially selecting each row of the pixel unit 7 in units of rows in synchronization with the timing at which the source driver 5 sequentially asserts each column signal line. The level shifter 62 shifts the level to the driving voltage of the switching element (corresponding to the FET Q1 in FIG. 9) in each pixel 8 according to the selection signal from the shift register 61, and sequentially shifts the plurality of pixels 8 in each row of the pixel unit 7 to each other. Selection is performed from the top to the bottom of the pixel unit 7 in units of rows.

  Further, since the liquid crystal element (LC in FIG. 9) in each pixel 8 can be stabilized for a long time by alternating current driving, the common electrode of the liquid crystal element (transparent common electrode 12 in FIGS. 8 and 9). The pixel electrode (14 in FIGS. 8 and 9) of the liquid crystal element has a positive voltage and a negative voltage that have the same light modulation rate according to the video signal. Alternating drive is given alternately.

  In some cases, for the purpose of reducing the dynamic range of the video signal, there is an application example in which the common voltage is switched according to the timing of driving the pixel electrode alternately with the positive and negative voltages. The same idea is the same.

  Here, the video data voltage held in the signal holding capacitor in each pixel is held in the vertical scanning period of the gate driver. Therefore, the above-described conventional active matrix liquid crystal display device has a feature that a high image quality characteristic can be obtained by high duty ratio driving because the pixel electrode can be continuously asserted at the same voltage during the vertical scanning period.

  However, in the above-described conventional active matrix liquid crystal display device, rewriting of video data for each pixel 8 is performed every vertical scanning period (one frame) of the gate driver 6, so that the transparent common electrode is alternately used every frame. On the other hand, the video signal data voltages on the positive side and the negative side are written in the signal holding capacitor, and the liquid crystal element is AC driven, which has a drawback that the AC driving frequency of the liquid crystal element is low.

  Up to now, countermeasures against feedthrough caused by parasitic capacitance of each switching element (corresponding to FET Q1 in FIG. 9) in the pixel 8 (for example, refer to Patent Document 1) and signal holding capacitance (corresponding to C1 ′ in FIG. 9). And the like (see, for example, Patent Document 2), a method for preventing deterioration of written video data is disclosed. However, it seems that the approach of alternating-current driving the liquid crystal element with a higher number of peripheral liquids has not been studied much.

  On the other hand, in the case of a general liquid crystal element, when a DC voltage is applied to the liquid crystal element, an ion balance in the liquid crystal layer is lost, and a burn-in phenomenon that the liquid crystal element does not move occurs. Therefore, the voltage asserted to the transparent common electrode of the liquid crystal element has an offset in advance. That is, as shown in FIG. 11, the voltage applied to the pixel electrode of the liquid crystal element is a positive voltage of V_LC with respect to the voltage (Vcom) asserted to the transparent common electrode in the DC balance + period. In the DC balance period, the voltage is negative by V_LC with respect to the voltage (Vcom) asserted to the transparent common electrode.

  In other words, it is necessary to assert data to the signal holding capacitor in the pixel so that the pixel electrode can be asserted at least two different voltages in order to display one piece of image data. In this way, it is necessary to adjust the driving of the liquid crystal element so that the direction of the potential in the liquid crystal layer within a certain time with respect to the liquid crystal element becomes zero.

  For this reason, the pixel circuit of FIG. 9 requires a DC balance + direction and a DC balance − direction, and a voltage twice as high as that required for liquid crystal modulation. There is a problem that the withstand voltage becomes large, which causes an increase in cost.

  FIG. 12 is a timing chart for explaining the above driving method of the liquid crystal element. As shown in the figure, in order to make the data transfer period in which the liquid crystal element is not driven shorter than the drive period and to efficiently transfer data to the liquid crystal element, the drive is performed with the time axis shifted for each line. Further, in order to make the DC balance zero, the voltage applied to the pixel electrode is a positive voltage in the DC balance + period and the DC balance + period that alternately appear as shown in FIG. In the DC balance period, the voltage is negative.

  By the way, in the liquid crystal display device, a right-eye image displayed on the liquid crystal display device in the projector is projected onto the screen, and a left-eye image switched and displayed on the liquid crystal display device in the projector is projected onto the screen as one frame. Frame-switching type 3D display that repeats alternately within the period, and alternately switches between light transmission through one of the right eye and left eye of a pair of glasses equipped with a liquid crystal shutter and light blocking the other. The device is known.

  According to this stereoscopic display device, the displayed right-eye image is imaged on the retina through the viewer's right eye by selecting the right eye portion of the glasses for light transmission, and the left-eye image displayed subsequently is the glasses. By selecting the left eye portion for light transmission, an image is formed on the retina through the viewer's left eye, and the viewer can integrate it in the brain and perceive it as a color stereoscopic image.

  However, as the liquid crystal display device in the above-described stereoscopic display device, a line drive type liquid crystal display device that is driven with a time axis shifted for each line in order to shorten the time during which the liquid crystal element is not driven, as described with reference to FIGS. Is difficult to apply. The reason is that in a liquid crystal display device in a stereoscopic display device, it is necessary to switch the entire screen at the same time, but in a line drive type liquid crystal display device, an image corresponding to the previous subframe and an image corresponding to the current subframe are This is because the switching pixels of the pixels proceed line-sequentially.

  Therefore, conventionally, two holding capacitors are provided in the pixel circuit, and one holding capacitor holds the image data of one of the odd-numbered subframe and the even-numbered subframe while the other holding capacitor already holds the image data. A liquid crystal display device configured to alternately read out image data of the other subframe and drive the pixel electrode for each of the two storage capacitors every subframe period has been proposed (for example, (See Patent Document 4).

JP 2006-10897 A JP 2002-250938 A JP 2004-354742 A JP 2000-227782 A

  However, as described above, it is desirable to drive the liquid crystal element with an alternating current at a high frequency as a means for improving reliability such as prevention of burn-in of the liquid crystal element, but it is asserted to the common electrode due to restrictions such as writing time to the pixel. It is difficult to alternately write the video data on the positive side and the negative side with respect to the voltage (Vcom) at high speed. Conventionally, the frequency of AC driving is only performed at the frame rate or about twice that frequency.

  In addition, the voltage (Vcom) asserted to the common electrode of the liquid crystal element has an offset in advance, so that the liquid crystal element is driven so that the potential direction in the liquid crystal layer is zero within a certain period. However, if the above-mentioned fixed period is long, that is, if the AC driving frequency of the liquid crystal element is a frame rate or a frequency that is twice as low as that of the frame rate, the ion balance in the liquid crystal layer can be easily lost, and reliability / stability There is a problem of being easily affected.

  Further, since the conventional liquid crystal display device is configured to perform display by pixel rewriting in the vertical scan by the gate driver, as shown in FIG. 11, the voltage (Vcom) asserted to the common electrode is kept constant while the DC voltage is constant. It is necessary to change the direction of the potential of the pixel electrode between the balance + period and the DC balance-period. For this reason, in the conventional liquid crystal display device, it is necessary to have the ability to hold a voltage twice as high as that required for the modulation of the liquid crystal in the signal holding capacitor in the pixel, which increases the cost of the liquid crystal display device. .

  In the liquid crystal display device described in Patent Document 3, the polarity of the compensation voltage can be reversed only for each frame, and the image signal voltage is on the positive side and the negative side with respect to the voltage (Vcom) asserted to the common electrode. Two types of voltage are required.

  Further, in the conventional liquid crystal display device described in Patent Document 1, each image data is alternately supplied and held in units of subframes in the two holding capacitors in the pixel circuit, so that the reliability is improved. However, when increasing the number of times of polarity reversal, it is necessary to increase the data transfer band, which causes a problem in reliability. Further, in the above conventional liquid crystal display device, it is necessary to re-hold the image data for polarity inversion in order to set the DC balance essential for driving the liquid crystal element to 0, and therefore a buffer for one frame is also necessary. It becomes. Furthermore, a luminance abnormality may occur due to a difference in characteristics of a circuit unit that supplies a video signal to two storage capacitors in the pixel circuit.

  The present invention has been made in view of the above points, can increase the AC drive frequency, can perform a stable video display, and can suppress luminance abnormality due to errors caused by differences in the characteristics of the pixel circuit, It is another object of the present invention to provide a stereoscopic video display system and a liquid crystal display device capable of performing a stable stereoscopic video display operation with a minimum necessary data transfer band.

  In order to achieve the above object, the stereoscopic video display system of the present invention transfers a video signal for one of a right-eye video signal and a left-eye video signal for a first transfer period and a first transfer period. A first pixel driving period for displaying one video signal, a second transfer period for transferring the other video signal of the right-eye video signal and the left-eye video signal, and the other of the other signals transferred in the second transfer period. Image display means including a liquid crystal display device that cyclically switches in a cycle of two frame periods in the order of a second pixel drive period for displaying a video signal, and at least a first pixel drive period of the liquid crystal display device Only the eye corresponding to the image to be displayed among the right eye and the left eye of the observer is used to display the light of the image based on one video signal and the light of the image based on the other video signal displayed in the second pixel driving period. Binocular to be incident on Characterized in that it comprises a glasses utilizing difference.

  Here, the liquid crystal display device includes a plurality of pixels connected to each intersection of a plurality of column signal lines each including two column signal lines, and a plurality of row scanning lines, and a plurality of pixels. A positive-polarity video signal and a negative-polarity video signal obtained from one of the right-eye video signal and the left-eye video signal are simultaneously applied to each of a pair of two column signal lines of the pair of column signal lines. The supply is sequentially performed on a plurality of sets of column signal lines in units of sets within one horizontal scanning period, and a positive video signal and a negative video signal are switched every frame period, and one frame is supplied. Video signal supply means for switching and supplying a positive video signal and a negative video signal to each of two column signal lines for each period, and a row for selecting a plurality of row scanning lines for each horizontal scanning period. A selection signal is sequentially supplied to a plurality of row scanning lines so that a plurality of pixels A row selection signal supply means for selecting in units of rows and a plurality of selection signal lines including a pair of two selection signal lines are connected in units of groups for each pixel in each row among a plurality of pixels, Pixel drive selection signal supply means for supplying two pixel drive selection signals which are rectangular waves having a predetermined cycle shorter than one vertical scanning cycle and having a logic value opposite to each other to two sets of selection signal lines; , Reset signal supply means for supplying a reset signal at a predetermined timing to a reset control line connected to each pixel in each row of the plurality of pixels, and one of the right-eye video signal and the left-eye video signal A first transfer period for transferring a signal, a first pixel drive period for displaying one video signal transferred in the first transfer period, and the other video signal among the right-eye video signal and the left-eye video signal. A second transfer period to transfer and Video signal supply means, pixel drive selection signal supply means, and so on, so as to perform a cyclic switching operation in a cycle of two frame periods in the order of the second pixel drive period for displaying the other video signal transferred in the second transfer period. Each of the plurality of pixels includes a liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and a pair of two Sampling and holding means for sampling a positive-polarity video signal or a negative-polarity video signal supplied via one of the column signal lines and holding it as a first video signal voltage for a certain period; Second sampling in which a negative video signal or a positive video signal supplied via the other column signal line of a set of two column signal lines is sampled and held as a second video signal voltage for a certain period of time. And a first video signal voltage held by the first sampling and holding means, and a second video signal voltage held by the second sampling and holding means, and two pixel drive selection signals. And a switching unit that alternately switches the pixel electrode in a predetermined cycle and applies the pixel electrode to the pixel electrode, and a reset unit that resets the holding voltage held in the parasitic capacitance in the vicinity of the pixel electrode by a reset signal.

  In order to achieve the above object, the stereoscopic video display system of the present invention includes a right-eye liquid crystal shutter and a left-eye liquid crystal shutter in which the glasses are controlled to be opened and closed independently of each other in the right eye part and the left eye part. In the first and second transfer periods, both the right-eye liquid crystal shutter and the left-eye liquid crystal shutter are controlled to be in a closed state that blocks light, and in the first and second pixel driving periods, the right-eye liquid crystal shutter and the left-eye liquid crystal shutter are controlled. Among the liquid crystal shutters for use, only the right-eye liquid crystal shutter or the left-eye liquid crystal shutter corresponding to the displayed right-eye image or left-eye image is shutter glasses that are controlled to be in an open state that transmits light.

In order to achieve the above object, the liquid crystal display device of the present invention is provided at each intersection of a plurality of column signal lines each composed of two column signal lines and a plurality of row scanning lines. Positive video obtained from one of the right-eye video signal and the left-eye video signal on each of a plurality of connected pixels and a set of two column signal lines of the plurality of column signal lines. The signal and the negative polarity video signal are simultaneously supplied to a plurality of sets of column signal lines in units of sets within one horizontal scanning period, and the positive polarity video signal and the negative polarity video signal are provided every frame period. Video signal supply means for switching and supplying a positive video signal and a negative video signal to each of two column signal lines every one frame period, and horizontal scanning of a plurality of row scanning lines A plurality of row scanning lines select a row selection signal for each period. A row selection signal supply means for sequentially supplying and selecting a plurality of pixels in units of rows and a plurality of sets of selection signal lines each including two selection signal lines are provided for each pixel in each row of the plurality of pixels. Two pixel drive selection signals which are rectangular waves having a predetermined cycle shorter than one vertical scanning cycle and having a relation of opposite logic values to two selection signal lines of each set. A pixel drive selection signal supply means for supplying a reset signal, a reset signal supply means for supplying a reset signal at a predetermined timing to a reset control line connected to each pixel of each row among a plurality of pixels, and a video signal for the right eye And a first transfer period for transferring one of the video signals for the left eye, a first pixel driving period for displaying one video signal transferred in the first transfer period, a video signal for the right eye, and a left eye Video signal for video The video signal so as to perform a cyclic switching operation in a cycle of 2 frame periods in the order of the second transfer period for transferring the second video signal and the second pixel drive period for displaying the other video signal transferred in the second transfer period. A control means for controlling the supply means, the pixel drive selection signal supply means and the reset signal supply means,
Each of the plurality of pixels is supplied via a liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode, and one column signal line of a set of two column signal lines. Sampling and holding means for sampling a positive-polarity video signal or a negative-polarity video signal to be held as a first video signal voltage for a certain period, and the other column signal of a set of two column signal lines A second sampling and holding means for sampling a negative-polarity video signal or a positive-polarity video signal supplied via a line and holding it as a second video signal voltage for a certain period, and held by the first sampling and holding means The first video signal voltage and the second video signal voltage held by the second sampling and holding means are alternately switched at a predetermined cycle by the two pixel drive selection signals to be applied to the pixel electrode. Comprising a switching means, and reset means for resetting by a reset signal holding voltage held in the parasitic capacitance existing in the vicinity of the pixel electrodes,
In the first and second transfer periods, the control means outputs a reset signal from the reset signal supply means, resets the holding voltage held in the parasitic capacitance near the pixel electrode, and then supplies the video signal. The positive and negative video signals of the right-eye video signal or the left-eye video signal, which are switched every frame period by controlling the means, are supplied to the two column signal lines of each set, and the first and second The sampling and holding means hold the first and second video signal voltages respectively, and in the first and second pixel driving periods, the pixel driving selection signal supply means is controlled to output two pixel driving selection signals. The first video signal voltage held by the first sampling and holding means and the second video signal voltage held by the second sampling and holding means are alternately switched at a predetermined cycle. Instead, it characterized in that applied to the pixel electrode.

  According to the present invention, it is possible to eliminate the need for a buffer for one frame for re-holding image data for polarity inversion to make the DC balance essential for driving the liquid crystal element zero, and to provide the minimum necessary data. A stable image display operation can be performed in the transfer band, and a liquid crystal display device suitable for a sequential color system or a stereoscopic display system can be realized.

  Further, according to the present invention, even if there is an error due to the characteristics of the transistor between the two voltage write / read circuit units for each of the two signal holding capacitors in one pixel, the error is reduced. By canceling between two frames, it is possible to visually reduce luminance abnormality caused by an error.

1 is a basic configuration diagram of an embodiment of a liquid crystal display device of the present invention. It is a block diagram of an example of the inverting circuit in FIG. It is an equivalent circuit diagram of one embodiment of one pixel in the liquid crystal display device of the present invention. 4 is a timing chart for explaining the operation of an embodiment of the liquid crystal display device of the present invention. It is a schematic diagram explaining an example of each applied voltage of the pixel electrode and transparent common electrode of the liquid crystal element in one embodiment of the liquid crystal display device of the present invention. It is a schematic diagram explaining the switching period of the liquid crystal shutter of the video signal transfer period and video signal drive period and shutter glasses in an embodiment of the stereoscopic video display system and the liquid crystal display device of the present invention. 1 is a schematic configuration diagram of an embodiment of a stereoscopic video display system of the present invention. It is sectional drawing which shows the structure of one pixel of an example of the conventional liquid crystal display device. It is an equivalent circuit diagram of one pixel of an example of a conventional liquid crystal display device. It is a drive circuit block diagram of an example of the conventional liquid crystal display device. It is a schematic diagram explaining an example of DC balance of the liquid crystal element in the conventional liquid crystal display device. It is a schematic diagram explaining an example of the driving method of the conventional liquid crystal display device.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a basic configuration diagram of an embodiment of a liquid crystal display device according to the present invention. In the figure, a liquid crystal display device 100 of this embodiment includes an inverting circuit 101, a DA converter (hereinafter referred to as DAC) 102, a source driver 103, a pixel unit 104, a gate driver 106, an AND circuit 107, and an AND circuit 108. An active matrix including a plurality of selection signal lines each including a reset signal line R connected to each pixel in the row direction and two selection signal lines through which the pixel drive selection signals S1 and S2 are transmitted. Type liquid crystal display device.

  The inversion circuit 101 performs predetermined inversion processing from the input video data DATA, which is a digital video signal, with an external select signal SEL, and generates and outputs two types of digital data DATA1 and DATA2. Here, the inversion processing is processing for switching two types of video signal voltages supplied to the column signal lines D1 and D2 for each frame period.

  FIG. 2 shows a block diagram of an example of the inverting circuit 101. As shown in the figure, the inverting circuit 101 includes a first selector 1011 in which video data DATA is input to the A input terminal, a second selector 1012 in which video data DATA is input to the B input terminal, and video data. And an arithmetic unit 1013 that calculates and generates data DATA (V−) from DATA. The selectors 1011 and 1012 each have two input terminals, an A input terminal and a B input terminal. When the select signal SEL is at a high level, the selector 1011 and 1012 select and output the input signal at the A input terminal, and the select signal SEL is low. At the level, the input signal at the B input terminal is selected and output.

  For example, when DATA of value X is input, the arithmetic unit 1013 calculates a value (= MAX−X) obtained by subtracting the value X of the input data DATA from the maximum value MAX of DATA, and the calculated value is B of the selector 1011. Output to the input terminal and the A input terminal of the selector 1012 respectively. Here, it is assumed that the input video data DATA of the inverting circuit 101 is expressed as DATA (V +) for DC balance +, and the output value of the arithmetic unit 1013 is expressed as DATA (V−) for DC balance−. DATA (V +) for DC balance + is positive-polarity video data. When the value is the maximum value, the maximum gradation (white level) is indicated, and when the value is the minimum value, the minimum gradation (black level) is indicated. On the other hand, DATA (V-) for DC balance is negative-polarity video data. When the value is the maximum value, the minimum gradation (black level) is indicated, and when the value is the minimum value, the maximum gradation (white level) is indicated. .

  The selector 1011 selects DATA (V +) input to the A input terminal when the select signal SEL is high level, and selects DATA (V-) input to the B input terminal when the select signal SEL is low level. Each of them is output as first data DATA1. On the other hand, the selector 1012 selects DATA (V−) input to the A input terminal when the select signal SEL is high level, and DATA (V +) input to the B input terminal when the select signal SEL is low level. Are selected and output as second data DATA2, respectively. Therefore, when one of the data DATA1 and DATA2 is DATA (V +), the other is DATA (V-), and the value is switched according to the logical value of the select signal SEL.

  Returning again to FIG. The DAC 102 receives the data DATA1 and DATA2 from the inverting circuit 101 as input signals, converts the input signals from digital to analog, and outputs two types of analog video signal voltages DA1 and DA2.

  The source driver 103 sequentially shifts the video signal voltages DA1 and DA2 supplied from the DAC 102 in the horizontal direction within one horizontal scanning period and sequentially every pixel transmission period. The source driver 103 has a plurality of shift signal output terminals connected to a plurality of column signal lines each including two column signal lines (data lines) D1 and D2, and each shift signal output terminal. The output of the shifted video signal voltage DA1 to the column signal line D1 and the output of the shifted video signal voltage DA2 to the column signal line D2 are sequentially performed in units of column signal lines within one horizontal scanning period. Do.

  As described above, the source driver 103 applies the video signal voltage DA1 and the video signal voltage DA2 to the plurality of column signal lines each including the two column signal lines D1 and D2 for one horizontal scanning period. Are supplied sequentially in pairs. However, as will be described later, the period during which the source driver 103 supplies the video signal voltages DA1 and DA2 to a plurality of sets of column signal lines each including two column signal lines D1 and D2 is 1 / This is a ½ frame period every two frame periods.

  As described later, the inverting circuit 101, the DAC 102, and the source driver 103 are provided with a right-eye video signal and a left-eye video signal respectively on a pair of two column signal lines D 1 and D 2 out of a plurality of column signal lines. Simultaneously supplying a positive polarity video signal and a negative polarity video signal obtained from one of the video signals within a horizontal scanning period in units of a plurality of column signal lines, The present invention switches a positive video signal and a negative video signal every frame period, and switches and supplies a positive video signal and a negative video signal to each of two column signal lines every frame period. Video signal supply means.

  The pixel portion 104 has a configuration in which a plurality of pixels 105 are arranged in a two-dimensional matrix (that is, in a row direction and a column direction). Each of the plurality of pixels 105 is disposed at an intersection where a plurality of column signal lines each including two column signal lines D1 and D2 intersect with a plurality of row scanning lines W. . The configuration of an equivalent circuit (that is, a pixel circuit) of each pixel 105 will be described later. A reset signal line R is connected to each pixel in each row among the plurality of pixels 105 constituting the pixel unit 104.

  In addition, a plurality of sets of selection signal lines including two selection signal lines connected to the output terminals of the AND circuits 107 and 108 are connected to each pixel in each row among the plurality of pixels 105 constituting the pixel unit 104. Connected in pairs. The AND circuit 107 outputs a signal obtained by a logical product operation of the first pixel drive selection signal S1 and the gate signal GATE to one selection signal line of a pair of selection signal lines. The AND circuit 108 outputs a signal obtained by performing a logical product operation of the second pixel drive selection signal S2 and the gate signal GATE to the other selection signal line of the pair of selection signal lines.

  The pixel drive selection signals S1 and S2 are symmetric rectangular waves having a predetermined cycle shorter than one vertical scanning cycle and having a relationship of opposite logical values (that is, opposite phases). These AND circuits 107 and 108 constitute a pixel drive selection signal supply means of the present invention together with a pixel drive selection signal generator (not shown) that generates pixel drive selection signals S1 and S2.

  The gate driver 106 receives a VSTART pulse every vertical scanning period (one frame), and sequentially performs a row for every horizontal scanning period from the top to the bottom with respect to all the row scanning lines W within a ½ frame period. A selection signal is supplied to activate the row scanning lines W one by one. In one horizontal scanning period in which one row scanning line W is active, the source driver 103 applies to all the column signal lines including two column signal lines (data lines) D1 and D2 as one set. The video signal voltages DA1 and DA2 are sequentially asserted in units of each set.

  Accordingly, the video signal voltages DA1 and DA2 output from the source driver 103 are gated to each of the plurality of pixels 105 in one row (one line) connected to the row scanning line W activated by the gate driver 106. This is held when the signal GATE is at a low level, and the held video signal voltages DA1 and DA2 are read in synchronization with the pixel drive selection signals S1 and S2 from the AND circuits 107 and 108 when the gate signal is at a high level. . Details of the operation will be described later.

  When the reset signal supplied to the reset signal line R is activated, the reset signal is held in the parasitic capacitance existing in the vicinity of the pixel drive electrodes of the plurality of pixels 105 in each row to which the reset signal is supplied in units of rows. Reset the holding voltage. The parasitic capacitance is a capacitance existing between wirings of semiconductor elements.

  FIG. 3 shows an equivalent circuit diagram of an embodiment of one pixel in FIG. In the figure, the same components as those in FIGS. 1 and 8 are denoted by the same reference numerals. As shown in FIG. 3, one pixel 105 holds pixel selection field effect transistors (FETs) Q1 and Q2 for writing video signal voltages DA1 and DA2, and video signal voltages of each polarity in parallel. It consists of two independent signal holding capacitors Cs1 and Cs2, field effect transistors (FETs) Q3 to Q9, and a liquid crystal element LC having the same structure as the conventional one described with reference to FIGS.

  The drains of the transistors Q1 and Q2 are respectively connected to column signal lines D1 and D2 of a corresponding column of the source driver 103. One end of the first signal holding capacitor Cs1 is connected between the source of the transistor Q1 and the gate of the transistor Q3. Similarly, one end of the second signal holding capacitor Cs2 is connected between the source of the transistor Q2 and the gate of the transistor Q4. The transistor Q1 and the signal holding capacitor Cs1 constitute a first sampling and holding unit of the present invention, and the transistor Q2 and the signal holding capacitor Cs2 constitute a second sampling and holding unit of the present invention.

  The impedance conversion source follower circuit including the transistors Q3 and Q7 constitutes a first buffer amplifier. Similarly, the impedance conversion source follower circuit including the transistors Q4 and Q8 constitutes a second buffer amplifier. The transistor Q5 whose drain is connected to the source of the transistor Q3 and the transistor Q6 whose drain is connected to the source of the transistor Q4 are switching transistors and constitute the switching means of the present invention. The sources of the transistors Q5 and Q6 are connected to the pixel electrode 14 of the liquid crystal element LC.

  The gate of the transistor Q1 and the gate of the transistor Q2 are connected to the row scanning line W. The transistor Q5 is subjected to switching control by applying a pixel drive selection signal S1 to the gate via the first selection signal line. Similarly, the transistor Q6 is subjected to switching control by applying a pixel drive selection signal S2 to the gate via the second selection signal line. The gates of the transistors Q7 and Q8 are connected to the load characteristic control line B. The transistor Q9 has a drain connected to a common connection point between the drains of the transistors Q5 and Q6 and the pixel electrode 14 of the liquid crystal element LC, a source connected to the power source Vss (low level), and a gate connected to the reset signal line R. This is a reset transistor connected to.

  Note that the load characteristic control signal transmitted by the load characteristic control line B is a pulse train, and the transistors Q7 and Q8, which are constant current load transistors of the source follower circuit, are not always active, and the polarity switching switching transistors Q5 and Q6 are not activated. This is a signal for reducing current consumption by making it active only for a limited period within the conduction period.

  Next, regarding the operation of the pixel 105 shown in FIG. 1, an example of an equivalent circuit (pixel circuit) of the pixel 105 shown in FIG. 3, a timing chart of FIG. 4, and applied voltages of the pixel electrode and the transparent common electrode of FIG. This will be described with reference to the schematic diagram shown.

  Here, as an example, the period of the vertical start pulse VSTART is set to one frame, and a period including one set of the left-eye video signal and the right-eye video signal is divided into four, and each divided half frame period In the right-eye video signal transfer period (Ta to Tb), right-eye video signal drive period (Tb to Tc), left-eye video signal transfer period (Tc to Td), and left-eye video signal drive period (Td to Te). It will be described as being assigned. The operations described below are performed by the control means of the present invention, not shown in FIG. 1, by a video signal generator, a select signal SEL generator, a gate signal GATE generator, a vertical start pulse VSTART generator, a reset (not shown). This is realized by outputting a right-eye video signal, a left-eye video signal, SEL, GATE, VSTART, a reset signal, and the like at predetermined timings by controlling each signal generation unit.

  After the vertical start pulse VSTART is input at time Ta as shown in FIG. 4A, the pixel 105 shown in FIG. 3 is connected at time T1 within a ½ frame period as shown in FIG. 4D. The row scanning line W is asserted by a row selection signal from the gate driver 106, and a plurality of pixels 105 in one row connected to the row scanning line W are selected, and transistors in the pixels 105 are selected. Q1 and Q2 are turned on.

  Also, column signal lines D1 and D2 connected to a plurality of selected pixels 105 in one row within a ½ frame period from time Ta to immediately before time Tb are shown in FIGS. ), The video signal voltages DA1 and DA2 of the right-eye video signal are output from the source driver 103. It should be noted that the right-eye video signal for one frame is transmitted from the source driver 103 to all the column signal lines in the ½ frame period from time Ta to immediately before time Tb, as schematically shown in FIG. Output in time division.

  At this time, in one frame period from time Ta to immediately before time Tc, as shown in FIG. 4C, the select signal SEL is at a high level, so the right-eye video output to the column signal line D1. The video signal voltage DA1 of the signal is a DC balance + voltage (positive video signal voltage) obtained by performing DA conversion on DATA1, which is DATA (V +) for DC balance +. The video signal voltage DA2 of the right-eye video signal output to the column signal line D2 is a DC balance-voltage (negative electrode) obtained by DA-converting DATA2, which is the DC balance-DATA (V-). Video signal voltage).

  Therefore, the DC balance + voltage (here, the positive video signal voltage of the right-eye video signal) is sampled by the transistor Q1 in the pixel 105 selected by the row selection signal and held in the signal holding capacitor Cs1. . At the same time, the DC balance-voltage (here, the negative video signal voltage of the video signal for the right eye) is sampled by the transistor Q2 in the pixel 105 selected by the row selection signal and applied to the signal holding capacitor Cs2. Retained. The DC balance voltage of the video signal for the right eye held in the signal holding capacitors Cs1 and Cs2 is as shown in FIGS. 4G and 4H until this pixel is selected again at time T2 after one frame. Retained.

  On the other hand, in the ½ frame period from time Ta including time T1 to immediately before time Tb, the gate signal GATE is at a low level as shown in FIG. The pixel drive selection signals S1 and S2 supplied to each set of selection signal lines are set to a low level as shown in FIGS. 4J and 4K, and are asserted to the transparent common electrode 12. The common voltage Vcom is also set to a low level as shown in FIG. At time Ta, as shown in FIG. 4L, the reset signal of the reset signal line R becomes high level, and the transistor Q9 in FIG. 3 is turned on. As a result, the low level potential of the power supply Vss is applied to the parasitic capacitance existing in the vicinity of the pixel electrode 14 of the liquid crystal element LC through the source and drain of the transistor Q9, and the holding voltage held in the parasitic capacitance is reset.

  Therefore, the applied voltage Vpe of the pixel electrode 14 is 0 [V] as shown in FIG. 4M, and the difference between the applied voltage Vpe of the pixel electrode 14 and the common voltage Vcom of the transparent common electrode 12 applied to the liquid crystal layer 13. The voltage V_LC is also 0 [V] as shown in FIG. 4O, and the liquid crystal layer 13 is not driven.

  In the ½ frame period from the next time Tb to immediately before the time Tc, as shown in FIG. 4 (I), the gate signal GATE changes to the high level. As shown in FIGS. 4J and 4K, each group of selection signal lines is a pixel drive selection signal which is a rectangular wave having a predetermined cycle shorter than one vertical scanning cycle and having a logical value opposite to each other. S1 and S2 are taken out and supplied to the pixel 105 selected at time T1. Accordingly, the transistor Q5 in FIG. 3 in the selected pixel 105 is turned on while the pixel drive selection signal S1 is at the high level, and the DC balance + voltage (here, for the right eye) held in the signal holding capacitor Cs1. A positive video signal voltage of the video signal) is applied to the pixel electrode 14 of the liquid crystal element LC. On the other hand, the transistor Q6 in FIG. 3 in the selected pixel 105 is turned on while the pixel drive selection signal S2 is at a high level, and the DC balance-voltage (here, the right-eye image) held in the signal holding capacitor Cs2 is maintained. The negative video signal voltage of the signal) is applied to the pixel electrode 14 of the liquid crystal element LC.

  Here, as described above, the pixel drive selection signals S1 and S2 having a predetermined cycle shorter than one vertical scanning cycle are symmetric rectangular waves having opposite logical values, so that the transistors Q5 and Q6 are driven by the pixels. The selection signals S1 and S2 are alternately turned on in units of 1/2 cycle. As a result, DC balance + voltage and DC balance-voltage are applied to the pixel electrode 14 in units of 1/2 cycle of the pixel drive selection signals S1 and S2. Applied alternately. FIG. 4M shows the DC balance voltage Vpe applied to the pixel electrode 14.

  On the other hand, the transparent common electrode 12 of the liquid crystal element LC is synchronized with the pixel drive selection signals S1 and S2 in a ½ frame period from time Tb to immediately before time Tc, as shown in FIG. In addition, a common voltage Vcom (high level is Vcom_H, low level is Vcom_L), which is a rectangular wave having a constant amplitude, is applied in the same cycle as the pixel drive selection signals S1 and S2.

  Here, in the ½ frame period from time Tb to immediately before time Tc, the pixel drive selection signal S1 when the common voltage Vcom applied to the transparent common electrode 12 from the common voltage supply means (not shown) is at the low level Vcom_L. Becomes the high level, and the DC balance + voltage (Vcom_L + V_LC) of the video signal for the right eye held in the signal holding capacitor Cs1 is applied to the pixel electrode 14. In the ½ frame period from time Tb to immediately before time Tc, when the common voltage Vcom applied to the transparent common electrode 12 is Vcom_H, which is a high level, the pixel drive selection signal S2 becomes a high level, and the pixel electrode 14 Is applied with the DC balance-voltage (Vcom_H-V_LC) of the video signal for the right eye held in the signal holding capacitor Cs2.

  The voltage applied to the pixel electrode 14 and the transparent common electrode 12 during the AC driving will be described with reference to FIG. In the figure, in the DC balance + voltage application period shown in the left half, the voltage Vcom_L is applied to the transparent common electrode 12 as described above, and the DC balance + voltage (Vcom_L + V_LC) is applied to the pixel electrode 14. As a result, the difference voltage between the applied voltage Vpe of the pixel electrode 14 applied to the liquid crystal layer 13 and the common voltage Vcom becomes + V_LC as shown in the left half of FIG. 5, and as shown in FIG. It changes in synchronization with the pixel drive selection signals S1 and S2 around [V].

  In the DC balance-voltage application period shown in the right half of FIG. 5, the voltage Vcom_H is applied to the transparent common electrode 12 as described above, and the DC balance-voltage (Vcom_H-V_LC) is applied to the pixel electrode 14. . Thereby, the difference voltage between the applied voltage Vpe of the pixel electrode 14 applied to the liquid crystal layer 13 and the common voltage Vcom becomes −V_LC as shown in the right half of FIG. 5, and as shown in FIG. It changes in synchronization with the pixel drive selection signals S1 and S2 with O [V] as the center. Since the DC balance + voltage application period and the DC balance−voltage application period are the same time, the DC balance can be kept at zero.

  Further, the liquid crystal element LC is AC driven at a high frequency of several kHz in synchronization with the pixel drive selection signals S1 and S2 having a predetermined period (several kHz order) shorter than one vertical scanning period, and from time Tb to time Tc. The right-eye video signal is displayed for the ½ frame period until immediately before.

  Next, as shown in FIG. 4A, after the vertical start pulse VSTART is input at time Tc, the row scanning line W to which the pixel 105 shown in FIG. 3 is connected at time T2 one frame after time T1. 4D is asserted again by a row selection signal, and a plurality of pixels 105 in one row connected to the row scanning line W are selected, and the transistors Q1 and Q1 in the pixels 105 are selected. Q2 is turned on.

  In addition, column signal lines D1 and D2 connected to a plurality of selected pixels 105 in one row within a ½ frame period from time Tc to immediately before time Td are shown in FIGS. ), The video signal voltages DA1 and DA2 of the video signal for the left eye are output from the source driver 103. Note that the left-eye video signal for one frame is time-divided from the source driver 103 to the column signal line in the ½ frame period from time Tc to immediately before time Td, as schematically shown in FIG. Is output automatically.

  At this time, in one frame period from time Tc to immediately before time Te, as shown in FIG. 4C, since the select signal SEL is at a low level, the above left-eye video output to the column signal line D1. The video signal voltage DA1 of the signal is a DC balance-voltage (negative video signal voltage) obtained by DA-converting DATA1, which is DATA (V-) for DC balance. Further, the video signal voltage DA2 of the left-eye video signal output to the column signal line D2 is a DC balance + voltage (positive electrode) obtained by DA-converting DATA2, which is DATA (V +) for DC balance +. Video signal voltage).

  Therefore, the DC balance-voltage (here, the negative video signal voltage of the video signal for the left eye) is sampled by the transistor Q1 in the pixel 105 selected by the row selection signal and held in the signal holding capacitor Cs1. . At the same time, the DC balance + voltage (here, the positive video signal voltage of the video signal for the left eye) is sampled by the transistor Q2 in the pixel 105 selected by the row selection signal, and is stored in the signal holding capacitor Cs2. Retained. The DC balance voltage of the video signal for the left eye held in the signal holding capacitors Cs1 and Cs2 is held as shown in FIGS. 4G and 4H until this pixel is selected again at a time one frame later. Is done.

  On the other hand, in the ½ frame period from time Tc including time T2 to immediately before time Td, the gate signal GATE is at a low level as shown in FIG. The pixel drive selection signals S1 and S2 supplied to each set of selection signal lines are set to a low level as shown in FIGS. 4J and 4K, and are asserted to the transparent common electrode 12. The common voltage Vcom is also set to a low level as shown in FIG. At time Tc, as shown in FIG. 4L, the reset signal of the reset signal line R becomes high level, and the transistor Q9 in FIG. 3 is turned on. As a result, the low level potential of the power supply Vss is applied to the parasitic capacitance existing in the vicinity of the pixel electrode 14 of the liquid crystal element LC through the source and drain of the transistor Q9, and the holding voltage held in the parasitic capacitance is reset.

  Therefore, the applied voltage Vpe of the pixel electrode 14 is 0 [V] as shown in FIG. 4M, and the difference between the applied voltage Vpe of the pixel electrode 14 and the common voltage Vcom of the transparent common electrode 12 applied to the liquid crystal layer 13. The voltage V_LC is also 0 [V] as shown in FIG. 4O, and the liquid crystal layer 13 is not driven.

  In the ½ frame period from the next time Td to just before the time Te, as shown in FIG. 4 (I), the gate signal GATE changes to high level. As shown in FIGS. 4 (J) and 4 (K), pixel drive selection is a rectangular wave having a predetermined cycle shorter than one vertical scanning cycle and having a logical value opposite to each other. Signals S1 and S2 are taken out and supplied to the selected pixel 105 at time T2. As a result, the transistor Q5 in FIG. 3 in the selected pixel 105 is turned on while the pixel drive selection signal S1 is at the high level, and the DC balance-voltage (here, for the left eye) held in the signal holding capacitor Cs1. A negative video signal voltage of the video signal) is applied to the pixel electrode 14 of the liquid crystal element LC. On the other hand, the transistor Q6 in FIG. 3 in the selected pixel 105 is turned on while the pixel drive selection signal S2 is at a high level, and the DC balance + voltage (here, the left-eye image) held in the signal holding capacitor Cs2 is held. The positive video signal voltage of the signal is applied to the pixel electrode 14 of the liquid crystal element LC.

  Here, as described above, the pixel drive selection signals S1 and S2 having a predetermined cycle shorter than one vertical scanning cycle are symmetric rectangular waves having opposite logical values, so that the transistors Q5 and Q6 are driven by the pixels. The selection signals S1 and S2 are alternately turned on in units of 1/2 cycle. As a result, DC balance-voltage and DC balance + voltage are applied to the pixel electrode 14 in units of 1/2 cycle of the pixel drive selection signals S1 and S2. Applied alternately. FIG. 4M shows the DC balance voltage Vpe applied to the pixel electrode 14.

  On the other hand, the transparent common electrode 12 of the liquid crystal element LC is synchronized with the pixel drive selection signals S1 and S2 during the ½ frame period from time Td to immediately before time Te, as shown in FIG. In addition, a common voltage Vcom (high level is Vcom_H, low level is Vcom_L), which is a rectangular wave having a constant amplitude, is applied in the same cycle as the pixel drive selection signals S1 and S2.

  Here, in the ½ frame period from the time Td to immediately before the time Te, the pixel drive selection signal S1 when the common voltage Vcom applied to the transparent common electrode 12 from the common voltage supply means (not shown) is Vcom_L which is a low level. Becomes the high level, and the DC balance-voltage (Vcom_L + V_LC) of the video signal for the left eye held in the signal holding capacitor Cs1 is applied to the pixel electrode 14. In the ½ frame period from time Td to immediately before time Te, the pixel drive selection signal S2 becomes high level when the common voltage Vcom applied to the transparent common electrode 12 is Vcom_H, which is high level, and the pixel electrode 14 Is applied with the DC balance + voltage (Vcom_H−V_LC) of the video signal for the left eye held in the signal holding capacitor Cs2.

  As a result, the difference voltage between the applied voltage Vpe of the pixel electrode 14 applied to the liquid crystal layer 13 and the common voltage Vcom is applied to the pixel drive selection signals S1 and S2 around 0 [V] as shown in FIG. It changes synchronously. At this time, as described above, the difference voltage between the applied voltage Vpe of the pixel electrode 14 applied to the liquid crystal layer 13 and the common voltage Vcom becomes + V_LC during the period in which the DC balance-voltage is applied to the pixel electrode 14. During the period in which the DC balance + voltage is applied, −V_LC, and the application period is set to the same time, so that the DC balance can be kept at zero. Note that in each pixel on the same line, the DC balance voltage Vpe applied to the pixel electrode 14 changes as shown in FIG. 4M depending on the picture of the video signal, so the value of | V_LC | itself is also shown in FIG. As shown in O), it changes every frame.

  Further, the liquid crystal element LC is AC driven at a high frequency of several kHz in synchronization with the pixel drive selection signals S1 and S2 having a predetermined cycle (several kHz order) shorter than one vertical scanning cycle, and from time Td to time Te. The left-eye video signal is displayed for the ½ frame period until immediately before. Thereafter, the same operation as that from the time Ta to immediately before the time Te is cyclically repeated in units of two frames.

  As described above, in the present embodiment, as schematically illustrated in FIG. 6A, the right-eye video signal is transferred and the pixel unit 104 is transferred during a ½ frame period from time Ta to immediately before time Tb. The right eye video signal transfer period t1 held in each of the pixels 105, and the subsequent half frame period from time Tb to immediately before time Tc is the pixel drive period t2, and each pixel in the immediately right eye video signal transfer period t1. The right-eye video signal held in 105 is displayed on each pixel 105.

  Further, in the ½ frame period from the subsequent time Tc to immediately before the time Td, the left-eye video signal is transferred and held in the pixel 105 in the pixel unit 104 as the left-eye video signal transfer period t3. The half-frame period immediately before Te is displayed in each pixel 105 as the pixel drive period t4, and the left-eye video signal held in each pixel 105 in the immediately preceding left-eye video signal transfer period t3. The liquid crystal display device 100 of the present embodiment repeats this sequence in units of two frames hereinafter.

  Thus, according to the liquid crystal display device 100 of the present embodiment, the positive video signal voltage (DC balance + voltage) is held in one of the two signal holding capacitors CS1 and CS2, and the negative video signal is held in the other. After a 1/2 frame period in which the operation of holding the voltage (DC balance-voltage) is performed simultaneously in parallel, the voltage applied to the liquid crystal element LC is once reset and then held in the two signal holding capacitors Cs1 and Cs2. The positive polarity video signal (DC balance + voltage) and the negative polarity video signal (DC balance−voltage) are alternately read, and the pixel electrode 14 is AC driven for a ½ frame period.

  For this reason, according to the present embodiment, the image data is held again for polarity inversion to make the DC balance necessary for driving the liquid crystal element 0, which is necessary in the conventional liquid crystal display device. A buffer for one frame can be eliminated.

  Further, according to the liquid crystal display device 100 of the present embodiment, the positive video signal voltage (DC balance + voltage) asserted to one of the column signal lines D1 and D2 and the negative video signal voltage (DC balance) asserted to the other. -Voltage) are alternately switched for each frame, the characteristics of the transistor between the two voltage writing / reading circuit units for the two signal holding capacitors Cs1 and Cs2 in one pixel 105, respectively. Even when there is an error due to the above, the error can be canceled between two frames, and an abnormality in luminance caused by the error can be visually reduced.

  Further, in the conventional liquid crystal display device, it is necessary to input and hold a positive image signal and a negative image signal alternately in two holding capacitors in the pixel circuit within a predetermined time, so that reliability In order to improve the number of times of polarity inversion of a signal to be AC driven for improvement, it is necessary to increase the transfer band of data (image signal) input to the pixel circuit, and there is a problem in reliability.

  On the other hand, according to the present embodiment, even if the number of times of polarity inversion of the AC drive signal is increased in order to improve reliability, the positive and negative video signals are connected to the column signal lines D1 and D2. Since it is supplied in parallel and simultaneously held in parallel in the two signal holding capacitors Cs1 and Cs2, it can be held in the minimum data transfer band as compared with the conventional liquid crystal display device, and the sequential color A liquid crystal display device suitable for a method or a three-dimensional display method can be realized.

  Next, the stereoscopic video display system of the present embodiment using the liquid crystal display device 100 will be described.

  FIG. 7 shows a schematic configuration diagram of an embodiment of a stereoscopic video display system according to the present invention. In the figure, a stereoscopic video display system 200 according to the present embodiment displays a two-dimensional image by projecting a projector 201 having the liquid crystal display device 100 as a projection liquid crystal display and image light from the projector 201. It consists of a screen 202 and shutter glasses 203. The projector 201 and the screen 202 constitute the image display means of the present invention. The video observer wears the shutter glasses 203 and sees the two-dimensional image on the screen 202.

  The shutter glasses 203 have a known configuration including a right-eye liquid-crystal shutter and a left-eye liquid-crystal shutter that are controlled to be opened and closed independently of each other in the right-eye part and the left-eye part. That is, as schematically shown in FIG. 6B, the shutter glasses 203 have a right-eye liquid crystal shutter and a left-eye liquid crystal shutter during a period corresponding to the right-eye video signal transfer period t1 shown in FIG. Is a light blocking period (closed period) t11 for blocking light, and a period corresponding to the pixel driving period t2 for displaying the right-eye video signal is a right-eye light transmission period (open period) in which only the right-eye liquid crystal shutter transmits light. t12. Subsequently, the period corresponding to the left-eye video signal transfer period t3 is again the light-shielding period (closed period) t13 in which the right-eye liquid crystal shutter and the left-eye liquid crystal shutter respectively block light, and the pixels displaying the left-eye video signal A period corresponding to the driving period t4 is a left-eye light transmission period (open period) t14 in which only the left-eye liquid crystal shutter transmits light. Thereafter, the switching operation of the two liquid crystal shutters of the glasses is repeated in synchronization with the display operation of the liquid crystal display device in the same manner as described above.

  According to this stereoscopic image display system 200, the image for the right eye displayed on the screen 202 is imaged on the retina through the right eye of the observer when the right eye liquid crystal shutter of the shutter glasses 203 is selected to transmit light. The left-eye image switched and displayed on the screen 202 after one frame period is imaged on the retina through the left eye of the observer when the left-eye liquid crystal shutter of the shutter glasses 203 is selected to transmit light. Thus, the viewer can integrate these parallax images in the brain and perceive them as a three-dimensional image, that is, a stereoscopic image.

  According to the stereoscopic video display system 200, since the stereoscopic display is performed using the projector 201 having the liquid crystal display device 100 having the above-described configuration, a stable stereoscopic image display can be performed with the minimum necessary data transfer band. Can do. Further, as described above, even if the liquid crystal display device 100 has an error between the two voltage write / read circuit units for each of the two signal holding capacitors in the same pixel, the error is reduced to 2 frames. The stereoscopic image display system 200 can perform high-quality stereoscopic image display because the luminance abnormality caused by the error can be visually reduced.

  In this stereoscopic image display system 200, the shutter glasses 203 are provided with a light shielding period t13 between the right eye light transmission period t12 and the left eye light transmission period t14, and the left eye light transmission period t14 and the right eye light transmission period of the next frame. Since the light shielding period t11 is provided between t12 and t12, the right eye light transmission period and the left eye light transmission period do not overlap at all. Therefore, according to the stereoscopic image display system 200, crosstalk, which occurs when the right-eye light transmission period and the left-eye light transmission period partially overlap, is observed when the right-eye image is observed with the left eye and the left-eye image is observed with the right eye. Can be prevented.

  Note that the present invention is not limited to the above-described embodiment. For example, the pixel circuit may have a configuration in which the transistors Q7 and Q8 in FIG. 3 are omitted.

  In the stereoscopic video display system of the above embodiment, as shown in FIG. 6, the period corresponding to the video signal transfer period is a light shielding period in which both the right eye liquid crystal shutter and the left eye liquid crystal shutter of the shutter glasses are closed. However, since the holding voltage of the parasitic capacitance in the vicinity of the pixel electrode 14 of the liquid crystal display device 100 is reset at the start of the video signal transfer period, black is displayed. For example, the liquid crystal shutter on the image side to be displayed next may be set to the light transmission period.

  Furthermore, in the stereoscopic image display system of the above-described embodiment, the shutter glasses 203 are used. However, polarized glasses having a known configuration for separately observing a right eye image and a left eye image having different polarization directions are used. It may be. In this case as well, stereoscopic vision using binocular parallax can be realized as in the case of shutter glasses. However, in this case, the right-eye image light projected on the screen is polarized in the first polarization direction in the pixel driving period in which the right-eye video signal is displayed between the liquid crystal display device 100 and the screen, and the left-eye video is displayed. In the pixel drive period for displaying signals, polarization switching means for polarizing the left-eye image light projected on the screen in a second polarization direction different from the first polarization direction is necessary. The polarizing glasses have a known configuration in which the right eye part transmits only the polarized light in the first polarization direction and the left eye part transmits only the polarized light in the second polarization direction.

12 transparent common electrode 13 liquid crystal layer 14 pixel electrode 100 liquid crystal display device 101 inversion circuit 102 DA converter (DAC)
DESCRIPTION OF SYMBOLS 103 Source driver 104 Pixel part 105 Pixel 106 Gate driver 107, 108 AND circuit 1011, 1012 Selector 1013 Arithmetic unit 200 Three-dimensional image display system 201 Projector 202 which has the liquid crystal display device of this invention Screen 203 Shutter glasses Q1, Q2 Electric field for pixel selection Effect transistors Q3, Q4, Q7, Q8 Source follower circuit transistors Q5, Q6 Switching transistor Q9 Reset transistor LC Liquid crystal element Cs1, Cs2 Signal holding capacity W Row scanning line D1, D2 Column signal line R Reset signal line S1, S2 Pixel Drive selection signal

Claims (3)

A first transfer period for transferring one of the right-eye video signal and the left-eye video signal; a first pixel driving period for displaying the one video signal transferred in the first transfer period; A second transfer period for transferring the other video signal of the right-eye video signal and the left-eye video signal, and a second pixel driving period for displaying the other video signal transferred in the second transfer period. Image display means including a liquid crystal display device that cyclically switches in a cycle of two frame periods in order;
At least light of an image based on the one video signal displayed in the first pixel driving period of the liquid crystal display device and light of an image based on the other video signal displayed in the second pixel driving period. Glasses that use binocular parallax to enter only the eye corresponding to the displayed image of the right and left eyes of the observer,
The liquid crystal display device
A plurality of sets of column signal lines each including two column signal lines, and a plurality of pixels respectively connected to intersections of the plurality of row scanning lines;
A positive-polarity video signal and a negative-polarity video signal obtained from one of the right-eye video signal and the left-eye video signal on each of the two column signal lines in the set of column signal lines. Are sequentially supplied to the plurality of sets of column signal lines in one horizontal scanning period in units of sets, and the positive video signal and the negative video signal are supplied for each frame period. Video signal supply means for switching and supplying the positive video signal and the negative video signal to each of the two column signal lines for each frame period;
A row selection signal for selecting the plurality of row scanning lines sequentially for each of the plurality of row scanning lines by selecting a plurality of row scanning lines one by one in a horizontal scanning period, and supplying the plurality of pixels in units of rows. Means,
A plurality of sets of selection signal lines each including two selection signal lines are connected to each pixel in each row among the plurality of pixels, and one set is connected to each of the two selection signal lines in each group. Pixel drive selection signal supply means for supplying two pixel drive selection signals which are rectangular waves having a predetermined cycle shorter than the vertical scanning cycle and having a relationship of opposite logical values to each other;
Reset signal supply means for supplying a reset signal at a predetermined timing to a reset control line connected to each pixel in each row of the plurality of pixels;
A first transfer period for transferring one of the right-eye video signal and the left-eye video signal; and a first pixel driving period for displaying the one video signal transferred in the first transfer period; , A second transfer period for transferring the other video signal of the right-eye video signal and the left-eye video signal, and a second pixel driving period for displaying the other video signal transferred in the second transfer period Control means for controlling each of the video signal supply means, the pixel drive selection signal supply means, and the reset signal supply means so as to perform a cyclic switching operation in a cycle of 2 frames in this order, Each of the pixels includes a liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode,
The positive video signal or the negative video signal supplied via one column signal line of the set of two column signal lines is sampled and held as a first video signal voltage for a certain period. A sampling and holding means;
The negative video signal or the positive video signal supplied via the other column signal line of the set of the two column signal lines is sampled and held as a second video signal voltage for a certain period. Two sampling and holding means;
The two pixel drive selection signals are the first video signal voltage held by the first sampling and holding means and the second video signal voltage held by the second sampling and holding means. Switching means for alternately switching at the predetermined period and applying to the pixel electrode;
A stereoscopic image display system comprising: a reset unit that resets a holding voltage held in a parasitic capacitance near the pixel electrode by the reset signal.   The glasses include a right-eye liquid-crystal shutter and a left-eye liquid-crystal shutter that are controlled to be opened and closed independently of each other in the right-eye portion and the left-eye portion, and the right-eye liquid-crystal shutter and the right-eye liquid-crystal shutter in the first and second transfer periods Both the left-eye liquid crystal shutter and the left-eye liquid crystal shutter are controlled to be in a closed state that blocks light, and the right-eye liquid crystal shutter and the left-eye liquid crystal shutter that are displayed in the first and second pixel driving periods are displayed. The stereoscopic video display system according to claim 1, wherein only the right-eye liquid crystal shutter or the left-eye liquid crystal shutter corresponding to an image for use is shutter glasses controlled to be in an open state in which light is transmitted. A plurality of sets of column signal lines each including two column signal lines, and a plurality of pixels respectively connected to intersections of the plurality of row scanning lines;
A positive-polarity video signal and a negative-polarity video signal obtained from one of the right-eye video signal and the left-eye video signal on each of the two column signal lines in the set of column signal lines. Are sequentially supplied to the plurality of sets of column signal lines in one horizontal scanning period in units of sets, and the positive video signal and the negative video signal are supplied for each frame period. Video signal supply means for switching and supplying the positive video signal and the negative video signal to each of the two column signal lines for each frame period;
A row selection signal for selecting the plurality of row scanning lines sequentially for each of the plurality of row scanning lines by selecting a plurality of row scanning lines one by one in a horizontal scanning period, and supplying the plurality of pixels in units of rows. Means,
A plurality of sets of selection signal lines each including two selection signal lines are connected to each pixel in each row among the plurality of pixels, and one set is connected to each of the two selection signal lines in each group. Pixel drive selection signal supply means for supplying two pixel drive selection signals which are rectangular waves having a predetermined cycle shorter than the vertical scanning cycle and having a relationship of opposite logical values to each other;
Reset signal supply means for supplying a reset signal at a predetermined timing to a reset control line connected to each pixel in each row of the plurality of pixels;
A first transfer period for transferring one of the right-eye video signal and the left-eye video signal; and a first pixel driving period for displaying the one video signal transferred in the first transfer period; , A second transfer period for transferring the other video signal of the right-eye video signal and the left-eye video signal, and a second pixel driving period for displaying the other video signal transferred in the second transfer period Control means for controlling each of the video signal supply means, the pixel drive selection signal supply means, and the reset signal supply means so as to perform a cyclic switching operation in a cycle of 2 frames in this order, Each of the pixels includes a liquid crystal element in which a liquid crystal layer is sandwiched between an opposing pixel electrode and a common electrode,
The positive video signal or the negative video signal supplied via one column signal line of the set of two column signal lines is sampled and held as a first video signal voltage for a certain period. A sampling and holding means;
The negative video signal or the positive video signal supplied via the other column signal line of the set of the two column signal lines is sampled and held as a second video signal voltage for a certain period. Two sampling and holding means;
The two pixel drive selection signals are the first video signal voltage held by the first sampling and holding means and the second video signal voltage held by the second sampling and holding means. Switching means for alternately switching at the predetermined period and applying to the pixel electrode;
Resetting means for resetting the holding voltage held in the parasitic capacitance existing near the pixel electrode by the reset signal, the control means,
In the first and second transfer periods, after the reset signal is output from the reset signal supply means to reset the holding voltage held in the parasitic capacitance existing near the pixel electrode, the video signal supply means And the positive-polarity video signal and the negative-polarity video signal of the right-eye video signal or the left-eye video signal switched every frame period are supplied to the two column signal lines in each set, respectively. First and second sampling and holding means hold the first and second video signal voltages, respectively, and control the pixel drive selection signal supply means during the first and second pixel driving periods to Two pixel drive selection signals are output and the first video signal voltage held by the first sampling and holding unit and the second sampling and holding unit A liquid crystal display device comprising applying to said pixel electrode and said held second video signal voltage is switched alternately at the predetermined period.

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