JP2012064652A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor circuit device, which includes trench gate-type MOSFETs with each gate electrode completely embedded in a trench gate and which offers an excellent performance.SOLUTION: The trench gate-type MOSFET includes: a first conductivity type well layer 4; a second conductivity type well layer 5 formed in the well layer 4; a trench channel 7 of a lattice shape surrounding the well layer 5 with a gate electrode material 9 embedded therein; a first insulative film 8 formed between a side face of the trench channel 7 and the second conductivity type well layer 5; and a second insulative film 14 formed between a side face of the trench channel 7 and the first conductivity type well layer 4. The first insulative film 8 is thinner than a second insulative film 14.

Description

  The present invention relates to a semiconductor device including a trench gate type MOS field effect transistor.

  In recent years, a wide variety of portable devices have been distributed, and Li-ion batteries that have a high energy density and do not generate a memory effect are frequently used as power sources. Accordingly, a protection IC for detecting overcharge and overdischarge of the Li ion battery has become essential. For example, a Li-ion battery for a mobile phone has a battery voltage of about 3.6V, but when charged, a voltage of 20V or more is applied, and the IC is required to include an element having a high breakdown voltage. Is done.

  At this time, if the CMOS transistor process is to satisfy the above IC specifications, it is necessary to form a MOS transistor suitable for a low breakdown voltage and a MOS transistor suitable for a high breakdown voltage. This is because, in order to satisfy the specifications of the high voltage element, it is necessary to increase the element size to some extent. When the entire IC is composed of the high voltage element, the final chip size increases and the IC is not cost competitive. This makes it difficult to meet the market price requirements. Therefore, a high voltage element is used for a circuit portion to which a high voltage is applied, and a chip size is suppressed by using a low voltage element in other circuit areas. Furthermore, by incorporating a power MOS field effect transistor (hereinafter abbreviated as a power MOSFET) in the protection IC, it is required to further reduce the chip size and reduce the on-resistance of the power MOSFET.

  Here, since the on-resistance of the power MOSFET is required to be as low as about 50 mΩ, the ratio of the power MOSFET to the entire chip is very large, and the performance improvement of the power MOSFET greatly contributes to the reduction of the chip size.

  Therefore, when focusing on the power MOSFET, the circuit in which the drains of two N-type power MOSFETs are short-circuited as shown in FIG. 1 may be used. As shown in the cross-sectional view of FIG. 3, the drain electrode is formed by the N-type buried layer 2, the drains are short-circuited by the N-type buried layer 2, and the trench gates 7a and 7b are completely made of the gate electrode material 9a and 9b. When the circuit is configured using a trench gate type MOSFET embedded in the n-type MOSFET, it is desirable that the distance between the MOSFETs be short in order to reduce the parasitic resistance component of the N-type embedded layer 2. However, since it is necessary to ensure the punch-through breakdown voltage between the P-type wells 5a and 5b of the MOSFET, the distance between the MOSFETs is sufficiently widened, and the N-type relaxation layer 4 is provided there.

Mitsumasa Koyanagi, “Submicron Device I”, Maruzen Co., Ltd., July 31, 1987, p170

  When the N-type relaxation layer 4 is provided between the P-type wells 5a and 5b in order to ensure the punch-through breakdown voltage between the P-type wells 5 of the trench gate type MOSFET, between the P-type wells 5a and 5b and the N-type relaxation layer 4 In order to prevent the occurrence of avalanche breakdown, the concentration of the N-type relaxation layer 4 must be reduced, thereby making it necessary to increase the distance between the P-type wells 5a and 5b. If the distance between the P-type wells 5a and 5b is increased, the area efficiency deteriorates and the chip size increases. Further, since the distance between the P-type wells 5a and 5b is increased, the distance of the N-type high concentration buried layer 2 that connects the drains of the trench gate type MOSFET is increased, and the drain resistance is increased. The performance of the type MOSFET will be degraded.

  An object of the present invention is to provide a semiconductor circuit device having excellent performance in a trench gate type MOSFET in which the trench gate 7 is completely filled with the gate electrode materials 9a and 9b.

In order to solve the above problems, the present invention uses the following means.
(1) A trench gate type MOSFET in which a second conductivity type well layer formed in a first conductivity type well layer is surrounded by a grid-like trench groove embedded in a gate electrode material, A first insulating film formed between the side surface of the trench groove and the second conductivity type well layer is formed between the side surface of the trench groove and the first conductivity type well layer. The semiconductor device is characterized by being thinner than the insulating film.
(2) The semiconductor device described in (1) is characterized in that the first insulating film has a thickness of 20 nm or less and the second insulating film has a thickness greater than 20 nm.
(3) The semiconductor device described in (1) and (2) is characterized in that the gate electrode material is polysilicon.

  According to the first aspect of the present invention, in the trench gate type MOSFET in which the trench groove is embedded with the gate electrode material, the punch-through breakdown voltage between the P type wells of the MOSFET is increased by surrounding the P type well layer with the trench groove. And the distance between the MOSFETs can be reduced to the minimum pitch of the trench grooves. Thereby, since the distance between MOSFETs can be shortened, a semiconductor circuit device having a small chip size and excellent performance can be provided.

It is a circuit diagram of power MOSFET concerning the present invention. 1 is a cross-sectional structure diagram of a semiconductor circuit device having a trench gate type MOSFET according to an embodiment. It is a figure which shows the example of the cross-section of the semiconductor circuit device which has the conventional trench gate type MOSFET.

  Hereinafter, the semiconductor device according to the present invention will be described with reference to the schematic cross-sectional view of the semiconductor circuit device according to the embodiment of the present invention shown in FIG. In the following description, an N-channel MOSFET will be described as an example.

  On the P-type semiconductor substrate 1, an N-type buried layer 2 serving as a high-concentration drain and a P-type epitaxial layer 3 are formed. An N-type well layer 4 serving as a low-concentration drain is formed on the surface of the P-type epitaxial layer 3 so as to reach the N-type buried layer 2, and the gate electrode material 9 a, Trench grooves 7a and 7b embedded in 9b and P-type well layers 5a and 5b constituting a channel region are formed, and the P-type well layers 5a and 5b are surrounded by the trench grooves 7a and 7b. The first gate oxide films 8a and 8b are formed on the side in contact with the P-type well layers 5a and 5b in the trench groove, and the second gate oxide films 14a and 14b are connected to the N-type well layer 4 in the trench groove. The second gate oxide film 14a, 14b is thicker than the first gate oxide film 8a, 8b. N ++ type source layers 10a and 10b and P ++ type body contact layers 13a and 13b are selectively formed inside the P type well layers 5a and 5b. Although not shown, an intermediate insulating film is formed on the surface of the P type epitaxial layer 3, and N ++ type high concentration source layers 10a and 10b of each MOSFET, P ++ type high concentration body contact layers 13a and 13b, and gate electrode material 9a. 9b, contact holes are formed, and a gate electrode and a source electrode are formed of metal through the contact holes. Here, the N ++ type source layers 10a and 10b and the P ++ type body contact layers 13a and 13b are respectively short-circuited by the source electrode.

  An operation of the trench gate type MOSFET according to the embodiment will be described. In the trench gate type MOSFET, when a voltage equal to or higher than the threshold voltage Vt is applied to the gate electrodes connected to the gate electrode materials 9a and 9b, the P-type well layers 5a and 5b in contact with the side walls of the first trench groove 7 are formed. The channel is inverted and drain current flows.

  The operation of the trench gate type MOSFET in the circuit shown in FIG. 1 will be described in detail. The drains of the first MOSFET and the second MOSFET are short-circuited, and as a current path at the time of on, for example, the forward bias is applied to the gate electrode 9a of the first MOSFET and the second P ++ type high concentration body contact layer 13b. Is applied, the N ++ type source layer 10a of the first MOSFET, the channel region, the N type well layer 4, the N type buried layer 2, the N type well layer 4, the P type well layer 5b of the second MOSFET, and the P ++ type. High concentration body contact layer 13b exists. Further, when a forward bias is applied to the P ++ type high concentration body contact layer 13b without applying a voltage to the gate electrode 9a of the first MOSFET, it is turned off, and a high voltage may be applied between the P type well layers 5a and 5b. The breakdown voltage at this time can be a PN junction breakdown voltage composed of the N-type well layer 4 and the P-type well layer 5a, or a parasitic bipolar transistor composed of the P-type well layer 5b, the N-type well layer 4 and the P-type well layer 5a. It depends on the punch-through pressure resistance.

  The trench gate type MOSFET according to the present embodiment has a structure in which the P-type well layer 5 is surrounded by the trench groove 7. For this reason, the punch-through breakdown voltage between the P-type well layers 5a and 5b can be sufficiently increased.

  In this embodiment, the oxide film formed on the inner surface of the trench groove 7 is in contact with the N-type well layer 4 at the side surface of the trench groove, but this portion of the oxide film is not destroyed within the voltage range used. Must be structured. Since power MOSFETs are required to have low on-resistance, it is common to make the gate oxide film thin. Therefore, an oxide film 14 thicker than the gate oxide film 8 is formed on the side surfaces of the N-type well layer 4 and the trench groove. For example, in the case of a MOSFET having a source-drain voltage of 20 V, the oxide film 14 is not destroyed if the film thickness is 20 nm or more.

  A method for manufacturing the gate oxide films 8a and 8b and the oxide films 14a and 14b will be briefly described. First, after the oxide film is formed by thermally oxidizing the entire inner surface of the trench grooves 7a and 7b, the portions where the oxide films 8a and 8b are formed by photolithography are opened, and the portions where the oxide films 8a and 8b are formed by wet etching The oxide film is removed. Then, after removing the resist, the entire inner surface of the trench groove 7 is thermally oxidized again, whereby the gate oxide film 8 and the oxide film 14 are formed.

  P-type well layers 5a and 5b are formed so as to be surrounded by trench grooves 7a and 7b, and the oxide film thickness at the portion where the side surfaces of trench grooves 7a and 7b are in contact with the N-type well layer is increased. The breakdown voltage between the drain and the gate can be increased while increasing the punch-through breakdown voltage between the mold well layers 5a and 5b. As a result, the distance between the trench gate MOSFETs opened to ensure the punch-through breakdown voltage between the P-type well layers 5a and 5b can be reduced to the minimum pitch of the trench grooves determined by the manufacturing method.

  Although the present invention has been described with respect to an N-channel trench gate type MOSFET, the present invention is also applicable to a P-channel trench gate type MOSFET. Further, although an example of element isolation of two trench gate type MOSFETs has been shown, the present invention can also be applied to a single unit or three or more trench gate type MOSFETs. What has been described above is only one embodiment of the present invention, and various other modified embodiments can be considered without departing from the spirit of the present invention. is there.

DESCRIPTION OF SYMBOLS 1 P type semiconductor substrate 2 N type buried drain layer 3 P type epitaxial layer 4 N type well layer 5a, 5b P type well layer 6 Field insulating film 7a, 7b Trench groove 8a, 8b First gate oxide film 9a, 9b Gate Electrode 10a, 10b N ++ type source layer 11 First vertical MOSFET
12 Second vertical MOSFET
13a, 13b P ++ type body contact layers 14a, 14b Second gate oxide film

Claims (3)

A first conductivity type semiconductor substrate, a second conductivity type buried layer serving as a high-concentration drain provided on the semiconductor substrate;
An epitaxial layer of a first conductivity type provided on and around the buried layer;
A first well layer of a second conductivity type serving as a low concentration drain provided on the surface of the epitaxial layer so as to reach the buried layer;
A plurality of second well layers of a first conductivity type constituting a channel region electrically separated from the surface of the first well layer;
A trench groove surrounding each of the plurality of second well layers;
A first gate oxide film formed on the inner surface of the trench groove on the side where the trench groove is in contact with the first well layer;
A second gate oxide having a thickness smaller than that of the first gate oxide film formed on the inner surface of the trench groove on the side in contact with one of the plurality of second well layers surrounded by the trench groove; A membrane,
A gate electrode material embedded in the trench groove; and a source layer and a body contact layer disposed on the surface of each of the plurality of second well layers;
Semiconductor device having   2. The semiconductor device according to claim 1, wherein the thickness of the first gate oxide film is 20 nm or less and the thickness of the second gate oxide film is larger than 20 nm.   3. The semiconductor device according to claim 1, wherein the gate electrode material is polysilicon.

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