JP2011234128A - Baud rate detecting device for serial communication, baud rate correcting device for serial communication, and baud rate detecting method for serial communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain a baud rate within an error tolerable range, and to lower the frequency of clock pulse used for measuring time.SOLUTION: There are provided a clock generator 33 which generates a clock pulse whose cycle is constant, an edge detection circuit 41 which detects timing of a communication signal for a predetermined domain that appears on a communication line 13, and a time measurement timer 43 which counts the time period of the predetermined domain and outputs the counting result as a binary time measurement value. It further includes an adder 46 in which the binary of the time measurement value is divided into a high order bit part and a low order bit part according to a bit configuration in the predetermined domain, and a value of the highest-order bit in the low order bit part is added to a value of the lowest-order bit in the high order bit part. The range of (-1<calculation error≤0) is corrected to be (-0.5<calculation error≤+0.5).

Description

  The present invention relates to a baud rate detection device for serial communication used for automatically correcting a baud rate (transmission speed) used for communication by a serial communication system in accordance with an actual communication signal.

  For example, a communication device connected to a communication network of an automobile control system often employs LIN (Local Interconnect Network) or CAN (Controller Area Network) as a communication standard. A large number of electronic control units called ECUs (Electronic Control Units) are mounted on the vehicle to control each of various control systems. In order for a plurality of ECUs to exchange information and control each other, these ECUs are connected by an in-vehicle communication network of a control system. LIN and CAN are used for this in-vehicle communication network.

  For example, when connecting ECUs connected with various sensors and actuators having advanced functions on a vehicle, a relatively low communication speed (transmission speed) may be used, so an in-vehicle communication network using LIN is used. It is often done. In the case of LIN, the maximum transmission rate is 20 kbps.

  The LIN communication protocol is a serial communication protocol based on a data format called UART (Universal Asynchronous Receiver Transmitter) or SCI (Serial Communication Interface). And it is utilized in order to connect between a single master node (ECU used as a master) and several slave nodes (ECU used as a slave) with a communication network.

  Access control to the network in the LIN is a time trigger method. For this reason, a message sequence is preset in the master task as a transfer schedule. The master node can execute an application as a LIN cluster and manage a network. That is, all communication tasks in the LIN are managed by time, and message collision does not occur as long as the transmission timing is synchronized between nodes.

  Synchronizing in the LIN means correcting the sampling clock cycle for acquiring or transmitting serial data so as to match the reference cycle. Usually, synchronization is achieved by correcting the baud rate of the slave node so that it matches the baud rate of the master node. The slave node detects the length of the period of the reference clock (sink field) transmitted from the master node, and corrects the baud rate of the slave node based on this. This baud rate correction is executed every time the header arrives.

  By installing a function that automatically adjusts the baud rate on the slave node side to match the master node in this way, there is no need to provide a crystal oscillation circuit or the like that generates a high-accuracy clock on the slave node. Reduction is possible.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a conventional technique related to a baud rate generator equipped with a function for automatically correcting a baud rate. Patent Document 1 proposes a technique for reducing the load on the CPU when correcting the baud rate.

JP 2007-324679 A

  In the case of LIN, a communication frame (also referred to as a message frame) transmitted from the master node to the slave node is configured as shown in FIG. That is, in the frame header, a sync break field (break field), a sync field (synchronization byte), and an ID field (protection ID) are arranged in order from the top. Following this header, a response containing a data field of up to 8 bytes and a checksum of 1 byte is transferred. The break field is composed of a low level (dominant level) of 13 bits or more. A predetermined 8-bit data value “0x55 (hexadecimal notation)”, that is, “01010101” in which “0” and “1” are alternately arranged appears in the sync field. The ID field is composed of a 6-bit ID and a 2-bit parity.

  The slave node can detect the baud rate used for communication by the master node (transmission side) using the sync field of the communication frame that appears on the transmission path. That is, since “0” and “1” appear alternately during the sync field period, the time corresponding to the switching can be measured to detect the time corresponding to the baud rate.

  As a method for detecting this time, the following method is recommended in the LIN specification. That is, the time of 8 bits (corresponding to “0x55”) from the fall of the start bit to the fall of bit 7 is measured in the sync field. Then, the result is divided by 8. Thus, a time corresponding to the length of 1-bit data is obtained. The reciprocal of this time becomes the baud rate.

  In the prior art disclosed in Patent Document 1, the time of 8 bits in the sync field is measured using a counter, and the time value (binary number) obtained by the measurement is shifted by 4 bits in the lower direction. That is, the lower 4 bits of the time value (binary number) are truncated and only the remaining higher bits are extracted. This shift operation means that the time value (binary number) is divided by the decimal number “16”. By dividing the time length of 8 bits by “16”, the time corresponding to the data length of (1/2) bits is detected as a value corresponding to the baud rate.

  Incidentally, in the LIN specification, the allowable error of the corrected baud rate is within ± 2%. In order to satisfy this requirement, it is necessary to measure the time with high accuracy in the above-described baud rate detection. Specifically, it is necessary to sufficiently shorten the cycle of the clock pulse counted by the counter that measures time. That is, in order to make the time error corresponding to the time length (T1) of 1-bit data within ± 2%, it is necessary to make the cycle of the clock pulse within (T1 / 50) at the maximum.

  If the period of the clock pulse is (T1 / 50), the value of “50” is counted while the time length (T1) of 1-bit data is measured by the counter. A measurement error within “± 1” occurs in this count value due to a timing difference. That is, the measurement error of this counter is within (1/50), that is, within 2%.

  However, when the time length (T1) of 1-bit data is obtained by division (binary shift operation) from the 8-bit time obtained by measurement, the lower bits are rounded down. Calculation errors within the range of (−1 <calculation error ≦ 0) are also included. Therefore, considering this calculation error (absolute value is at most 1 or less) and measurement error (absolute value is at most 1 or less), in order to maintain the final error within the allowable range (within ± 2%) The period of the clock pulse needs to be within (T1 / 100) at the maximum.

  Further, in reality, counting and computation are performed in binary numbers, so the clock pulse cycle must be within (T1 / 128). However, when handling a clock pulse having a shorter cycle (high frequency), an oscillation circuit and a counter that operate at a high speed are required. Therefore, the cost of the circuit is increased, and an increase in power consumption is inevitable.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to make it possible to maintain the corrected baud rate within an allowable error range and to reduce the frequency of the clock pulse used for time measurement. A serial communication baud rate detecting device, a serial communication baud rate correcting device, and a serial communication baud rate detecting method are provided.

In order to achieve the above-described object, a serial communication baud rate detection apparatus according to the present invention is characterized by the following (1) to (2).
(1) A serial communication baud rate detection device that detects a baud rate of a transmission source using a measurement result related to a time length of a predetermined section of a serial communication signal transmitted through a transmission path,
A clock generator for generating clock pulses with a constant period;
A section detector for detecting the timing of the predetermined section;
A time measurement counter unit that counts clock pulses output from the clock generation unit during the predetermined period, and outputs a count result as a binary time measurement value;
The binary value of the time measurement value output by the time measurement counter unit is divided into an upper bit part and a lower bit part according to the bit configuration of the predetermined section, and the value of the most significant bit in the lower bit part is And a bit adder for adding to the value of the least significant bit in the upper bit part.
(2) The serial communication baud rate detecting device according to (1),
The bit adder section divides the lower 3 bits of the binary number of the time measurement value output from the time measurement counter section into the lower bit section and the other bits into the upper bit section.

According to the serial communication baud rate detection apparatus having the configuration (1), the frequency of the clock pulse used for time measurement can be lowered. That is, the calculation error included in the value extracted as the high-order bit part from the time measurement value is within the range of (−1 <calculation error ≦ 0), but the calculation error included in the result of the bit addition part. Is corrected to a range of (−0.5 <calculation error ≦ + 0.5). For this reason, the frequency of the clock pulse necessary for maintaining the baud rate within the allowable range (−2% ≦ final error ≦ + 2%) is reduced to about half compared with the case where the bit adder does not exist. That is, the cycle of the clock pulse can be changed from (T1 / 128) to (T1 / 64).
According to the serial communication baud rate detection device having the configuration (2), when the time measurement value is the time length of 8-bit data, the time length of 1-bit data (result divided by 8) is The upper bit part is extracted, and the lower bit part is a fractional part of the time length.

In order to achieve the above-described object, a serial communication baud rate correction apparatus according to the present invention is characterized by the following (3).
(3) Serial communication that detects the baud rate of the transmission source using the measurement result related to the time length of the predetermined section of the serial communication signal transmitted through the transmission path, and corrects the baud rate used by the own station based on the detected baud rate. Baud rate correction device for
A clock generator for generating clock pulses with a constant period;
A section detector for detecting the timing of the predetermined section;
A time measurement counter unit that counts clock pulses output from the clock generation unit during the predetermined period, and outputs a count result as a binary time measurement value;
The binary value of the time measurement value output by the time measurement counter unit is divided into an upper bit part and a lower bit part according to the bit configuration of the predetermined section, and the value of the most significant bit in the lower bit part is And a bit adder for adding to the value of the least significant bit in the upper bit part.

  According to the serial communication baud rate correction apparatus having the configuration (3), the frequency of the clock pulse necessary for maintaining the baud rate correction error in an allowable range can be lowered.

In order to achieve the above-described object, the serial communication baud rate detection method according to the present invention is characterized by the following (4).
(4) A serial communication baud rate detection method for detecting a baud rate of a transmission source using a measurement result relating to a time length of a predetermined section of a serial communication signal transmitted through a transmission path,
Generate clock pulses with a constant period,
Detecting the timing of the predetermined section;
The clock pulse is counted during the predetermined interval, and the counting result is acquired as a binary time measurement value,
The binary number of the time measurement value is divided into an upper bit part and a lower bit part according to the bit configuration of the predetermined section, and the value of the most significant bit in the lower bit part is set in the upper bit part. Output the result of adding to the value of the least significant bit.

  According to the serial communication baud rate detection method having the configuration (4), the frequency of the clock pulse used for time measurement can be lowered.

  According to the present invention, the frequency of the clock pulse used for measuring the time related to the baud rate can be lowered. Therefore, the circuit cost can be reduced and the increase in power consumption can be suppressed.

  The present invention has been briefly described above. Further, details of the present invention will be further clarified by reading through the modes for carrying out the invention described below with reference to the accompanying drawings.

It is a block diagram which shows the structural example of a communication system. It is a block diagram which shows the structure of the baud rate correction circuit of embodiment. It is a time chart which shows the structure of the communication frame which appears on a communication line. It is a time chart showing the operation | movement which measures the time of a sync field. It is a schematic diagram showing the operation | movement which calculates a baud rate correction value.

  Specific embodiments relating to a baud rate detection device for serial communication, a baud rate correction device for serial communication, and a baud rate detection method for serial communication according to the present invention will be described below with reference to the drawings.

  The baud rate detection device for serial communication of the present invention is used in a communication system having a configuration as shown in FIG. The communication system shown in FIG. 1 has a single master node 10 and two slave nodes 11 and 12, which are connected to each other via a communication line 13. The master node 10 controls subordinate slave nodes 11 and 12 in order to control the overall operation of the system. Each slave node 11, 12 performs control according to an instruction from the master node 10.

  Specifically, the communication system shown in FIG. 1 is assumed to be used as an in-vehicle communication system. That is, each of the master node 10 and the slave nodes 11 and 12 corresponds to an electronic control unit (ECU) for controlling the in-vehicle device, and these are communication networks conforming to the LIN communication standard, that is, via the communication line 13. As shown in FIG. In FIG. 1, the components other than those related to communication are not shown.

  As shown in FIG. 1, the master node 10 includes a microcomputer (CPU) 21, a memory 22, a clock generator 23, and a communication unit 24. The communication unit 24 includes an I / O (input / output) interface 25 and a baud rate correction circuit 26.

  The microcomputer 21 controls communication by executing a program prepared in advance on the memory 22. On the memory 22, programs for a master task and a slave task are prepared.

  The clock generator 23 generates a clock pulse for determining a reference timing related to an operation such as communication. In order to realize stable operation of the entire system, the clock generator 23 of the master node 10 is provided with a crystal oscillation circuit. The frequency of the clock pulse generated by the clock generator 23 is set to 64 times the baud rate used by the master node 10 for communication.

  The baud rate correction circuit 26 generates a timing signal necessary for the serial communication operation based on the clock pulse output from the clock generator 23. The baud rate correction circuit 26 includes a function (described later) for correcting the baud rate. However, since the master operation timing is a reference, the baud rate correction circuit 26 in the master node 10 does not perform the baud rate correction operation.

  The I / O interface 25 inputs transmission target data of the microcomputer 21 as parallel data, converts it into serial data, and sends serial data to the communication line 13 at a timing corresponding to the determined baud rate and the clock pulse. The serial data input from the communication line 13 is sampled at a timing corresponding to the baud rate and clock pulse, and the acquired data is converted into parallel data and output to the microcomputer 21.

  On the other hand, the slave node 11 includes a microcomputer (CPU) 31, a memory 32, a clock generator 33, and a communication unit 34. The communication unit 34 includes an I / O (input / output) interface 35 and a baud rate correction circuit 36.

  The microcomputer 31 controls communication by executing a program prepared in advance on the memory 32. On the memory 32, a slave task program is prepared.

  The clock generator 33 generates a clock pulse for determining a reference timing related to an operation such as communication. Since the clock pulse output from the clock generator 33 of the slave node 11 is not required to have high accuracy, the clock generator 33 can be configured with an inexpensive CR oscillation circuit or the like. The frequency of the clock pulse generated by the clock generator 33 is set to 64 times the baud rate used for communication.

  The baud rate correction circuit 36 generates a timing signal necessary for the serial communication operation based on the clock pulse output from the clock generator 33. The baud rate correction circuit 36 includes a function for maintaining the error of the baud rate used by the slave node 11 within an allowable range. The configuration and operation of the baud rate correction circuit 36 will be described in detail later.

The I / O interface 35 inputs transmission target data of the microcomputer 31 as parallel data, converts it into serial data, and sends serial data to the communication line 13 at a timing corresponding to the determined baud rate and the clock pulse. The serial data input from the communication line 13 is sampled at a timing corresponding to the baud rate and clock pulse, and the acquired data is converted into parallel data and output to the microcomputer 31.
The slave node 12 also has the same components as the slave node 11 described above.

  Next, an outline of the communication operation will be described. When the microcomputer 21 executes the master task program provided in the memory 22 of the master node 10, the master task is processed. In this master task, a message sequence for transferring a predetermined communication frame via the communication line 13 is incorporated in advance as a transfer schedule.

  When the microcomputer 21 processes the master task, a frame header of the communication frame is generated, and this frame header is sent from the I / O interface 25 to the communication line 13. In response to this frame header, a response from a specific slave node (slave node 11 or 12) designated by this frame header appears on the communication line 13, so the microcomputer 21 sends the response via the I / O interface 25. Receive.

  The slave task prepared in the memory 22 of the master node 10 or the memory 32 of the slave node 11 prepares a data field to be transferred for each communication frame. The slave task has a function of receiving a response from the master node or another slave node in addition to a function of transmitting a response.

  The communication frame (also referred to as a message frame) is configured as shown in FIG. That is, in the frame header, a sync break field (break field), a sync field (synchronization byte), and an ID field (protection ID) are arranged in order from the top. Following this header, a response containing a data field of up to 8 bytes and a checksum of 1 byte is transferred. The break field is composed of a low level (dominant level) of 13 bits or more. A predetermined 8-bit data value “0x55 (hexadecimal notation)”, that is, “01010101” in which “0” and “1” are alternately arranged appears in the sync field. The ID field is composed of a 6-bit ID and a 2-bit parity.

  The slave node can detect the baud rate used for communication by the master node (transmission side) using the sync field of the communication frame that appears on the transmission path. That is, since “0” and “1” appear alternately during the sync field period, the time corresponding to the switching can be measured to detect the time corresponding to the baud rate.

  A specific configuration of the baud rate correction circuit 36 in the present embodiment is shown in FIG. As shown in FIG. 2, the baud rate correction circuit 36 includes a baud rate detection circuit 40, a baud rate initial value register 51, a data selector 52, a counter 53, and a coincidence detection circuit 54. The baud rate detection circuit 40 includes an edge detection circuit 41, an edge counter 42, a time measurement timer 43, a measurement value holding unit 44, a measurement value holding unit 45, an adder 46, and a baud rate correction value register 47.

  When a sync field (L level of 11 bits or more) appears in a communication signal (serial signal as shown in FIG. 3) on the communication line 13, a sync field detection signal is input to the edge detection circuit 41 from a circuit not shown. In response to the sync field detection signal, the edge detection circuit 41 starts the falling edge detection operation of the serial signal. That is, the edge detection circuit 41 outputs a sync field start signal (measurement start signal) to the edge counter 42 and the time measurement timer 43 when detecting the falling edge of the start bit of the sync field. The edge detection circuit 41 outputs an edge detection signal to the edge counter 42 every time a falling edge is detected in the sync field. The detection operation of the edge detection circuit 41 is performed in synchronization with the clock pulse output from the clock generator 33.

  The edge counter 42 starts operation in response to the sync field start signal output from the edge detection circuit 41 and counts the edge detection signal. That is, the edge counter 42 counts the number of falling edges in the sync field. When the edge counter 42 counts the edge detection signal up to a predetermined number of times after receiving the sync field start signal (measurement start signal in FIG. 4), the sync counter ends with respect to the time measurement timer 43 and the baud rate correction value register 47. A signal (measurement end signal in FIG. 4) is output.

  The time measurement timer 43 measures time by counting clock pulses having a constant cycle output from the clock generator 33. Specifically, the time measurement timer 43 starts from the time when the sync field start signal (measurement start signal) output from the edge detection circuit 41 appears until the time when the sync field end signal (measurement end signal) output from the edge counter 42 appears. Is measured by the number of clock pulses. Accordingly, the time measurement timer 43 outputs a value corresponding to the length of the “measurement time” shown in FIG.

  The time measurement timer 43 is composed of the “measurement time”, which is a measurement result, by bits B1, B2, B3, B4, B5, B6, B7, B8, B9, and B10 such as the count value D1 shown in FIG. Output as 10-bit data. Here, in the 10-bit count value D1, the least significant bit (LSB) is B1, and the most significant bit (MSB) is B10.

  By the way, the “measurement time” corresponds to the time required for 8-bit serial data to appear in the sync field. Therefore, in order to obtain the time length of data per bit that is the reciprocal of the baud rate, the “measurement time” may be divided by “8”. In the calculation of binary numbers, truncating the lower 3 bits of data means dividing by “8”. That is, in the count value D1 shown in FIG. 5, when “B1, B2, B3” is classified as the lower bit part and “B4, B5, B6, B7, B8, B9, B10” is divided as the upper bit part, By extracting only the part, the time length of data per bit can be obtained.

  However, a calculation error occurs for the lower-order bit portion that is discarded. The range of the calculation error in this case is (−1 <calculation error ≦ 0) when the value of the upper bit part extracted after division is considered as an integer in decimal. That is, a calculation error occurs only in the minus direction. This calculation error has an important meaning in the control for maintaining the baud rate error within an allowable range.

  That is, in the LIN specification, the allowable error of the baud rate is in the range of (−2% ≦ error ≦ + 2%), whereas the detection error of the baud rate includes a calculation error that is biased only in the negative direction. Therefore, it is necessary to greatly reduce errors that occur during time measurement. For this purpose, the frequency of the clock pulse output from the clock generator 33 must be sufficiently high.

  In the baud rate detection circuit 40 shown in FIG. 2, the baud rate is within an allowable range (−2% ≦ error ≦ + 2%) even when the frequency of the clock pulse output from the clock generator 33 is relatively low (the cycle is long). ) Is specially devised so that it can be maintained.

  The measurement value holding unit 44 inputs the upper bit part (B4 to B10) of “measurement time (D1 in FIG. 5)” output from the time measurement timer 43 when the time measurement timer 43 completes the measurement. Hold. The measurement value holding unit 45 is the highest bit among the lower-order bits (B1 to B3) of “measurement time (D1 in FIG. 5)” output from the time measurement timer 43 when the time measurement timer 43 completes the measurement. The bit (B3) is input and held.

  The adder 46 inputs the 7-bit value (B4 to B10) held by the measurement value holding unit 44 and the 1-bit value (B3) held by the measurement value holding unit 45 and inputs them. Add as a binary number. The addition result of the adder 46 is held in the baud rate correction value register 47.

  For example, as shown on the left side of FIG. 5 (plus correction), when the most significant bit (B3) of the lower bit part (B1 to B3) is “1”, this and the upper bit part (B4 to B10) Are added by the adder 46, and the influence of the bit (B3) is reflected in the result (baud rate correction value). On the other hand, as shown on the right side of FIG. 5 (minus correction), when the most significant bit (B3) of the lower bit portion (B1 to B3) is “0”, this and the upper bit portion (B4 to B10). Are added by the adder 46 (baud rate correction value), and the influence of the lower bits (B1 to B3) does not appear.

  That is, in the addition process in the adder 46, only the most significant bit (B3) of the lower bit part (B1 to B3) is added to the upper bit part (B4 to B10) as shown in FIG. This means that the above-mentioned range of (−1 <calculation error ≦ 0) is corrected to (−0.5 <calculation error ≦ + 0.5).

  Thereby, even when the frequency of the clock pulse counted by the time measurement timer 43 is relatively low, it is possible to maintain the deviation of the baud rate caused by the calculation error within an allowable range (−2% ≦ error ≦ + 2%). Become. Specifically, when the addition process shown in FIG. 5 is not performed by the adder 46, the clock pulse frequency must be set to 128 times the baud rate or more in order to maintain the deviation of the baud rate within an allowable range. However, by performing addition processing by the adder 46, even if the frequency of the clock pulse is 64 times the baud rate, the deviation of the baud rate can be maintained within an allowable range.

  The baud rate initial value register 51 holds an initial value of a predetermined baud rate as a constant. In the initial state where the actual baud rate is unknown, the microcomputer 31 applies the initial value of the baud rate held in the baud rate initial value register 51 to the coincidence detection circuit 54 via the data selector 52. Then, after the baud rate detection circuit 40 completes the above-described operation and the baud rate correction value, which is a measured value, is held in the baud rate correction value register 47, the microcomputer 31 switches the data selector 52 to change the baud rate correction value register 47. The baud rate correction value is applied to the coincidence detection circuit 54.

  The counter 53 counts clock pulses output from the clock generator 33. The coincidence detection circuit 54 compares the count value of the counter 53 with the baud rate initial value of the baud rate initial value register 51 or the baud rate correction value of the baud rate correction value register 47 to identify the presence or absence of the coincidence, and the coincidence detection signal Is output. The coincidence detection signal is input to the I / O interface 35 and generates a sampling clock signal for acquiring information from serial data appearing on the communication line 13 and a shift clock signal for transmitting serial data. Used as a timing signal.

  The I / O interface 35 acquires serial data input from the communication line 13 at a timing according to the sampling clock signal, and converts it into parallel data. The converted data is read by the microcomputer 31. Further, each bit of the parallel data output for transmission from the microcomputer 31 is sequentially output to the communication line 13 as serial data at a timing according to the shift clock signal.

  As described above, the baud rate correction circuit 36 provided in the slave nodes 11 and 12 detects the actual baud rate of the communication signal sent from the master node 10 to the communication line 13, and corrects the baud rate so as to follow the detected value. A value is generated to automatically correct the communication timing. Therefore, high accuracy and stability are not required for the clock pulse generated by the clock generator 33. Therefore, there is no problem even if the clock generator 33 employs an inexpensive circuit such as a CR oscillation circuit.

  In order to maintain the deviation of the baud rate within an allowable range (−2% ≦ error ≦ + 2%), the time measurement timer 43 measures the time length using a clock pulse having a frequency sufficiently higher than the baud rate. There is a need to do. However, since the adder 46 in the baud rate detection circuit 40 performs the above-described processing, even if the clock pulse frequency is lowered to about 64 times the baud rate, the deviation of the baud rate can be maintained within an allowable range.

  By reducing the frequency of the clock pulse, the cost of the clock generator 33 itself and the circuit for processing the clock pulse output from the clock generator 33 itself can be reduced, and the power consumed by these circuits can also be reduced.

  Note that, as in the circuit configuration shown in FIG. 2, by installing dedicated hardware as a baud rate correction circuit, the burden of processing executed by the microcomputer 31 can be reduced. However, when the processing capability of the microcomputer 31 is sufficient, the processing of the baud rate detection circuit 40 and the like can be realized by the internal processing of the microcomputer 31, that is, the execution of the program. The mounting of the wear can be partially omitted.

  As described above, the serial communication baud rate detection device, serial communication baud rate correction device, and serial communication baud rate detection method of the present invention perform data communication between a plurality of units in accordance with a standard such as LIN, for example, as in an in-vehicle control system. The present invention can be applied to a communication system. By implementing the present invention, it is possible to reduce the frequency of the clock pulse used when detecting the baud rate and the like, thereby realizing a reduction in circuit cost and power consumption.

10 Master node 11, 12 Slave node 13 Communication line 21, 31 Microcomputer (CPU)
22, 32 Memory 23, 33 Clock generator 24, 34 Communication unit 25, 35 I / O interface 26, 36 Baud rate correction circuit (baud rate correction device for serial communication)
40 Baud rate detection circuit (Baud rate detection device for serial communication)
41 Edge detection circuit 42 Edge counter 43 Time measurement timer 44, 45 Measurement value holding unit 46 Adder 47 Baud rate correction value register 51 Baud rate initial value register 52 Data selector 53 Counter 54 Match detection circuit

Claims (4)

A serial communication baud rate detection device that detects a baud rate of a transmission source using a measurement result relating to a time length of a predetermined section of a serial communication signal transmitted through a transmission path,
A clock generator for generating clock pulses with a constant period;
A section detector for detecting the timing of the predetermined section;
A time measurement counter unit that counts clock pulses output from the clock generation unit during the predetermined period, and outputs a count result as a binary time measurement value;
The binary value of the time measurement value output by the time measurement counter unit is divided into an upper bit part and a lower bit part according to the bit configuration of the predetermined section, and the value of the most significant bit in the lower bit part is A baud rate detecting device for serial communication, comprising: a bit adding unit that adds to a value of the least significant bit in the upper bit unit. The bit addition unit divides the lower 3 bits of the binary number of the time measurement value output from the time measurement counter unit into the lower bit unit and the other bits into the upper bit unit. The baud rate detection device for serial communication according to 1. Baud rate correction for serial communication that detects the baud rate of the transmission source using the measurement result related to the time length of a predetermined section of the serial communication signal transmitted through the transmission path, and corrects the baud rate used by the own station based on the detected baud rate A device,
A clock generator for generating clock pulses with a constant period;
A section detector for detecting the timing of the predetermined section;
A time measurement counter unit that counts clock pulses output from the clock generation unit during the predetermined period, and outputs a count result as a binary time measurement value;
The binary value of the time measurement value output by the time measurement counter unit is divided into an upper bit part and a lower bit part according to the bit configuration of the predetermined section, and the value of the most significant bit in the lower bit part is A baud rate correction device for serial communication, comprising: a bit addition unit that adds to a value of the least significant bit in the upper bit unit. A serial communication baud rate detection method for detecting a baud rate of a transmission source using a measurement result related to a time length of a predetermined section of a serial communication signal transmitted through a transmission path,
Generate clock pulses with a constant period,
Detecting the timing of the predetermined section;
The clock pulse is counted during the predetermined interval, and the counting result is acquired as a binary time measurement value,
The binary number of the time measurement value is divided into an upper bit part and a lower bit part according to the bit configuration of the predetermined section, and the value of the most significant bit in the lower bit part is set in the upper bit part. A baud rate detection method for serial communication, characterized in that the result of adding to the value of the least significant bit is output.

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