JP2011228762A - Differential output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the waveform quality of an output signal.SOLUTION: A controller (102) switches over a first output state where switching elements (SW1 and SW4) are in ON state and switching elements (SW2 and SW3) are in OFF state and a second output state where switching elements (SW1 and SW4) are in OFF state and switching elements (SW2 and SW3) are in ON state. In addition, when switching from the first output state to the second output state, the controller (102) switches the switching elements (SW1 and SW4) from ON state to OFF state at a lapse of a variable delay time from when the switching elements (SW2 and SW3) are switched from OFF state to ON state. Further, when switching from the second output state to the first output state, the controller (102) switches the switching elements (SW2 and SW3) from ON state to OFF state at a lapse of the variable delay time from when the switching elements (SW1 and SW4) are switched from OFF state to ON state.

Description

  The present invention relates to a differential output circuit integrated in a semiconductor, and more particularly to a differential output circuit having a function of adjusting a slew rate, which is a transition time of a waveform output, in order to realize high-speed transmission of the waveform. .

  In recent years, with the miniaturization / acceleration of integrated circuits, differential output circuits such as LVDS (Low Voltage Differential Signals) interfaces have come to be adopted as high-speed signal transmission means.

  FIG. 7 shows a configuration example of a general differential output circuit. The differential output circuit 80 outputs a pair of output signals OUT81 and OUT82 corresponding to the input signal IN to the receiving unit 90, and includes an inverter 800, current sources IS81 and IS82, and switching elements SW81 to SW84. . A load resistor R90 and a parasitic capacitance C90 are added to the signal lines L81 and L82.

  Here, the operation of the differential output circuit 80 shown in FIG. 7 will be described with reference to FIG.

  At time t91, the signal level of the non-inverted signal INP (input signal IN) changes from the low level to the high level, and the signal level of the inverted signal INN changes from the high level to the low level. As a result, the switching elements SW81 and SW84 transition from the on state to the off state, and the switching elements SW82 and SW83 transition from the off state to the on state. As a result, the direct current supplied from the current source IS81 flows into the ground node via the switching element SW82, the signal line L82, the load resistor R90, the signal line L81, the switching element SW83, and the current source IS82.

  At time t92, the signal level of the non-inverted signal INP changes from a high level to a low level, and the signal level of the inverted signal INN changes from a low level to a high level. As a result, the switching elements SW81 and SW84 transition from the off state to the on state, and the switching elements SW82 and SW83 transition from the on state to the off state. As a result, the direct current supplied from the current source IS81 flows into the ground node via the switching element SW81, the signal line L81, the load resistor R90, the signal line L82, the switching element SW84, and the current source IS82.

  In order to actually perform high-speed signal transmission, it is necessary to improve the waveform quality of the output signals OUT81 and OUT82 so as not to cause a malfunction. Ringing and transmission reflection can be considered as factors that deteriorate the waveform quality. Ringing and transmission reflection are affected by parasitic components (inductance component (L), capacitance component (C), resistance component (R)) in IO cells, lead frames, and bonding wires on the differential output circuit side and the receiving unit side, It occurs due to the influence of parasitic components between the semiconductor chip and the substrate wiring on the board on which the semiconductor chip is mounted. Also, ringing and transmission reflection are closely related to transmission speed and slew rate, and it is necessary to select an optimal slew rate in order to realize high-speed transmission with good waveform quality.

  Therefore, in Patent Document 1, a variable capacitor is provided between two signal lines for transmitting a pair of output signals constituting a differential signal, and the capacitance value of the variable capacitor is adjusted by register control. A technique for adjusting the slew rate is described.

JP-A-2005-191915

  However, with the technique (slew rate adjustment) disclosed in Patent Document 1, it is difficult to sufficiently improve the waveform quality of the output signal. Here, the waveform of the output signal will be described with reference to FIG. The waveform line a91 indicates the waveform of the output signal when the capacitance value of the variable capacitor (variable capacitor provided between the two signal lines for transmitting the output signal) is relatively small, and the waveform line a92. Shows the waveform of the output signal when the capacitance value of the variable capacitor is relatively large. By increasing the capacitance value of the variable capacitor, as shown in FIG. 9, the slew rate of the output signal is reduced (the waveform of the output signal is reduced) in the section from the cross point CP9 to the saturation voltage, but the rising point RP9. The slew rate of the output signal does not change during the period from to the cross point CP9. This is because the slew rate of the output signal is determined by the CR time constant defined by the ON resistance value of the switching element, the resistance value of the external load resistance, the capacitance value of the variable capacitor, and the capacitance value of the parasitic capacitance of the signal line. It is. Thus, it is difficult for the technique of Patent Document 1 to linearly adjust the slew rate of the output signal.

  Therefore, an object of the present invention is to provide a differential output circuit that can improve the waveform quality of an output signal by adjusting the slew rate substantially linearly.

  According to one aspect of the present invention, the differential output circuit is a circuit that outputs first and second output signals, and outputs the first and second current sources and the first output signal. A first switching element connected between the first output node for the first current source and the first current source; a second output node for outputting the second output signal; and the first current A second switching element connected between the source, a third switching element connected between the first output node and the second current source, the second output node, and the A fourth switching element connected to the second current source, and the first and fourth switching elements are in an on state and the second and third switching elements are in an off state. Output state and the first and fourth switches Switching the second output state in which the second and third switching elements are in the on state and the second output state is switched from the first output state to the second output state. In the case, the first and fourth switching elements are switched from the on state to the off state after the variable delay time has elapsed since the switching of the second and third switching elements from the off state to the on state, and When the second output state is switched to the first output state, the second and third switching elements are switched after the variable delay time has elapsed after the first and fourth switching elements are switched from the off state to the on state. And a control unit that switches the switching element from the on state to the off state.

  In the above differential output circuit, the slew rate of the output signal can be adjusted while shifting the cross point of the output signal by adjusting the variable delay time, so that the slew rate of the output signal can be adjusted substantially linearly. Thereby, the waveform quality of an output signal can be improved.

  The control unit is provided with first and second input signals whose signal levels change complementarily, and the control unit receives a second voltage from the first voltage level of the first input signal. A first amplifier for generating a first control signal by delaying a transition to a voltage level by a time constant corresponding to the variable delay time; and a second voltage from a first voltage level of the second input signal. A second amplifier for generating a second control signal by delaying the transition to the level by a time constant corresponding to the variable delay time; and a first voltage level from the second voltage level of the first input signal. A third amplifier for generating a third control signal by delaying the transition to a time constant corresponding to the variable delay time, and from the second voltage level of the second input signal to the first voltage level. The fourth transition is delayed by a time constant corresponding to the variable delay time. A time constant of each of the first to fourth amplifiers is variable, and the first switching element has a signal level of the first control signal of the first amplifier. When the voltage level is 1, the signal is turned on. When the signal level of the first control signal is the second voltage level, the signal is turned off. The second switching element is When the signal level of the second control signal is the first voltage level, it is turned on, and when the signal level of the second control signal is the second voltage level, it is turned off. The switching element is turned off when the signal level of the third control signal is the first voltage level, and when the signal level of the third control signal is the second voltage level. The fourth switch is turned on The switching element is turned off when the signal level of the fourth control signal is the first voltage level, and is turned on when the signal level of the fourth control signal is the second voltage level. It may be in a state. With this configuration, the variable delay time can be adjusted by adjusting the time constants of the first to fourth amplifiers.

  Each of the first to fourth amplifiers includes a resistor and a capacitor that define a time constant of the amplifier. In each of the first to fourth amplifiers, a resistance value of the resistor and a capacitance of the capacitor At least one of the values may be variable. With this configuration, by adjusting at least one of the resistance value of the resistor and the capacitance value of the capacitor included in each of the first to fourth amplifiers, each time of the first to fourth amplifiers is adjusted. The constant can be adjusted.

  Alternatively, each of the first to fourth amplifiers includes a resistor, a capacitor, and a current source that define a time constant of the amplifier. In each of the first to fourth amplifiers, a resistance value of the resistor, At least one of the capacitance value of the capacitor and the current value of the current source may be variable. With this configuration, the first to fourth amplifiers are adjusted by adjusting at least one of the resistance value of the resistor, the capacitance value of the capacitor, and the current value of the current source included in each of the first to fourth amplifiers. The time constant of each of the four amplifiers can be adjusted.

  As described above, the slew rate of the output signal can be adjusted almost linearly, and the waveform quality of the output signal can be improved.

The figure which shows the structural example of a differential output circuit. The figure which shows the structural example of the control part shown in FIG. FIG. 3 is a diagram for explaining the operation of the differential output circuit shown in FIG. 1. The figure for demonstrating the waveform of the output signal of the differential output circuit shown in FIG. The figure for demonstrating the modification 1 of the control part shown in FIG. The figure for demonstrating the modification 2 of the control part shown in FIG. The figure which shows the structural example of the conventional differential output circuit. FIG. 8 is a diagram for explaining an operation of the differential output circuit illustrated in FIG. 7. The figure for demonstrating the waveform of the output signal of the differential output circuit shown in FIG.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Differential output circuit)
FIG. 1 shows a configuration example of a differential output circuit. The differential output circuit 10 outputs a pair of output signals OUT1 and OUT2 corresponding to the input signal IN to the receiving unit 20, and includes an inverter 100, an output unit 101, and a control unit 102. A load resistor R20 and a parasitic capacitance C20 are added to the signal lines L1 and L2. The inverter 100 inverts the input signal IN to generate an inverted signal INN.

[Output section]
Output unit 101 includes current sources IS1 and IS2 and switching elements SW1 to SW4. Switching element SW1 is connected between output node N1 (node for outputting output signal OUT1) and current source IS1, and switching element SW2 is connected to output node N2 (node for outputting output signal OUT2). It is connected between the current source IS1. Switching element SW3 is connected between output node N1 and current source IS2, and switching element SW4 is connected between output node N2 and current source IS2.

(Control part)
The control unit 102 includes a state in which the switching elements SW1 and SW4 are in the on state and the switching elements SW2 and SW3 are in the off state (first output state), a state in which the switching elements SW1 and SW4 are in the off state, and the switching element SW2 , SW3 is switched to the on state (second output state). In addition, when switching from the first output state to the second output state, the control unit 102 switches the switching elements SW2 and SW3 from the off state to the on state after the variable delay time Δt has elapsed. SW1 and SW4 are switched from the on state to the off state. Further, when switching from the second output state to the first output state, the control unit 102 switches the switching elements SW1 and SW4 from the off state to the on state after the variable delay time Δt has elapsed. SW2 and SW3 are switched from the on state to the off state. The variable delay time Δt can be changed by register control (control signal CTRL from the register 30). For example, the control unit 102 includes amplifiers 111 to 114 that generate control signals S1 to S4 for controlling on / off of the switching elements SW1 to SW4, respectively.

〔Amplifier〕
The amplifiers 111 and 112 respectively delay the transition from the low level to the high level of the inverted signal INN and the non-inverted signal INP (that is, the input signal IN) by a predetermined time constant (time constant corresponding to the variable delay time Δt). The control signals S1 and S2 are generated, and the amplifiers 113 and 114 change the inversion signal INN and the non-inversion signal INP from high level to low level, respectively, with a predetermined time constant (time constant corresponding to the variable delay time Δt). ) To generate control signals S3 and S4. The time constants of the amplifiers 111 to 114 can be changed by register control (control signal CTRL from the register 30).

  As shown in FIG. 2, each of the amplifiers 111 and 112 may include an nMOS transistor Tr11, a resistor R11, and a variable capacitor C11. The source of the nMOS transistor Tr11 is connected to the ground node, and the inverted signal INN (or non-inverted signal INP) is applied to the gate of the nMOS transistor Tr11. The resistor R11 is connected between the drain of the nMOS transistor Tr11 and a power supply node (a node to which the power supply voltage Vcc is applied), and the variable capacitor C11 is connected between the drain of the nMOS transistor Tr11 and the ground node. Further, the capacitance value of the variable capacitor C11 can be changed by a control signal CTRL from the register 30. Each of the amplifiers 113 and 114 may include an nMOS transistor Tr12, a resistor R12, and a variable capacitor C12. The drain of the nMOS transistor Tr12 is connected to the power supply node, and the inverted signal INN (or the non-inverted signal INP) is applied to the gate of the nMOS transistor Tr12. The resistor R12 is connected between the source of the nMOS transistor Tr12 and the ground node, and the variable capacitor C12 is connected between the source of the nMOS transistor Tr12 and the ground node. Further, the capacitance value of the variable capacitor C12 can be changed by the control signal CTRL from the register 30.

  For example, by increasing the capacitance value of the variable capacitor C11 of the amplifier 111 by the control signal CTRL, the time constant of the amplifier 111 (time constant when the control signal S1 transits from high level to low level) is increased, and as a result The time from when the switching elements SW2 and SW3 transition from the off state to the on state until the switching element SW1 transitions from the on state to the off state (that is, the variable delay time Δt) can be increased. The same applies to the amplifiers 112 to 114. Thus, the variable delay time Δt can be adjusted by the control signal CTRL.

[Operation]
Next, the operation of the differential output circuit 10 shown in FIG. 1 will be described with reference to FIG.

  At time t1, the signal level of the non-inverted signal INP changes from the low level to the high level, and the signal level of the inverted signal INN changes from the high level to the low level. As a result, the signal level of the control signal S1 changes from a high level to a low level, and the signal level of the control signal S4 changes from a low level to a high level. As a result, the switching elements SW1 and SW4 transition from the off state to the on state. On the other hand, the signal level of the control signal S2 changes from a low level to a high level with a time constant defined by the capacitance value of the variable capacitor C11 and the resistance value of the resistor R11 of the amplifier 112, and the signal level of the control signal S3 is A transition is made from a high level to a low level with a time constant defined by the capacitance value of the variable capacitor C12 113 and the resistance value of the resistor R12. Therefore, the signal level of the control signal S2 does not reach the high level and the signal level of the control signal S3 reaches the low level until the variable delay time Δt elapses from the time t1 (that is, until the time t2 is reached). do not do. Therefore, the switching elements SW2 and SW3 are maintained in the on state.

  As described above, since all of the switching elements SW1 to SW4 are in the ON state during the period of time t1 to t2, the direct current supplied from the current source IS1 passes through the switching elements SW1 to SW4 and the load resistor R20. Flow into the ground node. Therefore, a current corresponding to the difference between the direct current flowing from the current source IS1 and the current flowing through the switching elements SW1 to SW4 flows through the load resistor R20, and the output signals OUT1 and OUT2 fluctuate transiently.

  At time t2, the signal level of the control signal S2 reaches a high level, and the signal level of the control signal S3 reaches a low level. As a result, the switching elements SW2 and SW3 transition from the on state to the off state.

  Thus, in the period from time t2 to t3, the switching elements SW1 and SW4 are in the on state and the switching elements SW2 and SW3 are in the off state, so the direct current supplied from the current source IS1 is It flows into the ground node via the switching element SW1, the signal line L1, the load resistor R20, the signal line L2, the switching element SW4, and the current source IS2. Therefore, a current flows through the load resistor R20 in the direction A in the figure, and the output signals OUT1 and OUT2 have constant values.

  At time t3, the signal level of the non-inverted signal INP changes from the high level to the low level, and the signal level of the inverted signal INN changes from the low level to the high level. As a result, the signal level of the control signal S2 changes from a high level to a low level, and the signal level of the control signal S3 changes from a low level to a high level. As a result, the switching elements SW2 and SW3 transition from the off state to the on state. On the other hand, the signal level of the control signal S1 changes from a low level to a high level with a time constant defined by the capacitance value of the variable capacitor C11 and the resistance value of the resistor R11 of the amplifier 111, and the signal level of the control signal S4 is The transition is made from the high level to the low level with a time constant defined by the capacitance value of the variable capacitor C12 and the resistance value of the resistor R12. Therefore, the signal level of the control signal S1 does not reach the high level until the variable delay time Δt elapses from the time t3 (that is, until the time t4), and the signal level of the control signal S4 reaches the low level. do not do. Therefore, the switching elements SW1 and SW4 are maintained in the on state.

  As described above, since all of the switching elements SW1 to SW4 are in the ON state during the period of time t3 to t4, the direct current supplied from the current source IS1 passes through the switching elements SW1 to SW4 and the load resistor R20. Flow into the ground node. Therefore, a current corresponding to the difference between the direct current flowing from the current source IS1 and the current flowing through the switching elements SW1 to SW4 flows through the load resistor R20, and the output signals OUT1 and OUT2 fluctuate transiently.

  At time t4, the signal level of the control signal S1 reaches a high level, and the signal level of the control signal S4 reaches a low level. As a result, the switching elements SW1 and SW4 transition from the on state to the off state.

  Thus, in the period from time t4 to t5, the switching elements SW1 and SW4 are in the off state, and the switching elements SW2 and SW3 are in the on state, so that the direct current supplied from the current source IS1 is switched It flows into the ground node via element SW2, signal line L2, load resistor R20, signal line L1, switching element SW3, and current source IS2. Therefore, a current flows through the load resistor R20 in the direction B in the figure, and the output signals OUT1 and OUT2 have constant values.

  After time t5, the above-described operations from time t1 to t4 are repeated. That is, the first output state (the switching elements SW1 and SW4 are in the on state and the switching elements SW2 and SW3 are in the off state) to the second output state (the switching elements SW1 and SW4 are in the off state and the switching is performed). When the elements SW2 and SW3 are switched to the ON state) or when switching from the second output state to the first output state, all the switching elements SW1 to SW4 are turned on.

[Slew rate adjustment]
Next, the slew rate adjustment will be described with reference to FIG. The waveform line a1 indicates the waveforms of the output signals OUT1 and OUT2 when the variable delay time Δt is relatively short (when the time constants of the amplifiers 111 to 114 are relatively small), and the waveform line a2 indicates the variable delay time Δt. Shows the waveforms of the output signals OUT1, OUT2 when is relatively long (when the time constants of the amplifiers 111 to 114 are relatively large). When the variable delay time Δt is increased, as shown in FIG. 4, the slew rate of the output signals OUT1 and OUT2 is reduced (the waveforms of the output signals OUT1 and OUT2 are reduced), and the cross point CP of the output signals OUT1 and OUT2 is delayed. To do.

  As described above, by adjusting the variable delay time Δt, the slew rate of the output signals OUT1 and OUT2 can be adjusted while shifting the cross point CP of the output signals OUT1 and OUT2. Thereby, the slew rate can be adjusted almost linearly, and the waveform quality of the output signal of the differential output circuit can be improved. Further, since the optimum slew rate can be selected, the design period of the differential output circuit can be shortened.

(Modification 1 of control part)
As shown in FIG. 5, each of the amplifiers 111 and 112 may include a capacitor C13 and a variable resistor R13 instead of the capacitor C11 and the resistor R11 shown in FIG. In addition, each of the amplifiers 113 and 114 may include a capacitor C14 and a variable resistor R14 instead of the variable capacitor C12 and the resistor R12 shown in FIG. The resistance values of the variable resistors R13 and R14 can be changed by a control signal CTRL from the register 30. Even in such a configuration, the time constants of the amplifiers 111 to 114 can be adjusted by the control signal CTRL, and as a result, the variable delay time Δt can be adjusted. In the amplifiers 111 to 114 shown in FIG. 5, the capacitance values of the capacitors C13 and C14 may be changeable by the control signal CTRL. That is, in each of the amplifiers 111 to 114, at least one of the resistance value of the resistor and the capacitance value of the capacitor may be variable.

(Modification 2 of the control unit)
Further, as shown in FIG. 6, each of the amplifiers 111 and 112 may include a capacitor C13 and a variable current source IS13 instead of the variable capacitor C11 shown in FIG. Each of the amplifiers 113 and 114 may include a capacitor C14 and a variable current source IS14 instead of the variable capacitor C12 shown in FIG. The current values of the variable current sources IS13 and IS14 can be changed by the control signal CTRL from the register 30. Even in such a configuration, the time constants of the amplifiers 111 to 114 can be adjusted by the control signal CTRL, and as a result, the variable delay time Δt can be adjusted. In each of the amplifiers 111 to 114 shown in FIG. 6, the resistance values of the resistors R11 and R12 may be changed by the control signal CTRL, and the capacitance values of the capacitors C13 and C14 can be changed by the control signal CTRL. It may be. That is, in each of the amplifiers 111 to 114, at least one of the resistance value of the resistor, the capacitance value of the capacitor, and the current value of the current source may be variable.

  As described above, the differential output circuit described above can improve the waveform quality of the output signal by adjusting the slew rate of the output signal substantially linearly, and thus is useful for devices that perform high-speed data transmission.

DESCRIPTION OF SYMBOLS 10 Differential output circuit 101 Output part IS1, IS2 Current source SW1, SW2, SW3, SW4 Switching element 102 Control part 111,112,113,114 Amplifier Tr11, Tr12 nMOS transistor C11, C12 Variable capacity | capacitance R11, R12 Resistance C13, C14 Capacitance R13, R14 Variable resistance IS13, IS14 Variable current source

Claims (4)

A circuit for outputting first and second output signals,
First and second current sources;
A first switching element connected between a first output node for outputting the first output signal and the first current source;
A second switching element connected between a second output node for outputting the second output signal and the first current source;
A third switching element connected between the first output node and the second current source;
A fourth switching element connected between the second output node and the second current source;
A first output state in which the first and fourth switching elements are on and the second and third switching elements are off; and the first and fourth switching elements are off. In addition, the second and third switching elements are switched to the second output state where the second and third switching elements are in the on state, and when switching from the first output state to the second output state, the second output state And after the variable delay time has elapsed since switching the third switching element from the off state to the on state, the first and fourth switching elements are switched from the on state to the off state, and the second output state to the first state In the case of switching to the output state 1, the first and fourth switching elements are switched from the off state to the on state, and then the variable delay time is reached. Differential output circuit, characterized in that it comprises a control unit but for switching the second and third switching element from the on state after a lapse of the off-state. In claim 1,
The control unit is provided with first and second input signals whose signal levels change complementarily,
The controller is
A first amplifier for generating a first control signal by delaying a transition from a first voltage level to a second voltage level of the first input signal by a time constant corresponding to the variable delay time;
A second amplifier for generating a second control signal by delaying a transition from a first voltage level to a second voltage level of the second input signal by a time constant corresponding to the variable delay time;
A third amplifier for delaying a transition from the second voltage level to the first voltage level of the first input signal by a time constant corresponding to the variable delay time to generate a third control signal;
A fourth amplifier for generating a fourth control signal by delaying a transition from the second voltage level to the first voltage level of the second input signal by a time constant corresponding to the variable delay time. ,
The time constant of each of the first to fourth amplifiers is variable,
The first switching element is turned on when the signal level of the first control signal is the first voltage level, and the signal level of the first control signal is the second voltage level. In the off state,
The second switching element is turned on when the signal level of the second control signal is the first voltage level, and the signal level of the second control signal is the second voltage level. In the off state,
The third switching element is turned off when the signal level of the third control signal is the first voltage level, and the signal level of the third control signal is the second voltage level. In the case,
The fourth switching element is turned off when the signal level of the fourth control signal is the first voltage level, and the signal level of the fourth control signal is the second voltage level. In some cases, the differential output circuit is turned on. In claim 2,
Each of the first to fourth amplifiers includes a resistor and a capacitor that define a time constant of the amplifier,
In each of the first to fourth amplifiers, at least one of a resistance value of the resistor and a capacitance value of the capacitor is variable. In claim 2,
Each of the first to fourth amplifiers includes a resistor, a capacitor, and a current source that define a time constant of the amplifier,
In each of the first to fourth amplifiers, at least one of a resistance value of the resistor, a capacitance value of the capacitor, and a current value of a current source is variable.

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