JP2011228651A - Method for reclaiming semiconductor substrate, method for manufacturing reclaimed semiconductor substrate, and method for manufacturing soi substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a suitable method for reclaiming a semiconductor substrate, a method for manufacturing a reclaimed semiconductor substrate using a suitable method for reclaiming a semiconductor substrate, and a method for manufacturing an SOI substrate using the reclaimed semiconductor substrate.SOLUTION: A semiconductor substrate having projections including damaged semiconductor region and insulating layer at the peripheries of the semiconductor substrate is reclaimed by performing: an etching treatment for removing an insulating layer; an etching treatment for removing the damaged semiconductor region in preference to an undamaged semiconductor region using a mixture containing a substance oxidizing a semiconductor material forming the semiconductor substrate, a substance dissolving the oxidized semiconductor material, and a substance controlling the speed of oxidizing the semiconductor material and the speed of dissolving the oxidized semiconductor material; and a laser beam irradiation step.

Description

One embodiment of the present invention relates to a method for recycling a semiconductor substrate. Alternatively, the present invention relates to a method for manufacturing a regenerated semiconductor substrate using a method for regenerating a semiconductor substrate, and a method for manufacturing an SOI (Silicon on Insulator) substrate.

In recent years, integrated circuits using an SOI (Silicon on Insulator) substrate in which a thin single crystal silicon layer is provided on an insulating surface instead of a bulk silicon wafer have been developed. When a thin single crystal silicon layer formed over an insulating surface is used, each transistor included in the integrated circuit can be easily separated and a fully depleted type can be obtained. Accordingly, a semiconductor integrated circuit with high added value such as high integration, high speed driving, and low power consumption can be realized.

As one of methods for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known. In the hydrogen ion implantation separation method, a single crystal silicon substrate (bond substrate) into which hydrogen ions are implanted is bonded to another substrate (base substrate) through an insulating layer, and then the single crystal silicon substrate (bond substrate) is bonded by heat treatment. This is a method of obtaining a single crystal silicon layer by separating in an ion implantation region. By using the hydrogen ion implantation separation method, an SOI substrate having a single crystal silicon layer over an insulating substrate such as a glass substrate can be manufactured (see, for example, Patent Document 1).

JP 2004-87606 A

In an SOI substrate manufacturing method using a hydrogen ion implantation separation method, a plurality of SOI substrates can be manufactured from one bond substrate, which has an advantage of reducing the cost of the bond substrate in manufacturing the SOI substrate. This is because the bond substrate after use can be reused for manufacturing an SOI substrate by performing a regeneration process on the bond substrate after the single crystal silicon layer is separated.

Here, a region (edge) called edge roll-off (ERO: Edge Roll Off) caused by CMP (Chemical Mechanical Polishing) processing is provided at the periphery of the bond substrate used in the hydrogen ion implantation separation method. A roll-off region). The region is formed by polishing the edge of the bond substrate with a polishing cloth. In the edge roll-off region of the bond substrate, the surface is curved, and the plate thickness is thinner than the central portion of the bond substrate.

In a method for manufacturing an SOI substrate using a hydrogen ion implantation separation method, a bond substrate and a base substrate are bonded to each other. Since the bonding is based on an intermolecular force or van der Waals force, a predetermined flatness is required on the bonding surface. Therefore, the bond substrate and the base substrate are not bonded in the edge roll-off region where the surface flatness cannot be ensured.

For this reason, in the bond substrate after separating the single crystal silicon layer, the single crystal silicon layer region and the insulating layer remain as protrusions on the periphery of the semiconductor substrate where the edge roll-off region exists. And the said convex part becomes a problem in the step of the reproduction | regeneration processing of a bond substrate. The height difference between the convex portion and the other region (a region where bonding is appropriately performed) is only about several hundred nm. However, in order to remove the convex portion by surface polishing by CMP treatment and regenerate it as a new bond substrate, the substrate must be removed about 10 μm in the thickness direction, and the bond substrate is regenerated and used sufficiently. It has a problem that it cannot be secured.

Accordingly, one embodiment of the present invention disclosed in this specification relates to a solution to the above problem, a method suitable for regenerating a semiconductor substrate, a method for manufacturing a regenerated semiconductor substrate using a method suitable for regenerating a semiconductor substrate, and the method A method for manufacturing an SOI substrate using a recycled semiconductor substrate is provided.

In one embodiment of the present invention disclosed in this specification, a convex portion is removed using a method in which a semiconductor region damaged by addition of ions or the like can be preferentially, in other words, selectively removed. Alternatively, the present invention relates to manufacturing a recycled semiconductor substrate using the above method and manufacturing an SOI substrate using the recycled semiconductor substrate.

One embodiment of the present invention disclosed in this specification is directed to a semiconductor substrate in which a protruding portion including a damaged semiconductor region and an insulating layer is present at a peripheral portion. Damaged semiconductor regions with respect to an undamaged semiconductor region using a mixed solution comprising a substance that oxidizes the material, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate and dissolution rate of the semiconductor material And a laser beam irradiation process for irradiating the semiconductor substrate with laser light from the surface side from which the damaged semiconductor region has been removed preferentially. is there.

In addition, according to another embodiment of the present invention disclosed in this specification, a protrusion including a damaged semiconductor region and an insulating layer is formed at a peripheral portion by being partly separated as a semiconductor layer through ion irradiation and heat treatment. Etching treatment to remove the insulating layer on the remaining semiconductor substrate, a substance that oxidizes the semiconductor material constituting the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and the oxidation rate and dissolution rate of the semiconductor material are controlled. An etching process for preferentially removing the damaged semiconductor region with respect to an undamaged semiconductor region using a liquid mixture containing a substance to be damaged; And a laser beam irradiation treatment for irradiating the semiconductor substrate.

In addition, according to another embodiment of the present invention disclosed in this specification, a protrusion including a damaged semiconductor region and an insulating layer is formed at a peripheral portion by being partly separated as a semiconductor layer through ion irradiation and heat treatment. Etching treatment to remove the insulating layer and a substance that oxidizes the semiconductor material constituting the semiconductor substrate and a substance that dissolves the oxidized semiconductor material to the remaining semiconductor substrate where the damaged semiconductor region remains in other regions And an etching process for preferentially removing the damaged semiconductor region over the undamaged semiconductor region using a mixed solution containing a material that controls the oxidation rate and dissolution rate of the semiconductor material, and the damaged semiconductor region takes precedence And a laser beam irradiation process for irradiating the semiconductor substrate with a laser beam from the side of the surface that has been removed.

The ion irradiation is preferably performed by an ion doping method in which mass separation is not performed. The ion doping apparatus is inexpensive and excellent for large area processing. In addition, by irradiating H ₃ ⁺ with an ion doping apparatus, hydrogen ions can be efficiently added to the semiconductor substrate.

In the etching process for removing the damaged semiconductor region preferentially, it is preferable that the etching selectivity of the damaged semiconductor region with respect to the undamaged semiconductor region is 2 or more. Further, it is preferable to stop the etching process after the etching selectivity of the convex portion with respect to the undamaged semiconductor region is lowered to less than 2.

In addition, it is preferable to remove at least a region having an angle of 0.5 ° or less between the tangent plane of the convex portion and the back surface of the semiconductor substrate by an etching process that preferentially removes the damaged semiconductor region. Further, the surface of the semiconductor substrate may be polished thereafter.

Further, nitric acid is preferable as the substance that oxidizes the semiconductor material constituting the semiconductor substrate, hydrofluoric acid is preferable as the substance that dissolves the oxidized semiconductor material, and acetic acid is used as the substance that controls the oxidation rate and dissolution rate of the semiconductor material. Is preferred.

For the laser light irradiation treatment, not only a pulsed laser but also a continuous wave laser can be used.

A recycled semiconductor substrate can be manufactured using the above method. Further, ions are added to the regenerated semiconductor substrate manufactured by the method to form an embrittled region, the regenerated semiconductor substrate and the base substrate are bonded to each other through an insulating layer, and the regenerated semiconductor substrate is separated by heat treatment. By forming a semiconductor layer over a base substrate, an SOI substrate can be manufactured.

Note that in this specification and the like, an SOI substrate refers to a substrate in which a semiconductor layer is formed over an insulating surface, and is not limited to a structure in which a silicon layer is provided over an insulating layer. For example, a structure in which a silicon layer is directly formed on a glass substrate and a structure in which a silicon carbide layer is formed on an insulating layer are included.

In one embodiment of the invention disclosed in this specification, a damaged semiconductor region can be preferentially removed with respect to an undamaged semiconductor region or a semiconductor region with a small degree of damage. Therefore, it is possible to suppress a loss that has been removed by polishing or the like in the recycling process of the semiconductor substrate, and to increase the number of times the semiconductor substrate is recycled and used.

In addition, by manufacturing an SOI substrate using the recycled semiconductor substrate, the cost for manufacturing the SOI substrate can be reduced.

Sectional drawing explaining the reproduction | regeneration processing method of a semiconductor substrate. Sectional drawing explaining the reproduction | regeneration processing method of a semiconductor substrate. 10 is a cross-sectional view illustrating a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating a method for manufacturing an SOI substrate. FIG. 4A and 4B illustrate a manufacturing process of an SOI substrate. FIG. 14 is a cross-sectional view illustrating a semiconductor device using an SOI substrate. The figure which shows the optical microscope photograph of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The figure which shows the optical microscope photograph of a semiconductor substrate. The figure which shows the optical microscope photograph of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The figure which shows the relationship between etching time and etching amount. The figure which shows the optical microscope photograph of a semiconductor substrate. The graph which shows the level | step difference of a semiconductor substrate. The figure which shows the cross-sectional TEM photograph of a semiconductor substrate. The figure which shows the optical microscope photograph of a semiconductor substrate.

Hereinafter, embodiments will be described with reference to the drawings. However, it will be apparent to those skilled in the art that the invention can be implemented in many different forms and that various changes can be made in form and detail without departing from the spirit and scope thereof. Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in this specification and the like, portions having the same or similar functions are denoted by the same reference numerals, and description thereof may be omitted.

(Embodiment 1)
In this embodiment mode, a method for regenerating a semiconductor substrate is described with reference to FIGS.

FIG. 1A illustrates an example of a structure of a semiconductor substrate 121 (a semiconductor substrate after a semiconductor layer is separated) before a regeneration process.

A convex portion 126 exists at the peripheral edge of the semiconductor substrate 121. The convex portion 126 includes an insulating layer 123, an unseparated semiconductor region 125, and a semiconductor region 127 to which ions are added. Note that the unseparated semiconductor region 125 and the semiconductor region 127 to which ions are added are damaged by an ion addition process in the manufacturing process of the SOI substrate and include many crystal defects and voids. Therefore, the unseparated semiconductor region 125 and the semiconductor region 127 to which ions are added can be collectively referred to as a damaged semiconductor region.

Note that, for example, in the case of a single crystal semiconductor substrate, a damaged semiconductor region is due to the addition of ions or the like to the single crystal semiconductor region in which atoms constituting the crystal are arranged spatially and regularly. This refers to a region partially including disordered arrangement (crystal structure) of atoms constituting a crystal, crystal defects, distortion of crystal lattice, and the like. An undamaged semiconductor region refers to a region equivalent to a single crystal semiconductor region to which ions or the like are not added.

The above-mentioned convex portion 126 includes an edge roll-off region of the semiconductor substrate. The edge roll-off region is caused by the surface treatment (CMP treatment) of the semiconductor substrate. The CMP process is a process for planarizing the surface of an object to be processed by a chemical / mechanical combined action. The plate thickness in the vicinity of the edge roll-off region is thinner than the thickness of the central portion of the semiconductor substrate before the semiconductor layer is separated, and the edge roll-off region is attached when the SOI substrate is manufactured. This is an area where alignment is not performed. As a result, the protrusion 126 remains in the edge roll-off region of the semiconductor substrate 121.

Note that a semiconductor region 129 to which ions are added exists in a region other than the convex portion 126 of the semiconductor substrate 121 (particularly, a region surrounded by the edge roll-off region). The semiconductor region 129 to which ions are added is formed by leaving the region to which ions formed in the manufacturing process of the SOI substrate are added to the semiconductor substrate 121 after the semiconductor layer is separated.

Here, the semiconductor region 129 to which ions are added is sufficiently thin as compared to the semiconductor regions (the semiconductor region 125 and the semiconductor region 127) in the convex portion 126. Further, the semiconductor region 129 to which ions are added contains many crystal defects and the like that are generated by damage due to ions. Therefore, the semiconductor region 129 to which ions are added can also be referred to as a damaged semiconductor region, like the semiconductor region 125 and the semiconductor region 127.

FIG. 1B is a schematic diagram in which the convex portion 126 is enlarged. The convex portion 126 includes a region corresponding to the edge roll-off region and a region corresponding to the chamfered portion. In the present embodiment, the edge roll-off region is a region in which points where the angle θ between the tangent plane on the surface of the convex portion 126 and the reference surface is 0.5 ° or less are gathered. Here, a plane parallel to the front surface or the back surface of the semiconductor substrate is employed as the reference surface.

Further, the chamfered portion may be defined as a region having a distance of less than 0.2 mm from the edge of the substrate, and the edge roll-off region may be defined as a region where the inner side is not bonded. Specifically, a region whose distance from the edge of the substrate is 0.2 mm or more and 0.9 mm or less can be referred to as an edge roll-off region.

Note that since the chamfered portion is not involved in the bonding of the base substrate and the bond substrate, the flatness of the chamfered portion does not cause a problem in the substrate recycling process. On the other hand, the vicinity of the edge roll-off region is involved in the bonding of the base substrate and the bond substrate. Therefore, depending on the flatness of the edge roll-off region, the recycled semiconductor substrate may not be used for the manufacturing process of the SOI substrate. For these reasons, it is extremely important to improve the flatness by removing the convex portions 126 in the edge roll-off region in the semiconductor substrate recycling process.

The semiconductor substrate regeneration process includes at least two processes, namely, an etching process for removing the insulating layer 123 (hereinafter referred to as a first etching process) and an etching process for removing a damaged semiconductor region (hereinafter referred to as a second etching process). Includes an etching process. These will be described in detail below.

First, the first etching process is described with reference to FIG. The first etching process is an etching process for removing the insulating layer 123 of the semiconductor substrate 121 as described above.

Here, the insulating layer 123 can be removed by wet etching using a solution containing hydrofluoric acid as an etchant. As the solution containing hydrofluoric acid, it is preferable to use a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (for example, trade name: LAL500, manufactured by Stella Chemifa Corporation). The wet etching process is preferably performed for about 120 seconds to 1200 seconds, for example, about 600 seconds.

Note that the wet etching process can be performed by immersing the semiconductor substrate 121 in a solution in the treatment tank, and thus a plurality of semiconductor substrates 121 can be collectively processed. For this reason, the efficiency of the reproduction process can be improved.

Further, a dry etching process may be performed as the first etching process. Further, a wet etching process and a dry etching process may be used in combination. As the dry etching process, a parallel plate RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) etching method, or the like can be used.

Next, the second etching process will be described. In the second etching process, the damaged semiconductor region, that is, the unseparated semiconductor region 125 constituting the convex portion 126, the semiconductor region 127 to which ions are added, and the semiconductor region 129 to which ions are added is preferentially expressed in other words. And selectively remove.

More specifically, a liquid mixture containing a substance that oxidizes the semiconductor material, a substance that dissolves the oxidized semiconductor material, and a substance that controls the rate of oxidation of the semiconductor material and the rate of dissolution of the oxidized semiconductor material. A wet etching process using an etchant is performed. The etching treatment is preferably performed for about 1 minute to 10 minutes. For example, in the case of using a mixed solution having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid described below of 1: 3: 10, 2 minutes to 4 minutes. It is preferable to do so. Moreover, it is preferable that the temperature of a liquid mixture shall be about 10 degreeC or more and 30 degrees C or less, for example, it is suitable to set it as 25 degreeC.

Here, nitric acid is preferably used as the substance that oxidizes the semiconductor material. Further, hydrofluoric acid is preferably used as the substance that dissolves the oxidized semiconductor material. In addition, acetic acid is preferably used as a substance that controls the rate of oxidation of the semiconductor material and the rate of dissolution of the oxidized semiconductor material.

When a mixed solution of nitric acid (concentration: 70% by weight), hydrofluoric acid (concentration: 50% by weight) and acetic acid (concentration: 97.7% by weight) is used as the etchant, the volume of nitric acid is 0% of the volume of acetic acid. More than 0.01 times and less than 1 time and more than 0.1 times and less than 100 times the volume of hydrofluoric acid, and the volume of hydrofluoric acid is more than 0.01 times and less than 0.5 times the volume of acetic acid It is preferable to do. For example, the volume ratio of hydrofluoric acid, nitric acid, and acetic acid is preferably 1: 3: 10. When the structure is expressed by the molar ratio of the constituent molecules, HF: HNO ₃ : CH ₃ COOH: H ₂ O = 2.1: 3.3: 12: 7.5. In addition, it does not need to specifically limit about the structure of another molecule | numerator.

In the damaged semiconductor region, there are crystal defects and voids formed with the addition of ions, and the etchant easily penetrates. For this reason, in the damaged semiconductor region, etching proceeds not only from the surface but also from the inside.

Specifically, etching proceeds to form deep vertical holes in a direction perpendicular to the substrate plane, and tends to be performed to enlarge the vertical holes. That is, in the damaged semiconductor region, the etching process proceeds at a higher etching rate than the low-damaged semiconductor region or the undamaged semiconductor region.

Specifically, the etching rate of the damaged semiconductor region when the above etchant is used is twice or more the etching rate of the undamaged semiconductor region (or the low-damage semiconductor region). That is, the etching selection ratio of the damaged semiconductor region to the undamaged semiconductor region (or the low-damage semiconductor region) is 2 or more.

Here, “etching rate” refers to the etching amount per unit time (the amount to be etched). That is, “high etching rate” means that etching is easier, and “low etching rate” means that etching is more difficult. Further, “the etching selectivity can be taken” means, for example, a condition where there is a sufficient difference between the etching rate of the A layer and the etching rate of the B layer when the A layer and the B layer are etched. The low-damage semiconductor region is a semiconductor region that is relatively less damaged than the unisolated semiconductor region 125, the semiconductor region 127 to which ions are added, the semiconductor region 129 to which ions are added, and the like. Say.

As described above, a mixed liquid containing a substance that oxidizes a semiconductor material, a substance that dissolves the oxidized semiconductor material, and a substance that controls the rate of oxidation of the semiconductor material and the rate of dissolution of the oxidized semiconductor material. By performing a wet etching process as an etchant, the damaged semiconductor region can be selectively removed, that is, selectively removed.

Therefore, in the substrate recycling process, the loss that has been removed by polishing or the like can be greatly reduced, and the number of times of recycling can be increased. Further, by using the wet etching process, a plurality of semiconductor substrates 121 can be processed at once, so that the efficiency of the substrate recycling process can be improved. Furthermore, the second etching process can be performed in a shorter time than the CMP process, and the efficiency of the substrate regeneration process is also achieved in this respect.

Note that the thickness of the damaged semiconductor region (semiconductor region 125 and semiconductor region 127) in the protrusion 126 and the thickness of the damaged semiconductor region (semiconductor region 129) in other regions are greatly different. For this reason, the etching selectivity between the convex portion 126 (peripheral portion) and the other region (central portion) is not constant during the second etching process.

Specifically, it is as follows. First, immediately after the start of the second etching process, the damaged semiconductor region is etched in both the convex portion 126 and other regions, and the etching selectivity is about 1. After the damaged semiconductor region (semiconductor region 129) other than the convex portion 126 is removed, a low-damage semiconductor region or an undamaged semiconductor region appears in the region. Therefore, the damaged semiconductor region of the protrusion 126 is preferentially removed, and the etching selectivity is 2 or more. When the damaged semiconductor region (semiconductor region 125, semiconductor region 127) of the protrusion 126 is removed, a low-damage semiconductor region or an undamaged semiconductor region also appears in the region, so that the etching selectivity is Again around 1.

As described above, since the etching selection ratio varies between the second etching processes, the change in the selection ratio can be used as a guide at the end of etching. For example, by stopping the etching process when the etching selectivity is reduced to less than 2, the damaged semiconductor region can be removed while suppressing unnecessary over-etching in the second etching process.

The etching selection ratio is obtained by comparing the reduction amounts of the film thicknesses of the convex portion 126 (peripheral portion) and the other region (center portion) at a predetermined time (for example, 30 seconds, 1 minute, etc.). It may be a difference value (difference value), or may be a difference value (differential value) obtained by comparing instantaneous film thickness reduction amounts.

Next, laser light irradiation treatment for planarizing the surface of the semiconductor substrate will be described with reference to FIG. In the laser beam irradiation process, the semiconductor substrate is irradiated with the laser beam 134 from the surface side from which the damaged semiconductor region is preferentially removed after the second etching process is performed.

Since the damaged semiconductor region formed by ion irradiation is not uniformly formed in the depth direction, the surface flatness of the semiconductor substrate is lost when the second etching is completed.

In a state where the surface flatness is lost, a problem occurs in reuse as a bond substrate, and thus laser light irradiation treatment for flattening the surface is performed.

As the laser beam 134, for example, a pulse laser can be used. A pseudo CW laser may also be used. For example, an excimer laser, an Ar laser, a Kr laser, a CO ₂ laser, a YVO ₄ laser, a YLF laser, a YAlO ₃ laser, a GdVO ₄ laser, a KGW laser, a KYW laser, an alexandrite laser, Ti: sapphire laser, Y ₂ O ₃ laser, dye laser, semiconductor laser, or the like can be used. Note that the pseudo CW laser can keep the portion irradiated with the laser light in a completely melted state in the same manner as the CW laser.

By irradiating the laser beam 134, the semiconductor substrate is partially melted. Note that partial melting refers to a state where there are a molten portion and a solid portion. By partial melting, the solid portion below the melting region becomes a seed, and the surface is recrystallized into a single crystal. At this time, crystal defects generated in the manufacturing process are reduced, and the surface of the semiconductor substrate is flattened.

Thus, the semiconductor substrate 121 is regenerated, and the regenerated semiconductor substrate 132 is completed as shown in FIG.

Note that most of the semiconductor region 129 to which ions are added is removed by the second etching treatment, but a part of the semiconductor region 129 may remain. In such a case, it is preferable to perform another surface treatment after the second etching treatment to completely remove the semiconductor region 129 to which ions are added. Examples of the surface treatment include polishing treatment represented by CMP treatment.

Further, the polishing process and the laser beam irradiation process may be performed a plurality of times. The order of the processing steps is not limited and can be selected as appropriate. Instead of laser light irradiation, lamp light irradiation processing may be performed.

As shown in this embodiment mode, after the insulating layer is removed by the first etching process, the substance that oxidizes the semiconductor material, the substance that dissolves the oxidized semiconductor material, the oxidation rate and the oxidation of the semiconductor material By performing the second etching process using the mixed liquid containing the substance that controls the dissolution rate of the semiconductor material, the damaged semiconductor region remaining on the peripheral edge of the semiconductor substrate can be removed preferentially. Accordingly, the loss of the substrate that has been removed by polishing or the like can be greatly reduced, and the number of times the semiconductor substrate is regenerated and used can be increased.

Further, as shown in this embodiment mode, by performing the laser light irradiation treatment, the planarity of the surface of the semiconductor substrate after the first etching treatment and the second etching treatment can be improved.

Moreover, since the semiconductor substrate is partially melted by performing the laser light irradiation treatment, defects generated in the manufacturing process are reduced, and the crystallinity of the surface of the semiconductor substrate can be improved.

Note that polishing treatment may be performed as the final surface treatment. By performing the laser light irradiation treatment before the polishing treatment, the amount of polishing by the polishing treatment can be reduced, and the manufacturing cost can be reduced as compared with the case where the laser light irradiation treatment is not performed.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, another example of a method for reprocessing a semiconductor substrate will be described with reference to FIGS.

First, a first etching process is performed on the semiconductor substrate 121 (see FIG. 2A). For details, Embodiment 1 may be referred to. As a result, the insulating layer present on the surface of the semiconductor substrate 121 is removed.

Next, a second etching process is performed on the semiconductor substrate 121 (see FIG. 2B). Embodiment 1 can be referred to for details of the second etching process. Thereby, the semiconductor substrate 130 from which the semiconductor region 125, the semiconductor region 127, and the semiconductor region 129 are removed is formed.

In this embodiment, a planarization process is performed on the semiconductor substrate 130 after the second etching process, so that the recycled semiconductor substrate 132 is manufactured (see FIG. 2C). This is because, as shown in FIG. 2B, when the flatness of the surface of the semiconductor substrate 130 after the second etching process is not sufficient, the semiconductor substrate cannot be used for the manufacturing process of the SOI substrate. Because.

Note that in this embodiment mode, the semiconductor region 129 is completely removed by the second etching process, but the semiconductor region 129 cannot be sufficiently removed by the second etching process. For this, the remaining semiconductor region 129 is preferably removed by the planarization treatment described below.

In this embodiment mode, means for using a polishing process for the planarization process will be described. Needless to say, the laser light irradiation treatment described in Embodiment Mode 1 may be performed. These processes may be combined, and the order and number of processes are not limited. Further, a lamp light irradiation process may be performed instead of the laser light irradiation process.

As the polishing process for the semiconductor substrate 130, a CMP process is preferably used.

For example, it is performed by attaching a polishing cloth on the polishing stage and rotating or swinging the polishing stage and the workpiece while supplying slurry (abrasive) between the workpiece and the polishing cloth. . Thus, the surface of the object to be processed is polished by the chemical reaction between the slurry and the surface of the object to be processed and the action of mechanical polishing of the object to be processed by the polishing cloth.

The number of times of the polishing process using the CMP process may be one or a plurality of times. When the polishing treatment is performed a plurality of times, for example, it is preferable to perform final polishing at a low polishing rate after performing primary polishing at a high polishing rate. For primary polishing, a polyurethane polishing cloth is preferably used, and the particle size of the slurry is preferably 120 nm or more and 180 nm or less, for example, about 150 nm. For the final polishing, it is preferable to use a suede polishing cloth, and the particle diameter of the slurry is 45 nm or more and 75 nm or less, for example, about 60 nm.

As described above, in addition to the above-described regeneration method, the semiconductor substrate 130 is subjected to a polishing process using a CMP process, and thereby the regenerated semiconductor substrate 132 planarized to have an average surface roughness of about 0.2 nm to 0.5 nm. Can be formed. In addition, the semiconductor substrate 130 can be planarized in a short time by performing a plurality of polishing processes with different polishing rates.

As described above, after the semiconductor region 125, the semiconductor region 127, and the semiconductor region 129 are removed by the first etching process and the second etching process, the surface is polished by the CMP process, so that the planarity is further improved. A good recycled semiconductor substrate 132 can be obtained.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 3)
In the method for manufacturing an SOI substrate according to this embodiment, an SOI substrate is manufactured by bonding a semiconductor layer separated from a semiconductor substrate which is a bond substrate to a base substrate. Then, the semiconductor substrate after the semiconductor layer is separated is subjected to a regeneration process and reused as a bond substrate. Hereinafter, an example of a method for manufacturing an SOI substrate according to this embodiment will be described.

First, a process of forming the embrittled region 104 in the semiconductor substrate 100 and preparing for bonding with the base substrate 120 will be described. This process relates to a process for the semiconductor substrate 100 and corresponds to the process A in the SOI substrate manufacturing process diagram shown in FIG.

First, the semiconductor substrate 100 is prepared (see FIG. 3A and the step (A-1) in FIG. 6). As the semiconductor substrate 100, for example, a single crystal semiconductor substrate such as silicon or a polycrystalline semiconductor substrate can be used. Commercially available silicon substrates include circular shapes having a diameter of 5 inches (about 125 mm), a diameter of 6 inches (about 150 mm), a diameter of 8 inches (about 200 mm), a diameter of 12 inches (about 300 mm), and a diameter of 16 inches (about 400 mm). The ones are typical.

Further, a chamfered portion for preventing chipping and cracking as shown in FIG. The shape is not limited to a circular shape, and a silicon substrate processed into a rectangular shape or the like can also be used. In the following description, a case where a rectangular single crystal silicon substrate is used as the semiconductor substrate 100 is described.

Note that the surface of the semiconductor substrate 100 is appropriately cleaned using sulfuric acid / hydrogen peroxide (also referred to as SPM), ammonia / hydrogen peroxide (also referred to as APM), hydrochloric acid / hydrogen peroxide (also referred to as HPM), dilute hydrofluoric acid (also referred to as DHF), or the like. It is preferable to keep it. Alternatively, the surface of the semiconductor substrate 100 may be cleaned by alternately discharging dilute hydrofluoric acid and ozone water.

Next, after cleaning the surface of the semiconductor substrate 100, the insulating layer 102 is formed over the semiconductor substrate 100 (see FIG. 3B and step (A-2) in FIG. 6). The insulating layer 102 is not limited to a single layer, and may be a stack of a plurality of insulating films. The insulating layer 102 can be formed using an insulating film containing silicon as a composition, such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In this embodiment, as an example, the case where silicon oxide is used for the insulating layer 102 is described.

Note that in this specification and the like, a silicon oxynitride film has a composition that includes more oxygen atoms than nitrogen atoms, and includes Rutherford Backscattering Spectroscopy (RBS) and Hydrogen Forward Scattering (HFS). When measured using Forward Scattering Spectrometry), oxygen concentration ranges from 50 atom% to 70 atom%, nitrogen ranges from 0.5 atom% to 15 atom%, silicon ranges from 25 atom% to 35 atom%, The hydrogen is contained in the range of 0.1 atomic% to 10 atomic%.

In addition, the silicon nitride oxide film has a composition in which the number of nitrogen atoms is larger than that of oxygen atoms, and when measured using RBS and HFS, oxygen concentration ranges from 5 atomic percent to 30 atomic percent, and nitrogen concentration. It includes 20 atomic% to 55 atomic%, silicon in a range of 25 atomic% to 35 atomic%, and hydrogen in a range of 10 atomic% to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

In the case where silicon oxide is used as the insulating layer 102, the insulating layer 102 uses a mixed gas such as silane and oxygen, tetraethoxysilane (TEOS) and oxygen, or a chemical vapor phase such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD. It can be formed by a growth method. In this case, the surface of the insulating layer 102 may be densified by oxygen plasma treatment.

Alternatively, silicon oxide formed by a chemical vapor deposition method using an organosilane gas may be used as the insulating layer 102. Examples of the organic silane gas include tetraethoxysilane (TEOS), tetramethylsilane (TMS), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), and triethoxysilane (TRIES). ), And a silicon-containing compound such as trisdimethylaminosilane (TDMAS) can be used.

Alternatively, the insulating layer 102 can be formed using an oxide film obtained by oxidizing the semiconductor substrate 100. The oxide film can be formed by thermal oxidation treatment. At this time, halogen or a gas containing halogen may be added to the oxidizing atmosphere. As the halogen or a gas containing halogen, one or more kinds of gases selected from HCl, HF, NF ₃ , HBr, Cl ₂ , ClF, BCl ₃ , F ₂ , Br _{2, and the} like can be used.

Note that in FIG. 3B, the insulating layer 102 is formed so as to cover the semiconductor substrate 100; however, this embodiment is not limited thereto. In the case where the insulating layer 102 is provided on the semiconductor substrate 100 using a CVD method or the like, the insulating layer 102 may be formed only on one surface of the semiconductor substrate 100.

As an example of the conditions for forming the oxide film, 700 ° C. or more and 1100 ° C. or less (typical) in an atmosphere containing HCl in a ratio of 0.5 volume% to 10 volume% (preferably 3 volume%) with respect to oxygen. In some cases, the heat treatment is performed at about 950 ° C. The treatment time may be 0.1 to 6 hours, preferably 0.5 to 1 hour. The thickness of the oxide film to be formed is 10 nm or more and 1100 nm or less (preferably 50 nm or more and 150 nm or less), and can be, for example, 100 nm.

By such thermal oxidation treatment in an atmosphere containing a halogen element, the oxide film can contain the halogen element. By including a halogen element in the oxide film at a concentration of 1 × 10 ¹⁷ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less, heavy metals (for example, Fe, Cr, Ni, Mo, etc.) that are extrinsic impurities are contained. ) Is trapped in the oxide film, so that contamination of a semiconductor layer to be formed later can be prevented.

In addition, by including a halogen element such as chlorine in the insulating layer 102, impurities (for example, movable ions such as Na) that adversely affect the semiconductor substrate 100 can be gettered.

Specifically, impurities included in the semiconductor substrate 100 are precipitated in the insulating layer 102 by heat treatment performed after the insulating layer 102 is formed, and are reacted with and captured by halogen atoms (for example, chlorine atoms). Therefore, the impurity is fixed in the insulating layer 102 and contamination of the semiconductor substrate 100 can be prevented. The insulating layer 102 also functions as a film that fixes impurities such as Na contained in the glass when bonded to a glass substrate.

In particular, inclusion of halogen such as chlorine in the insulating layer 102 in the above process is effective in the case where the semiconductor substrate 100 is not sufficiently cleaned or in the removal of contamination of the semiconductor substrate that is used after repeated regeneration treatment. .

In addition, since the defects on the surface of the semiconductor substrate 100 are terminated by the halogen element contained in the oxidation treatment atmosphere, the localized level density at the interface between the oxide film and the semiconductor substrate 100 can be reduced.

Further, the halogen element contained in the insulating layer 102 causes distortion in the insulating layer 102. As a result, the moisture absorption rate of the insulating layer 102 is improved, and the moisture diffusion rate is increased. That is, when moisture exists on the surface of the insulating layer 102, moisture present on the surface can be quickly absorbed and diffused into the insulating layer 102.

In the case where a glass substrate containing an impurity that lowers the reliability of a semiconductor device such as an alkali metal or an alkaline earth metal is used as the base substrate, an insulating film that can prevent diffusion of the impurity into the semiconductor layer is used as the insulating layer 102 It is preferable to contain one or more layers. Examples of such an insulating film include a silicon nitride film and a silicon nitride oxide film. The insulating layer 102 including the insulating film can function as a barrier film (also referred to as a blocking film).

The silicon nitride film can be formed, for example, by a chemical vapor deposition method such as plasma CVD using a mixed gas of silane and ammonia. The silicon nitride oxide film can be formed by a chemical vapor deposition method such as plasma CVD using a mixed gas of silane, ammonia, and dinitrogen monoxide, for example.

For example, when the insulating layer 102 is formed as a barrier film having a single-layer structure, the insulating layer 102 can be formed using a silicon nitride film or a silicon nitride oxide film with a thickness of 15 nm to 300 nm.

In the case where the insulating layer 102 is formed as a barrier film having a two-layer structure, an insulating film having a high barrier function is used as an upper layer. The upper insulating film can be formed of, for example, a silicon nitride film or a silicon nitride oxide film with a thickness of 15 nm to 300 nm. These films have a high blocking effect for preventing the diffusion of impurities, but have a high internal stress. Therefore, it is preferable to select a film having an effect of relaxing the stress of the upper insulating film as the lower insulating film in contact with the semiconductor substrate 100. As an insulating film having an effect of relieving the stress of the upper insulating film, there are a silicon oxide film, a silicon oxynitride film, an oxide film formed by thermally oxidizing the semiconductor substrate 100, and the like. The thickness of the lower insulating film can be greater than or equal to 5 nm and less than or equal to 200 nm.

For example, in order to function the insulating layer 102 as a barrier film, a silicon oxide film and a silicon nitride film, a silicon oxynitride film and a silicon nitride film, a silicon oxide film and a silicon nitride oxide film, or a silicon oxynitride film and a silicon nitride oxide film The insulating layer 102 is preferably formed by a combination of the above.

Next, an ion beam composed of ions accelerated by an electric field is irradiated to the semiconductor substrate 100 through the insulating layer 102 as indicated by an arrow, and an embrittled region 104 is formed in a region at a desired depth from the surface of the semiconductor substrate 100. It forms (refer FIG.3 (C) and the process (A-3) of FIG. 6). The depth at which the embrittlement region 104 is formed is approximately the same as the average penetration depth of ions, and this can be adjusted by the acceleration energy of the ion beam and the incident angle of the ion beam. The acceleration energy of the ion beam can be adjusted by the acceleration voltage and the dose amount.

The thickness of the semiconductor layer 124 to be separated from the semiconductor substrate 100 later is determined by the depth at which the embrittled region 104 is formed. The depth at which the embrittled region 104 is formed can be, for example, from 10 nm to 500 nm from the surface of the semiconductor substrate 100, and the preferable depth range is from 50 nm to 200 nm, for example, about 100 nm. Note that in this embodiment mode, ion irradiation is performed after the insulating layer 102 is formed; however, the present invention is not limited to this, and ion irradiation may be performed before the insulating layer 102 is formed.

The embrittlement region 104 can be formed by an ion doping method using an ion doping apparatus. As a typical example of an ion doping apparatus, a non-mass separation type apparatus that irradiates an object to be processed with all ion species without mass separation of ion species in plasma is known.

The main components of the ion doping apparatus are a chamber in which an object to be processed is arranged, an ion source for generating desired ions, and an acceleration mechanism for accelerating and irradiating ions.

The ion source includes a gas supply device that supplies a source gas for generating a desired ion species, an electrode for generating a plasma by exciting the source gas, and the like. As an electrode for forming plasma, a filament-type electrode, an electrode for capacitively coupled high-frequency discharge, or the like is used.

The acceleration mechanism includes electrodes such as an extraction electrode, an acceleration electrode, a deceleration electrode, and a ground electrode, and a power source for supplying power to these electrodes. The electrode constituting the acceleration mechanism is provided with a plurality of openings and slits, and ions generated by the ion source are accelerated through the openings and slits provided in the electrodes. The configuration of the ion doping apparatus is not limited to that described above, and the configuration can be changed as necessary.

In this embodiment, the case where ions generated from hydrogen gas are added to the semiconductor substrate 100 using an ion doping apparatus will be described. As the plasma source gas, hydrogen or a gas containing hydrogen is supplied. For example, plasma is generated by exciting hydrogen gas, ions included in the plasma are accelerated without mass separation, and the semiconductor substrate 100 is irradiated with the accelerated ions.

In the ion addition treatment, the ratio of H ₃ ^{+ to} the total amount of ion species (H ⁺ , H ₂ ⁺ , H ₃ ⁺ ) generated from hydrogen gas is set to 50% or more. More preferably, the ratio of H ₃ ⁺ is 80% or more. By increasing the ratio of H ₃ ⁺ ions in the plasma, hydrogen ions can be efficiently added to the semiconductor substrate 100.

In the case H ₃ ⁺ ions are because of its 3-fold the mass of H ⁺ ions, which one hydrogen atom is added to the same depth, the acceleration voltage of H ₃ ⁺ ions, 3 an accelerating voltage of H ⁺ ions It is possible to double. As a result, the tact time of the ion irradiation process can be shortened, and productivity and throughput can be improved. Further, by irradiating ions with the same mass, the ions can be added while being concentrated at the same depth of the semiconductor substrate 100.

Since the ion doping apparatus is relatively inexpensive and excellent in large-area processing, effects such as cost reduction and productivity improvement can be obtained by irradiating H ₃ ⁺ using the ion doping apparatus. When an ion doping apparatus is used, heavy metal may be added to the semiconductor substrate at the same time. By irradiating ions through the above-described insulating layer 102 containing halogen, the semiconductor substrate made of heavy metal is used. 100 contamination can be prevented.

The embrittlement region 104 may be formed using an ion implantation apparatus. The ion implantation apparatus is a mass separation type apparatus that mass-separates a plurality of ion species generated by plasma excitation of a source gas and irradiates a target object disposed in a chamber with specific ion species. When an ion implantation apparatus is used, H ⁺ ions, H ₂ ⁺ ions, and H ₃ ⁺ ions generated by exciting hydrogen gas or PH ₃ are mass-separated and the semiconductor substrate 100 is irradiated with any of these. To do.

In the ion implantation apparatus, it is possible to irradiate a single ion to the semiconductor substrate 100, and ions can be added while being concentrated at the same depth of the semiconductor substrate 100. For this reason, the depth profile of the ions added to the semiconductor substrate 100 becomes sharp, and the surface flatness of the separated semiconductor layer becomes relatively good. In addition, due to the electrode structure, the semiconductor layer is characterized by relatively little contamination by heavy metals.

Next, a step of cleaning the semiconductor substrate 100 over which the insulating layer 102 is formed is performed. This cleaning step may be performed by ultrasonic cleaning with pure water, two-fluid jet cleaning with pure water and nitrogen, or the like. As the ultrasonic cleaning, megahertz ultrasonic cleaning (megasonic cleaning) is preferably used. The semiconductor substrate 100 may be cleaned with ozone water after ultrasonic cleaning or two-fluid jet cleaning. By washing with ozone water, organic substances can be removed and the surface can be activated to improve the hydrophilicity of the surface of the insulating layer 102.

The surface activation treatment of the insulating layer 102 can be performed by cleaning with ozone water, irradiation treatment with an atomic beam or ion beam, ultraviolet treatment, ozone treatment, plasma treatment, biased plasma treatment, or radical treatment (see FIG. Step 6 (A-4)). When an atomic beam or an ion beam is used, an inert gas neutral atom beam or inert gas ion beam such as argon can be used.

Here, an example of ozone treatment will be described. For example, the surface of the object to be processed can be subjected to ozone treatment by irradiation with ultraviolet light (UV) in an atmosphere containing oxygen. The ozone treatment in which ultraviolet rays are irradiated in an atmosphere containing oxygen is also called UV ozone treatment or ultraviolet ozone treatment. In an atmosphere containing oxygen, irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more of ultraviolet light can generate ozone and singlet oxygen can be generated from ozone. Further, by irradiating light including a wavelength of less than 180 nm among ultraviolet rays, ozone can be generated and singlet oxygen can be generated from ozone.

Examples of reactions that occur by irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more in an atmosphere containing oxygen are shown below.
O ₂ + hν ₁ (λ ₁ nm) → O ( ³ P) + O ( ³ P) (1)
O ( ³ P) + O ₂ → O ₃ (2)
O ₃ + hν ₂ (λ ₂ nm) → O ( ¹ D) + O ₂ (3)

In the above reaction formula (1), irradiation with light (hν ₁ ) containing a wavelength (λ ₁ nm) of less than 200 nm in an atmosphere containing oxygen (O ₂ ) results in ground-state oxygen atoms (O ( ³ P) ) Is generated.

Next, in reaction formula (2), ground state oxygen atoms (O ( ³ P)) and oxygen (O ₂ ) react to generate ozone (O ₃ ).

In the reaction formula (3), light (hν ₂ ) including a wavelength (λ ₂ nm) of 200 nm or more is irradiated in an atmosphere including the generated ozone (O ₃ ), whereby a singlet in an excited state. Oxygen O ( ¹ D) is generated.

In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 200 nm among ultraviolet rays, and singlet oxygen is generated by decomposing ozone by irradiating light having a wavelength of 200 nm or more. To do. The ozone treatment as described above can be performed, for example, by irradiation with a low-pressure mercury lamp (λ ₁ = 185 nm, λ ₂ = 254 nm) in an atmosphere containing oxygen.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 180 nm in an oxygen-containing atmosphere is shown.
O ₂ + hν ₃ (λ ₃ nm) → O ( ¹ D) + O ( ³ P) (4)
O ( ³ P) + O ₂ → O ₃ (5)
O ₃ + hν ₃ (λ ₃ nm) → O ( ¹ D) + O ₂ (6)

In the reaction formula (4), irradiation with light (hν ₃ ) containing a wavelength (λ ₃ nm) of less than 180 nm in an atmosphere containing oxygen (O ₂ ) results in singlet oxygen (O ( ¹ D)) and a ground state oxygen atom (O ( ³ P)).

Next, in reaction formula (5), oxygen atoms (O ( ³ P)) in the ground state and oxygen (O ₂ ) react to generate ozone (O ₃ ).

In the reaction formula (6), light (hν ₃ ) containing a wavelength (λ ₃ nm) of less than 180 nm is irradiated in an atmosphere containing the generated ozone (O ₃ ), whereby singlet oxygen ( O ( ¹ D)) and oxygen (O ₂ ) are produced.

In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 180 nm among ultraviolet rays, and ozone or oxygen is decomposed to generate singlet oxygen. The ozone treatment as described above can be performed, for example, by irradiation with a Xe excimer UV lamp (λ ₃ = 172 nm) in an atmosphere containing oxygen.

By irradiating with light having a wavelength of less than 200 nm, the chemical bond of the organic substance attached to the surface of the object to be processed is cut. Then, the organic substance adhering to the surface of the object to be processed or the organic substance having a broken chemical bond can be removed by oxidative decomposition by ozone or singlet oxygen generated from ozone. By performing the ozone treatment as described above, the hydrophilicity and cleanliness of the surface of the object to be processed can be improved, and bonding can be performed satisfactorily.

Ozone is generated by irradiating ultraviolet rays in an atmosphere containing oxygen. Ozone is effective in removing organic substances adhering to the surface of the object to be processed. Singlet oxygen is also effective in removing organic substances adhering to the surface of the object to be processed, equivalent to or higher than ozone. Ozone and singlet oxygen are examples of oxygen in an active state, and are collectively referred to as active oxygen. As explained in the above reaction formulas and the like, ozone is generated when singlet oxygen is generated, or there is a reaction that generates singlet oxygen from ozone. This is called ozone treatment.

Next, a process for preparing the base substrate 120 for bonding to the semiconductor substrate 100 will be described. This process relates to a process for the base substrate 120 and corresponds to the process B in FIG.

First, the base substrate 120 is prepared (see step (B-1) in FIG. 6). As the base substrate 120, a quartz substrate, a ceramic substrate, a sapphire substrate, and the like can be used in addition to various glass substrates used for the electronic industry such as aluminosilicate glass, barium borosilicate glass, and aluminoborosilicate glass. Further, a single crystal semiconductor substrate (for example, a single crystal silicon substrate) or a polycrystalline semiconductor substrate (for example, a polycrystalline silicon substrate) may be used as the base substrate 120. For example, a polycrystalline silicon substrate is advantageous in that it is cheaper than a single crystal silicon substrate and has higher heat resistance than a glass substrate.

When a glass substrate is used as the base substrate 120, for example, a mother glass substrate developed for manufacturing a liquid crystal panel is preferably used. As the mother glass, the third generation (550 mm × 650 mm), the third generation (600 mm × 720 mm), the fourth generation (680 mm × 880 mm or 730 mm × 920 mm), the fifth generation (1100 mm × 1300 mm), the sixth Generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm), 10th generation (2850mm x 3050mm), etc. are known ing. By manufacturing an SOI substrate using a large-area mother glass substrate as the base substrate 120, an increase in the area of the SOI substrate can be realized. If an SOI substrate with a large area is realized, a plurality of semiconductor devices can be manufactured at a time, and the number of semiconductor devices manufactured from a single substrate increases, thereby dramatically improving productivity. be able to.

In addition, an insulating layer 122 is preferably formed over the base substrate 120 (see step (B-2) in FIG. 6). Here, the insulating layer 122 formed over the base substrate 120 is not an essential component; however, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, or the like that also functions as a barrier film is formed. It is preferable to keep. The barrier film can prevent impurities from diffusing from the base substrate 120 to the semiconductor substrate 100.

In addition, since the insulating layer 122 is used as a bonding layer, the surface of the insulating layer 122 is preferably smoothed in order to suppress bonding failure. Specifically, the average surface roughness (Ra) of the surface of the insulating layer 122 is 0.50 nm or less, the root mean square roughness (Rms) is 0.60 nm or less, and more preferably the average surface roughness is 0.35 nm or less. The insulating layer 122 is formed so that the root mean square roughness is 0.45 nm or less. The film thickness is appropriately set in the range of 10 nm to 200 nm, preferably 50 nm to 100 nm.

Before the bonding, the surface of the base substrate 120 is cleaned. The surface of the base substrate 120 may be cleaned using cleaning using hydrochloric acid and hydrogen peroxide, megahertz ultrasonic cleaning, two-fluid jet cleaning, cleaning using ozone water, or the like. Similarly to the insulating layer 102, surface activation treatment such as atomic beam or ion beam irradiation treatment, ultraviolet treatment, ozone treatment, plasma treatment, bias application plasma treatment, or radical treatment is performed on the surface of the insulating layer 122. (See step (B-3) in FIG. 6).

Next, a process of bonding the semiconductor substrate 100 and the base substrate 120 and separating the semiconductor substrate 100 into the semiconductor layer 124 and the semiconductor substrate 121 will be described. This step corresponds to step C in FIG.

First, the semiconductor substrate 100 and the base substrate 120 that have undergone the above-described steps are bonded together (see FIG. 4A and the step (C-1) in FIG. 6). Here, the semiconductor substrate 100 and the base substrate 120 are attached to each other with the insulating layer 102 and the insulating layer 122 interposed therebetween, but this is not the case when the insulating layer is not formed.

The bonding is realized by applying a pressure of 0.1 N / cm ² or more and 500 N / cm ² or less, preferably 1 N / cm ² or more and 20 N / cm ² or less to one end of the base substrate 120. When pressure is applied to a part of the base substrate 120, the bonding with the semiconductor substrate 100 starts from that part, and the bonding is spontaneously spread over the entire surface to complete the bonding between the base substrate 120 and the semiconductor substrate 100. The bonding is based on the principle of van der Waals force and the like, and a strong bonded state is formed even at room temperature.

Note that an edge roll-off region exists in the peripheral portion of the semiconductor substrate 100, and the insulating layer 102 formed over the semiconductor substrate 100 and the insulating layer 122 formed over the base substrate 120 may not contact with each other in the region. is there. The same applies to the chamfered portion existing outside the edge roll-off region (near the end of the semiconductor substrate 100).

In the CMP process used for manufacturing the semiconductor substrate 100, the polishing of the peripheral portion of the semiconductor substrate tends to proceed faster than the central portion in principle. Therefore, a region having a lower thickness and a lower flatness than the central portion of the semiconductor substrate 100 is formed in the peripheral portion of the semiconductor substrate 100. This area is an edge roll-off area. Even in the case where the end portion of the semiconductor substrate 100 is not chamfered, it may be impossible to bond the base substrate 120 to the edge roll-off region.

In addition, when a plurality of semiconductor substrates are bonded to one base substrate, it is preferable to use a mechanism that applies an individual pressure to each semiconductor substrate. By using this mechanism, even if the thickness of the semiconductor substrate is different, the base substrate and the plurality of semiconductor substrates can be favorably bonded. Note that this is not the case when the plurality of semiconductor substrates and the base substrate can be brought into close contact with each other even when the thicknesses of the plurality of semiconductor substrates are different.

After the semiconductor substrate 100 is bonded to the base substrate 120, heat treatment for strengthening bonding is preferably performed (see step (C-2) in FIG. 6). The temperature of the heat treatment is preferably a temperature at which cracks are not generated in the embrittled region 104, for example, 200 ° C. or higher and 450 ° C. or lower.

In addition, bonding can be similarly strengthened by bonding the semiconductor substrate 100 to the base substrate 120 while being heated in this temperature range. Note that the above heat treatment is preferably performed continuously in an apparatus or a place where bonding is performed in order to prevent the substrate from being peeled off due to vibrations such as conveyance.

Note that when the semiconductor substrate 100 and the base substrate 120 are bonded to each other, if particles or the like adhere to the bonding surface, the bonding is not performed on that portion. In order to prevent adhesion of particles, it is preferable that the semiconductor substrate 100 and the base substrate 120 be bonded in a processing chamber in which airtightness is ensured. Further, when the semiconductor substrate 100 and the base substrate 120 are bonded to each other, the processing chamber may be in a reduced pressure state (for example, about 5.0 × 10 ⁻³ Pa) to clean the bonding process atmosphere. .

Next, by performing heat treatment, the semiconductor substrate 100 is separated in the embrittled region 104, the semiconductor layer 124 is formed over the base substrate 120, and the semiconductor substrate 121 is formed (FIG. 4B and FIG. 6). Step (see C-3)). In the region other than the edge roll-off region and the chamfered portion, the semiconductor substrate 100 and the base substrate 120 are bonded to each other, and thus the semiconductor layer 124 separated from the semiconductor substrate 100 is fixed on the base substrate 120. Will be.

Here, the temperature of the heat treatment for separating the semiconductor layer 124 is set so as not to exceed the strain point of the base substrate 120. The heat treatment can be performed using an RTA (Rapid Thermal Anneal) apparatus, a resistance heating furnace, a microwave heating apparatus, or the like.

The RTA apparatus includes a GRTA (Gas Rapid Thermal Anneal) apparatus and an LRTA (Lamp Rapid Thermal Anneal) apparatus. When the GRTA apparatus is used, the treatment time can be set to 0.5 to 60 minutes at a temperature of 550 ° C. to 650 ° C. In the case of using a resistance heating furnace, the treatment time can be 2 hours or more and 4 hours or less at a temperature of 200 ° C. or more and 650 ° C. or less.

The heat treatment may be performed by irradiation with microwaves or the like. Specifically, for example, the semiconductor substrate 100 can be separated by irradiating a microwave of 2.45 GHz at 900 W for about 5 minutes to 30 minutes.

In the semiconductor layer 124 and the semiconductor substrate 121, a semiconductor region 129 and a semiconductor region 133 that are regions to which ions are added respectively remain. This region corresponds to the embrittled region 104 before separation. For this reason, the semiconductor region 129 and the semiconductor region 133 contain a lot of hydrogen and have many crystal defects.

In addition, a region where the semiconductor substrate 121 is not bonded (specifically, a region corresponding to the edge roll-off region and the chamfered portion of the semiconductor substrate 100) is a convex portion 126. The protrusion 126 includes a semiconductor region 127 to which ions are added, an unseparated semiconductor region 125, and an insulating layer 123. Since the semiconductor region 127 is a part of the embrittlement region 104 like the semiconductor region 129 and the like, it contains a lot of hydrogen and has many crystal defects. In addition, the semiconductor region 125 has a smaller hydrogen content than the semiconductor region 127 or the like, but includes crystal defects generated by the addition of ions or the like.

Next, a process of planarizing the surface of the semiconductor layer 124 bonded to the base substrate 120 and restoring crystallinity will be described. This step corresponds to step D in FIG.

The semiconductor region 133 over the semiconductor layer 124 that is in close contact with the base substrate 120 is a part of the embrittled region 104 including crystal defects, and flatness is impaired. Therefore, the semiconductor region 133 may be removed by polishing or the like, and the surface of the semiconductor layer 124 may be planarized (see FIG. 4C and FIG. 6D-1).

Although planarization is not essential, planarization can improve the characteristics of the interface between the semiconductor layer and a layer (eg, an insulating layer) formed later on the surface of the semiconductor layer. Specifically, the polishing can be performed by CMP treatment or liquid jet polishing. Here, when the semiconductor region 133 is removed, part of the semiconductor layer 124 is also polished, and the semiconductor layer 124 may be thinned.

Alternatively, the semiconductor region 133 can be removed by etching, and the semiconductor layer 124 can be planarized. Examples of the etching include a reactive ion etching (RIE) method, an ICP (Inductively Coupled Plasma) etching method, an ECR (Electron Cyclotron Resonance) etching method, a parallel plate type (capacitive coupling type) etching method, and a magnetron. A dry etching method such as a plasma etching method, a two-frequency plasma etching method, or a helicon wave plasma etching method can be used. Note that the semiconductor region 133 may be removed by using both the polishing and the etching, and the surface of the semiconductor layer 124 may be planarized.

Further, by the polishing and the etching, the surface of the semiconductor layer 124 can be planarized and the semiconductor layer 124 can be thinned to an optimum thickness for a semiconductor element to be formed later.

In addition, the semiconductor region 133 and the semiconductor layer 124 may be irradiated with laser light in order to reduce crystal defects and improve planarity (see step (D-2) in FIG. 6).

Note that in the case where the semiconductor region 133 is removed by dry etching and the surface of the semiconductor layer 124 is planarized, defects may occur near the surface of the semiconductor layer 124. In such a case, the defect can be repaired by irradiation with the laser beam.

In the laser light irradiation step, the temperature rise of the base substrate 120 can be reduced, so that a substrate with low heat resistance can be used as the base substrate 120. It is preferable that the semiconductor region 133 is completely melted and the semiconductor layer 124 is partially melted by the laser light irradiation.

When the semiconductor layer 124 is completely melted, the semiconductor layer 124 is recrystallized due to disordered nucleation in the semiconductor layer 124 in a liquid phase, so that the crystallinity of the semiconductor layer 124 is lowered. By partially melting the semiconductor layer 124, crystal growth proceeds from a solid phase portion that is not melted, crystal defects in the semiconductor layer 124 are reduced, and crystallinity is recovered.

Note that the semiconductor layer 124 being completely melted means that the semiconductor layer 124 is melted to the interface with the insulating layer 102 to be in a liquid state. On the other hand, the partial melting of the semiconductor layer 124 means that a part (here, the upper layer) of the semiconductor layer 124 is melted to become a liquid phase, and another part (here, the lower layer) maintains the solid phase.

Here, the surface of the semiconductor layer 124 may be etched either before or after the step of laser irradiation. By the etching, the surface of the semiconductor layer 124 can be planarized and the semiconductor layer 124 can be thinned to an optimum thickness for a semiconductor element to be formed later.

After the laser light irradiation, heat treatment at 500 ° C. to 650 ° C. is preferably performed on the semiconductor layer 124 (see step (D-3) in FIG. 6). By this heat treatment, defects in the semiconductor layer 124 can be further reduced and distortion of the semiconductor layer 124 can be reduced.

For the heat treatment, an RTA apparatus, a resistance heating furnace, a microwave heating apparatus, or the like can be used. The RTA device includes a GRTA device and an LRTA device. For example, when a resistance heating furnace is used, heat treatment may be performed at 600 ° C. for about 4 hours.

Various semiconductor devices can be manufactured by using the SOI substrate obtained by the above-described steps in the subsequent manufacturing steps of the semiconductor device (see FIG. 6).

Next, a process for manufacturing a recycled semiconductor substrate by performing a recycling process on the semiconductor substrate 121 will be described. This step corresponds to step E in FIG. Note that the first embodiment can be referred to for details of the process, and thus an outline of the process will be described here.

A protrusion 126 is formed on the peripheral edge of the semiconductor substrate 121 (see FIG. 5A). The protrusion 126 includes a semiconductor region 127 to which ions are added, an unseparated semiconductor region 125, and an insulating layer 123. Crystal defects are formed in the semiconductor region 125 and the semiconductor region 127 by the above-described ion irradiation. In addition, crystal defects are also formed in the semiconductor region 129 of the semiconductor substrate 121, and the flatness is impaired. Therefore, the semiconductor region 125, the semiconductor region 127, and the semiconductor region 129 can be collectively referred to as a damaged semiconductor region.

A first etching process is performed on the semiconductor substrate 121 to remove the insulating layer 123 of the semiconductor substrate 121 (see FIG. 5B and step (E-1) in FIG. 6). Embodiment 1 can be referred to for details of this step.

Next, a second etching process is performed to preferentially remove the semiconductor region 125 and the semiconductor region 127 that form the protrusions 126 of the semiconductor substrate 121, thereby forming the regenerated semiconductor substrate 132 (FIG. 5B and FIG. FIG. 6 (see step (E-2)). At the same time, the semiconductor region 129 is also removed. Embodiment 1 can also be referred to for details of this step.

Here, when the flatness of the semiconductor substrate 121 after the second etching treatment is not sufficient, the semiconductor substrate 121 can be polished and planarized (see step (E-3) in FIG. 6). Embodiment 1 can be referred to for details.

As described above, after removing the convex portion 126 of the semiconductor substrate 121 by the first etching process and the second etching process, the polishing process is performed, whereby the regenerated semiconductor substrate 132 with high flatness can be obtained.

As described above, the semiconductor substrate 121 is regenerated into the regenerated semiconductor substrate 132. The obtained recycled semiconductor substrate 132 can be reused as the semiconductor substrate 100 in the process A.

As shown in this embodiment mode, the manufacturing cost of an SOI substrate can be reduced by repeatedly using a semiconductor substrate that has undergone a regeneration treatment process. In particular, when the method described in this embodiment and the like is used, a damaged semiconductor region can be removed preferentially, so that the loss of the substrate that has been removed by polishing or the like can be suppressed. In addition, the number of times the semiconductor substrate is regenerated and used can be increased.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, the case where an SOI substrate is manufactured using a silicon substrate or the like with high heat resistance as a base substrate will be described. Note that the method described in this embodiment mode is common to the above embodiment mode in many parts. Therefore, in the present embodiment, differences will be mainly described. Since the drawing is common to the previous embodiment, it is not particularly shown here.

An insulating layer and an embrittlement region are formed in a semiconductor substrate used as a bond substrate. The processing for the semiconductor substrate including the formation of the insulating layer and the embrittlement region is the same as that described in the above embodiment. Therefore, the description of the above embodiment can be referred to for these details.

In this embodiment, a substrate having high heat resistance is used as the base substrate. Examples of the substrate having high heat resistance include a quartz substrate, a sapphire substrate, and a semiconductor substrate (for example, a single crystal silicon substrate or a polycrystalline silicon substrate). In this embodiment, the case where a single crystal silicon substrate is used as a base substrate is described.

As a single crystal silicon substrate, a circular shape having a diameter of 5 inches (about 125 mm), a diameter of 6 inches (about 150 mm), a diameter of 8 inches (about 200 mm), a diameter of 12 inches (about 300 mm), and a diameter of 16 inches (about 400 mm). Things are typical. The shape is not limited to a circular shape, and a silicon substrate processed into a rectangular shape or the like can also be used. In the following description, a case where a rectangular single crystal silicon substrate is used as the base substrate will be described. Note that the base substrate and the bond substrate may have the same size or different sizes.

The surface of the base substrate is preferably cleaned as appropriate using sulfuric acid / hydrogen peroxide, ammonia / hydrogen peroxide, dilute hydrofluoric acid, or the like. Alternatively, the surface of the base substrate may be cleaned by alternately discharging dilute hydrofluoric acid and ozone water.

An insulating layer may be formed over the base substrate. In the case where an insulating layer is formed over the base substrate, a structure in which the insulating layer on the bond substrate side is omitted can be employed. The insulating layer is not limited to a single layer, and may be a stack of a plurality of insulating films. As the insulating layer, an insulating film containing silicon as a composition such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be used.

As an example, the insulating layer can be formed by thermal oxidation treatment. As the thermal oxidation treatment, dry oxidation is preferably used, and halogen or a gas containing halogen may be added to the oxidizing atmosphere. As the halogen or a gas containing halogen, one or more kinds of gases selected from HCl, HF, NF ₃ , HBr, Cl ₂ , ClF, BCl ₃ , F ₂ , Br _{2, and the} like can be used.

Before the bonding, the surface of the base substrate is cleaned. The surface of the base substrate is preferably cleaned using cleaning using hydrochloric acid and hydrogen peroxide, megahertz ultrasonic cleaning, two-fluid jet cleaning, or cleaning using ozone water. Alternatively, the surfaces may be bonded after performing surface activation treatment such as irradiation treatment with an atomic beam or ion beam, ultraviolet treatment, ozone treatment, plasma treatment, biased plasma treatment or radical treatment.

Next, the semiconductor substrate (bond substrate) and the base substrate are bonded together, and the semiconductor substrate is separated. As a result, a semiconductor layer is formed on the base substrate. For the details of this step, the previous embodiment can be referred to.

In this embodiment, a single crystal silicon substrate with high heat resistance is used as the base substrate. For this reason, it is possible to raise the upper limit of various heat treatment temperatures to near the melting point of the single crystal silicon substrate.

For example, the upper limit of the heat treatment temperature for separating the semiconductor substrate can be about 1200 ° C. Further, by setting the temperature of the heat treatment to 700 ° C. or higher, the bonding with the base substrate is further strengthened.

Next, the surface of the semiconductor layer bonded to the base substrate is planarized to recover crystallinity.

The surface of the semiconductor layer in close contact with the base substrate is a part of the embrittled region including crystal defects, and the flatness is impaired. Therefore, it is preferable to perform heat treatment to reduce crystal defects and improve surface flatness.

The heat treatment is preferably performed at a temperature of 800 ° C. to 1300 ° C., typically 850 ° C. to 1200 ° C. By performing heat treatment under such a relatively high temperature condition, crystal defects can be reduced and surface flatness can be improved.

For the heat treatment, an RTA apparatus, a resistance heating furnace, a microwave heating apparatus, or the like can be used. For example, in the case of using a resistance heating furnace, heat treatment may be performed at 950 ° C. to 1150 ° C. for about 1 minute to 4 hours. Note that the heat treatment for separating the semiconductor substrate can be performed at a high temperature to replace the heat treatment.

The semiconductor layer may be irradiated with laser light before or after heat treatment. By irradiating laser light, crystal defects that cannot be repaired by heat treatment can be repaired. For the details of the laser light irradiation, the previous embodiment can be referred to.

Further, the semiconductor region above the semiconductor layer may be removed by polishing or the like before and after the heat treatment to planarize the surface. By the planarization treatment, the surface of the semiconductor layer can be further planarized. Specifically, the polishing can be performed by CMP treatment or liquid jet polishing. Note that the semiconductor layer may be thinned by the treatment.

Further, the semiconductor region above the semiconductor layer can be removed by etching and planarized. For the etching, for example, a dry etching method such as a reactive ion etching method, an ICP etching method, an ECR etching method, a parallel plate etching method, a magnetron plasma etching method, a two-frequency plasma etching method or a helicon wave plasma etching method is used. be able to. Note that planarization may be performed using both the polishing and the etching.

Further, by the polishing and the etching, the surface of the semiconductor layer can be planarized and the semiconductor layer can be thinned to an optimum thickness for a semiconductor element to be formed later.

Various semiconductor devices can be manufactured by using the SOI substrate obtained by the above-described process in the subsequent manufacturing process of the semiconductor device.

For the details of the reproduction process, the previous embodiment can be referred to.

As shown in this embodiment mode, the manufacturing cost of an SOI substrate can be reduced by repeatedly using a semiconductor substrate that has undergone a regeneration treatment process. In particular, when heat treatment at a high temperature as shown in this embodiment mode or the like is used, an SOI substrate having favorable characteristics can be manufactured even when a slight defect remains in the bond substrate. It is.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example of a semiconductor device formed using the SOI substrate manufactured in the above embodiment will be described.

FIG. 7 illustrates an example of a semiconductor device including the transistor 280 which is an n-channel transistor and the transistor 281 which is a p-channel transistor. The transistor 280 and the transistor 281 are formed over the base substrate 120 with the insulating layer 102 and the insulating layer 122 interposed therebetween. Various semiconductor devices can be formed by combining such a plurality of transistors. Hereinafter, a method for manufacturing the semiconductor device illustrated in FIGS.

First, an SOI substrate is prepared. As the SOI substrate, the SOI substrate manufactured in the above embodiment can be used.

Next, the semiconductor layers are separated by etching to form island-shaped semiconductor layers 251 and 252. The semiconductor layer 251 constitutes an n-channel transistor, and the semiconductor layer 252 constitutes a p-channel transistor.

After the insulating layer 254 is formed over the semiconductor layers 251 and 252, the gate electrode 255 is formed over the semiconductor layer 251 with the insulating layer 254 interposed therebetween, and the gate electrode 256 is formed over the semiconductor layer 252.

Note that an impurity element serving as an acceptor such as boron, aluminum, or gallium, or an impurity element serving as a donor such as phosphorus or arsenic is added to the semiconductor layer in order to control the threshold voltage of the transistor. Is preferred. For example, an impurity element serving as an acceptor is added to a region where an n-channel transistor is formed, and an impurity element serving as a donor is added to a region where a p-channel transistor is formed.

Next, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251, and a p-type high concentration impurity region 259 is formed in the semiconductor layer 252. Specifically, first, a semiconductor layer 252 to be a p-channel transistor is covered with a resist mask, an impurity element is added to the semiconductor layer 251, and an n-type low-concentration impurity region 257 is formed in the semiconductor layer 251. As an impurity element to be added, phosphorus or arsenic may be used. By using the gate electrode 255 as a mask, an n-type low concentration impurity region 257 is formed in the semiconductor layer 251 in a self-aligning manner. Further, a region of the semiconductor layer 251 that overlaps with the gate electrode 255 becomes a channel formation region 258.

Next, after removing the mask covering the semiconductor layer 252, the semiconductor layer 251 to be an n-channel transistor is covered with a resist mask. Then, an impurity element is added to the semiconductor layer 252. As the impurity element to be added, boron, aluminum, gallium, or the like may be used. Here, the gate electrode 256 functions as a mask, and a p-type high concentration impurity region 259 is formed in the semiconductor layer 252 in a self-aligning manner. A region overlapping with the gate electrode 256 of the semiconductor layer 252 becomes a channel formation region 260. Although the method of forming the p-type high-concentration impurity region 259 after forming the n-type low-concentration impurity region 257 has been described here, the p-type high-concentration impurity region 259 may be formed first. it can.

Next, after removing the resist mask covering the semiconductor layer 251, an insulating layer having a single-layer structure or a stacked structure including a nitride such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like. Then, anisotropic etching in the vertical direction is applied to the insulating layer, so that the side wall insulating layer 261 and the side wall insulating layer 262 in contact with the side surfaces of the gate electrode 255 and the gate electrode 256 are formed. Note that the insulating layer 254 is also etched by the anisotropic etching.

Next, the semiconductor layer 252 is covered with a resist mask, and an impurity element is added to the semiconductor layer 251 with a high dose. Thus, the n-type high concentration impurity region 267 is formed using the gate electrode 255 and the sidewall insulating layer 261 as a mask.

After the impurity element activation treatment (heat treatment), an insulating layer 268 containing hydrogen is formed. After the insulating layer 268 is formed, heat treatment is performed at a temperature of 350 ° C. to 450 ° C., and hydrogen contained in the insulating layer 268 is diffused into the semiconductor layer 251 and the semiconductor layer 252. The insulating layer 268 can be formed by depositing silicon nitride or silicon nitride oxide by a plasma CVD method with a process temperature of 350 ° C. or lower. By supplying hydrogen to the semiconductor layer 251 and the semiconductor layer 252, defects that become trapping centers in the semiconductor layer 251 and the semiconductor layer 252 or at the interface between them and the insulating layer 254 are effectively compensated. Can do.

After that, an interlayer insulating layer 269 is formed. The interlayer insulating layer 269 has a single-layer structure or a stacked structure using an insulating film containing an inorganic material such as silicon oxide or BPSG (Boron Phosphorus Silicon Glass), or an insulating film containing an organic material such as polyimide or acrylic. be able to. After a contact hole is formed in the interlayer insulating layer 269, a wiring 270 is formed. For the formation of the wiring 270, for example, a conductive film having a three-layer structure in which a low-resistance metal film such as an aluminum film or an aluminum alloy film is sandwiched between barrier metal films can be used. For the barrier metal film, molybdenum, chromium, titanium, or the like can be used.

Through the above steps, a semiconductor device including an n-channel transistor and a p-channel transistor can be manufactured. The SOI substrate used in the semiconductor device of this embodiment is manufactured at a very low cost as shown in the previous embodiment. For this reason, it is possible to suppress the cost concerning manufacture of a semiconductor device.

Note that in this embodiment, the semiconductor device and the manufacturing method thereof according to FIGS. 7A to 7C are described; however, the structure of the semiconductor device according to one embodiment of the present invention is not limited thereto. The semiconductor device may include a capacitor, a resistor, a photoelectric conversion element, a light-emitting element, and the like in addition to the transistor.

Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

In this example, the insulating layer was removed and wet etching using various etchants was performed on a semiconductor substrate produced by manufacturing an SOI substrate. The results are shown below.

First, the semiconductor substrate used in this example will be described.

In this embodiment, a rectangular single crystal silicon substrate of 5 inches square is used as the semiconductor substrate. First, the semiconductor substrate was thermally oxidized in an atmosphere containing HCl to form an oxide film having a thickness of 100 nm on the substrate surface. The thermal oxidation conditions were 950 ° C. for 4 hours, and the thermal oxidation atmosphere contained HCl at a rate of 3% by volume with respect to oxygen.

Next, ions were added from the surface of the oxide film to the semiconductor substrate using an ion doping apparatus. In this example, hydrogen was ionized and irradiated to form an embrittled region in the semiconductor substrate. The ion doping conditions were an acceleration voltage of 40 kV and a dose of 2.0 × 10 ¹⁶ ions / cm ² .

And the semiconductor substrate was bonded together to the glass substrate through the oxide film. After that, heat treatment was performed at 200 ° C. for 120 minutes, and further, heat treatment was performed at 600 ° C. for 120 minutes, so that the single crystal silicon layer was separated from the semiconductor substrate with the embrittled region as a boundary. As a result, an SOI substrate was manufactured and a semiconductor substrate having a convex portion at the peripheral edge was manufactured.

Next, processing for the above-described semiconductor substrate will be described.

First, in order to remove the insulating layer formed so as to cover the semiconductor substrate, a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (product name: LAL500, manufactured by Stella Chemifa Corporation) is used for the semiconductor substrate. Wet etching treatment was applied. At this time, the liquid temperature was room temperature and the etching time was 5 minutes.

Next, a mixed solution (hereinafter referred to as a mixed solution A) in which hydrofluoric acid, nitric acid, and acetic acid are mixed at a volume ratio of 1: 3: 10 to the semiconductor substrate from which the insulating layer has been removed, hydrofluoric acid, nitric acid, and acetic acid. Is mixed at a volume ratio of 1: 100: 100 (hereinafter referred to as “mixture B”), and a mixed solution of hydrofluoric acid, nitric acid and acetic acid is mixed at a volume ratio of 1: 0.1: 10 (hereinafter referred to as “mixed liquid”). C), a mixed liquid in which hydrofluoric acid, nitric acid, and acetic acid were mixed at a volume ratio of 1:10:10 (hereinafter, mixed liquid D), and hydrofluoric acid and hydrogen peroxide solution were mixed at a volume ratio of 1: 5. Wet etching was performed using either a mixed solution (hereinafter referred to as a mixed solution E) or an aqueous solution (also referred to as a TMAH aqueous solution) containing 2.38 wt% of TMAH (Tetra Methyl Ammonium Hydroxide) as an etchant.

In the preparation of the above mixture, hydrofluoric acid having a concentration of 50% by weight (manufactured by Stella Chemifa), nitric acid having a concentration of 70% by weight (manufactured by Wako Pure Chemical Industries, Ltd.), and acetic acid having a concentration of 97.7% by weight (Kishida Chemical Co., Ltd.) And hydrogen peroxide water (Mitsubishi Gas Chemical Co., Ltd.) having a concentration of 31% by weight was used. The etchant liquid temperature was room temperature, and the etching time was 30 seconds, 1 minute, 2 minutes, 4 minutes, 6 minutes, or 8 minutes. The details of the etchant are shown in Table 1.

Step measurement of the periphery of the semiconductor substrate (using a surf coder (step difference measuring device) ET4100 manufactured by Kosaka Laboratories) on the semiconductor substrate wet-etched at each time using the above six types of etchants, and The etching amount measurement of the central part of the semiconductor substrate (using Sorter 1000 manufactured by Lappmaster SFT Co., Ltd. and LK-G30 manufactured by Keyence Corporation) was performed. In addition, the substrate etched with the mixed solution A was photographed at the periphery of the semiconductor substrate (using an optical microscope MX61L manufactured by Olympus Corporation, a Nomarski image). Here, the central portion of the semiconductor substrate refers to a region excluding the peripheral portion of the semiconductor substrate where a step is formed.

FIG. 8A shows an optical micrograph of the periphery immediately after the semiconductor substrate is separated, and FIG. 8B shows an optical micrograph after the insulating layer is removed. 9A and 9B show the results of the step measurement at the periphery of the semiconductor substrate corresponding to FIGS. 8A and 8B, respectively. Here, in the graph of the level difference measurement results, the vertical axis indicates the level difference (μm) when the central portion of the semiconductor substrate is 0 (reference), and the horizontal axis indicates the width (mm) of the semiconductor substrate. The same applies to the graphs of the subsequent step measurement.

In FIG. 8A and FIG. 8B, the left side of the photograph corresponds to the convex portion on the peripheral edge of the substrate, the right side represents the separation portion where the single crystal silicon layer is separated, and the boundary corresponds to the step portion. In FIG. 8A, the remaining insulating layer is observed, and in FIG. 8B, silicon remaining in the lower layer of the removed insulating layer is observed. Moreover, it can be seen that unevenness due to minute voids is formed at the peripheral edge of the semiconductor substrate, and the flatness is low. On the right side of the photograph, silicon that follows the center of the semiconductor substrate is observed.

The same can be said from the step measurement graphs of FIGS. 9A and 9B. In FIG. 9A, the step between the peripheral portion of the semiconductor substrate and the central portion of the semiconductor substrate is about 0.2 μm, whereas in FIG. 9B, since the insulating layer is removed, the peripheral portion of the semiconductor substrate and the semiconductor The step at the center of the substrate is about 0.1 μm.

Next, optical micrographs of the peripheral portion of the semiconductor substrate that has been wet-etched using the mixed solution A are shown in FIGS. Here, each optical micrograph and etching time correspond as follows. 10 (A1) and FIG. 10 (A2) are 30 seconds, FIG. 10 (B1) and FIG. 10 (B2) are 1 minute, FIG. 10 (C1) and FIG. 10 (C2) are 2 minutes, FIG. 11 (A1) 11 (A2) is 4 minutes, FIG. 11 (B1) and FIG. 11 (B2) are 6 minutes, and FIG. 11 (C1) and FIG. 11 (C2) are 8 minutes. 10 and 11, (A1), (B1), and (C1) are 50 times magnification, and (A2), (B2), and (C2) are 500 times magnification.

In FIG. 12, the result of the level | step difference measurement of the semiconductor substrate peripheral part which performed the wet etching using the liquid mixture A is shown. Each figure corresponds to the etching time as follows. 12 (A) is 30 seconds, FIG. 12 (B) is 1 minute, FIG. 12 (C) is 2 minutes, FIG. 12 (D) is 4 minutes, FIG. 12 (E) is 6 minutes, FIG. Is 8 minutes.

Further, in FIGS. 13 to 17, 30 seconds, 1 minute, 2 minutes, 4 minutes, 6 minutes, using any of the mixed solution B, mixed solution C, mixed solution D, mixed solution E, and TMAH aqueous solution, The result of the level | step difference measurement of the semiconductor substrate peripheral part which performed the wet etching for 8 minutes is shown. Each figure and etchant correspond as follows. FIG. 13 shows the result when the mixed solution B, FIG. 14 shows the mixed solution C, FIG. 15 shows the mixed solution D, FIG. 16 shows the mixed solution E, and FIG. Moreover, each figure of FIG. 13 thru | or FIG. 17 respond | corresponds as follows. (A) is 30 seconds, (B) is 1 minute, (C) is 2 minutes, (D) is 4 minutes, (E) is 6 minutes, and (F) is 8 minutes.

FIG. 18 shows the result of measuring the etching amount at the center of the semiconductor substrate when wet etching is performed using the mixed solution A and the mixed solution D. In FIG. 18, black circles are results when the mixed solution A is used, and white circles are results when the mixed solution D is used. The vertical axis of the graph shown in FIG. 18 indicates the etching amount (μm) of the semiconductor substrate in the central portion of the semiconductor substrate, and the horizontal axis indicates the etching time (minutes).

Here, the measurement of the etching amount in the central part of the semiconductor substrate is calculated from the change in the substrate thickness in the central part of the semiconductor substrate before and after the etching. The substrate thickness was determined from the difference between laser displacement meters (LK-G30 manufactured by Keyence) provided above and below the measurement stage (Sorter 1000 manufactured by Lapmaster SFT Co., Ltd.). The substrate thickness was measured at 10 × 10 points in a 107 mm square area at the center of the semiconductor substrate. Moreover, the etching amount of the semiconductor substrate center part was calculated | required by the comparison of those average values. The repeatability of the laser displacement meter is ± 0.05 μm, and the repeatability of the substrate thickness is ± 0.5 μm.

From the comparison of the optical micrographs shown in FIGS. 10 and 11, it can be seen that the level difference due to the convex portion on the left side of the photo is reduced as the etching time increases. For example, when the etching time shown in FIG. 11A is 4 minutes, there is almost no step. The same can be said from the step measurement graph shown in FIG.

From FIG. 12, in the wet etching using the mixed solution A, first, a vertical hole is formed in a step perpendicular to the substrate plane at the step of the peripheral edge of the semiconductor substrate, and the etching proceeds so as to enlarge the vertical hole. I understand that This indicates that the mixed solution A penetrates into a semiconductor region (damaged semiconductor region having crystal defects or microvoids) forming a step at the periphery of the semiconductor substrate, and the step is removed from the inside of the semiconductor region. . The state of wet etching with such a mixed solution A tends to be different from that of other etchants described later.

Further, from the graph of the etching amount of the semiconductor substrate in the central portion of the semiconductor substrate shown in FIG. 18, the etching amount of the semiconductor substrate is sufficiently small and within the error range in the substrate thickness measurement until at least the etching time of 6 minutes.

Table 2 shows the relationship between the etching time, the etching amount (μm) at the central portion of the semiconductor substrate, and the etching amount (μm) at the peripheral portion of the semiconductor substrate. Further, an etching selection ratio (selection ratio 1) obtained from the etching amount at the central portion of the semiconductor substrate and the etching amount at the peripheral edge portion of the semiconductor substrate and the selection ratio of the difference (selection ratio 2) are shown together.

Here, the selection ratio 1 is obtained by dividing the average value of the etching amount in the step (region having a width of 0.1 mm) at the peripheral edge of the semiconductor substrate by the average value of the etching amount in the central portion of the semiconductor substrate. The difference selection ratio (selection ratio 2) is the etching amount between 0 minute and 1 minute, the etching amount between 1 minute and 2 minutes, the etching amount between 2 minutes and 4 minutes, and 4 minutes to 6 minutes, respectively. It is the selection ratio calculated | required from the etching amount in between. For example, the etching amount in the central portion of the semiconductor substrate between 1 minute and 2 minutes is 0.14-0.096 = 0.044 (μm), and the etching amount in the peripheral portion of the semiconductor substrate is 0.225-0. Since 101 = 0.124 (μm), the selection ratio 2 in this case is 0.124 / 0.044 = 2.818.

From Table 2, it can be seen that the difference selection ratio (selection ratio 2) varies with the etching time. Specifically, the selection ratio, which was about 1 at the time immediately after the start of etching, becomes 2 or more and returns to about 1 again. This is considered to be due to the following reason.

First, at the start of etching, the damaged semiconductor region at the peripheral portion of the semiconductor substrate is removed and the damaged semiconductor region remaining at the central portion of the semiconductor substrate is removed, so in the peripheral portion of the semiconductor substrate and the central portion of the semiconductor substrate, Etching rates are not significantly different. That is, the selection ratio is about 1. After the damaged semiconductor region in the central part of the semiconductor substrate is removed, the etching rate decreases in the central part of the semiconductor substrate, but the damaged semiconductor region still remains in the peripheral part of the semiconductor substrate, and the etching rate does not decrease. . For this reason, the selection ratio is increased (specifically, 2 or more). Thereafter, the damaged semiconductor region in the peripheral portion of the semiconductor substrate is removed, so that the etching rates of the peripheral portion of the semiconductor substrate and the central portion of the semiconductor substrate become approximately the same. That is, the selection ratio returns to about 1. It can be said that the damaged semiconductor region is removed preferentially with such a change in the selection ratio.

Further, the selection ratio 1 of the etching time of 2 minutes and 4 minutes is as high as 1.607 and 1.748, respectively. The selection ratio 2 of 1 minute to 2 minutes, 2 minutes to 4 minutes is also as high as 2.818 and 2.609, respectively. As described above, by using the mixed solution A (a mixed solution in which hydrofluoric acid, nitric acid, and acetic acid are mixed at a volume ratio of 1: 3: 10) as an etchant, a step (convex portion) at the peripheral edge of the semiconductor substrate can be obtained in a short time. Can be removed preferentially.

In the etching using the mixed solution B, the progress of the etching is slow, and the step is not removed even if the etching time is 8 minutes (see FIG. 13). Further, unlike the case of the mixed liquid A, the step at the periphery of the semiconductor substrate is gradually etched from the surface, and no deep vertical hole is formed. Thus, it has been found that even when the semiconductor substrate is etched using the mixed solution B, the step at the periphery of the semiconductor substrate is not removed, or it takes a long time to remove the step.

In the etching using the mixed liquid C, the step at the peripheral edge of the semiconductor substrate is not removed (see FIG. 14). Thus, it was found that even when the semiconductor substrate was etched using the mixed solution C, the etching of the semiconductor substrate hardly progressed.

In the etching using the mixed solution D, as shown in FIG. 18, the etching amount at the central portion of the semiconductor substrate increases in proportion to the etching time, but the step at the peripheral portion of the semiconductor substrate remains maintained (see FIG. 15). ). Thus, it was found that even when the mixed solution D was used as the etching solution, the entire semiconductor substrate was etched uniformly, and the step at the peripheral edge of the semiconductor substrate could not be removed preferentially.

In the etching using the mixed liquid E, the step at the peripheral edge of the semiconductor substrate is not removed as in the case of using the mixed liquid C (see FIG. 16). Thus, it was found that even when the semiconductor substrate was etched using the mixed solution E, the etching of the semiconductor substrate hardly progressed.

In the etching using the TMAH aqueous solution, the progress of the etching is slow, and the step is not removed even if the etching time is 8 minutes (see FIG. 17). Thus, it has been found that even when the semiconductor substrate is etched using the TMAH aqueous solution, the step at the periphery of the semiconductor substrate is not removed, or it takes a long time to remove the step.

Here, the mixed solution A, the mixed solution B, the mixed solution C, and the mixed solution D are ternary mixed solutions composed of hydrofluoric acid, nitric acid, and acetic acid, and the role and reaction of each element are as follows.

Nitric acid oxidizes silicon. The reaction is expressed as in Formula (1).
3Si + 4HNO ₃ → 3SiO ₂ + 2H ₂ O + 4NO (1)

Hydrofluoric acid dissolves silicon oxide. The reaction is expressed as shown in Formula (2).
SiO ₂ + 6HF → 2H ⁺ + [SiF ₆ ] ² + 2H ₂ O (2)

Acetic acid stabilizes the mixed solution and suppresses rapid etching.

In this way, the ternary mixed liquid composed of hydrofluoric acid, nitric acid, and acetic acid etches silicon by repeating the oxidation of silicon shown in formula (1) and the dissolution of silicon oxide shown in formula (2). It has a function. In other words, in a ternary mixture composed of hydrofluoric acid, nitric acid, and acetic acid, when the amount of hydrofluoric acid is large, the oxidation of silicon by nitric acid shown in the formula (1) is rate limiting, and the amount of nitric acid is large. The rate of dissolution of silicon oxide by hydrofluoric acid shown in formula (2) becomes the rate-limiting factor.

From this, it is considered that in the mixed solution C, the amount of nitric acid is small, so that the oxidation of silicon becomes rate limiting, and wet etching has not progressed. The same applies to the mixed solution E in which hydrogen peroxide oxidizes silicon. It is considered that the wet etching did not proceed in the mixed solution E because the oxidizing power of hydrogen peroxide was small.

Further, in the mixed solution D, since the amounts of hydrofluoric acid and nitric acid are large, the reactions of the formulas (1) and (2) proceed rapidly, and as a result, the selection between the semiconductor substrate peripheral portion and the semiconductor substrate central portion is performed. It is considered that the ratio was not achieved and the entire substrate was wet etched uniformly.

In the mixed solution B, since the amount of hydrofluoric acid is small, the dissolution of silicon oxide becomes rate limiting, and it is considered that wet etching did not proceed. This is because when the amount of hydrofluoric acid is reduced, etching from the inside of the damaged semiconductor region due to crystal defects and microvoids hardly occurs, and etching from the surface of the damaged semiconductor region proceeds preferentially.

On the other hand, in the mixed solution A, since the balance of hydrofluoric acid, nitric acid, and acetic acid is good, the reaction of either formula (1) or formula (2) does not become rate-limiting. Moreover, since the effect of suppressing etching by acetic acid is obtained, the entire substrate is not etched uniformly.

In this way, by etching the step at the periphery of the semiconductor substrate using the mixed solution A (mixed solution having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid of 1: 3: 10), the periphery of the semiconductor substrate and the center of the semiconductor substrate are etched. The convex portions present on the peripheral edge of the semiconductor substrate can be removed in a short time while taking the selection ratio of the portions. For this reason, it is possible to reliably and efficiently perform the regeneration processing of the semiconductor substrate.

Note that the structure described in this example can be combined as appropriate with any of the structures described in the other embodiments and examples.

In this embodiment, as a regeneration process, a wet etching process using a mixed solution of hydrofluoric acid, nitric acid and acetic acid and a CMP process are used in combination, and a CMP process is mainly performed without using the wet etching process described above. The results of comparison are shown for the case of use.

As the CMP process, a process with a low polishing rate (finish polishing) was used after a process with a high polishing rate. In the case where the above-described wet etching process is not used, the CMP process is performed for a long time in order to realize a regeneration process equivalent to the case where the wet etching process is used.

The semiconductor substrate to be subjected to the regeneration process was manufactured in the same manner as in the previous example. For details, refer to the previous example.

A recycled semiconductor substrate (hereinafter referred to as substrate A) using the above-described wet etching process and CMP process with a short polishing time was manufactured as follows.

First, in order to remove the insulating layer formed so as to cover the semiconductor substrate, a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (product name: LAL500, manufactured by Stella Chemifa Corporation) is used for the semiconductor substrate. Wet etching treatment was applied. At this time, the liquid temperature was room temperature and the etching time was 300 seconds.

Next, a mixed solution (corresponding to the mixed solution A in the previous embodiment) in which hydrofluoric acid, nitric acid, and acetic acid are mixed at a volume ratio of 1: 3: 10 is used for the semiconductor substrate from which the insulating layer has been removed. Wet etching treatment was applied. At this time, the liquid temperature was room temperature and the etching time was 2 minutes. In the preparation of the above mixture, hydrofluoric acid having a concentration of 50% by weight (manufactured by Stella Chemifa), nitric acid having a concentration of 70% by weight (manufactured by Wako Pure Chemical Industries, Ltd.), and acetic acid having a concentration of 97.7% by weight (Kishida Chemical). Used).

Next, CMP processing at a high polishing rate was performed on the semiconductor substrate. In the CMP treatment, a polyurethane-based polishing cloth and a silica-based slurry liquid (ILD1300 manufactured by Nitta Haas Co., Ltd., particle size 150 nm, diluted 20 times) were used. The slurry flow rate was 200 ml / min, the polishing pressure was 0.02 MPa, the spindle rotation speed was 30 rpm, the table rotation speed was 30 rpm, and the treatment time was 3 minutes.

Thereafter, CMP processing at a low polishing rate was performed on the semiconductor substrate. In the CMP treatment, a suede polishing cloth (supreme manufactured by Nitta Haas Co., Ltd.) and a silica-based slurry (NP8020 manufactured by Nitta Haas Co., Ltd., particle size 60 nm, diluted 20 times) were used. The slurry flow rate was 200 ml / min, the polishing pressure was 0.01 MPa, the spindle rotation speed was 30 rpm, the table rotation speed was 30 rpm, and the treatment time was 3 minutes.

On the other hand, a recycled semiconductor substrate (hereinafter referred to as substrate B) that does not use the above-described wet etching process is manufactured as follows.

First, in order to remove the insulating layer formed so as to cover the semiconductor substrate, a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (product name: LAL500, manufactured by Stella Chemifa Corporation) is used for the semiconductor substrate. Wet etching treatment was applied. At this time, the liquid temperature was room temperature and the etching time was 300 seconds.

Next, CMP processing at a high polishing rate was performed on the semiconductor substrate. In the CMP treatment, a polyurethane-based polishing cloth and a silica-based slurry liquid (ILD1300 manufactured by Nitta Haas Co., Ltd., particle size 150 nm, diluted 20 times) were used. The slurry flow rate was 200 ml / min, the polishing pressure was 0.02 MPa, the spindle rotation speed was 30 rpm, the table rotation speed was 30 rpm, and the treatment time was 12 minutes.

Thereafter, CMP processing at a low polishing rate was performed on the semiconductor substrate. In the CMP treatment, a suede polishing cloth (supreme manufactured by Nitta Haas Co., Ltd.) and a silica-based slurry (NP8020 manufactured by Nitta Haas Co., Ltd., particle size 60 nm, diluted 20 times) were used. The slurry flow rate was 200 ml / min, the polishing pressure was 0.01 MPa, the spindle rotation speed was 30 rpm, the table rotation speed was 30 rpm, and the treatment time was 10 minutes.

For two types of regenerative semiconductor substrates produced by the above-described method, observation with an optical microscope, level difference measurement with a level difference measuring device (using a surf coder manufactured by Kosaka Laboratory Ltd.), evaluation of flatness with a scanning probe microscope ( SII NanoTechnology Co., Ltd. SPA-500 and SII NanoTechnology Co., Ltd. SPI3800N are used), and the measurement of the reduction in the thickness of the semiconductor substrate in the recycling process (Sorter1000 manufactured by LAPMASTER SFT Co., Ltd. is used). Went.

FIG. 19A shows an optical micrograph (a Nomarski image at a magnification of 50) of the periphery of the semiconductor substrate before the regeneration process, and FIG. 19B shows the periphery of the semiconductor substrate after the wet etching process described above. Similarly, the results of the step measurement are shown in FIGS. 20 (A) and 20 (B).

As shown in FIG. 19A, the semiconductor substrate before the regeneration process has a step (convex portion) at the periphery, an insulating layer on the peripheral surface, and an insulating layer on the central surface. Silicon is observed. FIG. 20A also shows that there is a step of about 0.2 μm at the periphery of the semiconductor substrate before the regeneration process.

On the other hand, in the semiconductor substrate shown in FIG. 19B, the step (convex portion) present at the peripheral edge disappears, and silicon is observed on the entire surface. Note that the white line running vertically to the left in FIG. 19B represents the edge of the semiconductor substrate. It can be confirmed from FIG. 20B that the level difference disappears.

Next, the results of evaluating the flatness of two types of regenerative semiconductor substrates using a scanning probe microscope are shown. The measurement conditions with the scanning probe microscope were a scanning speed of 1.0 Hz, a measurement area of 1 μm × 1 μm, and two measurement points. Moreover, the dynamic force mode (DFM: dynamic force mode) was used for the said measurement. Here, the dynamic force mode is a method of measuring the surface shape while controlling the distance between the probe and the sample so that the vibration amplitude of the lever is constant in a state where the cantilever is resonated.

The flatness of the regenerated semiconductor substrate was evaluated by average surface roughness (Ra) and maximum height difference (P-V). Here, the average surface roughness (Ra) is a three-dimensional extension of the centerline average roughness Ra defined in JIS B0601: 2001 (ISO 4287: 1997) so that it can be applied to the measurement surface. It is expressed as an average value of absolute values of deviation from the reference plane to the specified plane. Further, the maximum height difference (P−V) is expressed by a difference between the highest altitude at the highest peak and the lowest altitude at the lowest valley bottom on the designated plane. The summit and valley floor are three-dimensional extensions of the “mountain peak” and “valley floor” defined in JIS B601: 2001 (ISO 4287: 1997). The summit is the highest point on the specified mountain. The point with the lowest elevation on the designated surface.

Table 3 shows the evaluation results of the flatness of the regenerated semiconductor substrate using a scanning probe microscope.

For both the substrate A and the substrate B, there is no step between the central portion and the peripheral portion, and the flatness of the central portion and the peripheral portion is almost the same. Comparing the substrate A and the substrate B, in the substrate A, Ra is 0.05 nm and PV is 0.393 nm in the peripheral portion, whereas in the substrate B, Ra is 0.06 nm and P in the peripheral portion. -V is 0.47 nm. From this, it can be said that the flatness of the substrate A is better.

Next, the result of measuring the reduction amount of the thickness of the semiconductor substrate in the regeneration process will be described. Here, the reduction amount (semiconductor removal amount) in the central portion of the semiconductor substrate was measured from the change in thickness before and after the regeneration treatment step. Table 4 shows the reduction amount (removal amount) in the production of the substrate A and the substrate B.

In the production of the substrate A, the amount of decrease in the thickness of the semiconductor substrate was 1.38 μm. On the other hand, in the production of the substrate B, the amount of decrease in the thickness of the semiconductor substrate was 6.96 μm. From this, it can be seen that the reduction amount in the production of the substrate A is about one-fourth of the reduction amount in the production of the substrate B. In particular, the amount of reduction in etching in the production of the substrate A was only 0.41 μm.

As described above, by performing the regenerating process in which the etching process and the CMP process are combined, it is possible to suppress the reduction of the semiconductor substrate in the regenerating process while maintaining the flatness of the regenerated semiconductor substrate.

Note that the structure described in this example can be combined as appropriate with any of the structures described in the other embodiments and examples.

In this example, an oxide film is formed on a semiconductor substrate and then irradiated with hydrogen ions, and a cross section of the semiconductor substrate is observed.

In this embodiment, a rectangular single crystal silicon substrate of 5 inches square is used as the semiconductor substrate. First, the semiconductor substrate was thermally oxidized in an atmosphere containing HCl to form an oxide film having a thickness of 100 nm on the substrate surface. The thermal oxidation conditions were 950 ° C. for 4 hours, and the thermal oxidation atmosphere contained HCl at a rate of 3% by volume with respect to oxygen.

Next, hydrogen was added to the semiconductor substrate from the surface of the oxide film using an ion doping apparatus. In this example, hydrogen was ionized and irradiated to form an embrittled region in the semiconductor substrate. The ion doping conditions were an acceleration voltage of 50 kV and a dose of 2.0 × 10 ¹⁶ ions / cm ² . As a result, an embrittled region was formed at a depth of about 250 nm from the surface of the oxide film.

FIG. 21A shows a cross-sectional TEM image of the semiconductor substrate subjected to the above-described treatment. FIG. 21B shows a cross-sectional TEM image after the semiconductor substrate is subjected to heat treatment and separated in the embrittled region.

21A and 21B that many crystal defects are formed near the surface of the single crystal substrate. Further, FIG. 21B shows that the semiconductor substrate is separated from the surface at a depth of about 139 nm.

Here, a convex portion is formed on the peripheral edge portion of the semiconductor substrate after the separation described above, because it is not bonded to the base substrate. Then, the remaining semiconductor layer (damaged semiconductor region) constituting the convex portion has crystal defects and microvoids in the same manner as the separated semiconductor layer. Therefore, by performing etching using a mixed solution containing hydrofluoric acid, nitric acid, and acetic acid as shown in the previous embodiment, the protrusions formed on the peripheral edge of the semiconductor substrate after separation are preferentially removed. It becomes easy to do.

Note that the structure described in this example can be combined as appropriate with any of the structures described in the other embodiments and examples.

In this embodiment, a mixed liquid (mixed liquid A) obtained by mixing hydrofluoric acid, nitric acid, and acetic acid at a volume ratio of 1: 3: 10, and hydrofluoric acid, nitric acid, and acetic acid at a volume ratio of 1: 2: 10. An investigation result in the case of using a mixed liquid mixture (hereinafter, mixed liquid A +) as an etchant will be described.

The semiconductor substrate used in this example is the same as that used in Example 1, and details thereof are omitted.

The processing for the semiconductor substrate described above is as follows.

First, in order to remove the insulating layer formed so as to cover the semiconductor substrate, a mixed solution containing hydrofluoric acid, ammonium fluoride, and a surfactant (product name: LAL500, manufactured by Stella Chemifa Corporation) is used for the semiconductor substrate. Wet etching treatment was applied. At this time, the liquid temperature was room temperature and the etching time was 300 seconds.

Next, a mixed solution (mixed solution A) in which hydrofluoric acid, nitric acid, and acetic acid are mixed at a volume ratio of 1: 3: 10, or hydrofluoric acid, nitric acid, and acetic acid, with respect to the semiconductor substrate from which the insulating layer has been removed. Wet etching was performed using a mixed liquid (mixed liquid A +) mixed at a volume ratio of 1: 2: 10 as an etchant. In the preparation of the mixed solution A and the mixed solution A +, hydrofluoric acid having a concentration of 50% by weight (manufactured by Stella Chemifa), nitric acid having a concentration of 70% by weight (manufactured by Wako Pure Chemical Industries, Ltd.), and acetic acid having a concentration of 97.7% by weight ( Kishida Chemical Co., Ltd.) was used.

FIG. 22A shows an optical micrograph (a Nomarski image with a magnification of 50 times) observing the periphery of the semiconductor substrate after wet etching using the mixed solution A +. FIG. 22B shows an optical micrograph (Nomarski image) with a magnification of 500 times. As can be seen from FIG. 22, in the case of the wet etching using the mixed solution A +, no residue was confirmed even under the condition that the etching residue may be generated in the wet etching using the mixed solution A. It is considered that by slightly increasing the ratio of hydrofluoric acid to nitric acid from 1: 3 (hydrofluoric acid: nitric acid), the formed oxide film is quickly removed and the generation of residues is suppressed.

In this way, when etching the step at the peripheral edge of the semiconductor substrate using the mixed solution A + (mixed solution having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid of 1: 2: 10), the mixed solution A (hydrofluoric acid, It was found that the generation of residues can be suppressed as compared with the case of using a mixed solution having a volume ratio of nitric acid and acetic acid of 1: 3: 10. The same applies to the case where a mixed solution having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid of 1.5: 3: 10 is used. On the other hand, as compared with a mixed solution having a volume ratio of hydrofluoric acid, nitric acid, and acetic acid of 1: 1: 10, a hydrofluoric acid, nitric acid, and acetic acid solution having a volume ratio of 1: 3: 10 was used. When the ratio of the acid was increased too much, surface roughness, remaining steps, etc. were confirmed.

According to this embodiment, the ratio of hydrofluoric acid to nitric acid is slightly increased from 1: 3 (hydrofluoric acid: nitric acid), so that the semiconductor substrate can be regenerated more reliably and efficiently. Understood.

Note that the structure described in this example can be combined as appropriate with any of the structures described in the other embodiments and examples.

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 102 Insulating layer 104 Embrittlement region 120 Base substrate 121 Semiconductor substrate 122 Insulating layer 123 Insulating layer 124 Semiconductor layer 125 Semiconductor region 126 Protruding portion 127 Semiconductor region 129 Semiconductor region 130 Semiconductor substrate 132 Reproduction semiconductor substrate 133 Semiconductor region 134 Laser light 251 Semiconductor layer 252 Semiconductor layer 254 Insulating layer 255 Gate electrode 256 Gate electrode 257 Low concentration impurity region 258 Channel formation region 259 High concentration impurity region 260 Channel formation region 261 Side wall insulating layer 262 Side wall insulating layer 267 High concentration impurity region 268 Insulation Layer 269 Interlayer insulating layer 270 Wiring 280 Transistor 281 Transistor

Claims (12)

For a semiconductor substrate in which a convex portion including a damaged semiconductor region and an insulating layer exists in the peripheral portion,
An etching process for removing the insulating layer;
Using a liquid mixture comprising a substance that oxidizes a semiconductor material constituting the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate and dissolution rate of the semiconductor material, An etching process for preferentially removing the damaged semiconductor region with respect to the semiconductor region;
A laser beam irradiation process for irradiating the semiconductor substrate with a laser beam from the surface side from which the damaged semiconductor region has been removed preferentially;
A method for reclaiming a semiconductor substrate, comprising: By separating a part as a semiconductor layer through ion irradiation and heat treatment, for the semiconductor substrate in which the convex part including the damaged semiconductor region and the insulating layer remains in the peripheral part,
An etching process for removing the insulating layer;
Using a liquid mixture comprising a substance that oxidizes a semiconductor material constituting the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate and dissolution rate of the semiconductor material, An etching process for preferentially removing the damaged semiconductor region with respect to the semiconductor region;
A laser beam irradiation process for irradiating the semiconductor substrate with a laser beam from the surface side from which the damaged semiconductor region has been removed preferentially;
A method for reclaiming a semiconductor substrate, comprising: A semiconductor substrate in which a convex portion including a damaged semiconductor region and an insulating layer remains in the peripheral portion by separating a part as a semiconductor layer through ion irradiation and heat treatment, and a damaged semiconductor region remains in other regions. Whereas
An etching process for removing the insulating layer;
Using a liquid mixture comprising a substance that oxidizes a semiconductor material constituting the semiconductor substrate, a substance that dissolves the oxidized semiconductor material, and a substance that controls the oxidation rate and dissolution rate of the semiconductor material, An etching process for preferentially removing the damaged semiconductor region with respect to the semiconductor region;
A laser beam irradiation process for irradiating the semiconductor substrate with a laser beam from the surface side from which the damaged semiconductor region has been removed preferentially;
A method for reclaiming a semiconductor substrate, comprising: 4. The method for regenerating a semiconductor substrate according to claim 1, wherein the ion irradiation is performed using an ion doping method. 5. The method for regenerating a semiconductor substrate according to claim 1, wherein the ions include H ₃ ⁺ . 6. The etching process for preferentially removing the damaged semiconductor region according to claim 1, wherein an etching selection ratio of the damaged semiconductor region to the undamaged semiconductor region is 2 or more. A method for reclaiming a semiconductor substrate. 7. The etching process for preferentially removing the damaged semiconductor region according to claim 1, after the etching selectivity of the convex portion with respect to the undamaged semiconductor region is lowered to less than 2. 8. A method for reclaiming a semiconductor substrate. 8. The region according to claim 1, wherein an angle formed by a tangent plane of the convex portion and a back surface of the semiconductor substrate is 0.5 ° or less by an etching process that preferentially removes the damaged semiconductor region. A method for reclaiming a semiconductor substrate, characterized in that at least is removed. 9. The method of reclaiming a semiconductor substrate according to claim 1, wherein the surface of the semiconductor substrate is polished after the etching process for preferentially removing the damaged semiconductor region. In any one of Claims 1 thru | or 9, Nitric acid is used as a substance which oxidizes the semiconductor material which comprises the said semiconductor substrate,
Hydrofluoric acid as a substance that dissolves the oxidized semiconductor material,
Acetic acid as a substance that controls the oxidation rate and dissolution rate of the semiconductor material,
A method for reclaiming a semiconductor substrate, comprising using the semiconductor substrate. A method for producing a regenerated semiconductor substrate, comprising producing a regenerated semiconductor substrate from the semiconductor substrate using the method according to any one of claims 1 to 10. An ion is added to the regenerated semiconductor substrate manufactured by the method according to claim 11 to form an embrittled region,
Through the insulating layer, the regenerated semiconductor substrate and the base substrate are bonded together,
A method for manufacturing an SOI substrate, wherein the recycled semiconductor substrate is separated by heat treatment, and a semiconductor layer is formed over the base substrate.