JP2011216966A - Solid-state imaging element, and method of driving the same, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the generation of noise when capturing images by a CMOS (Complementary Metal Oxide Semiconductor) image sensor.SOLUTION: The high luminance detection part 118e of a signal processing portion 118' detects a voltage value corresponding to the current value of an overflow drain for each unit pixel of a pixel array portion 111 as a received light quantity of a pixel unit. A level analysis portion 118a' obtains the order of a light receiving level in units of rows for pixels configuring the pixel array portion 111 on the basis of the voltage value read by the high luminance detection part 118e, and registers the order of the light receiving level in an address list 118b. The signal processing portion 118' updates the address list 115a of a system control portion 115 by the information of the address list 118b. The system control portion 115 causes the pixel array portion 111 to read light receiving signals in units of rows successively from the high order of the row unit of the address list 115a. This invention is applicable to an imaging apparatus.

Description

  The present invention relates to a solid-state imaging device, a solid-state imaging device driving method, and an electronic apparatus, and more particularly to a solid-state imaging device, a solid-state imaging device driving method, and an electronic device that reduce noise when an image is captured. Regarding equipment.

  A general CMOS (Complementary Metal Oxide Semiconductor) image sensor has a mechanism that sequentially scans a pixel array that is two-dimensionally arranged for each pixel row and performs reading. This row sequential scanning causes a time lag in the accumulation period for each pixel row, causing a phenomenon called focal plane distortion in which the captured image is distorted during moving subject imaging.

  In sensing applications that require high-speed moving subjects where image distortion cannot be tolerated, and sensing images that require simultaneous image capture, the entire array of pixels is accumulated by simultaneous reset driving of photodiodes (PD) in the pixel array. Is started at the same time, and the entire storage is simultaneously completed by the simultaneous transfer drive of all rows to the charge storage portion such as the floating diffusion region (FD: floating diffusion), thereby driving the pixel array to have the same storage period. There is something to do.

  Reading is performed by row-sequential scanning, but the signal held in the charge accumulation unit such as the floating diffusion region FD until read is caused by charge leaks or noise due to photoelectric conversion of the floating diffusion region FD itself (these are false It is deteriorated by a signal). On the other hand, instead of outputting the difference between the light reception signal readout and noise readout, which is a general CMOS image sensor operation, the output of only the light reception signal readout is performed to shorten the time required for one side readout, and as a result A method for reducing the influence of leak components has been proposed (see Patent Document 1). In addition, a method has been proposed in which the influence of a leak component is reduced by reading in order of increasing light quantity (see Patent Document 2).

JP 2000-4403 A JP 2009-188650 A

  By the way, as described above, the false signal of the CMOS image sensor having the synchronization period of the photodiode of each pixel of the pixel array mainly includes two components, one of which increases in proportion to time. The other is due to photoelectric conversion of the charge storage unit itself.

  For a leak component that is one of the components, the light reception signal of each pixel is not the difference between the read light reception signal and the noise component, and the read light reception signal itself is regarded as the light reception signal of each pixel. Techniques have been proposed for reducing the influence of components. That is, by using the read light reception signal itself as the light reception signal of each pixel, the readout period of the noise component in the readout of the row sequential scanning can be omitted, so that the readout process can be speeded up, and the processing period Techniques have been proposed for reducing the influence of leak components due to length.

  Also, the amount of noise due to photoelectric conversion of the charge storage unit itself, which is the other noise component, increases in proportion to the time it takes to store a subject with high brightness separately from the intended imaging before reading. For example, as shown in FIG. 1, from time ta to tb, the accumulation of the subject is completed at the same time on the first to Nth rows at the same time, and after time tb, until the read time t (n) in each row n. In the case where the subject moves, or in another example, in the case where a high-brightness subject such as a flashing light bulb appears after reading is completed, the slower reading, that is, the pixel array In the scanning, the amount of noise due to photoelectric conversion of the charge storage unit itself increases toward the end. That is, as shown in FIG. 1, in the case of row sequential readout, exposure of the light receiving element is started by global reset at time ta, and is globally transferred at time tb, so that readout time t ( n) becomes longer as the read row n advances, and becomes the longest in the Nth row which is the last row. In FIG. 1, the horizontal axis indicates the elapsed time, and the vertical axis indicates the accumulation state of each row.

  Since the position of a high-luminance subject is not conscious at the time of general imaging, the conventional technology that simply speeds up the reading is more effective when there is such a subject at the back of the scan, for example, below the image. A false signal will come out strongly. In addition, when there are high-luminance subjects at the top and bottom of the image, the intensity of the false signal varies depending on the scanning direction, that is, the top and bottom of the image, so that the captured image may be unnatural.

  The present invention has been made in view of such a situation. In particular, when an image is picked up by an image pickup device, the charge storage period of the light reception signal in each pixel is synchronized, and photoelectric conversion of the charge storage unit itself is performed. This also minimizes the false signal due to the influence of.

  A solid-state imaging device according to one aspect of the present invention stores a light receiving element that generates and accumulates a charge as a light receiving signal in response to received light, and a charge as a light receiving signal transferred by the light receiving element. Reset by releasing the charge accumulated in the charge accumulating unit based on a reset signal based on a charge accumulating unit, transfer means for transferring the charge as a light receiving signal accumulated from the light receiving element to the charge accumulating unit, and a reset signal Pixels in units of reset means, amplification means for amplifying a light reception signal composed of charges transferred to the charge storage section, and selection means for outputting the light reception signal amplified by the amplification means based on the selection signal A CMOS (Complementary Metal Oxide Semiconductor) image sensor having a plurality of pixels based on the level of a received light signal accumulated in the light receiving element. The analysis unit that analyzes the order of the level of the received light signal level in units of rows, and the generation of the selection signal in the unit of rows is controlled based on the order of row units that is the analysis result by the analysis unit After the transfer means transfers all the charges accumulated in the light receiving element to the charge accumulation section, and the reset means resets the charge accumulation section. When the light receiving element starts to accumulate charges as a light receiving signal generated according to the received light, and when a predetermined accumulation time has elapsed since the charge accumulation by the light receiving element is started, the reset means Then, after resetting the charge accumulating unit, the transfer unit collectively transfers the charge of the light receiving element to the charge accumulating unit, and then the control unit in the order of the row unit as an analysis result of the analyzing unit. Controlling the generation of the selection signal in units of rows in the array, and the selection unit is stored in the charge storage unit in units of rows in the array in the order of the row as an analysis result of the analysis unit A light receiving signal composed of electric charges is amplified by the amplifying means and output.

  A discharge wiring common to the light receiving elements of the unit pixel in the row direction, connection control means for controlling connection between the discharge wiring and the light receiving elements based on a discharge selection signal, and a current amount of the discharge wiring are detected. A current amount detecting means, and the analyzing means can be obtained corresponding to the current amount detected by the current amount detecting means for all pixels in a predetermined frame. Based on the level of the received light signal generated by the light receiving element, the order of the level of the received light signal level in a row unit composed of the pixels in the predetermined frame is analyzed, and the control means includes the analyzing means The generation of the selection signal in the row unit in the predetermined frame is controlled based on the order of the row unit that is the analysis result of the predetermined frame. Can.

  The analyzing means includes a light receiving signal generated by the light receiving element, which is obtained corresponding to the amount of current detected by the current amount detecting means each time the control means generates a selection signal in units of rows. On the basis of the level of the received light signal, it is possible to analyze the order of the level of the received light signal in the row unit in which the generation of the selection signal is not controlled by the control means in the predetermined frame. .

  When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit transfers the charge of the light receiving element to the charge accumulation unit. After the collective transfer, the control means generates the discharge selection signal for the connection control means corresponding to all pixels, and the connection control means connects the discharge wiring and the light receiving element, The discharge wiring and the charge overflow path as the light reception signal accumulated in the light receiving element can be shared.

  The analyzing means includes, for all the pixels in the first frame, the light receiving signal of the row unit composed of the pixels based on the level of the light receiving signal output from the amplifying means and accumulated in the light receiving element. The order of level height is analyzed, and the control means causes the first time frame after the first frame to be based on the order of the row units as the analysis result of the first frame by the analysis means. It is possible to control generation of the selection signal in units of rows in two frames.

  Based on the signal level of the received light signal accumulated in the light receiving element, the analyzing unit analyzes whether the light receiving signal is distributed in the lower side or the upper side in the order of the level of the received light signal level. The control means controls the generation of the selection signal in the row unit by setting the order of the row unit in the upward direction of the row arrangement or the order of the downward direction based on the analysis result by the analysis unit. You can make it.

  The analysis means includes a plurality of row units obtained by dividing the entire row of pixels into 1 / n based on the level of the light reception signal accumulated in the light receiving element, and the order of the level of the light reception signal level. And the control means generates the selection signal in the plurality of line units based on the order of the plurality of line units obtained by dividing all the lines as the analysis result by the analysis means into 1 / n. Can be controlled.

  The control means controls the generation of the reset signal during the generation period of the selection signal in units of rows, and the amplification means causes the charge storage section to be controlled by the selection means based on the selection signal. When the light receiving signal composed of the charges transferred to is amplified and output, the first level of the light receiving signal output by the amplifying unit, and then the reset unit converts the charge accumulated in the charge accumulating unit. When reset by opening, the difference from the second level of the light reception signal output by the amplifying means can be the level of the light reception signal of the pixel.

  In the image sensor, charge as a light reception signal transferred from the charge storage unit is stored, another charge storage unit different from the charge storage unit, and a light reception signal stored from the charge storage unit. Another transfer means different from the transfer means for transferring the charge to another charge storage section, a discharge wiring common to the light receiving element of the unit pixel in the row direction, and the discharge wiring based on a discharge selection signal Connection control means for controlling connection with the light receiving element can be further included, and the reset means releases the charge accumulated in the other charge accumulation portion based on the reset signal. The amplifying unit can amplify a light reception signal composed of the charges transferred to the other charge storage unit.

  The image sensor may have a structure in which a plurality of pixels share one or more of the charge storage unit, the transfer unit, the reset unit, the amplification unit, and the selection unit.

  The solid-state imaging device driving method according to one aspect of the present invention includes a light receiving element that generates and accumulates a charge as a light receiving signal corresponding to received light, and a charge as a light receiving signal transferred by the light receiving element. A charge storage unit for storing the charge, a transfer means for transferring the charge as a light reception signal stored from the light receiving element to the charge storage unit, and releasing the charge stored in the charge storage unit based on a reset signal A reset means for resetting by means of, an amplifying means for amplifying a received light signal composed of charges transferred to the charge storage section, and a selecting means for outputting the received light signal amplified by the amplifying means based on a selection signal. Based on a complementary metal oxide semiconductor (CMOS) image sensor having pixels in the form of an array and a level of a received light signal accumulated in the light receiving element Analyzing means for analyzing the order of the level of the received light signal level in units of rows composed of pixels, and generation of the selection signal in units of rows based on the order of row units as a result of analysis by the analyzing means A solid-state imaging device including a control unit for controlling the light receiving signal in a row unit composed of the plurality of pixels based on a level of a light receiving signal accumulated in the light receiving device in the analyzing unit. An analysis step for analyzing the order of the level of the signal level, and the generation of the selection signal in the row unit are controlled based on the order of the row unit as an analysis result by the processing of the analysis step in the control means. And the transfer means transfers all the charges accumulated in the light receiving element to the charge accumulation section all at once, and the reset means After the resetting of the unit, the light receiving element starts to accumulate charges as a light receiving signal generated according to the received light, and a predetermined accumulation time has elapsed since the charge accumulation by the light receiving element was started. After the reset unit resets the charge storage unit, the transfer unit batch-transfers the charge of the light receiving element to the charge storage unit, and then the process of the control step is an analysis result of the analysis unit. The generation of the selection signal in the row unit of the array-like is controlled in the order of the row unit, and the selection unit is arranged in the order of the row in the order of the row as the analysis result in the processing of the analysis step. A light receiving signal composed of charges accumulated in the charge accumulating unit in a row unit is amplified by the amplifying means and output.

  A discharge wiring common to the light receiving elements of the unit pixel in the row direction, connection control means for controlling connection between the discharge wiring and the light receiving elements based on a discharge selection signal, and a current amount of the discharge wiring are detected. Current amount detecting means can be further included, and the processing of the analyzing step is obtained for all pixels in a predetermined frame corresponding to the current amount detected by the current amount detecting means. Based on the level of the received light signal generated by the light receiving element, the order of the level of the received light signal level in the row unit of the pixels in the predetermined frame is analyzed, and the processing of the control step The selection signal in the row unit in the predetermined frame based on the order of the row unit that is the analysis result of the predetermined frame by the processing in the analysis step It is possible to Yo to control the generation.

  The processing of the analyzing step is generated at the light receiving element, which is obtained corresponding to the amount of current detected by the current amount detecting means each time the selection step is generated by the processing of the control step. Based on the level of the received light signal, the order of the level of the received light signal is analyzed in a row unit in which the generation of the selection signal is not controlled by the control means in the predetermined frame. can do.

  When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit transfers the charge of the light receiving element to the charge accumulation unit. After the batch transfer, the process of the control step generates the discharge selection signal to the connection control means corresponding to all pixels, and the connection control means connects the discharge wiring and the light receiving element. Thus, the discharge wiring and the charge overflow path as the light reception signal accumulated in the light receiving element can be shared.

  In the processing of the analysis step, for all pixels in the first frame, the light reception in units of rows composed of the pixels based on the level of the light reception signal output from the amplification unit and accumulated in the light reception element. The order of signal level height is analyzed, and the control step processing is performed from the first frame on the basis of the order of row units as the analysis result of the first frame by the analysis step processing. It is possible to control generation of the selection signal in units of rows in a second frame that is temporally later.

  Based on the signal level of the received light signal accumulated in the light receiving element, the analyzing unit analyzes whether the light receiving signal is distributed in the lower side or the upper side in the order of the level of the received light signal level. In the process of the control step, the selection signal in the row unit is set based on the analysis result by the process of the analysis step, with the order of the row unit being the order of the upper direction of the row arrangement or the order of the lower direction. Can be controlled.

  In the processing of the analysis step, the level of the level of the light receiving signal in a plurality of rows obtained by dividing all the rows of the pixels into 1 / n based on the level of the light receiving signal accumulated in the light receiving element. In the control step, the processing in the control step is based on the order of the plurality of rows based on the order of the plurality of rows obtained by dividing all the rows as the analysis result by the processing in the analysis step into 1 / n. The generation of the selection signal can be controlled.

  In the process of the control step, the generation of the reset signal is controlled during the generation period of the selection signal in units of rows, and the amplification unit is configured to control the charge by the selection unit based on the selection signal. When a light reception signal composed of charges transferred to the storage unit is amplified and output, the first level of the light reception signal output by the amplification unit and then the reset unit are stored in the charge storage unit. When reset by releasing the charge, the difference from the second level of the light reception signal output by the amplifying means can be the level of the light reception signal of the pixel.

  An electronic device according to one aspect of the present invention includes a light receiving element that generates and accumulates a charge as a light reception signal in response to received light, and a charge that accumulates a charge as a light reception signal transferred by the light reception element. A storage unit, transfer means for transferring a charge as a light reception signal stored by the light receiving element to the charge storage unit, and a reset for releasing the charge stored in the charge storage unit based on a reset signal A pixel having the following units: amplifying means for amplifying the received light signal comprising the charges transferred to the charge storage unit; and a selecting means for outputting the received light signal amplified by the amplifying means based on the selection signal. A CMOS (Complementary Metal Oxide Semiconductor) image sensor having an array and a plurality of pixels based on a level of a received light signal accumulated in the light receiving element Analysis means for analyzing the order of the level of the received light signal level in units, and control for controlling the generation of the selection signal in the row unit based on the order of the row unit as an analysis result by the analysis means And the transfer means transfers all the charges accumulated in the light receiving element to the charge accumulation section all at once, and the reset means resets the charge accumulation section, When the light receiving element starts accumulating charges as a light receiving signal generated according to the received light, and when a predetermined accumulation time has elapsed since the charge accumulating by the light receiving element is started, the reset means After resetting the charge storage unit, the transfer unit collectively transfers the charge of the light receiving element to the charge storage unit, and then the control unit performs the previous operation in the order of the row as the analysis result of the analysis unit. Controlling the generation of a selection signal in units of rows in the array, and the selection unit stores the charges accumulated in the charge storage unit in units of rows in the array in the order of rows that are the analysis results of the analysis unit Is amplified by the amplifying means and output.

  In one aspect of the present invention, charge as a light reception signal is generated and accumulated in response to light received by a light receiving element in a pixel unit of a CMOS (Complementary Metal Oxide Semiconductor) image sensor having an array, Charge as a light receiving signal transferred by the light receiving element is accumulated by the charge accumulating unit, and electric charge as a light receiving signal accumulated from the light receiving element is transferred to the charge accumulating unit by the transferring unit, and by the reset unit, Based on the reset signal, the charge accumulated in the charge accumulating unit is reset by being released, and the amplifying unit amplifies the received light signal composed of the charges transferred to the charge accumulating unit, and the selecting unit selects Based on the signal, the light receiving signal amplified by the amplifying means is output, and the level of the light receiving signal accumulated in the light receiving element is output. The order of the level of the received light signal level in units of rows composed of the plurality of pixels is analyzed, and the selection signal of the selection unit in units of rows is analyzed based on the order of the row units as the analysis result. Control means for controlling the generation, wherein the transfer means transfers all the charges accumulated in the light receiving element to the charge accumulation section in a batch, and the reset means controls the charge accumulation section. After the reset, the light receiving element starts to accumulate charges as a light receiving signal generated according to the received light, and when a predetermined accumulation time has elapsed since the charge accumulation by the light receiving element is started, After the reset unit resets the charge storage unit, the transfer unit collectively transfers the charge of the light receiving element to the charge storage unit, and then the control unit is a row unit that is an analysis result of the analysis unit. of Control the generation of the selection signal in units of rows in the array, and the selection means in the charge storage unit in units of rows in the order of the rows that are the analysis results of the analysis means. The light receiving signal composed of the accumulated electric charges is amplified by the amplifying means and output.

  The image sensor of the present invention may be an independent device or a block that performs drive control processing of the image sensor.

  According to one aspect of the present invention, it is possible to reduce the occurrence of noise when an image is captured by an image sensor.

It is a figure explaining operation | movement of the conventional CMOS image sensor. It is a block diagram which shows the structural example of 1st Embodiment of the CMOS image sensor to which the solid-state image sensor of this invention is applied. FIG. 3 is a circuit diagram illustrating a configuration example of unit pixels in the pixel array section of FIG. 2. 3 is a flowchart illustrating a driving process of the CMOS image sensor of FIG. 3 is a timing chart for explaining a driving process of the CMOS image sensor of FIG. 2. It is a figure explaining the effect by the drive processing of the CMOS image sensor of FIG. It is a block diagram which shows the structural example of 2nd Embodiment of a CMOS image sensor. FIG. 8 is a circuit diagram illustrating a configuration example of unit pixels in the pixel array section of FIG. 7. It is a circuit diagram explaining the structural example of the high-intensity detection part of FIG. It is a flowchart explaining the drive processing of the CMOS image sensor of FIG. It is a timing chart explaining the drive processing of the CMOS image sensor of FIG. It is a figure explaining the effect by the drive processing of the CMOS image sensor of FIG. It is a block diagram which shows the structural example of 3rd Embodiment of a CMOS image sensor. 14 is a flowchart illustrating a driving process of the CMOS image sensor in FIG. 13. 14 is a timing chart for explaining a driving process of the CMOS image sensor of FIG. 13. It is a block diagram which shows the structural example of 4th Embodiment of a CMOS image sensor. It is a circuit diagram explaining the structural example of the unit pixel in the pixel array part of FIG. FIG. 17 is a flowchart illustrating a driving process of the CMOS image sensor in FIG. 16. FIG. 17 is a timing chart illustrating a driving process of the CMOS image sensor in FIG. 16. It is a figure explaining the other structural example of another unit pixel. It is a figure explaining the 1st structural example of another unit pixel. It is a figure explaining the 2nd structural example of another unit pixel. It is a figure explaining the 3rd structural example of another unit pixel. It is a figure explaining the 4th structural example of another unit pixel. It is a figure explaining the 5th structural example of another unit pixel. It is a block diagram explaining the structural example of the electronic device provided with the CMOS image sensor to which the solid-state image sensor of this invention is applied.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. First embodiment (configuration example of a CMOS image sensor using a solid-state image sensor composed of general unit pixels)
2. Second embodiment (configuration example of a solid-state imaging device including a high-luminance detection unit)
3. Third embodiment (a configuration example using a difference between a signal level first read out and a reset level in a solid-state imaging device including a high-luminance detection unit)
4). Fourth Embodiment (a configuration example in which a solid-state imaging device including a high-intensity detection unit uses a difference between a reset level and a read signal level first)
5. Fifth embodiment (other structural example of unit pixel)
6). 6. Sixth Embodiment (Configuration Example of Electronic Device Provided with CMOS Image Sensor Using Solid-State Image Sensor of the Present Invention)

<1. First Embodiment>
[Configuration example of solid-state image sensor]
FIG. 2 is a block diagram showing a configuration example of a CMOS image sensor as a solid-state imaging device to which the present invention is applied.

  The CMOS image sensor 100 includes a pixel array unit 111, a vertical driving unit 112, a column processing unit 113, a horizontal driving unit 114, and a system control unit 115. The pixel array unit 111, the vertical driving unit 112, the column processing unit 113, the horizontal driving unit 114, and the system control unit 115 are formed on a semiconductor substrate (chip) (not shown). The pixel array unit 111 is provided with a constant current source unit 119.

  In the pixel array unit 111, unit pixels having photoelectric conversion elements that generate photoelectric charges having a charge amount corresponding to the amount of incident light (hereinafter sometimes simply referred to as “charge”) as light reception signals and store them in a matrix form a matrix. Are two-dimensionally arranged. In the following, a photocharge having a charge amount corresponding to the amount of incident light may be simply referred to as “charge”, and a unit pixel may be simply referred to as “pixel”.

  In the pixel array unit 111, pixel drive lines 116 are formed for each row in the horizontal direction of the drawing (pixel arrangement direction of the pixel row) with respect to the matrix-like pixel arrangement, and vertical signal lines are provided for each column. 117 is formed along the vertical direction of the drawing (the pixel arrangement direction of the pixel column). In FIG. 2, the pixel drive line 116 is shown as one line, but the number is not limited to one. One end of the pixel drive line 116 is connected to an output end corresponding to each row of the vertical drive unit 112.

  The CMOS image sensor 100 further includes a signal processing unit 118. The signal processing unit 118 may be an external signal processing unit provided on a separate substrate from the CMOS image sensor 100, for example, a DSP (Digital Signal Processor) or software processing, and is mounted on the same substrate as the CMOS image sensor 100. It doesn't matter.

  The vertical drive unit 112 is configured by a shift register, an address decoder, and the like, and is a pixel drive unit that drives each pixel of the pixel array unit 111 at the same time or in units of rows. Although the specific configuration of the vertical driving unit 112 is not illustrated, the vertical driving unit 112 generally has two scanning systems, a reading scanning system and a sweeping scanning system.

  The readout scanning system selectively scans the unit pixels of the pixel array unit 111 sequentially in units of rows in order to read out signals from the unit pixels. The sweep-out scanning system performs sweep-out scanning with respect to the readout row on which readout scanning is performed by the readout scanning system, preceding the readout scanning by a time corresponding to the shutter speed.

  By the sweep scanning by the sweep scanning system, unnecessary charges are swept (reset) from the photoelectric conversion elements of the unit pixels in the readout row. A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the previous read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation time (exposure time) in the unit pixel.

  Pixel signals output from each unit pixel in the pixel row selectively scanned by the vertical driving unit 112 are supplied to the column processing unit 113 through each of the constant current source unit 119 and the vertical signal line 117. The constant current source unit 119 supplies a bias current to each pixel and is arranged in each pixel column. The column processing unit 113 performs predetermined signal processing on the pixel signal (light reception signal) output from each unit pixel in the selected row through the vertical signal line 117 for each pixel column of the pixel array unit 111, and performs signal processing. The subsequent pixel signal is temporarily held.

  Specifically, the column processing unit 113 performs at least noise removal processing, for example, CDS (Correlated Double Sampling) processing as signal processing. By the CDS processing by the column processing unit 113, pixel-specific fixed pattern noise such as reset noise and threshold variation of the amplification transistor is removed. In addition to the noise removal processing, the column processing unit 113 may have, for example, an AD (analog-digital) conversion function and output a signal level as a digital signal.

  The horizontal driving unit 114 includes a shift register, an address decoder, and the like, and sequentially selects unit circuits corresponding to the pixel columns of the column processing unit 113. By the selective scanning by the horizontal driving unit 114, the pixel signals subjected to signal processing by the column processing unit 113 are sequentially output to the signal processing unit 118.

  The system control unit 115 includes a timing generator that generates various timing signals, and drives the vertical driving unit 112, the column processing unit 113, the horizontal driving unit 114, and the like based on the various timing signals generated by the timing generator. Take control. More specifically, the system control unit 115 includes an address list 115a that is updated by the signal processing unit 118, and can execute reading in units of rows in the order of the rows corresponding to the addresses described in the address list 115a. The drive control is performed as follows.

  The signal processing unit 118 includes a level analysis unit 118a, an address list 118b, a data storage unit 118c, and a rearrangement unit 118d. The level analysis unit 118a analyzes the signal level of the read pixel signal in units of rows, obtains an order corresponding to the level of the signal level, and designates an address for designating a row corresponding to the order in the address list 118b. sign up. Furthermore, when the address list 118b is newly registered, the level analysis unit 118a updates the address list 115a of the system control unit 115 with the address list 118b. In addition, the data storage unit 118c temporarily stores signal level information in the order of the read rows in the signal processing in the signal processing unit 118. The rearrangement unit 118d rearranges the signal levels stored in the data storage unit 118c in the original row unit order when reading of all rows is completed. The signal processing unit 118 outputs the pixel signals rearranged in this way.

[Circuit Configuration Example of Unit Pixel of CMOS Image Sensor 100 of FIG. 2]
Next, a circuit configuration example of the unit pixel 120 disposed in the pixel array unit 111 of FIG. 2 will be described with reference to FIG.

  A circuit configuration within a range surrounded by a dotted line in the drawing is a circuit configuration example of the unit pixel 120. The unit pixel 120 includes a photodiode PD, a reset transistor TR_RST, a transfer gate TR_ROG, a selection transistor TR_SEL, and a floating diffusion region FD.

  In the photodiode PD which is a photoelectric conversion element, the anode electrode of the photodiode PD is grounded, and the cathode electrode is connected to the source of the transfer gate TR_ROG made of a transistor. The transfer gate TR_ROG has a drain electrode connected to the anode of the photodiode PD, a source electrode connected to the floating diffusion region (floating diffusion) FD, the gate electrode of the amplification transistor TR_AMP, and the source electrode of the reset transistor TR_RST. Further, the gate electrode of the transfer gate TR_ROG is connected to the transfer pulse line ROG. That is, when the transfer pulse ROG is supplied via the transfer pulse line ROG under the control of the system control unit 115 in FIG. 2, the transfer gate TR_ROG transfers the charge accumulated by photoelectric conversion by the photodiode PD to the floating diffusion region FD. Forward.

  The floating diffusion region FD is photoelectrically converted and accumulated by the photodiode PD, temporarily holds the charge transferred from the transfer gate TR_ROG, and converts the charge into a voltage signal. For this reason, it is represented as a capacitor in FIG.

  The reset transistor TR_RST has a gate electrode connected to the reset pulse line RST, and a source electrode connected to the floating diffusion region FD, a source electrode of the transfer gate TR_ROG, and a gate electrode of the amplification transistor TR_AMP. The reset transistor TR_RST has a drain electrode connected to the power supply VDD and the drain of the amplification transistor TR_AMP. That is, when the reset pulse RST is supplied from the reset pulse line RST under the control of the system control unit 115, the charge in the floating diffusion region FD is released and reset. At this time, when the transfer gate TR_ROG is also turned on by the transfer pulse ROG, the charge accumulated by photoelectric conversion in the photodiode PD is also released from the reset transistor TR_RST via the floating diffusion region FD.

  The amplification transistor TR_AMP has a gate electrode connected to the source electrode of the reset transistor TR_RST, the source electrode of the transfer gate TR_ROG, and the floating diffusion region FD, and a drain electrode connected to the power supply VDD and the drain electrode of the reset transistor TR_RST. ing. The amplification transistor TR_AMP has a source electrode connected to the source electrode of the selection transistor TR_SEL. The amplification transistor TR_AMP amplifies a light reception signal which is a charging voltage of the floating diffusion region FD applied to the gate and outputs the amplified light reception signal from the source electrode.

  The selection transistor TR_SEL has a gate electrode connected to the selection pulse line SEL, a drain electrode connected to the source electrode of the amplification transistor TR_AMP, and a source electrode connected to the vertical signal line VSL. Therefore, when the selection pulse SEL is supplied from the selection pulse line SEL under the control of the system control unit 115, the selection transistor TR_SEL amplifies the light reception signal that is the voltage of the floating diffusion region FD output from the drain of the amplification transistor TR_AMP. The signal is output from the vertical signal line VSL. The vertical signal line VSL is provided with a constant current source I, and the value of the current flowing through the vertical signal line VSL is made constant. The constant current source I constitutes the constant current source unit 119 in FIG.

[Driving Process of CMOS Image Sensor 100 of FIG. 2]
Next, the driving process of the CMOS image sensor 100 of FIG. 2 will be described with reference to the flowchart of FIG. 4 and the timing chart of FIG. In FIG. 5, from the top to the third stage, the reset pulse RST, the transfer pulse ROG, and the selection pulse SEL for the pixels in the (n−1) th to (n + 1) th rows of the pixel array unit 111, respectively. The timing of occurrence is shown. In addition, at the lowermost stage, the generation timing of the sample hold timing pulse SHS is shown.

  In step S11, the system control unit 115 performs reset pulse RST and transfer pulse ROG on the reset pulse line RST and transfer pulse line ROG of all pixels, for example, as shown at times t1 to t2 in FIG. Is generated. That is, by this processing, so-called global reset is performed in which the photodiode PD is simultaneously reset for all the pixels.

  In step S12, all the photodiodes PD start to accumulate charges as light reception signals generated by photoelectric conversion by receiving light. That is, as shown in FIG. 5, at the time t2, since all the photodiodes PD are reset, it is the start timing of the exposure period.

  In step S13, the system control unit 115 generates a reset pulse RST for the reset pulse lines RST of all the pixels when a predetermined exposure period has elapsed, for example, as indicated by times t3 to t4 in FIG. Let

  In step S14, the system control unit 115 performs the transfer pulse ROG with respect to the transfer pulse line ROG of all pixels, as shown at the timing immediately after the reset pulse RST, that is, for example, at times t5 to t6 in FIG. Is generated.

  As a result, the transfer gate TR_ROG is turned on by the transfer pulse ROG, so that the charge as the light reception signal accumulated in the photodiode PD during the exposure period is transferred to the floating diffusion region FD. That is, so-called global transfer is performed.

  In step S15, the system control unit 115 reads the information in the address list 115a and reads the priority information in units of rows recorded in the address list 115a. In the first process, the priority information for each row recorded in the address list 115a is not determined in accordance with the level of the received light signal described later. For this reason, since the information on the order to be recorded in the address list 115a is unknown or inaccurate at this time, the order of simple line numbers in the upward or downward direction is recorded as an initial setting. Has been.

  In step S16, the system control unit 115 recognizes the unprocessed uppermost row as a processing target row based on the order of the row numbers in the address list 115a, and selects a selection pulse for pixels in the processing target row. A selection pulse SEL is generated from the line SEL. For example, when the nth row is a processing target row, the selection pulse SEL is generated from time t11 to t15 as shown in FIG. As a result, the vertical signal line VSL becomes effective, and charges as a light reception signal are transferred from the floating diffusion region FD. At the same time, the system control unit 115 generates a sample hold timing pulse SHS for the column processing unit 113. That is, when the processing target row is the n-th row, the sample hold timing pulse SHS is generated within the generation period of the selection pulse SEL, such as time t12 to t13.

  In step S17, the column processing unit 113 reads the light reception signal supplied from the vertical signal line VSL in response to the sample hold timing pulse SHS, and sequentially receives the light reception signal at the timing selected by the horizontal drive unit 114. 118. Then, the signal processing unit 118 stores the signal level information of the read light reception signal in the data storage unit 118c in association with the address designating the read row. That is, in the nth row in FIG. 5, the light reception signals of the pixels in the nth row are read out in the rectangular range indicated by the dotted line.

  In step S18, the system control unit 115 generates a reset pulse RST on the reset pulse line RST of the pixel in the processing target row. For example, when the processing target row is the nth row, the reset pulse RST is generated at times t14 to t15 which are the final timing of the generation period of the selection pulse SEL. By this processing, the floating diffusion region FD of the pixel in the processing target row is reset.

  In step S19, the system control unit 115 determines whether there is a row that has not been read out of the row order stored in the address list 115a. For example, if there is an unprocessed line, the process returns to step S16. That is, the processes of steps S16 to S19 are repeated until the light reception signals of the pixels in all the rows are read, and the signal levels of the light reception signals of the pixels are sequentially stored in the data storage unit 118c.

  When it is determined in step S19 that the light reception signals of the pixels in all rows have been read, in step S20, the rearrangement unit 118d reads the information on the light reception signals of each pixel stored in the data storage unit 118c. The images are rearranged in the upward or downward direction so as to be in the order of the original row numbers for display, and are configured and output as one image signal.

  In step S21, the level analysis unit 118a analyzes the signal level of the received light signal stored in the data storage unit 118c in units of rows. Then, the level analysis unit 118a obtains ranks in descending order of the signal level of the received light signal in units of rows, and registers addresses corresponding to the order of row units corresponding to the ranks in the address list 118b.

  In step S22, the level analysis unit 118a updates the address list 115a of the system control unit 115 by replacing it with the address list 118b.

  In step S23, the signal processing unit 118 determines whether or not the end of the driving operation of the solid-state imaging device is instructed. For example, when the end is instructed, the process ends and the end is not instructed. The process returns to step S11.

  That is, in the subsequent processing, the address list 115a is sequentially updated every time the processing of steps S11 to S22 is repeated. That is, in the address list 115a, addresses for specifying the rows in the order of the rows obtained corresponding to the signal level of the light reception signal in the row units of the image processed immediately before are recorded. As a result, the order sequentially read in steps S16 to S19 is read in the order of the higher signal level obtained based on the signal level of the received light signal for each row of the image processed immediately before.

  Therefore, for example, when the order of the signal level in the row unit is the nth row, the (n−1) th row, and the (n + 1) th row from the top, as shown in FIG. The n rows of selection pulses SEL are generated from time t11 to t15. Meanwhile, at time t12 to t13, a sample hold timing pulse SHS is generated, and at this timing, the received light signal supplied to the vertical signal line 117 in the nth row is read out by the column processing unit 113. Further, a reset pulse RST is generated from time t14 to t15, and the floating diffusion region FD in the nth row is reset by releasing the accumulated light reception signal.

  When the processing of the nth row is completed, the processing of the (n−1) th row is performed, and therefore the selection pulse SEL of the (n−1) th row is generated from time t16 to t20. Meanwhile, at time t17 to t18, a sample hold timing pulse SHS is generated, and at this timing, the received light signal supplied to the vertical signal line 117 of the (n−1) th row is read out by the column processing unit 113. It is. From time t19 to t20, a reset pulse RST is generated, and the floating diffusion region FD in the (n−1) th row is reset by discharging the accumulated light reception signal.

  Further, when the processing of the (n−1) -th row is completed, the processing of the (n + 1) -th row is performed, so that the selection pulse SEL for the (n + 1) -th row is generated from time t21 to t25. In the meantime, at time t22 to t23, a sample hold timing pulse SHS is generated, and at this timing, the received light signal supplied to the vertical signal line 117 in the (n + 1) th row is read out by the column processing unit 113. From time t24 to t25, a reset pulse RST is generated, and the floating diffusion region FD in the (n + 1) th row is reset by discharging the accumulated light reception signal.

  That is, when reading is simply performed in the order of the rows, as shown in the left part of FIG. 6, the accumulation time becomes longer as the floating diffusion region FD of the pixel whose reading order is postponed. Increases in proportion to Since the leak component of the floating diffusion region FD increases as the signal level of the pixel increases, the influence increases as the accumulation time increases.

  However, by the processing as described above, as shown in the right part of FIG. 6, reading is performed in the order set by the signal level in units of rows in the immediately preceding image. For this reason, it becomes possible to read out pixels with higher signal levels, in which the leakage component of the floating diffusion region FD greatly affects the accumulation time, in an earlier order. As a result, it becomes possible to reduce the influence of the leak component of the floating diffusion region FD. In FIG. 6, in both the left part and the right part, the black band from the top is the charge amount of the leak component in units of rows, and the white band is the signal level of the received light signal. In the right part of FIG. 6, an example is shown in which the ranking is the (n−1) th row, the nth row, and the (n + 1) th row from the top.

  Further, in the above processing, the order of the row unit in the immediately preceding image is used instead of the order of the row unit of the image from which the signal level of each pixel is to be read out. It is assumed that there is no significant change in the image. Therefore, at the moment of switching to a completely different image or when reading is started for the first time, as described above, it may be read in the order of simple lines in the upward or downward direction as in the prior art.

  Further, in the above processing, the order of the row unit has been described with respect to an example in which the signal levels of all the pixels are read out, but the range is determined at the timing when only the signal levels of pixels in a predetermined number of rows are read out. You may make it obtain | require the order of the line unit in. Further, when the total number of rows in the pixel array unit 111 is N rows, the signal level order is obtained for each predetermined plurality of rows obtained by dividing by an arbitrary m, and the processing is performed in units of a plurality of rows. It may be.

<2. Second Embodiment>
[Configuration example of other solid-state image sensor]
In the above, the order of the row unit obtained by the signal level of the light reception signal in the image processed immediately before the image to be processed is used, but the order of the row unit of the image to be processed is used. You may make it use for.

  FIG. 7 shows a configuration example of a CMOS image sensor 100 that is a solid-state imaging device that is used by obtaining the order of the row unit of the image to be processed. In addition, about the structure similar to FIG. 2, the same great general and the code | symbol are attached | subjected, and the description shall be abbreviate | omitted suitably.

  That is, the CMOS image sensor 100 of FIG. 7 differs from the CMOS image sensor 100 of FIG. 2 in that the circuit configuration of each pixel of the pixel array unit 111, the system control unit 115, and the signal processing unit 118 are The system control unit 115 ′ and the signal processing unit 118 ′ are provided. The circuit configuration of each pixel will be described later in detail with reference to FIG.

  The system control unit 115 ′ is basically the same as the system control unit 115, but further controls the generation of the discharge pulse OFG via the discharge pulse line OFG. Note that the system control unit 115 'includes an address list 115a that is updated based on the address list 118b of the signal processing unit 118', as in FIG.

  The signal processing unit 118 'includes a level analysis unit 118a' instead of the level analysis unit 118a, and a new high luminance detection unit 118e. The level analysis unit 118a ′ basically has the same function as the level analysis unit 118a, but the target is the signal level of the light reception signal of each photodiode PD detected by the high luminance detection unit 118e. Based on the signal level, the order of those row units is obtained and stored in the address list 118b. The configuration of the high luminance detection unit 118e is related to the configuration of each pixel, and will be described later with reference to FIG. 9 after describing an example of the circuit configuration of the unit pixel in FIG.

[Circuit Configuration Example of Unit Pixel of CMOS Image Sensor 100 of FIG. 7]
Next, a circuit configuration example of the unit pixel 120 disposed in the pixel array unit 111 of FIG. 7 will be described with reference to FIG. In addition, about the structure provided with the same function as the structure of FIG. 3, the same name and the same code | symbol are attached | subjected, and the description shall be abbreviate | omitted suitably.

  The circuit configuration of FIG. 8 is different from the circuit configuration of FIG. 3 in that a discharge transistor TR_OFG, a discharge pulse line OFG, and a discharge drain line OFD are provided.

  The discharge transistor TR_OFG has a gate electrode connected to the discharge pulse line OFG, a source electrode connected to the cathode of the photodiode PD and a source electrode of the transfer gate TR_ROG, and a drain electrode connected to the discharge drain line OFD. .

  During the accumulation of the photodiode PD, the system control unit 115 ′ generates the discharge pulse OFG at a low level (GND level) via the discharge pulse line OFG so as not to affect the operation of the photodiode PD, and generates the discharge transistor TR_OFG. The gate electrode is turned off. Further, after the transfer pulse ROG is generated for all the pixels and the charge as the light reception signal of the photodiode PD is collectively transferred to the floating diffusion region FD by the transfer gate TR_ROG, the system control unit 115 ′ Is generated by setting the discharge pulse OFG to the high level via the discharge pulse line OFG, turning on the discharge transistor TR_OFG, connecting the photodiode PD and the discharge drain line OFD, and remaining in the photodiode PD. To discharge the charge. The discharge drain line OFD is connected to the high luminance detection unit 118e.

  Here, the high luminance detection unit 118e will be described. For example, as illustrated in the upper part of FIG. 9, the high luminance detection unit 118e includes a resistor Rsense, a differential amplifier circuit AM, and a power supply VDD. The high luminance detection unit 118e reads the output voltage of the differential amplifier circuit AM as the current value of the discharge drain line OFD.

  More specifically, when the discharge transistor TR_OFG is turned on, the charge of the light reception signal generated by the photoelectric conversion by the photodiode PD flows down to the discharge drain line OFD provided in units of rows, and the resistance from the power supply VDD A current corresponding to the amount of light received by the photodiode PD flows through Rsense. For this reason, since a voltage corresponding to the amount of current is generated at both ends of the resistor Rsense, the differential amplifier circuit AM amplifies and outputs this voltage. Therefore, the high luminance detection unit 118e detects the signal level in units of rows by measuring the amount of current Iout flowing through the resistor Rsense based on the output voltage of the differential amplifier circuit AM.

  Note that the high luminance detection unit 118e not only detects the signal level of a single row unit from the current amount of the drain / drain line OFD of a single row, but also, for example, as shown in the lower part of FIG. It is also possible to obtain a signal level for the drain drain lines OFD1 to 4 in a plurality of rows at once.

[Driving process of CMOS image sensor in FIG. 7]
Next, a driving process by the CMOS image sensor 100 of FIG. 7 will be described with reference to a flowchart of FIG. 10 and a timing chart of FIG. In FIG. 11, from the top to the third stage, the reset pulse RST, the transfer pulse ROG, the discharge pulse OFG, the pixels in the (n−1) th to (n + 1) th rows of the pixel array unit 111, respectively. The generation timing of the selection pulse SEL is also shown. In addition, at the lowermost stage, the generation timing of the sample hold timing pulse SHS is shown. Furthermore, the processing of steps S42 to S44 in FIG. 10 is the same as the processing of steps S12 to S14 described with reference to FIG.

  That is, in step S41, the system control unit 115 ′, for example, as shown at times t101 to t102 in FIG. 11, applies the reset pulse RST and transfer pulse to the reset pulse line and transfer pulse line of all pixels. Generate ROG. By this processing, so-called global reset is performed. At the same time, the system control unit 115 ′ generates the discharge pulse OFG at the low level (GND level) for the discharge pulse line OFG of all the pixels, as indicated by times t 101 to t 107.

  As a result, the discharge transistor TR_OFG is turned off, so that it has substantially the same configuration as that of the unit pixel in FIG. 3. In step S42, charge accumulation is performed by photoelectric conversion in the photodiode PD according to light reception. Is started. In step S43, the system control unit 115 'generates a reset pulse RST from time t103 to t104 to reset the charge in the floating diffusion region FD. In step S44, the system control unit 115 'generates a transfer pulse ROG from time t105 to t106 to transfer the charge of the photodiode PD to the floating diffusion region FD. By this processing, so-called global transfer is performed.

  In step S45, the system control unit 115 'generates the discharge pulse OFG at a high level for the discharge pulse line OFG of all the pixels as indicated at time t107. By this processing, the discharge transistors TR_OFG of all the pixels are turned on, the cathode of the photodiode PD is connected to the discharge drain line OFD, and the charge accumulated in the photodiode PD is released to the discharge drain line OFD.

  In step S46, the high-intensity detection unit 118e of the signal processing unit 118 ′, for example, converts the current values of the discharge drain lines OFD of all the pixels at the time T in FIG. 11 into the differential amplifier circuit AM as shown in FIG. Further, it is read out as a signal level of a voltage value and stored as signal level information in units of rows. That is, as indicated by time T, at the timing when the period of global reset and global transfer at time t101 to t107 has passed and no readout is performed from any pixel, The light reception level of the pixel is detected.

  In step S47, the level analysis unit 118a ′ obtains the signal level of the voltage value corresponding to the current value of the discharge drain line OFD in units of rows detected by the high luminance detection unit 118e in descending order, and stores it in the address list 118b. sign up.

  In step S48, the level analysis unit 118a 'updates the address list 115a of the system control unit 115' by replacing it with the address list 118b. That is, here, in the address list 115a of the system control unit 115 ', the order of the row units based on the signal level received by each pixel from which charges are to be read will be registered.

  In step S49, the system control unit 115 'reads the information in the address list 115a' and reads the information on the rank of each row recorded in the address list 115a '.

  In step S50, the system control unit 115 ′ recognizes the unprocessed uppermost row as a processing target row based on the order of the row numbers in the address list 115a ′, and for the pixels of the processing target row, A selection pulse SEL is generated from the selection pulse line SEL. For example, when the nth row is a processing target row, a selection pulse SEL is generated at times t111 to t115 as shown in FIG. As a result, the vertical signal line VSL of the pixel in the n-th row becomes effective, and the received light signal is amplified and transferred from the floating diffusion region FD. At the same time, the system control unit 115 ′ generates a sample hold timing pulse SHS for the column processing unit 113. That is, when the processing target row is the n-th row, the sample hold timing pulse SHS is generated within the generation period of the selection pulse SEL such as time t112 to t113. In response to the sample hold timing pulse SHS, the column processing unit 113 reads the received light signal supplied from the vertical signal line VSL, and sequentially supplies the received light signal to the signal processing unit 118 ′ at the timing selected by the horizontal drive unit 114. To do. That is, in the nth row in FIG. 11, the light reception signals of the pixels in the nth row are read out in the rectangular range indicated by the dotted line.

  In step S51, the signal processing unit 118 'stores information on the signal level of the read light reception signal in the data storage unit 118c.

  In step S52, the system control unit 115 'generates a reset pulse RST on the reset pulse line RST of the pixel in the processing target row. For example, when the processing target row is the nth row, the reset pulse RST is generated at times t114 to t115 that are the final timing of the generation period of the selection pulse SEL. By this processing, the floating diffusion region FD of the pixel in the processing target row is reset by discharging the accumulated pixel of the received light signal.

  In step S <b> 53, the system control unit 115 ′ determines whether or not there is a row that has not been read out of the row order stored in the address list 115 a ′. For example, if there is an unprocessed line, the process returns to step S50. That is, the processes of steps S50 to S53 are repeated until the light reception signals of the pixels in all rows are read, and the signal levels of the light reception signals of the pixels are sequentially stored in the data storage unit 118c.

  If it is determined in step S53 that the light reception signals of the pixels in all rows have been read, in step S54, the rearrangement unit 118d reads the signal level information of each pixel stored in the data storage unit 118c. The order of the rows thus arranged is rearranged upward or downward to form a single image signal and output.

  In step S55, the signal processing unit 118 ′ determines whether or not the end of the driving operation of the solid-state imaging device is instructed. For example, when the end is instructed, the processing ends and the end is not instructed. If so, the process returns to step S41.

  That is, in step S49, the address list 115a ′ is in a state in which the rank of the row unit corresponding to the signal level of each pixel in the image to be processed is recorded, so the order of reading sequentially in steps S50 to S53 is as follows. Then, the signals are read in the order of the high signal level obtained based on the signal level in units of rows of the image to be processed.

  Therefore, for example, when the order of the signal level in the row unit is the nth row, the (n−1) th row, and the (n + 1) th row from the top, as shown in FIG. The n rows of selection pulses SEL are generated from time t111 to t115. Meanwhile, at time t112 to t113, a sample hold timing pulse SHS is generated, and at this timing, the received light signal supplied to the vertical signal line 117 of the nth row is read out by the column processing unit 113. Furthermore, a reset pulse RST is generated from time t114 to t115, and the floating diffusion region FD in the nth row is reset by releasing the accumulated light reception signal.

  When the processing of the nth row is completed, the processing of the (n−1) th row is performed, and therefore the selection pulse SEL of the (n−1) th row is generated from time t116 to t120. Meanwhile, at time t117 to t118, a sample hold timing pulse SHS is generated, and at this timing, the received light signal supplied to the vertical signal line 117 of the (n-1) th row is read out by the column processing unit 113. It is. Further, a reset pulse RST is generated from time t119 to t120, and the floating diffusion region FD in the (n−1) th row is reset by releasing the accumulated light reception signal.

  Further, when the processing of the (n−1) th row is completed, the processing of the (n + 1) th row is performed, so that the selection pulse SEL of the (n + 1) th row is generated from time t121 to t125. In the meantime, at time t122 to t123, a sample hold timing pulse SHS is generated. At this timing, the received light signal supplied to the vertical signal line 117 of the (n + 1) th row is read out by the column processing unit 113. Further, a reset pulse RST is generated from time t124 to t125, and the floating diffusion region FD in the (n−1) th row is reset by releasing the accumulated light reception signal.

  Through the processing as described above, as shown in the left part of FIG. 12, among the pixels to be read out in the image to be processed, as shown by the white band, the light reception level is high, that is, the signal As shown in the right part of FIG. 12, the high-level rows are read in the order set by the signal level in units of rows. For this reason, it becomes possible to read out pixels with higher signal levels, in which the leakage component of the floating diffusion region FD greatly affects the accumulation time, in an earlier order. As a result, it is possible to reduce the influence of the leak component of the floating diffusion region FD. Furthermore, the readout order can be set based on the order of the signal level in units of rows in the processing target image from which charges are to be read out, so the order of rows in units of high light reception level can be set with relatively high accuracy. It becomes possible to do. In addition, it is possible to read out from the first processed image in the order of rows in accordance with the signal level.

  Further, in the above processing, the order of the row unit in the immediately preceding image is used instead of the order of the row unit of the image from which the signal level of each pixel is to be read out. It is assumed that there is no significant change in the image. Therefore, at the moment of switching to a completely different image or when reading is started for the first time, as described above, it may be read in the order of simple lines in the upward or downward direction as in the prior art.

  Further, in the above processing, the order of the row unit has been described with respect to an example in which the signal levels of all the pixels are read out, but the range is determined at the timing when only the signal levels of pixels in a predetermined number of rows are read out. You may make it obtain | require the order of the line unit in. Further, based on the analysis result, when pixels with a high level of the received light signal are concentrated on the upper part of the image, the signal level may be sequentially read out in units of rows from the upper row to the lower row. Good. Similarly, when pixels with a high level of light reception signal are concentrated in the lower part of the image, the signal level may be read out in units of rows sequentially from the lower row to the upper row.

<3. Third Embodiment>
[Configuration example of other solid-state image sensor]
In the above description, the example in which the light reception signal read based on the charge transferred from the floating diffusion region FD is used as it is as the signal level of the pixel has been described. However, after reading the light reception signal indicating the signal level, the reset level is obtained. The light reception signal may be read out and the difference between them may be used as a signal level.

  FIG. 13 shows a configuration of a CMOS image sensor 100 using a solid-state imaging device in which a light reception signal at a signal level of an image to be processed is read out, a light reception signal at a reset level is read out, and a difference between them is set as a signal level. An example is shown. In FIG. 13, components having the same functions as those of the CMOS image sensor 100 of FIG. 7 are given the same names and the same reference numerals, and description thereof will be omitted as appropriate.

  That is, the CMOS image sensor 100 of FIG. 13 is different from the CMOS image sensor 100 of FIG. 7 in that the column processing unit 113 ′ and the system control unit 115 ′ are replaced with the column processing unit 113 and the system control unit 115 ′. It is a point with '.

  The column processing unit 113 ′ stores the read light reception signal and the reset light reception signal, obtains a difference between them, and supplies the signal level to the signal processing unit 118 ′.

  The system control unit 115 ″ has the same basic function as the system control unit 115 ′, but also maintains a high level state at the timing after the utterance period of the reset pulse during the readout period. And lengthen the generation period. Furthermore, the system control unit 115 ″ generates a sample hold timing pulse SHN for reading the reset level in addition to the sample hold timing pulse SHS for reading the signal level. Note that the configuration of the unit pixel is the same as that of FIG.

[Driving Process of CMOS Image Sensor 100 of FIG. 13]
Next, the driving process of the CMOS image sensor 100 of FIG. 13 will be described with reference to the flowchart of FIG. 14 and the timing chart of FIG. In the lowermost part of FIG. 15, the generation timing of the sample hold timing pulse SHN is shown in addition to the sample hold timing pulse SHS shown in FIG. Further, the processes in steps S71 to S79, S87, and S88 in FIG. 14 are the same as the processes in steps S41 to S49, S54, and S55 described with reference to FIG.

  That is, in step S79, when the information in the address list 115a ′ is read by the system control unit 115 ′ and the priority information in units of rows recorded in the address list 115a ′ is read, the process proceeds to step S80. .

  In step S80, the system control unit 115 '' recognizes the unprocessed uppermost row as a processing target row based on the order of the row numbers in the address list 115a ', and performs processing on the pixels of the processing target row. The selection pulse SEL is generated from the selection pulse line SEL. For example, when the nth row is a processing target row, the selection pulse SEL is generated from time t111 to t153 as shown in FIG. As a result, the vertical signal line VSL becomes effective and charges as a light reception signal are transferred from the floating diffusion region FD. At the same time, the system control unit 115 ″ generates a sample hold timing pulse SHS for the column processing unit 113 ′. That is, when the processing target row is the n-th row, the sample hold timing pulse SHS is generated within the generation period of the selection pulse SEL such as time t112 to t113.

  In step S81, in response to the sample hold timing pulse SHS, the column processing unit 113 'stores the received light signal read out through the vertical signal line 117 (VSL) as signal level information. That is, in the case of the unit pixel in the nth row, the light reception signal at the signal level is read out at a timing in the vicinity of time t112 to t113 indicated by the dotted line in FIG.

  In step S82, the system control unit 115 'generates a reset pulse RST on the reset pulse line of the pixel in the processing target row. That is, for example, when the processing target row is the n-th row, the reset pulse RST is generated at times t114 to t115 that are the final timing of the generation period of the selection pulse SEL. By this processing, the floating diffusion region FD of the pixel in the processing target row is reset.

  In step S83, the system control unit 115 '' generates a sample hold timing pulse SHN for the column processing unit 113 as shown in FIG. That is, when the processing target row is the n-th row, the sample hold timing pulse SHN is generated within the generation period of the selection pulse SEL such as the times t151 to t152.

  In step S84, the column processing unit 113 'stores the received light signal supplied from the vertical signal line 117 (VSL) as reset level information by the sample hold timing pulse SHN. That is, in the case of the unit pixel in the nth row, the light reception signal at the reset level is read out at a timing in the vicinity of time t151 to t152 indicated by the dotted line in FIG.

  In step S85, the column processing unit 113 ′ obtains a difference by subtracting the value of the light reception signal at the reset level from the light reception signal at the stored signal level, and the obtained difference is a signal of each pixel in the corresponding row. As a level, the received light signals are sequentially supplied to the signal processing unit 118 ′ at the timing selected by the horizontal drive unit 114.

  In step S <b> 86, the system control unit 115 ″ determines whether there is a row that has not been read out of the order of the rows stored in the address list 115 a. For example, if there is an unprocessed line, the process returns to step S80. That is, the light reception signals of the light reception levels and reset levels of the pixels in all rows are read out, and the processing of steps S80 to S86 is repeated until the difference is stored as the signal level, and sequentially stored in the data storage unit 118c. The signal level of the light reception signal of the pixel is stored.

  If it is determined in step S86 that the light reception signals of the pixels in all rows have been read, the process proceeds to step S87.

  That is, since the address list 115a records the rank of each row in accordance with the signal level of each pixel in the image to be processed, the order of reading sequentially in steps S80 to S86 is the image to be processed. Are read in the order of the higher signal level obtained based on the signal level in units of rows. Furthermore, since the signal level is the difference between the read signal level and the reset level, the influence of the charges that cannot be released from the discharge transistor TR_OFG is reduced in the floating diffusion region FD, and the signal level is more accurately detected. Can be measured.

  Therefore, for example, when the order of the signal level in the row unit is the nth row, the (n−1) th row, and the (n + 1) th row from the top, as shown in FIG. The n rows of selection pulses SEL are generated from time t111 to t153. Meanwhile, a sample hold timing pulse SHS is generated from time t112 to t113, and a reset pulse RST is generated from time t114 to t115, so that the signal level of each pixel in the nth row is read. Further, from time t151 to t152, a sample hold timing pulse SHN is generated, and the reset level of each pixel in the nth row is read out.

  When the processing of the nth row is completed, the processing of the (n−1) th row is performed, and therefore the selection pulse SEL of the (n−1) th row is generated from time t116 to t156. Meanwhile, a sample hold timing pulse SHS is generated from time t117 to t118, a reset pulse RST is generated from time t119 to t120, and the signal level of each pixel in the (n−1) th row is read. Further, from time t154 to t155, a sample hold timing pulse SHN is generated, and the reset level of each pixel in the (n−1) th row is read out.

  Further, when the processing of the (n−1) -th row is completed, the processing of the (n + 1) -th row is performed, so that the selection pulse SEL for the (n + 1) -th row is generated from time t121 to t159. In the meantime, a sample hold timing pulse SHS is generated from time t122 to t123, a reset pulse RST is generated from time t124 to t125, and the signal level of each pixel in the (n + 1) th row is read. Further, from time t157 to t158, a sample hold timing pulse SHN is generated, and the reset level of each pixel in the (n + 1) th row is read out.

  In other words, with the above processing, the difference between the read signal level, the read reset level, and the received light signal is treated as a normal signal level, so the signal level can be read with higher accuracy. It becomes. Also in this case, the pixels are read in order from the pixel having the higher light reception level, that is, the signal level of the pixel in which the leakage component noise is more likely to occur as the accumulation period of the floating diffusion region FD is higher. Generation of noise can be reduced.

<4. Fourth Embodiment>
[Configuration example of other solid-state image sensor]
In the above description, the example in which the signal level read based on the charge transferred from the floating diffusion region FD is read first and then the reset level is read is described. However, the floating diffusion before the charge is transferred is described. The signal level in the region FD may be read as the reset level, and then the signal level may be read.

  FIG. 16 shows a configuration example of the CMOS image sensor 100 in which the reset level of the image to be processed is read, the signal level is read, and the difference is set as the signal level. In FIG. 16, configurations having the same functions as those of the CMOS image sensor 100 of FIG. 13 are denoted by the same names and the same reference numerals, and description thereof will be omitted as appropriate.

  That is, the CMOS image sensor 100 of FIG. 16 differs from the CMOS image sensor 100 of FIG. 13 in that the unit pixel configuration of the pixel array unit 111 and the system control unit 115 ′ are replaced with the system control unit 115 ″. It is a point with ''.

  The system control unit 115 ′ ″ has the same basic function as the system control unit 115 ″, but further supplies a second transfer gate that is newly added to the unit pixel configuration described later. Two transfer pulses TRG are generated.

[Circuit Configuration Example of Unit Pixel of CMOS Image Sensor 100 in FIG. 16]
Next, a circuit configuration example of the unit pixel 120 disposed in the pixel array unit 111 in FIG. 16 will be described with reference to FIG. In addition, about the structure provided with the same function as the structure of FIG. 8, the same name and the same code | symbol are attached | subjected, and the description shall be abbreviate | omitted suitably.

  In other words, the circuit configuration example of the unit pixel 120 in FIG. 17 is different from the circuit configuration example of the unit pixel in FIG. 8 in that the second transfer gate TR_TRG and the gate of the transfer gate TR_TRG are new. The second transfer pulse line TRG for generating the transfer pulse TRG is provided, and the second floating diffusion region FD2 is provided between the first transfer gate and the transfer gate TR_ROG. It is. In FIG. 17, the transfer gate TR_ROG and the floating diffusion region FD in FIG. 8 are referred to as a first transfer gate TR_ROG and a first floating diffusion region FD1, respectively.

[Driving Process of CMOS Image Sensor 100 of FIG. 16]
Next, with reference to the flowchart of FIG. 18 and the timing chart of FIG. 19, the driving process of the CMOS image sensor 100 of FIG. 16 will be described. In FIG. 19, from the top to the third stage, the reset pulse RST, the second transfer pulse ROG, and the second transfer pulse ROG for the pixels in the (n−1) th to (n + 1) th rows of the pixel array unit 111, respectively. The timing of generating one transfer pulse ROG, discharge pulse OFG, and selection pulse SEL is shown. In addition, at the lowest stage, generation timings of the sample hold timing pulses SHN and SHS are shown. It should be noted that the display positions of the sample hold timing pulses SHN and SHS in FIG. 18 are upside down from the sample hold timing pulses SHS and SHN in FIG.

  That is, in step S101, the system control unit 115 ′ ″ performs the reset pulse line for all the pixels and the first and second transfer pulse lines as shown at times t101 to t102 in FIG. 19, for example. A reset pulse RST, a first transfer pulse ROG, and a second transfer pulse TRG are generated. By this processing, so-called global reset is performed. At the same time, the system control unit 115 ″ ″ generates the discharge pulse OFG at a low level (GND level) for the discharge pulse line OFG of all pixels, as indicated by times t 101 to t 107.

  As a result, the discharge transistor TR_OFG is turned off, and in step S102, charge accumulation is started by photoelectric conversion in the photodiode PD in response to light reception. That is, the exposure period is started.

  In step S103, the system control unit 115 '' '' generates the reset pulse RST and the first transfer pulse ROG from time t103 to t104 to reset the charge in the floating diffusion region FD1. That is, the exposure period ends.

  In step S <b> 104, the system control unit 115 ″ ″ generates the second transfer pulse TRG from time t <b> 105 to t <b> 106 to transfer the charge of the photodiode PD to the floating diffusion region FD <b> 2. That is, global transfer is performed.

  In step S <b> 105, the system control unit 115 ″ ″ generates the discharge pulse OFG at a high level for the discharge pulse line OFG of all pixels, as indicated at time t <b> 107. With this process, the discharge transistors TR_OFG of all the pixels are turned on, the cathode of the photodiode PD is connected to the discharge drain line OFD, and the charge accumulated in the photodiode PD is released from the discharge drain line OFD.

  In step S106, the high-intensity detection unit 118e of the signal processing unit 118 ′, for example, converts the current values of the drain drain lines OFD of all the pixels at the time T in FIG. 19 into the differential amplifier circuit AM as shown in FIG. As a signal level of the voltage value, it is read and stored as row unit information. That is, as indicated by time T, at the timing when the period of global reset and global transfer at time t101 to t107 has elapsed and no readout is performed from any pixel, the high luminance detection unit 118e ′ The light reception level of each pixel is detected.

  In step S107, the level analysis unit 118a ′ obtains the signal level of the voltage value corresponding to the current value of the drain drain line OFD in units of rows stored in the high luminance detection unit 118e in descending order, and stores it in the address list 118b. sign up.

  In step S108, the signal processing unit 118 'updates the address list 115a of the system control unit 115 "" by replacing it with the address list 118b'. That is, here, in the address list 115a of the system control unit 115 ′ ″, the order of the row unit based on the signal level received by each pixel from which charges are to be read is registered. Become.

  In step S <b> 109, the system control unit 115 ″ ″ reads out the information in the address list 115 a and reads out the priority information in units of rows recorded in the address list 115 a.

  In step S110, the system control unit 115 ′ ″ recognizes the unprocessed uppermost row as the processing target row based on the order of the row unit of the address list 115a, and performs processing on the pixels of the processing target row. The selection pulse SEL is generated from the selection pulse line. For example, when the n-th row is a processing target row, the system control unit 115 ″ ″ generates a reset pulse RST from time t111 to t171 as shown in FIG. By this process, the floating diffusion region FD1 is reset. Further, as shown in FIG. 19, the system control unit 115 ″ ″ generates the selection pulse SEL from time t111 to t153. As a result, the vertical signal line VSL becomes effective and charges as a light reception signal are transferred from the floating diffusion region FD. At the same time, the system control unit 115 ″ ″ generates a sample hold timing pulse SHN for the column processing unit 113. That is, when the processing target row is the n-th row, the sample hold timing pulse SHN is generated within the generation period of the selection pulse SEL, such as time t112 to t113.

  In step S111, the column processing unit 113 'stores the received light signal read out through the vertical signal line 117 (VSL) as reset level information by the sample hold timing pulse SHN. That is, in the case of the unit pixel in the nth row, the light reception signal at the reset level is read out at a timing in the vicinity of time t112 to t113 indicated by the dotted line in FIG. That is, since the reset pulse RST is generated from time t111 to t171 in FIG. 19, the column processing unit 113 'reads the light reception signal at the reset level of the floating diffusion region FD1.

  In step S112, the system control unit 115 '' '' generates a first transfer pulse ROG on the first transfer pulse line of the pixel in the processing target row. For example, when the processing target row is the n-th row, the first transfer pulse ROG is generated at times t114 to t115 which are the final timing of the generation period of the selection pulse SEL. With this processing, the charge in the floating diffusion region FD2 of the pixel in the processing target row is transferred to the floating diffusion region FD1, and the light reception signal of the floating diffusion region FD1 is read out as a signal level via the vertical signal line 117 (VSL). .

  In step S113, the system control unit 115 '' '' generates a sample hold timing pulse SHS for the column processing unit 113 as shown in FIG. That is, when the processing target row is the n-th row, the sample hold timing pulse SHS is generated within the generation period of the selection pulse SEL, such as times t151 to t152.

  In step S114, the column processing unit 113 'reads and stores the received light signal supplied from the vertical signal line VSL as a signal level by the sample hold timing pulse SHS. That is, in the case of the unit pixel in the n-th row, a light reception signal having a signal level is read out at a timing in the vicinity of times t151 to t153 indicated by dotted lines in FIG.

  In step S115, the column processing unit 113 ′ obtains a difference by subtracting the value of the light reception signal at the reset level from the light reception signal at the stored signal level, and obtains the difference from the signal of each pixel in the corresponding row. As a level, the received light signals are sequentially supplied to the signal processing unit 118 ′ at the timing selected by the horizontal drive unit 114.

  In step S <b> 116, the system control unit 115 ″ ″ determines whether or not there is an unprocessed row in the order of the rows stored in the address list 115 a. For example, if there is an unprocessed row, the process returns to step S110. That is, the light reception level and the reset level of the light reception signals of the pixels of all the rows are read out, and the processing of steps S110 to S116 is repeated until the difference is stored as the signal level, and the pixels are sequentially stored in the data storage unit 118c. The signal level of the received light signal is stored.

  If it is determined in step S116 that the light reception signals of the pixels in all rows have been read, the process proceeds to step S117.

  That is, since the address list 115a ′ ″ records the order of the row unit according to the signal level of each pixel in the image to be processed, the order of reading sequentially in steps S110 to S116 is the processing target. The images are read in the order of the higher signal level obtained based on the signal level of each image in the row unit. In addition, when the light-receiving signal at the reset level is read out first, then the light-receiving signal at the signal level is read out and the difference between the signal level and the reset level is obtained. In addition, it is possible to reduce the influence that the difference value cannot be obtained accurately due to variations in residual charges, and the signal level can be measured with higher accuracy.

  Therefore, for example, when the order of the signal level in units of rows is the nth row, the (n−1) th row, and the (n + 1) th row from the top, as shown in FIG. The n rows of selection pulses SEL are generated from time t111 to t153. In the meantime, a reset pulse RST is generated from time t111 to t171, a sample hold timing pulse SHN is generated from time t112 to t113, and a light reception signal at the reset level of each pixel in the nth row is read. Further, the first transfer pulse ROG is generated from time t114 to t115, the sample hold timing pulse SHS is generated from time t151 to t152, and the signal level of the signal level of each pixel in the nth row is read.

  When the processing of the nth row is completed, the processing of the (n−1) th row is performed, and therefore the selection pulse SEL of the (n−1) th row is generated from time t116 to t156. Meanwhile, a reset pulse RST is generated from time t116 to t172, a sample hold timing pulse SHN is generated from time t117 to t118, and the reset level of each pixel in the (n−1) th row is read. Further, the first transfer pulse ROG is generated from time t119 to t120, the sample hold timing pulse SHS is generated from time t154 to t155, and the signal level of each pixel in the (n−1) th row is read.

  Further, when the processing of the (n−1) -th row is completed, the processing of the (n + 1) -th row is performed, so that the selection pulse SEL for the (n + 1) -th row is generated from time t121 to t159. In the meantime, a reset pulse RST is generated from time t121 to t173, a sample hold timing pulse SHN is generated from time t122 to t123, and the signal level of each pixel in the (n + 1) th row is read. Further, the first transfer pulse ROG is generated from time t124 to t125, the sample hold timing pulse SHS is generated from time t157 to t158, and the signal level of each pixel in the (n−1) th row is read.

  That is, by reading the reset level light reception signal by the above processing, the signal level light reception signal is read out, and the difference between the read signal level and the reset level is handled as a normal signal level. The signal level can be read with higher accuracy. Also in this case, since the pixels are read in order from the pixels with the higher light reception level, the signals are read out in order from the signal level of the pixels where the noise is more likely to be generated as the accumulation period of the floating diffusion region FD is higher. Occurrence can be reduced.

<5. Fifth embodiment>
[Other structure of unit pixel]
The present invention can be applied not only to the unit pixel configuration described above but also to various unit pixel configurations. In the following, applicable unit pixel structures will be described.

  In addition to the floating diffusion region (capacitance) (also referred to as floating diffusion), the unit pixel 120 has a charge retention region (hereinafter also referred to as “memory unit”) that retains (accumulates) photocharge transferred from the photoelectric conversion element. It can be set as the structure which has.

  FIG. 20 is a diagram illustrating a configuration of the unit pixel 120A that illustrates a configuration example of the embodiment of the structure of the unit pixel 120.

  The unit pixel 120A includes, for example, a photodiode (PD) 121 as a photoelectric conversion element. The photodiode 121 is formed, for example, by embedding an N-type buried layer 134 by forming a P-type layer 133 on the substrate surface side with respect to a P-type well layer 132 formed on the N-type substrate 131. Type photodiode.

  The unit pixel 120 </ b> A includes a first transfer gate 122, a memory unit (MEM) 123, a second transfer gate 124, and a floating diffusion region (FD: Floating Diffusion) 125 in addition to the photodiode 121. Note that the memory unit 123 and the floating diffusion region 125 are shielded from light.

  The first transfer gate 122 performs photoelectric conversion by the photodiode 121 and transfers the charge accumulated therein by applying a transfer pulse TRX to the gate electrode 122A. The memory portion 123 is formed by an N-type buried channel 135 formed under the gate electrode 122A, and accumulates the charges transferred from the photodiode 121 by the first transfer gate 122. Since the memory portion 123 is formed by the buried channel 135, generation of dark current at the Si—SiO 2 interface can be suppressed, which can contribute to improvement in image quality.

  In the memory portion 123, the gate electrode 122A is disposed on the top thereof, and the memory portion 123 can be modulated by applying the transfer pulse TRX to the gate electrode 122A. That is, the potential of the memory unit 123 is deepened by applying the transfer pulse TRX to the gate electrode 122A. Thereby, the saturation charge amount of the memory unit 123 can be increased as compared with the case where no modulation is applied.

  The second transfer gate 124 transfers the charge accumulated in the memory unit 123 by applying a transfer pulse TRG to the gate electrode 124A. The floating diffusion region 125 is a charge-voltage conversion unit made of an N-type layer, and converts the charge transferred from the memory unit 123 by the second transfer gate 124 into a voltage.

  The unit pixel 120A further includes a reset transistor 126, an amplification transistor 127, and a selection transistor 128. As the reset transistor 126, the amplification transistor 127, and the selection transistor 128, N-channel MOS transistors are used in the example of FIG. However, the combination of conductivity types of the reset transistor 126, the amplification transistor 127, and the selection transistor 128 illustrated in FIG. 20 is merely an example, and is not limited to these combinations.

  The reset transistor 126 is connected between the power supply VDD and the floating diffusion region 125, and resets the floating diffusion region 125 by applying a reset pulse RST to the gate electrode. The amplification transistor 127 has a drain electrode connected to the power supply VDD and a gate electrode connected to the floating diffusion region 125, and reads the voltage of the floating diffusion region 125.

  In the selection transistor 128, for example, the drain electrode is connected to the source electrode of the amplification transistor 127, the source electrode is connected to the vertical signal line 117, and the selection signal SEL is applied to the gate electrode, so that the pixel signal should be read out. The unit pixel 120A is selected. Note that the selection transistor 128 may be connected between the power supply VDD and the drain electrode of the amplification transistor 127.

  Note that one or more of the floating diffusion region 125, the reset transistor 126, the amplification transistor 127, and the selection transistor 128 can be omitted depending on a pixel signal reading method, or can be shared among a plurality of pixels. is there.

  The unit pixel 120A further includes a charge discharging unit 129 for discharging the accumulated charge of the photodiode 121. The charge discharging unit 129 discharges the charge of the photodiode 121 to the drain unit 136 of the N-type layer by applying a control pulse ABG to the gate electrode 129A at the start of exposure. The charge discharging unit 129 further functions to prevent the photodiode 121 from saturating and overflowing charges during the readout period after the exposure is completed. A predetermined voltage VDD is applied to the drain portion 136.

  In addition, the unit pixel 120A employs a configuration in which a charge discharging unit 129 is provided in order to discharge the accumulated charge of the photodiode 21 and prevent the photodiode 121 from overflowing the charge. On the other hand, the same effect as that of the charge discharging unit 129 can be obtained by adopting a configuration in which the transfer pulses TRX and TRG and the reset pulse RST are all in an active state (in this example, “H” level). it can.

  Here, the potential of the gate electrode of the memory portion 123 serving as the charge holding region, that is, the potential of the gate electrode 122A of the first transfer gate 122 will be described.

  In the present embodiment, the potential of the gate electrode of the memory unit 123 serving as the charge holding region is at least one of the first transfer gate 122 and the second transfer gate 124, for example, the first transfer gate 122 is turned off. In the period, the potential is set to the pinning state. More specifically, when one or both of the first transfer gate 122 and the second transfer gate 124 is turned off, the voltage applied to the gate electrodes 122A and 124A is the Si surface immediately below the gate electrode. Is set to be in a pinning state where carriers can be accumulated.

  As in this embodiment, when the transistor forming the transfer gate is N-type, when the first transfer gate 122 is turned off, the voltage applied to the gate electrode 122A is grounded with respect to the P-type well layer 132. The voltage is set to a negative potential. Although not shown, when the transistor forming the transfer gate is a P-type, the P-type well layer becomes an N-type well layer, and the N-type well layer is set to a voltage higher than the power supply voltage VDD.

  The reason for setting the voltage applied to the gate electrode 122A to the pinning state in which carriers can be accumulated on the Si surface immediately below the gate electrode when the first transfer gate 122 is turned off is as follows. is there.

  When the potential of the gate electrode 122A of the first transfer gate 122 is set to the same potential (for example, 0 V) with respect to the P-type well layer 132, carriers generated from crystal defects on the Si surface are accumulated in the memory unit 123 and become a dark current. There is a risk of degrading the image quality. For this reason, in the present embodiment, the OFF potential of the gate electrode 122A formed on the memory unit 123 is set to a negative potential, for example, −2.0 V with respect to the P-type well layer 132. Thereby, in the present embodiment, it is possible to generate holes on the Si surface of the memory unit 123 during the charge retention period and recombine electrons (electrons) generated on the Si surface. As a result, dark current can be reduced.

  In the configuration of FIG. 20, since the gate electrode 124A of the second transfer gate 124 exists at the end of the memory unit 123, the end of the memory unit 123 is also set by setting the gate electrode 124A to a negative potential. It is possible to suppress the dark current generated in the same way.

  The CMOS image sensor 100 starts exposure at the same time for all pixels, ends exposure at the same time for all pixels, and transfers the charges accumulated in the photodiode 121 to the light-shielded memory unit 123 and the floating diffusion region 125, thereby globally. Realize exposure. With this global exposure, it is possible to capture images without distortion during an exposure period in which all pixels coincide.

  In addition, all the pixels in this Embodiment are all the pixels of the part which appears in an image, and a dummy pixel etc. are excluded. In addition, if the time difference and the distortion of the image are sufficiently small so as not to cause a problem, a method of scanning at a high speed for each of a plurality of lines (for example, several tens of lines) instead of the simultaneous operation of all the pixels is included.

  Note that the photodiode 121, the first transfer gate 122, the memory unit (MEM) 123, the second transfer gate 124, and the floating diffusion region (FD) 125 in FIG. 20 are the same as the photodiode PD in FIG. This corresponds to the second transfer gate TR_TRG, the floating diffusion region FD2, the first transfer gate TR_ROG, and the floating diffusion region FD1, and has the same effect by the corresponding operation.

[Other First Configuration Example of Unit Pixel]
The present invention can also be applied to structures other than the unit pixels described in the above-described embodiments. Hereinafter, the structure of other unit pixels to which the present invention is applicable will be described. In the following drawings, parts corresponding to those in FIG. 20 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  FIG. 21 is a diagram illustrating a structure of a unit pixel 120B which is another first configuration example of the unit pixel 120.

  In the unit pixel 120B, the first transfer gate 122 and the memory unit 123 in the unit pixel 120 of FIG. 20 are omitted, and the photodiode 121 and the floating diffusion region 125 are adjacent to each other with the P-type well layer 132 interposed therebetween. . A second transfer gate 124 is disposed on the upper side of the P-type well layer 132 between the photodiode 121 and the floating diffusion region 125.

  A global exposure operation in the unit pixel 120B will be described. First, after a charge discharging operation for emptying the charge stored in the embedded photodiode 121 is performed simultaneously for all pixels, exposure is started. As a result, photocharge is accumulated in the PN junction capacitance of the photodiode 121. At the end of the exposure period, the second transfer gates 124 are turned on simultaneously for all pixels, and all the accumulated photocharges are transferred to the floating diffusion region 125. By closing the second transfer gate 124, the photocharge accumulated in the same exposure period for all pixels is held in the floating diffusion region 125. Thereafter, the photoelectric charges held in the floating diffusion region 125 are sequentially read out through the vertical signal line 117 as pixel signals. Finally, the floating diffusion region 125 is reset, and then the reset level is read out.

  21 corresponds to the photodiode PD, the transfer gate TR_TRG, and the floating diffusion region FD in FIG. 3, respectively. The photodiode 121, the second transfer gate 124, and the floating diffusion region (FD) 125 in FIG. There is the same operation effect by corresponding operation.

[Other Second Configuration Example of Unit Pixel]
FIG. 22 is a diagram illustrating a structure of a unit pixel 120C which is another second configuration example of the unit pixel 120.

  The unit pixel 120C is different from the unit pixel 120 in that an overflow path 130 is formed by providing a P− impurity diffusion region 137 below the gate electrode 122A and at the boundary between the photodiode 121 and the memory unit 123. Different.

  In order to form the overflow path 130, it is necessary to lower the potential of the impurity diffusion region 137. The P− impurity diffusion region 137 can be formed by lightly doping the impurity diffusion region 137 with N impurity to lower the P impurity concentration. Alternatively, when the impurity diffusion region 137 is doped with P impurity during the formation of the potential barrier, the P− impurity diffusion region 137 can be formed by reducing the concentration thereof.

  In the unit pixel 120 </ b> C, an overflow path 130 formed at the boundary between the photodiode 121 and the memory unit 123 is used as means for preferentially storing charges generated at low illuminance in the photodiode 121.

  Providing a P− impurity diffusion region 137 at the boundary between the photodiode 121 and the memory unit 123 lowers the potential at the boundary. The portion where this potential is lowered becomes the overflow path 130. Then, the charges generated in the photodiode 121 and exceeding the potential of the overflow path 130 are automatically leaked to the memory unit 123 and accumulated. In other words, the generated charge below the potential of the overflow path 130 is accumulated in the photodiode 121.

  The overflow path 130 functions as an intermediate charge transfer unit. That is, the overflow path 130 serving as the intermediate charge transfer unit is generated by photoelectric conversion in the photodiode 121 during an exposure period in which all of the plurality of unit pixels simultaneously perform an imaging operation, and is a predetermined charge amount determined by the potential of the overflow path 130. The charge exceeding 1 is transferred to the memory unit 123 as signal charge.

  In the example of FIG. 22, a structure in which an overflow path 130 is formed by providing a P− impurity diffusion region 137 is employed. However, instead of providing the P− impurity diffusion region 137, an overflow path 130 may be formed by providing the N− impurity diffusion region 137.

  Note that the photodiode 121, the first transfer gate 122, the memory unit (MEM) 123, the second transfer gate 124, and the floating diffusion region (FD: Floating Diffusion) 125 of FIG. 22 are the photodiode PD of FIG. This corresponds to the second transfer gate TR_TRG, the floating diffusion region FD2, the first transfer gate TR_ROG, and the floating diffusion region FD1, and has the same effect by the corresponding operation.

[Other Third Configuration Example of Unit Pixel]
FIG. 23 is a diagram illustrating a structure of a unit pixel 120D which is another third configuration example of the unit pixel 120.

  The unit pixel 120D has a configuration in which a memory unit 123 similar to the floating diffusion region 125 is provided in the configuration of the unit pixel 120B in FIG. That is, in the unit pixel 120 </ b> D, the gate electrode 122 </ b> A of the first transfer gate 122 is provided on the P-type well layer 132 at the boundary between the photodiode 121 and the memory unit 123. In the unit pixel 120 </ b> D, the memory unit 123 is formed by the N-type layer 138 similar to the floating diffusion region 125.

  The global exposure operation in the unit pixel 120D is executed according to the following procedure. First, the charge discharging operation is executed simultaneously for all pixels, and simultaneous exposure is started. The generated photocharge is accumulated in the photodiode 121. At the end of exposure, the first transfer gate 122 is turned on simultaneously for all pixels, and the accumulated photocharge is transferred to the memory unit 123 and held. After the exposure is completed, the reset level and the signal level are read out sequentially. That is, the floating diffusion region 125 is reset, and then the reset level is read out. Subsequently, the charge held in the memory unit 123 is transferred to the floating diffusion region 125, and the signal level is read out.

  Note that the photodiode 121, the first transfer gate 122, the memory unit (MEM) 123, the second transfer gate 124, and the floating diffusion region (FD) 125 in FIG. 23 are the photodiode PD in FIG. This corresponds to the second transfer gate TR_TRG, the floating diffusion region FD2, the first transfer gate TR_ROG, and the floating diffusion region FD1, and has the same effect by the corresponding operation.

[Other Fourth Configuration Example of Unit Pixel]
FIG. 24 is a diagram illustrating a structure of a unit pixel 120E which is another fourth configuration example of the unit pixel 120.

  In the unit pixel 120 </ b> A of FIG. 20, the memory unit 123 is formed by a buried channel 135. On the other hand, in the unit pixel 120E of FIG. 24, a configuration in which the memory unit 123 is formed by the embedded N-type diffusion region 139 is employed.

  Even when the memory portion 123 is formed by the N-type diffusion region 139, the same operational effects as when formed by the buried channel 135 can be obtained. Specifically, the N-type diffusion region 139 is formed inside the P-type well layer 132, and the P-type layer 140 is formed on the substrate surface side, so that the dark current generated at the Si-SiO2 interface is reduced in the memory unit 123. Since accumulation in the N-type diffusion region 139 can be avoided, the image quality can be improved.

  Here, the impurity concentration of the N-type diffusion region 139 of the memory unit 123 is preferably lower than the impurity concentration of the floating diffusion region 125. With such an impurity concentration setting, the transfer efficiency of charges from the memory unit 123 to the floating diffusion region 125 by the second transfer gate 124 can be increased. The global exposure operation in the unit pixel 120E is the same as that of the unit pixel 120A in FIG.

  In the configuration of the unit pixel 120E shown in FIG. 24, the memory unit 123 is formed by the embedded N-type diffusion region 139. However, although the dark current generated in the memory unit 123 may increase, It may be a structure that does not.

  Also in the configuration of the unit pixel 120E, a configuration in which the charge discharging unit 129 is omitted and all of the transfer pulses TRX and TRG and the reset pulse RST are in an active state can be employed as in the case of the unit pixel 120A in FIG. . By adopting this configuration, the same effect as the charge discharging unit 129, that is, the charge of the photodiode 121 can be discharged, and the charge overflowed by the photodiode 121 during the reading period can be released to the substrate side.

  Note that the photodiode 121, the first transfer gate 122, the memory unit (MEM) 123, the second transfer gate 124, and the floating diffusion region (FD: Floating Diffusion) 125 of FIG. 24 are the photodiode PD of FIG. This corresponds to the second transfer gate TR_TRG, the floating diffusion region FD2, the first transfer gate TR_ROG, and the floating diffusion region FD1, and has the same effect by the corresponding operation.

[Other Fifth Configuration Example of Unit Pixel]
FIG. 25 is a diagram illustrating a structure of a unit pixel 120F that is another fifth configuration example of the unit pixel 120. As illustrated in FIG.

  In the unit pixel 120 of FIG. 20, one memory unit (MEM) 123 is disposed between the photodiode 121 and the floating diffusion region 125. However, in the unit pixel 120F of FIG. 25, another memory unit (MEM2) is arranged. 142) is arranged. That is, the memory unit has a two-stage configuration.

  The third transfer gate 141 transfers the charge accumulated in the memory unit 123 by applying the transfer pulse TRX2 to the gate electrode 141A. The memory unit 142 is formed by an N-type buried channel 143 formed under the gate electrode 141A, and accumulates charges transferred from the memory unit 123 by the third transfer gate 141. Since the memory portion 142 is formed by the embedded channel 143, generation of dark current at the Si—SiO 2 interface can be suppressed, which can contribute to improvement in image quality.

  Since the memory unit 142 has the same configuration as that of the memory unit 123, as with the memory unit 123, the saturation charge amount of the memory unit 142 may be increased more than when the modulation is not performed. it can.

  In the global exposure operation in the unit pixel 120 </ b> F, photocharges accumulated simultaneously in all the pixels are held in the photodiode 121 or the memory unit 123. The memory unit 142 is used to hold photocharges until a pixel signal is read out.

  Note that the photodiode 121, the first transfer gate 122, the memory unit (MEM) 123, the second transfer gate 124, and the floating diffusion region (FD) 125 of FIG. 25 are the photodiode PD of FIG. This corresponds to the second transfer gate TR_TRG, the floating diffusion region FD2, the first transfer gate TR_ROG, and the floating diffusion region FD1, and has the same effect by the corresponding operation.

  The present invention is not limited to application to a solid-state imaging device. That is, the present invention is applied to an image capturing unit (photoelectric conversion unit) such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function, or a copying machine using a solid-state imaging device as an image reading unit. The present invention can be applied to all electronic devices using a solid-state image sensor. The solid-state imaging device may be formed as a one-chip, or may be in a module shape having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.

  Note that the conductivity type of the device structure in the above-described unit pixels 120 and 120A to 120E is merely an example, and the N type and P type may be reversed, and the conductivity type of the N type substrate 131 is also N type, P Either type

  Further, in the above, an example in which signal level reading or the like is performed in units of rows has been described. However, it is not always necessary to perform processing in units of rows. For example, a plurality of units of pixels may be used. It may be a unit and a plurality of pixel units.

<6. Sixth Embodiment>
[Configuration Example of Electronic Device with CMOS Image Sensor to which Solid-State Image Sensor of the Present Invention is Applied]
FIG. 26 is a block diagram illustrating a configuration example of an imaging apparatus as an electronic apparatus including a CMOS image sensor to which the solid-state imaging device of the present invention is applied.

  An imaging apparatus 300 in FIG. 26 includes an optical unit 301 including a lens group, a solid-state imaging device (imaging device) 302 that employs each configuration of the unit pixel 120 described above, and a DSP (Digital Signal Processor) that is a camera signal processing circuit. ) Circuit 303. The imaging apparatus 300 also includes a frame memory 304, a display unit 305, a recording unit 306, an operation unit 307, and a power supply unit 308. The DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, the operation unit 307, and the power supply unit 308 are connected to each other via a bus line 309.

  The optical unit 301 takes in incident light (image light) from a subject and forms an image on the imaging surface of the solid-state imaging element 302. The solid-state imaging element 302 converts the amount of incident light imaged on the imaging surface by the optical unit 301 into an electrical signal in units of pixels and outputs the electrical signal. As this solid-state imaging device 302, a solid-state imaging device such as the CMOS image sensor 100 according to the above-described embodiment, that is, a solid-state imaging device capable of realizing imaging without distortion by global exposure can be used.

  The display unit 305 includes, for example, a panel type display device such as a liquid crystal panel or an organic EL (electroluminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 302. The recording unit 306 records a moving image or a still image captured by the solid-state imaging element 302 on a recording medium such as a video tape or a DVD (Digital Versatile Disk).

  The operation unit 307 issues operation commands for various functions of the imaging apparatus 300 under the operation of the user. The power supply unit 308 appropriately supplies various power sources serving as operation power sources for the DSP circuit 303, the frame memory 304, the display unit 305, the recording unit 306, and the operation unit 307 to these supply targets.

  As described above, by using the CMOS image sensor 100 according to the above-described embodiment as the solid-state imaging element 302, it is possible to reduce noise due to threshold variation of the pixel transistor and ensure a high S / N. . Therefore, it is possible to improve the image quality of captured images in the imaging apparatus 300 such as a video camera, a digital still camera, and a camera module for mobile devices such as a mobile phone.

  In the above-described embodiment, the case where the present invention is applied to a CMOS image sensor in which unit pixels that detect signal charges corresponding to the amount of visible light as physical quantities are arranged in a matrix has been described as an example. However, the present invention is not limited to application to a CMOS image sensor, and can be applied to all column-type solid-state imaging devices in which a column processing unit is arranged for each pixel column of a pixel array unit.

  Further, the present invention is not limited to application to a solid-state imaging device that detects the distribution of the amount of incident light of visible light and captures it as an image, but a solid that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image Applicable to imaging devices and, in a broad sense, solid-state imaging devices (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture images as images. is there.

  In this specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in time series in the order described, but of course, it is not necessarily performed in time series. Or the process performed separately is included.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

  100 CMOS image sensor, 111 pixel array unit, 112 vertical drive unit, 113 column processing unit, 114 horizontal drive unit, 115, 115 ′, 115 ″, 115 ′ ″ system control unit, 115a address list, 118, 118 ′ Signal processing unit, 118a, 118a ′ level analysis unit, 118b address list, 118c data storage unit, 118d rearrangement unit, 118e high brightness detection unit

Claims (19)

In response to the received light, a light receiving element that generates and stores a charge as a light receiving signal, a charge storage unit that stores a charge as a light receiving signal transferred by the light receiving element, and the light receiving element A transfer means for transferring the charge as the received light signal to the charge storage section, a reset means for resetting by releasing the charge stored in the charge storage section based on the reset signal, and a transfer means to the charge storage section. CMOS (Complementary Metal Oxide Semiconductor) having an array of pixels each having amplifying means for amplifying a received light signal composed of charges and a selecting means for outputting the received light signal amplified by the amplifying means based on the selection signal ) Image sensor,
Based on the level of the received light signal accumulated in the light receiving element, analysis means for analyzing the order of the height of the received light signal level in units of rows composed of the plurality of pixels;
Control means for controlling the generation of the selection signal in units of rows based on the order of units of rows that are analysis results by the analysis means,
The transfer means transfers all the charges accumulated in the light receiving element to the charge accumulating section in a batch, and after the reset means resets the charge accumulating section, the light receiving element receives the light. Start accumulating charge as a received light signal generated in response to the received light,
When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit converts the charge of the light receiving element into the charge accumulation unit. Bulk transfer to
Thereafter, the control means controls the generation of the selection signal in row units of the array in the order of the row units that are the analysis results of the analysis means,
The selecting means amplifies the light receiving signal composed of the charges accumulated in the charge accumulating section in the array-like row unit in the order of the row as the analysis result of the analyzing means, and outputs the amplified light signal from the amplifying means. Image sensor. A discharge wiring common to the light receiving element of the unit pixel in the row direction;
Connection control means for controlling connection between the discharge wiring and the light receiving element based on a discharge selection signal;
A current amount detecting means for detecting a current amount of the discharge wiring;
The analyzing means is configured to determine the predetermined light level based on a level of a light receiving signal generated by the light receiving element, which is obtained corresponding to the current amount detected by the current amount detecting means for all pixels in a predetermined frame. Analyzing the order of the height of the level of the received light signal in units of rows consisting of the pixels in the frame,
2. The generation unit according to claim 1, wherein the control unit controls generation of the selection signal in the row unit in the predetermined frame based on an order of the row unit that is an analysis result of the predetermined frame by the analysis unit. Solid-state image sensor. The analysis means calculates the light reception signal generated by the light receiving element, which is obtained corresponding to the current amount detected by the current amount detection means each time the control means generates a selection signal for each row. The solid according to claim 2, wherein, based on the level, the order of the level of the received light signal in the row unit in which generation of the selection signal is not controlled by the control means in the predetermined frame is analyzed. Image sensor. When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit transfers the charge of the light receiving element to the charge accumulation unit. After bulk transfer to
The discharge means signal is generated by the control means for the connection control means corresponding to all the pixels, and the connection control means connects the discharge wiring and the light receiving element, whereby the discharge wiring, The solid-state imaging element according to claim 2, wherein the charge overflow path as a light reception signal accumulated in the light receiving element is shared. The analyzing means outputs the level of the light receiving signal in units of rows composed of the pixels based on the level of the light receiving signal output from the amplifying means and accumulated in the light receiving element for all the pixels in the first frame. Analyzing the height order of
The control unit selects the row unit in the second frame temporally after the first frame, based on the row unit order which is the analysis result of the first frame by the analyzing unit. The solid-state imaging device according to claim 1, wherein generation of a signal is controlled. Based on the signal level of the received light signal accumulated in the light receiving element, the analyzing unit analyzes whether the light receiving signal is distributed in the lower side or the upper side in the order of the level of the received light signal level. The control unit controls generation of the selection signal in the row unit based on the analysis result by the analysis unit, with the order of the row unit being set in the upward order of the row arrangement or the order in the downward direction. The solid-state imaging device according to claim 1. The analyzing means determines the order of the level of the received light signal level in a plurality of row units obtained by dividing all rows of the pixels into 1 / n based on the received light signal level accumulated in the light receiving element. Parse and
2. The control unit controls generation of the selection signal in the plurality of row units based on the order of a plurality of row units obtained by dividing all the rows as analysis results by the analysis unit into 1 / n. The solid-state image sensor described in 1. The control means controls the generation of the reset signal during the selection signal generation period in the row unit,
Based on the selection signal, when the amplification means amplifies and outputs a light reception signal composed of the charges transferred to the charge storage section, the selection means outputs a first light reception signal output by the amplification means. And when the reset means resets by releasing the charge accumulated in the charge accumulation section, the difference between the second level of the received light signal output by the amplifying means is calculated as the pixel level. The solid-state imaging device according to claim 1, wherein the level of the received light signal is a level of the received light signal. The image sensor is
Another charge storage unit different from the charge storage unit that stores the charge as a light reception signal transferred from the charge storage unit, and another charge storage unit as a light reception signal stored from the charge storage unit A transfer unit that is different from the transfer unit that transfers to the unit, a discharge line that is common in the row direction to the light receiving element of the unit pixel, and a connection between the discharge line and the light receiving element based on a discharge selection signal And connection control means for controlling
The reset unit releases the charge accumulated in the other charge accumulation unit based on the reset signal,
The solid-state imaging device according to claim 1, wherein the amplifying unit amplifies a light reception signal composed of charges transferred to the other charge storage unit. The solid image according to claim 1, wherein the image sensor has a structure in which a plurality of pixels share one or more of the charge storage unit, the transfer unit, the reset unit, the amplification unit, and the selection unit. Image sensor. In response to the received light, a light receiving element that generates and stores a charge as a light receiving signal, a charge storage unit that stores a charge as a light receiving signal transferred by the light receiving element, and the light receiving element A transfer means for transferring the charge as the received light signal to the charge storage section, a reset means for resetting by releasing the charge stored in the charge storage section based on the reset signal, and a transfer means to the charge storage section. CMOS (Complementary Metal Oxide Semiconductor) having an array of pixels each having amplifying means for amplifying a received light signal composed of charges and a selecting means for outputting the received light signal amplified by the amplifying means based on the selection signal ) Image sensor,
Based on the level of the received light signal accumulated in the light receiving element, analysis means for analyzing the order of the height of the received light signal level in units of rows composed of the plurality of pixels;
A solid-state image sensor driving method including control means for controlling the generation of the selection signal in the row unit based on the order of the row unit as an analysis result by the analysis unit,
An analysis step of analyzing the order of the level of the light reception signal level in units of rows composed of the plurality of pixels based on the level of the light reception signal accumulated in the light receiving element in the analysis unit;
A control step of controlling the generation of the selection signal in the row unit based on the order of the row unit as an analysis result by the analysis step in the control unit;
The transfer means transfers all the charges accumulated in the light receiving element to the charge accumulating section in a batch, and after the reset means resets the charge accumulating section, the light receiving element receives the light. Start accumulating charge as a received light signal generated in response to the received light,
When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit converts the charge of the light receiving element into the charge accumulation unit. Bulk transfer to
Thereafter, the process of the control step controls the generation of the selection signal in units of rows of the array in the order of units of rows that are the analysis results of the analysis means,
The selection unit amplifies a light reception signal composed of charges accumulated in the charge storage unit in the array-like row unit by the amplification unit in the order of the row unit which is an analysis result in the process of the analysis step. Driving method of solid-state image sensor to be output. A discharge wiring common to the light receiving element of the unit pixel in the row direction;
Connection control means for controlling connection between the discharge wiring and the light receiving element based on a discharge selection signal;
A current amount detecting means for detecting a current amount of the discharge wiring;
The processing of the analysis step is based on the level of the light reception signal generated by the light receiving element, which is obtained corresponding to the current amount detected by the current amount detection means for all pixels in a predetermined frame. Analyzing the order of the height of the level of the received light signal in units of rows composed of the pixels in a predetermined frame,
The processing in the control step controls generation of the selection signal in the row unit in the predetermined frame based on the order of the row unit that is an analysis result of the predetermined frame by the processing in the analysis step. The driving method of the solid-state imaging device according to 11. The process of the analysis step is generated by the light receiving element, which is obtained corresponding to the amount of current detected by the current amount detection means every time the process of the control step generates a selection signal in units of rows. 13. The order of the level of the received light signal level in a row unit in which generation of the selection signal is not controlled by the control means in the predetermined frame is analyzed based on the received light signal level. The driving method of the solid-state image sensor described in 1. When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit transfers the charge of the light receiving element to the charge accumulation unit. After bulk transfer to
By the processing of the control step, the discharge selection signal is generated for the connection control means corresponding to all pixels, and the connection control means connects the discharge wiring and the light receiving element, thereby The solid-state imaging device driving method according to claim 12, wherein a charge overflow path as a light reception signal accumulated in the light receiving device is shared. The processing of the analyzing step is performed for each pixel in the first frame, based on the level of the light reception signal output from the amplification unit and accumulated in the light receiving element, for each pixel. Analyzing the order of height of levels
The process of the control step is based on the order of the row unit that is the analysis result of the first frame by the process of the analysis step, and the row unit in the second frame temporally after the first frame. The method for driving a solid-state imaging device according to claim 11, wherein the generation of the selection signal is controlled. Based on the signal level of the received light signal accumulated in the light receiving element, the analyzing unit analyzes whether the light receiving signal is distributed in the lower side or the upper side in the order of the level of the received light signal level. The processing of the control step is based on the analysis result by the processing of the analysis step, and the order of the row unit is set to the upper order of the row arrangement or the order of the lower order. The method for driving a solid-state imaging device according to claim 11, wherein the generation is controlled. The processing in the analysis step is performed based on the level of the light reception signal in a plurality of rows obtained by dividing all the rows of the pixels into 1 / n based on the level of the light reception signal accumulated in the light receiving element. Analyze the order,
The processing in the control step controls generation of the selection signal in the plurality of row units based on the order of the plurality of row units obtained by dividing all the rows that are the analysis results by the processing in the analysis step into 1 / n. The method for driving a solid-state imaging device according to claim 11. The process of the control step controls the generation of the reset signal during the generation period of the selection signal in the row unit,
Based on the selection signal, when the amplification means amplifies and outputs a light reception signal composed of the charges transferred to the charge storage section, the selection means outputs a first light reception signal output by the amplification means. And when the reset means resets by releasing the charge accumulated in the charge accumulation section, the difference between the second level of the received light signal output by the amplifying means is calculated as the pixel level. The solid-state imaging device driving method according to claim 11, wherein the level of the received light signal is set to a level of the received light signal. In response to the received light, a light receiving element that generates and stores a charge as a light receiving signal, a charge storage unit that stores a charge as a light receiving signal transferred by the light receiving element, and the light receiving element A transfer means for transferring the charge as the received light signal to the charge storage section, a reset means for resetting by releasing the charge stored in the charge storage section based on the reset signal, and a transfer means to the charge storage section. CMOS (Complementary Metal Oxide Semiconductor) having an array of pixels each having amplifying means for amplifying a received light signal composed of charges and a selecting means for outputting the received light signal amplified by the amplifying means based on the selection signal ) Image sensor,
Based on the level of the received light signal accumulated in the light receiving element, analysis means for analyzing the order of the height of the received light signal level in units of rows composed of the plurality of pixels;
Control means for controlling the generation of the selection signal in units of rows based on the order of units of rows that are analysis results by the analysis means,
The transfer means transfers all the charges accumulated in the light receiving element to the charge accumulating section in a batch, and after the reset means resets the charge accumulating section, the light receiving element receives the light. Start accumulating charge as a received light signal generated in response to the received light,
When a predetermined accumulation time has elapsed since the start of charge accumulation by the light receiving element, the reset unit resets the charge accumulation unit, and then the transfer unit converts the charge of the light receiving element into the charge accumulation unit. Bulk transfer to
Thereafter, the control means controls the generation of the selection signal in row units of the array in the order of the row units that are the analysis results of the analysis means,
The selection means amplifies and outputs the light reception signal composed of the charges accumulated in the charge accumulation unit in the array-like row unit by the amplification means in the order of the row unit as the analysis result of the analysis unit. machine.

Images