JP2011211159A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of cutting failure of a substrate in a method for manufacturing a semiconductor device.SOLUTION: A wiring board 20 including a semiconductor chip mounted in each of a plurality of device regions 20a is divided using a dicing blade (rotary blade) 40. In the dicing process, the wiring board 20 is divided along each dicing region 20c using the dicing blade 40 while a part of each surface 10a in each of the device regions 20a is supported by a top face 41e of a fixture 41 and a surface in the dicing region 20c is not supported, wherein a side face 40b and a tapered face (inclined face) 40a forming an angle of more than 90° are formed at a tip of the dicing blade 40.

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to a semiconductor device that cuts a substrate on which a semiconductor chip is mounted with a dicing blade.

  Japanese Patent Laid-Open No. 2002-110721 (Patent Document 1) discloses a BGA (Ball Grid Array) type semiconductor device in which a semiconductor chip is mounted on a wiring board and a plurality of solder balls are arranged on the back surface side. A manufacturing method is described. Patent Document 1 describes a method of manufacturing a semiconductor device of a collective mold type (also called a MAP (Mold Array Package) type) in which a sealing body is formed so as to collectively seal a plurality of device regions. .

  Japanese Patent Laying-Open No. 2006-108343 (Patent Document 2) describes cutting a wiring board and a collectively formed sealing resin with a dicing blade as a method for manufacturing a batch mold type semiconductor device.

  In Embodiment 1 of Japanese Patent Application Laid-Open No. 2006-344827 (Patent Document 3), a single-mold type semiconductor device is described in which a sealing body is formed so that the upper surface of a wiring board is exposed. In the second embodiment, a batch mold type semiconductor device is described.

  Japanese Patent Laying-Open No. 2005-317799 (Patent Document 4) describes that a wiring board and a resin part are cut using a rotary blade having a taper at a blade edge as a manufacturing method of a collective mold type semiconductor device. Yes.

JP 2002-110721 A JP 2006-108343 A JP 2006-344827 A JP 2005-317799 A

  As a so-called collective mold type cutting process, in which a sealing body that collectively seals a plurality of semiconductor chips mounted in a plurality of device regions of a wiring board (interposer) and the wiring board are cut. As described in Documents 1 to 4, there is a cutting method using a dicing blade (rotary blade). In the batch molding type cutting process, the sealing body and the wiring board are cut, so that the thickness of the object to be cut is increased. However, the cutting method using a dicing blade is compared with the cutting method of punching with a mold. There is an advantage that even a thick workpiece can be cut stably.

  Moreover, the cutting method using a dicing blade can reduce the area of the region (fixing allowance) provided in the object to be cut in order to fix the object to be cut at the time of cutting, compared to the cutting method in which punching is performed with a mold. There is a merit. Therefore, the inventor of the present application applies a cutting method using a dicing blade in a cutting process of a semiconductor device in which a part of the surface of the wiring board in the device region is exposed, for example, as in the individual mold type semiconductor device. Considered to do.

  First, in the BGA type semiconductor device, a plurality of external terminals (solder balls) are formed on the mounting surface side of the wiring board before the cutting process (dicing process). Therefore, in the collective mold type cutting step, the surface of the sealing body is fixed on a dicing stage via a dicing sheet (tape).

  However, in the case of an individual mold type semiconductor device, a sealing body is not formed in the dicing region. For this reason, it is difficult to support and fix the area to be cut with a dicing sheet as in Patent Document 1.

  Therefore, in the individual mold type cutting process, as in Embodiment 1 of Patent Document 3, a cutting method using a jig that can support the vicinity of a region to be cut by a dicing blade (dicing region) (hereinafter referred to as a jig). Called dicing) is effective. Thereby, since the vicinity of the cutting area | region of a wiring board can be supported, the vibration of a wiring board by cutting stress can be suppressed.

  Here, this inventor discovered the following subjects which arise in the cutting process by jig dicing like the dicing process (cutting process) indicated in the above-mentioned patent documents 3, for example. That is, when the wiring board is cut, a long, string-like foreign matter is generated.

  According to the study of the present inventor, this string-like foreign material is made of a material (insulating layer material) that constitutes the insulating layer of the wiring board and is not easily destroyed. For this reason, when a string-like foreign material is generated and is sandwiched between a jig for jig dicing and a wiring board that is an object to be cut, the wiring board cannot be firmly fixed during the cutting process. And if a wiring board is not fixed during a cutting process, it will become a cause of cutting failure. Further, if the string-like foreign matter is removed every time it is generated, the production efficiency is remarkably lowered.

  It has also been found that the above-mentioned string-like foreign matter does not occur in the batch mold type cutting process. That is, the problem found by the inventor described above is a problem that occurs when the wiring substrate is cut and the sealing body is not cut in the cutting step.

  In addition, in the said patent document 1 and the said patent document 2, only the collective mold type cutting process is disclosed, and if there is no suggestion about the above-mentioned subject, the concrete for solving said subject is mentioned. There is no description about the means.

  Moreover, in the said patent document 4, when performing the cutting process of a collective mold type with the dicing blade which has a flat blade edge | tip, resin of a sealing body (resin part) generate | occur | produces as a bowl-shaped cutting waste. Things are described. However, according to the study of the present inventor, the length and physical properties are completely different between the cutting waste derived from the resin of the sealing body and the string-like foreign material derived from the insulating layer material of the wiring board described above. .

  That is, the resin material constituting the sealing body is very fragile as compared with the material constituting the insulating layer of the wiring board. For this reason, the foreign material derived from the resin of the sealing body is very easy to break as compared with the string-shaped foreign material derived from the insulating layer material of the wiring board described above. Accordingly, the foreign matter derived from the resin of the sealing body is shorter than the string-like foreign matter, and if it is sandwiched between the jig for jig dicing and the wiring substrate to be cut, the wiring It will be destroyed by the force to fix the substrate. That is, Patent Document 4 does not describe a problem found by the inventors of the present application that occurs when the wiring substrate is cut and the sealing body is not cut in the cutting step described above.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of preventing or suppressing a cutting defect of a substrate.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In other words, the method for manufacturing a semiconductor device which is one embodiment of the present invention includes a singulation step of dividing a wiring board on which a semiconductor chip is mounted in each of a plurality of device regions using a rotary blade. In this singulation process, a part of the surface in each device area is supported by a fixing jig, and the surface in the dicing area is not supported, and a wiring is provided along the dicing area using a rotary blade. Divide the board. Here, a side surface and an inclined surface forming an angle larger than 90 degrees are formed at the tip of the rotary blade.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one aspect of the present invention, it is possible to prevent or suppress substrate cutting defects.

It is a top view which shows the surface of the semiconductor device of one embodiment of this invention. It is a top view which shows the back surface of the semiconductor device shown in FIG. FIG. 2 is a plan view showing an internal structure on the surface side of the semiconductor device shown in FIG. 1. It is sectional drawing along the AA line of FIG. It is a top view which shows the surface side of the wiring board shown in FIG. FIG. 6 is an enlarged plan view of a portion B shown in FIG. 5. It is an expanded sectional view along CC line of FIG. FIG. 5 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS. It is a top view which shows the whole structure of the wiring board prepared by the board | substrate preparation process shown in FIG. FIG. 10 is an enlarged plan view of a D part shown in FIG. 9. It is an enlarged plan view which shows the back surface side of the wiring board shown in FIG. It is an expanded sectional view along the EE line shown in FIG. It is an enlarged plan view which shows the state which mounted the semiconductor chip on the wiring board shown in FIG. It is an expanded sectional view along the FF line shown in FIG. FIG. 14 is an enlarged plan view showing a state in which the semiconductor chip and the wiring board shown in FIG. 13 are electrically connected by wire bonding. It is an expanded sectional view which shows the state which electrically connected the semiconductor chip and wiring board shown in FIG. 14 by wire bonding. It is an expanded sectional view which shows the state which clamped the wiring board shown in FIG. 16 with the shaping die. It is an expanded sectional view which shows the state which supplied sealing resin in the cavity shown in FIG. FIG. 16 is an enlarged plan view showing a state where the semiconductor chip and the wire shown in FIG. 15 are sealed with resin. It is sectional drawing along the FF line of FIG. FIG. 21 is an enlarged cross-sectional view illustrating a state in which a plurality of solder balls serving as external electrodes (external connection terminals) of the semiconductor device are formed (joined) on the back surface of the wiring board illustrated in FIG. 20. It is an expanded sectional view which shows the state which cut | disconnects the wiring board shown in FIG. 21 with a dicing blade. It is an expanded sectional view of the GG line of FIG. It is an enlarged plan view which shows the upper surface of the fixing jig shown in FIG. FIG. 25 is an enlarged plan view of a portion H in FIG. 24. It is an expanded sectional view of the dicing blade shown in FIG. It is an expanded sectional view of the Q section of FIG. It is an expanded sectional view of the RR line of FIG. It is an expanded sectional view of the SS line | wire of FIG. It is an expanded sectional view of the TT line | wire of FIG. It is an expanded sectional view which shows the state which the dicing blade shown in FIG. 26 deform | transformed by abrasion. FIG. 27 is an enlarged cross-sectional view showing a first modification of the dicing blade shown in FIG. 26. It is an expanded sectional view which shows the 2nd modification of the dicing blade shown in FIG. FIG. 23 is an enlarged cross-sectional view showing a cleaning process after cutting the wiring board shown in FIG. 22. FIG. 35 is an enlarged cross-sectional view showing a state where a semiconductor device separated from the fixing jig shown in FIG. 34 is taken out. FIG. 4 is a plan view showing a modification of the semiconductor device shown in FIG. 3. FIG. 37 is a cross-sectional view taken along the line U-U in FIG. 36. It is an expanded sectional view of the W section of FIG. It is an expanded sectional view which shows the individualization process of other embodiment of this invention. It is an expanded sectional view of the XX line of FIG. It is an expanded sectional view of the YY line of FIG. It is an expanded sectional view of the ZZ line of FIG. FIG. 37 is a plan view showing a modification of the semiconductor device shown in FIG. 36. FIG. 44 is a cross-sectional view taken along line Aa-Aa in FIG. 43. It is a top view which shows the surface of a lead frame mounting type semiconductor device. 46 is a plan view showing the back surface of the semiconductor device shown in FIG. 45. FIG. FIG. 46 is a plan view showing the internal structure of the surface side of the semiconductor device shown in FIG. 45. It is sectional drawing along the Ab-Ab line | wire of FIG. FIG. 49 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS. 45 to 48. FIG. 50 is a plan view showing the overall structure of a lead frame prepared in the lead frame preparation step shown in FIG. 49. It is an enlarged plan view of the Ac part of FIG. FIG. 52 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the lead frame shown in FIG. 51. FIG. 53 is an enlarged cross-sectional view along the Ad-Ad line shown in FIG. 52. FIG. 53 is an enlarged plan view showing a state where a plurality of pads of the semiconductor chip shown in FIG. 52 and a plurality of leads of a lead frame are electrically connected by wire bonding. FIG. 54 is an enlarged cross-sectional view showing a state where a plurality of pads of the semiconductor chip shown in FIG. 53 and a plurality of leads of the lead frame are electrically connected by wire bonding; FIG. 55 is an enlarged plan view showing a state in which a sealing resin is formed in each device region of the lead frame shown in FIG. 54. FIG. 56 is an enlarged cross-sectional view showing a state in which a sealing resin is formed in each device region of the lead frame shown in FIG. 55. It is an expanded sectional view which shows the modification with respect to FIG. It is an expanded sectional view which shows the modification with respect to FIG. It is an expanded sectional view which shows the modification with respect to FIG. It is an expanded sectional view which shows the modification with respect to FIG. It is an expanded sectional view which shows the modification with respect to FIG. It is sectional drawing which shows the modification with respect to FIG. FIG. 57 is an enlarged plan view showing a modified example with respect to FIG. 56. FIG. 65 is an enlarged cross-sectional view along the line Af-Af in FIG. 64. It is an expanded sectional view which shows the modification with respect to FIG. FIG. 61 is an enlarged cross-sectional view showing a modified example with respect to FIG. 60. It is an expanded sectional view showing the 1st comparative example to the individualization process of one embodiment of the present invention. It is an expanded sectional view of the JJ line of FIG. It is an expanded sectional view of the KK line | wire of FIG. It is an expanded sectional view of the LL line of FIG. It is an expanded sectional view showing the 2nd comparative example to the individualization process of one embodiment of the present invention. FIG. 73 is an enlarged sectional view taken along line NN in FIG. 72. It is an expanded sectional view of the PP line of FIG. FIG. 70 is an enlarged cross-sectional view showing a state where the dicing blade shown in FIG. 69 is deformed due to wear. FIG. 72 is an enlarged cross-sectional view showing a comparative example in which the lead frame shown in FIG. 67 is cut using the dicing blade shown in FIGS.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

(Embodiment 1)
<Semiconductor device>
First, the outline of the structure of the semiconductor device according to the present embodiment will be described. FIG. 1 is a plan view showing the surface of the semiconductor device of the present embodiment, and FIG. 2 is a plan view showing the back surface of the semiconductor device shown in FIG. FIG. 3 is a plan view showing the internal structure of the surface side of the semiconductor device shown in FIG. 4 is a cross-sectional view taken along the line AA in FIG. In FIG. 3, the position of the sealing resin 4 shown in FIG. 1 is indicated by a two-dot chain line.

  In the present embodiment, the semiconductor chip 2 is mounted on the wiring board (substrate) 10, and the sealing resin (sealing body) 4 formed on a part (for example, a substantially central portion) on the wiring board 10, The individual mold type semiconductor device 1 in which the semiconductor chip 2 is sealed will be described.

  The semiconductor device 1 includes a semiconductor chip 2 mounted on the surface 10a of the wiring substrate 10, a plurality of conductive members (wires 3 in this embodiment) that electrically connect the semiconductor chip 2 and the wiring substrate 10, and a semiconductor chip. 2 and a sealing resin 4 that seals the plurality of wires 3, and a solder ball (solder material) 5 that is formed on the back surface 10 b side of the wiring substrate 10 and is electrically connected to the semiconductor chip 2. Yes. The solder balls 5 are external electrodes (external connection terminals) for electrically connecting the semiconductor device 1 and the mounting board (motherboard).

  The mounting method of the semiconductor chip 2 on the wiring substrate 10 is a face-down mounting in which the main surface 2a side on which the plurality of pads 2c are formed is opposed to the surface 10a of the wiring substrate 10 and is mounted via a plurality of bump electrodes. A system (flip chip mounting system) and a face-up mounting system in which the back surface 2b located on the opposite side of the main surface 2a is mounted facing the front surface 10a as shown in FIG. In this embodiment, a face-up mounting method is used, and for example, a wire 3 is used as a conductive member that electrically connects the semiconductor chip 2 and the wiring board 10 as shown in FIG. The face-up mounting method has an advantage that the manufacturing cost can be reduced as compared with the face-down mounting method.

  In the face-up mounting method, the semiconductor chip 2 and the wiring substrate 10 are electrically connected by a wire bonding method. That is, a plurality of pads (electrodes, chip electrodes) 2c formed on the main surface 2a of the semiconductor chip 2 and the periphery of the semiconductor chip 2 in a plan view so as to be exposed on the surface 10a side of the wiring substrate 10 are arranged. A plurality of bonding leads (terminals, bonding pads) 11 are electrically connected via a plurality of wires 3. In the wire bonding method, since the joint portion of the wire 3 (joint portion with the pad 2c and the bonding lead 11) can be easily visually recognized, even if a connection failure occurs, this can be easily found. That is, the reliability of the finished semiconductor device 1 is high.

  However, in a state where the wire 3 is exposed, if the wire 3 is deformed due to an impact or the like, it may cause a short circuit or the like, and thus it is necessary to prevent deformation of the plurality of wires 3. Therefore, as shown in FIG. 4, the sealing resin 4 is formed on the surface 10 a of the wiring substrate 10, and the semiconductor chip 2 and the wire 3 are sealed, thereby protecting the wire 3.

  A plurality of solder balls 5 are formed on the back surface 10 b located on the opposite side of the front surface 10 a of the wiring substrate 10. The plurality of solder balls 5 are electrically connected to the bonding leads 11 formed on the surface 10 a side via the plurality of wirings 12 formed on the wiring substrate 10. For this reason, when the semiconductor device 1 is mounted on a mounting board (not shown), the solder balls 5 are joined and electrically connected to terminals (not shown) of the mounting board. That is, the solder ball 5 becomes an external electrode (external connection terminal) of the semiconductor device 1.

  Further, as shown in FIG. 2, the plurality of solder balls 5 are arranged in a matrix on the back surface 10 b side of the wiring substrate 10. That is, the semiconductor device 1 is a so-called area array type semiconductor device in which a plurality of external electrodes are arranged in a matrix on the back surface (mounting surface) 10 b side of the wiring substrate 10. The area array type semiconductor device can effectively utilize the back surface 10b side of the wiring substrate 10 as a space for arranging external electrodes. For this reason, for example, the number of external electrodes is increased as compared with a semiconductor device using a lead frame as a base material on which a semiconductor chip is mounted, such as QFP (Quad Flat Package) and QFN (Quad Flat Non-leaded Package). This is advantageous in that

  As the area array type semiconductor device, a BGA (Ball Grid Array) type semiconductor device in which solder balls 5 are attached as external electrodes, as in the semiconductor device 1 of the present embodiment, may be used. There is also an LGA (Land Grid Array) type semiconductor device in which a land 13 for attaching a joining member is exposed. Since the solder ball 5 functions as a bonding material when the semiconductor device is mounted on the mounting board (motherboard), the BGA type semiconductor device is advantageous in that it can be easily mounted on the mounting board.

  The solder ball 5 of the present embodiment is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only tin (Sn), tin-bismuth (Sn-Bi), or tin-copper- For example, silver (Sn—Cu—Ag). Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHs (Restriction of Hazardous Substances) directive. Hereinafter, in the present embodiment, when a solder or solder ball is described, it indicates a lead-free solder unless otherwise specified.

<Wiring board>
Next, details of the wiring board 10 shown in FIGS. 1 to 4 will be described. 5 is a plan view showing the surface side of the wiring board shown in FIG. 3, FIG. 6 is an enlarged plan view of a portion B shown in FIG. 5, and FIG. 7 is an enlarged cross-sectional view taken along line CC in FIG. .

  As shown in FIG. 7, the wiring board 10 includes an upper surface (main surface) 14a, a lower surface (back surface) 14b positioned on the opposite side of the upper surface 14a, and a side surface 14c positioned between the upper surface 14a and the lower surface 14b (see FIG. 4). ) Having an insulating layer (core layer) 14. The insulating layer 14 is made of, for example, a prepreg obtained by impregnating glass fiber or carbon fiber with a resin. The upper surface 14a and the lower surface 14b of the insulating layer 14 are covered with insulating films (solder resist film, protective film) 16 and 17, respectively. The insulating films 16 and 17 are protective films that are formed so as to cover the plurality of wirings 12 formed on the upper surface 14a and the lower surface 14b of the insulating layer 14 and prevent a short circuit or disconnection between the plurality of wirings 12. Accordingly, the insulating film (upper surface side insulating film) 16 is formed on the front surface 10 a that is the uppermost surface of the wiring substrate 10, and the insulating film (lower surface side insulating film) 17 is formed on the rear surface 10 b that is the lowermost surface of the wiring substrate 10. Has been.

  In the present application, the upper surface of the insulating film 16 that is the uppermost surface of the wiring substrate 10 and the upper surface 14a of the insulating layer 14 on which the uppermost wiring of the wiring substrate 10 is formed will be described separately. That is, as shown in FIG. 7, the surface 10 a of the wiring substrate 10 refers to the upper surface (outermost surface) of the insulating film 16 disposed on the uppermost layer of the wiring substrate 10, and the upper surface of the insulating layer 14 inside the wiring substrate 10. It is distinguished from 14a. Similarly, the back surface 10b of the wiring substrate 10 refers to the lower surface (outermost surface) of the insulating film 17 disposed in the lowermost layer of the wiring substrate 10, and is distinguished from the lower surface 14b of the insulating layer 14 inside the wiring substrate 10. .

  As shown in FIG. 5, the wiring board 10 forms a quadrangle in plan view. A chip mounting area 10c for mounting the semiconductor chip 2 (see FIG. 3) is provided on the surface 10a of the wiring board 10. In the present embodiment, the chip mounting area 10c forms a quadrangle along the outer shape of the wiring board 10 in a plan view, and is disposed at, for example, the approximate center (central part) of the surface 10a. A plurality of bonding leads (terminals and bonding pads) 11 are formed on the upper surface 14a around the chip mounting area 10c. The plurality of bonding leads 11 are made of, for example, copper (Cu), and a plating film (not shown) is formed on the surface thereof. In the present embodiment, the plating film is, for example, a laminated film in which a gold (Au) film is laminated on a nickel (Ni) film.

  Further, as shown in FIG. 5, the plurality of bonding leads 11 are arranged along each side of the chip mounting region 10c. In the present embodiment, a plurality of bonding leads 11 are arranged in one row along each side of the chip mounting region 10c (in other words, each side of the semiconductor chip 2). However, the arrangement of the bonding leads is not limited to the mode shown in FIG. 5. For example, the bonding leads may be arranged in a plurality of rows along each side of the chip mounting region 10 c (in other words, each side of the semiconductor chip 2). . In this case, an increase in the arrangement space of the bonding leads 11 can be suppressed, and a large number of bonding leads 11 can be arranged. Therefore, the present invention is effective when applied to a small-sized, narrow-pitch, multi-pin semiconductor device. .

  Each bonding lead 11 is exposed from the insulating film 16 in an opening 16a formed in the insulating film 16 covering the upper surface 14a of the insulating layer 14 as shown in FIG. In the present embodiment, as shown in FIG. 6, an opening 16 a smaller than the bonding lead 11 is formed at a position overlapping the bonding lead 11 of the insulating film 16, and a part of the bonding lead 11 is exposed.

  Each bonding lead 11 is electrically connected to a land (terminal, electrode) 13 formed on the lower surface 14 b of the insulating layer 14 via wiring 12 formed on a plurality of wiring layers of the wiring substrate 10. . Specifically, the wiring board 10 has a plurality of wiring layers. 4 and 7 show two wiring layers including a wiring layer formed on the upper surface 14a and a wiring layer formed on the lower surface 14b. In each wiring layer, a plurality of wirings 12 made of, for example, copper (Cu) are formed, and one surface (in this embodiment, the upper surface 14a) of the upper surface 14a and the lower surface 14b from the other surface (the main surface) In the embodiment, the wiring 12 of each wiring layer is electrically connected through the wiring (in-via wiring, interlayer wiring) 15 in the via (hole) 15a formed toward the lower surface 14b) side. The via 15 a is formed so as to penetrate from the upper surface 14 a to the lower surface 14 b, and electrically connects the wiring 12 a formed on the upper surface 14 a and the wiring 12 b formed on the lower surface 14 b via the wiring 15. . As shown in FIG. 7, the bonding lead 11 formed on the upper surface 14a of the insulating layer 14 is formed integrally with a plurality of wirings (uppermost layer wirings) 12a formed on the upper surface 14a. On the other hand, the land 13 formed on the lower surface 14b of the insulating layer 14 is formed integrally with the wiring (lowermost layer wiring) 12b formed on the lower surface 14b. That is, the conductive path connected to the plurality of bonding leads 11 is drawn out to the lower surface 14 b side via the wirings 12 and 15 and is electrically connected to the plurality of lands 13. Each land 13 is exposed from the insulating film 17 in the opening 17a formed in the insulating film 17 covering the lower surface 14b of the insulating layer 14 as shown in FIG. In the present embodiment, an opening 17a smaller than the land 13 is formed at a position overlapping the land 13 of the insulating film 17, and a part of the land 13 is exposed. As shown in FIG. 4, a plurality of solder balls 5, which are external electrodes, are joined to the plurality of lands 13, so that the plurality of bonding leads 11 are electrically connected to the plurality of solder balls 5.

  The plurality of lands 13 are made of, for example, copper (Cu), and a plating film (not shown) is formed on the surface thereof. In the present embodiment, the plating film is, for example, a laminated film in which a gold (Au) film is laminated on a nickel (Ni) film. Although not shown, the plurality of lands 13 are arranged in a matrix (array or matrix) on the lower surface 14b in the same manner as the solder balls 5 shown in FIG. In other words, the solder balls 5 are joined to the exposed portions of the plurality of lands 13 arranged in a matrix.

  6 and 7 show the wiring 12 extending from the bonding lead 11 toward the outer peripheral side of the wiring substrate 10 (left side with respect to the paper surface on which FIG. 6 or FIG. 7 is described). The wiring 12 is a power supply line 12c when the wiring 12 and the bonding lead 11 are formed on the upper surface 14a of the insulating layer 14 (FIG. 7) by an electrolytic plating method.

  In the present embodiment, a wiring board having two wiring layers in which the wiring 12 is formed on the upper surface 14a and the lower surface 14b of the insulating layer 14 is shown. However, the number of wiring layers of the wiring board 10 is not limited to two. For example, a so-called multilayer wiring board in which a plurality of wiring layers (wirings 12) are formed in the insulating layer 14 can be used. In this case, by further forming a wiring layer between the uppermost wiring layer and the lowermost wiring layer, it is possible to increase the space for routing the wiring, which is particularly effective when applied to a semiconductor device having a large number of terminals. is there. An example of an embodiment using a multilayer wiring board will be described in a second embodiment to be described later.

<Semiconductor chip>
Next, the semiconductor chip 2 mounted on the wiring board 10 will be described.

  As shown in FIG. 4, the semiconductor chip 2 of the present embodiment includes a main surface (first main surface) 2a, a back surface (second main surface) 2b located on the opposite side of the main surface 2a, and the main surface 2a It has a side surface located between the back surface 2b. As shown in FIG. 3, the planar shape of the semiconductor chip 2 (the shape of the main surface 2a and the back surface 2b) is substantially rectangular.

  On the main surface 2a of the semiconductor chip 2, a plurality of pads (electrodes, chip electrodes) 2c are formed. The plurality of pads 2 c are arranged on the peripheral edge side on the main surface 2 a along each side of the semiconductor chip 2.

  A plurality of semiconductor elements (circuit elements) such as diodes and transistors are formed on the main surface 2a of the semiconductor chip 2, and a plurality of wirings (wiring layers) (not shown) formed on the semiconductor elements are provided. Each is electrically connected to the pad 2c. Thus, the semiconductor chip 2 constitutes an integrated circuit by a plurality of semiconductor elements formed on the main surface 2a and wirings that electrically connect the plurality of semiconductor elements.

  In addition, the base material (semiconductor substrate) having the main surface 2a which is a semiconductor element formation surface of the semiconductor chip 2 is made of, for example, silicon (Si). In addition, a passivation film (not shown) that is an insulating film is formed on the outermost surface on the main surface 2a, and each surface of the plurality of pads 2c is insulated in the opening formed in the passivation film. Exposed from the membrane.

  The pad 2c is made of metal, and in this embodiment, is made of, for example, aluminum (Al). Further, a plating film is formed on the surface of the pad 2c. In the present embodiment, for example, a multilayer plating film having a multilayer structure in which a gold (Au) film is formed via a nickel (Ni) film is used. is there.

  In the present embodiment, the semiconductor chip 2 is mounted by a so-called face-up mounting method in which the semiconductor chip 2 is mounted on the chip mounting region 10c with the back surface 2b facing the front surface 10a of the wiring board 10. The semiconductor chip 2 is fixed on the surface 10a of the chip mounting area 10c through the adhesive material 6. The adhesive 6 is not particularly limited as long as it can firmly fix the semiconductor chip 2 to the surface 10a of the wiring board 10, but in the present embodiment, for example, an epoxy-based thermosetting resin is used.

  Further, as shown in FIGS. 3 and 4, the semiconductor chip 2 is electrically connected to the wiring substrate 10 through a plurality of wires 3. Specifically, one end of the wire 3 is connected to the pad 2 c on the main surface 2 a of the semiconductor chip 2, and the other is connected to the bonding lead 11 of the wiring substrate 10. In the present embodiment, the wire 3 is made of gold (Au), and is bonded to the gold plating film formed on the surface of the pad 2c of the semiconductor chip 2 and the bonding lead 11 of the wiring substrate 10 by Au—Au bonding. .

<Sealing resin>
Next, the sealing resin 4 that seals the semiconductor chip 2, the plurality of wires 3, and the plurality of bonding leads 11 will be described. As shown in FIG. 4, the sealing resin 4 of the present embodiment is formed on the surface 10 a of the wiring substrate 10 and seals the semiconductor chip 2, the plurality of wires 3, and the plurality of bonding leads 11. .

  In addition, the sealing resin 4 does not cover the entire surface 10a of the wiring substrate 10, but the peripheral portion of the wiring substrate 10 (in other words, the periphery of the semiconductor chip 2 mounted on the surface 10a of the wiring substrate 10) is the sealing resin. 4 is exposed. Generally, in a resin-encapsulated semiconductor device in which a sealing resin is formed on the surface of a wiring board, warping occurs due to a difference in linear expansion coefficient between the wiring board and the sealing resin. The degree of warpage increases in proportion to the planar size of the semiconductor device and the amount (volume) of the sealing body (sealing resin) to be formed. When the degree of warpage increases, the flatness on the mounting surface side (for example, the back surface 10b side in this embodiment) decreases, so that some external electrodes are mounted when mounted on a mounting board (not shown). This causes a mounting defect that does not connect to the land on the board side. In the semiconductor device 1 according to the present embodiment, a part (peripheral part) of the surface 10a of the wiring substrate 10 is exposed from the sealing resin 4, so that the entire surface 10a is covered with the sealing resin 4. Warpage can be reduced (suppressed) as compared with the apparatus. Therefore, it is particularly effective when applied to a large semiconductor device. For example, in the present embodiment, the planar size of the wiring board 10 is, for example, a quadrangle whose one side is 30 mm to 40 mm. On the other hand, on the surface 10a shown in FIG. 1, the exposed portion 10d from the sealing resin 4 disposed so as to surround the periphery of the sealing resin 4 has a frame shape having a width of about 1 mm to 2 mm, for example.

<Manufacturing process of semiconductor device>
Next, the manufacturing process of the semiconductor device 1 shown in FIGS. 1 to 4 will be described. The semiconductor device 1 in the present embodiment is manufactured along the assembly flow shown in FIG. FIG. 8 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS. Details of each step will be described below with reference to FIGS.

1. Substrate preparation process;
First, as a substrate preparation step (S1) shown in FIG. 8, a wiring substrate 20 as shown in FIG. 9 is prepared. 9 is a plan view showing the entire structure of the wiring board prepared in the board preparation step shown in FIG. 8, FIG. 10 is an enlarged plan view of a portion D shown in FIG. 9, and FIG. 11 is the back side of the wiring board shown in FIG. FIG. 12 is an enlarged cross-sectional view along the line EE shown in FIG.

  As shown in FIG. 9, the wiring substrate (substrate) 20 prepared in this step includes a plurality of device regions 20a inside a frame portion (frame body) 20b. Specifically, a plurality of device regions 20a are arranged in a matrix. The number of device regions 20a is not limited to the mode shown in FIG. 9, but the wiring board 20 of the present embodiment has, for example, 16 device regions arranged in a matrix (2 rows × 8 columns in FIG. 9). 20a. That is, the wiring board 20 is a so-called multi-piece board having a plurality of device regions 20a.

  Each device region 20a corresponds to the wiring substrate 10 shown in FIG. 5, and each member of the wiring substrate 10 described with reference to FIGS. 5 to 7 is formed. For example, as shown in FIG. 10, on the surface 10a of each device region 20a, a chip mounting region 10c and a plurality of bonding leads (terminals, bondings) arranged around the chip mounting region 10c and exposed from the insulating film 16 are arranged. Pad) 11 is formed. As shown in FIG. 11, on the back surface 10b of the wiring board 20, a plurality of lands 13 exposed from the insulating film 17 are arranged in a matrix in each device region 20a.

  In addition, around each device region 20a (between adjacent device regions among the plurality of device regions 20a), dicing is a region where the wiring substrate 20 is to be cut in the singulation step (S7) shown in FIG. A region (dicing line) 20c is arranged. As shown in FIG. 9, the dicing area 20c is arranged so as to surround each device area 20a between the adjacent device areas 20a and between the frame portion 20b and the device area 20a. Each device region 20a has, for example, a quadrangle with a side length of 30 mm to 40 mm. Further, the width of the dicing region 20c forming the frame shape is, for example, 200 μm to 400 μm.

  Here, the dicing region 20c is a region to be cut by a dicing blade (rotating blade) in the individualization step (S7) described later. In the individualization step, the dicing region 20c is a region in the dicing region 20c. A part is cut. Further, in consideration of the alignment accuracy between the dicing blade and the wiring substrate 20 and the thermal influence during the cutting process, the width of the dicing region 20c is wider than the width of the dicing blade. For this reason, the uncut portion of the dicing region 20c may remain on the peripheral edge of the wiring substrate 10 (see FIG. 1) of the completed semiconductor device 1 (see FIG. 1).

  The wiring board 20 shown in FIGS. 9-12 is manufactured as follows, for example. First, an insulating layer 14 is prepared, and vias (holes, through holes) 15a are formed from the upper surface 14a to the lower surface 14b as shown in FIG. 12, and then a conductor is embedded in the vias 15a to form wirings 15. To do.

  Next, wiring patterns are formed on the upper surface 14a and the lower surface 14b of the insulating layer 14, respectively. Specifically, a plurality of wirings 12 and a plurality of bonding leads 11 are formed on the upper surface 14a of the insulating layer 14, and a plurality of wirings 12 and a plurality of lands 13 are formed on the lower surface 14b. For example, the wiring pattern is formed by electrolytic plating using a semi-additive method.

  Next, an insulating film 16 covering the upper surface 14a of the insulating layer 14 and an insulating film 17 covering the lower surface 14b are formed. The insulating films 16 and 17 are formed (covered) so as to cover the wiring 12 formed on the upper surface 14a or the lower surface 14b of the insulating layer 14 and cured. For this reason, the surfaces of the insulating films 16 and 17 have irregularities following the shape of the wiring 12. That is, the flatness of the surfaces of the insulating films 16 and 17 is lower than the flatness of the upper surface 14 a or the lower surface 14 b of the insulating layer 14.

  Next, an opening 16a is formed in the insulating film 16, and an opening 17a is formed in the insulating film 17, and the plurality of bonding leads 11 and the plurality of lands 13 are exposed. The openings 16a and 17a are formed by etching, for example.

  Next, an etching process is performed on the dicing region 20c, and the insulating films 16 and 17 and the wiring 12 (feeding line 12c) in the dicing region 20c are removed. Thereby, the opening grooves 16b and 17b shown in FIG. 12 are formed in the dicing region 20c, and the upper surface 14a or the lower surface 14b of the insulating layer 14 is exposed from the insulating films 16 and 17. The opening grooves 16b and 17b are formed along the dicing region 20c. By removing the wiring 12 (feeding line 12c) in the dicing region 20c, the bonding leads 11 in the device region 20a are electrically connected to each other. To be separated. In addition, the lands 13 in the device region 20a are also electrically separated. Therefore, an electrical test such as a continuity test can be performed on each device region of the wiring board 20.

2. Semiconductor chip preparation process;
Further, as the semiconductor chip preparation step (S2) shown in FIG. 8, the semiconductor chip 2 shown in FIG. 3 is prepared. In this step, for example, a semiconductor wafer made of a plurality of semiconductor elements and a wiring layer electrically connected thereto is prepared on the main surface side of a semiconductor wafer made of silicon (not shown). Thereafter, a dicing blade is run along the dicing line of the semiconductor wafer (not shown) to cut the semiconductor wafer, thereby obtaining a plurality of semiconductor chips 2 shown in FIG.

3. Die bonding process;
Next, the die bonding step (S3) shown in FIG. 8 will be described. 13 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the wiring board shown in FIG. 10, and FIG. 14 is an enlarged cross-sectional view taken along line FF shown in FIG.

  In this step, the semiconductor chip 2 is mounted (adhered) on the chip mounting region 10c (chip mounting step). As shown in FIG. 14, in the present embodiment, the semiconductor chip 2 is mounted on the chip mounting area 10c via the adhesive 6 so that the back surface 2b of the semiconductor chip 2 faces the front surface 10a of the chip mounting area 10c (face). Up implementation).

  In the present embodiment, for example, the semiconductor chip 2 is mounted via an adhesive 6 that is an epoxy thermosetting resin. The adhesive 6 is a paste that has fluidity before being cured (thermoset). It is a material. Thus, when using a paste material as a die-bonding material, first, the adhesive material 6 is apply | coated on the chip | tip mounting area | region 10c, and the back surface 2b of the semiconductor chip 2 is adhere | attached on the surface 10a of the wiring board 20 after that. Then, after bonding, when the adhesive 6 is cured (for example, heat treatment is performed), the semiconductor chip 2 is fixed on the chip mounting region 10c via the adhesive 6 as shown in FIG.

  In the present embodiment, an embodiment in which a paste material made of a thermosetting resin is used as the adhesive 6 has been described, but various modifications can be applied. For example, instead of a paste material, an adhesive material, which is a tape material (film material) having adhesive layers on both sides, is attached in advance to the back surface 2b of the semiconductor chip 2, and the semiconductor chip 2 is attached to the chip mounting region via the tape material. It may be mounted on 10c.

4). Wire bonding process;
Next, the wire bonding step (S4) shown in FIG. 8 will be described. FIG. 15 is an enlarged plan view showing a state in which the semiconductor chip and the wiring board shown in FIG. 13 are electrically connected by wire bonding, and FIG. 16 is a diagram showing an electrical connection between the semiconductor chip and the wiring board shown in FIG. It is an expanded sectional view which shows the state connected to.

  In this step, as shown in FIGS. 15 and 16, the wiring substrate 20 and the plurality of semiconductor chips 2 are electrically connected through the plurality of wires 3, respectively. Specifically, a plurality of pads 2 c formed on the main surface of the semiconductor chip 2 and a plurality of bonding leads 11 formed on the surface 10 a side of the wiring substrate 20 and exposed from the insulating film 16 are connected via a plurality of wires 3. Connect them electrically. In the present embodiment, wire bonding is performed by a so-called positive bonding method in which the pad 2c of the semiconductor chip 2 is the first bond side and the bonding lead 11 of the wiring substrate 20 is the second bond side, and the pad 2c and the bonding lead 11 are formed. Are electrically connected.

  The wire 3 is made of metal, and is made of, for example, gold (Au) in the present embodiment. Therefore, as described above, by forming gold (Au) on the surface of the pad 2c of the semiconductor chip 2, the bondability between the wire 3 and the pad 2c can be improved, so that wire bonding failure can be prevented. it can.

5. Sealing step;
Next, the sealing step (S5) shown in FIG. 8 will be described. FIG. 17 is an enlarged cross-sectional view showing a state where the wiring board shown in FIG. 16 is clamped with a molding die. FIG. 18 is an enlarged cross-sectional view showing a state in which the sealing resin is supplied into the cavity shown in FIG. 19 is an enlarged plan view showing a state in which the semiconductor chip and the wire shown in FIG. 15 are sealed with resin, and FIG. 20 is a cross-sectional view taken along the line FF in FIG.

  In this step, first, a molding die 30 shown in FIG. 17 is prepared (die preparation step). The molding die 30 includes a lower die (die surface) 31a, and an upper die (die) 31 having a cavity (recessed portion, hollow portion) 31b formed on the lower surface 31a, and a lower surface (die) of the upper die 31. A lower mold (mold) 32 having an upper surface (mold surface) 32 a facing the mold surface 31 a is provided. Since FIG. 17 and FIG. 18 are enlarged sectional views, one cavity 31 b is shown, but the cavity 31 b of the upper mold 31 is formed for each device region 20 a of the wiring board 20. For example, since the wiring board 20 of the present embodiment has 16 device regions 20a as shown in FIG. 9, the upper mold 31 shown in FIGS. 17 and 18 has 16 cavities 31b. is doing.

  Each cavity 31b has a substantially rectangular planar shape (rectangular shape, quadrilateral shape) with four corners chamfered. Further, the upper mold 31 has a gate portion 31c which is a supply port of the sealing resin 4a (see FIG. 18) to the cavity 31b, and an air vent portion (not shown) disposed at a position different from the gate portion 31c. ) Are formed. For example, as shown in FIG. 17, the gate portion 31c is formed on the top surface of the cavity 31b (the bottom surface of the recess). That is, in the present embodiment, a so-called top gate method is used in which a sealing resin is supplied from the top surface of the cavity 31 b toward the surface of the wiring substrate 20.

  In the present embodiment, an air vent portion (not shown) is formed at each of the four corner portions of the cavity 31b. In the cavity 31b, the sealing resin flows from the gate portion 31c toward the air vent portion. Therefore, the sealing resin is firmly filled in the corner portion of the cavity 31b by arranging the air vent portion at the four corner portions. Because it can be done.

  Next, the wiring board 20 is arranged on the lower mold 32 of the molding die 30 (base material arranging step). Here, the cavity 31b formed in the upper mold 31 combined with the lower mold 32 has a smaller area than each device region 20a of the wiring board 20, and the peripheral portion of the device region 20a is more than the cavity 31b in plan view. Is also located outside.

  Next, the distance between the upper mold 31 and the lower mold 32 is reduced, and the wiring board 20 is clamped with the upper mold 31 and the lower mold 32 (clamping process). Thereby, the upper mold 31 (the lower surface 31a of the upper mold 31) and the surface 10a of the wiring substrate 20 are in close contact with each other in the cavity 31b, the region other than the gate portion 31c, and the air vent portion. Further, the lower mold 32 (the upper surface 32a of the lower mold 32) and the back surface 10b of the wiring board 20 are in close contact. In the present embodiment, the cavity 31b has a smaller (smaller) area (outer size) than each device region 20a of the wiring board 20, so that a part of the surface of the device region 20a (region outside the cavity 31b) is The upper mold 31 is in close contact with the lower surface 31a.

  In addition, in order to improve the adhesiveness in a clamping process, the film which consists of soft resins, such as a polyimide resin, for example can be affixed on the lower surface 31a side of the upper metal mold 31, and it can also contact | adhere through this film. In this case, the film and the sealing resin 4 can be easily peeled in the substrate take-out process described later.

  Next, the sealing resin 4a is supplied into the cavity 31b and cured to form the sealing resin 4 (sealing body forming step). In this step, the resin tablet disposed in the pot portion (not shown) is softened by heating, and the sealing resin 4a is supplied from the gate portion 31c into the cavity 31b, and is formed by a transfer mold method. The resin tablet is made of, for example, an epoxy-based resin that is a thermosetting resin, and has a characteristic of being softened by heating and improving fluidity at a temperature lower than the curing temperature. Therefore, for example, when a softened resin tablet is pushed in by a plunger (not shown), the sealing resin 4a enters the cavity 31b (specifically, on the surface 10a side of the wiring board 20) from the gate portion 31c formed in the molding die 30. Flows in. The gas in the cavity 31b is discharged from the air vent portion by the pressure at which the sealing resin 4a flows, and the cavity 31b is filled with the sealing resin 4a. As a result, the semiconductor chip 2 and the plurality of wires 3 mounted on the surface 10a side of the wiring board 20 are sealed with the sealing resin 4a. At this time, the bonding leads 11 of the wiring board 20 are also sealed. Thereafter, by heating the inside of the cavity 31b, the sealing resin 4a is heat-cured (temporarily cured) to form the sealing resin 4.

  Next, the wiring board 20 on which the plurality of sealing resins 4 are formed is taken out from the molding die 30 used in the above-described sealing body forming step (substrate taking step). In this step, after the gate resin (resin in gate) 4b in which the sealing resin 4a in the gate portion 31c shown in FIG. 18 is cured is divided (gate break) from the sealing resin 4 in the cavity 31b, the upper mold 31 and the lower mold 32 are pulled apart to take out the wiring board 20.

  Next, the wiring board 20 taken out from the molding die 30 is transferred to a baking furnace (not shown), and the wiring board 20 is heat-treated again. The sealing resin 4a heated in the molding die 30 is in a so-called temporary curing state in which more than half (for example, about 70%) of the curing component in the resin is cured. In this temporarily cured state, not all of the cured components in the resin are cured, but more than half of the cured components are cured, and at this point, the semiconductor chip 2 and the wires 3 are sealed. . However, since it is preferable to completely cure all the curing components from the viewpoint of strength stability of the sealing resin 4, so-called main curing, in which the temporarily cured sealing resin 4 is heated again in the baking step. I do. As described above, the step of curing the sealing resin 4a is divided into two times, so that the next wiring substrate 20 that is next transferred to the molding die 30 can be quickly subjected to the sealing step. For this reason, manufacturing efficiency can be improved.

  Next, for example, resin burrs remaining in the gate portion 31c and the air vent portion are removed. Although the removal method is not particularly limited, for example, it can be removed by laser irradiation.

  By performing the above-described sealing process, as shown in FIG. 19, a part of the surface in each of the plurality of device regions 20a (peripheral portion on the surface 10a of the wiring substrate 10 shown in FIG. 1) and the dicing region 20c Sealing resin (sealing body) that seals the semiconductor chip 2 and the plurality of wires (conductive members) 3 so that the surface (in this embodiment, the upper surface 14a of the insulating layer 14 shown in FIG. 20) is exposed. 4 is formed in each device region 20 a of the wiring substrate 20.

6). Ball mounting process;
Next, the ball mounting step (S6) shown in FIG. 8 will be described. FIG. 21 is an enlarged cross-sectional view showing a state in which a plurality of solder balls serving as external electrodes (external connection terminals) of the semiconductor device are formed (joined) on the back surface of the wiring board shown in FIG.

  In this step, a plurality of solder balls (solder materials) 5 are mounted on each of the plurality of lands 13 formed on the back surface 10b side of the wiring board 20 shown in FIG. More specifically, first, as shown in FIG. 21, the wiring board 20 is turned upside down, and a plurality of solder balls 5 are respectively disposed on the plurality of lands 13 exposed from the insulating film 17 on the back surface 10 b of the wiring board 20. . Subsequently, heat treatment (reflow) is performed on the wiring board 20 on which the solder balls 5 are arranged, and the plurality of solder balls 5 are melted and bonded to the plurality of lands 13 respectively. In the reflow process, the wiring board 20 is placed in a reflow furnace and heated to a temperature higher than the melting point of the solder balls 5, for example, 260 ° C. or higher. Since the insulating film 17 is a solder resist film, it is possible to prevent bonding (bridge) between adjacent solder balls 5.

  In this step, in order to securely bond the solder ball 5 and the land 13, for example, bonding is performed using an activator called a flux. For example, the flux can be removed by coming into contact with an oxide film formed on the surface of the solder ball 5, so that the wettability of the solder ball 5 can be improved. When bonding is performed using the flux in this way, cleaning is performed to remove the residue of the flux component after the heat treatment.

7). Individualization step;
Next, the individualizing step (S7) shown in FIG. 8 will be described. In the description of this step, the individualization step of the present embodiment and the individualization step of a comparative example for the present embodiment will be described. The order of explanation will be as follows. First, a configuration common to the present embodiment and the comparative example will be described, and then the individualization process and the problem of the comparative example will be described. Finally, the individualization of the present embodiment will be described. The process will be described.

  22 is an enlarged cross-sectional view showing a state in which the wiring board shown in FIG. 21 is cut by a dicing blade, and FIG. 23 is an enlarged cross-sectional view taken along line GG in FIG. 24 is an enlarged plan view showing an upper surface of the fixing jig shown in FIG. 22, and FIG. 25 is an enlarged plan view of a portion H in FIG. FIG. 23 is a cross-sectional view taken along the dicing region of the wiring board. In order to easily understand that the upper and lower surfaces of the wiring board are reversed, the sealing resin or the like formed on the wiring board is indicated by a dotted line. Show.

  In the individualization step, the wiring board 20 is cut (divided) along the dicing area (dicing line) 20c using a dicing blade (rotating blade) 40, and is separated into individual device areas 20a. Specifically, as shown in FIG. 22, either the dicing blade 40 or the wiring board 20 is fixed with the wiring board 20 having the plurality of sealing resins 4 formed on the surface 10 a side fixed on the fixing jig 41. One or both are moved along the dicing region 20c and cut. The dicing blade 40 is a cutting jig (rotating blade) in which abrasive grains such as diamond are fixed to the outer periphery of a thin plate having a substantially circular outer shape, and the abrasive grains fixed to the outer periphery by rotating the thin plate. However, the workpiece is cut and cut.

  It has been described that the semiconductor wafer is cut by the dicing blade in the semiconductor chip preparation step. However, the dicing blade for cutting the semiconductor wafer and the dicing blade for cutting the wiring board 20 have different blade widths (thicknesses). A dicing blade used for cutting a semiconductor wafer is formed to have a relatively narrow width (thin thickness) from the viewpoint of preventing damage to the semiconductor wafer or improving the efficiency of the obtained chip. For example, in the present embodiment, cutting is performed with a dicing blade having a width of about 30 μm to 100 μm. Since the semiconductor wafer is mainly composed of a semiconductor material such as silicon (Si), for example, even if such a thin dicing blade is used, the dicing blade is hardly damaged. On the other hand, when cutting the wiring substrate 20 which is a so-called rigid substrate, the dicing blade having a narrow width described above is likely to be damaged due to cutting resistance of the wiring substrate 20 or the like. As described above, the insulating layer 14 of the wiring board 20 is made of a material harder than the semiconductor wafer (semiconductor chip 2), such as a prepreg. Moreover, the thickness of the wiring board 20 is also thicker than the thickness of the semiconductor wafer (semiconductor chip 2) (for example, 200 μm to 400 μm in the present embodiment). For this reason, a dicing blade having a narrow width is easily damaged, the replacement frequency accompanying the damage is increased, and the manufacturing efficiency is lowered. Further, if the dicing blade is damaged during the cutting process, it may cause a cutting failure. Therefore, the dicing blade 40 for cutting the wiring board 20 is wider than the dicing blade used in the semiconductor chip preparation process. For example, in this embodiment, it is set to 200 μm to 300 μm. Thereby, even if the wiring board 20 is cut, the replacement frequency due to the damage of the dicing blade 40 can be reduced, so that the manufacturing efficiency can be improved. Moreover, it can suppress that the dicing blade 40 is damaged during cutting and becomes defective in cutting. The other structure of the dicing blade 40 will be described in detail after describing the comparative example.

  Further, in the singulation process using a rotary blade such as the dicing blade 40, the wiring board 20 is moved in the cutting direction 44 while the dicing blade 40 is rotated in the rotation direction 43 as shown in FIG. Then, cutting is performed sequentially along the dicing region 20c (see FIG. 22) of the wiring board 20 and cut.

  There are generally two types of rotation directions of the dicing blade 40. That is, as shown in FIG. 23, one is a down-cut method that rotates from the back surface 10b of the wiring board 20 toward the front surface 10a. In the down-cut method, in the case of a cutting method in which the wiring board 20 that is a workpiece is moved, the dicing blade 40 cuts the cutting object forward with respect to the cutting direction (movement direction) 44 of the wiring board 20. Rotate. And although illustration is abbreviate | omitted, another is an upper cut system rotated from the surface 10a of the wiring board 20 toward the back surface 10b. In the upper cut method, in the case of a cutting method in which the wiring board 20 that is a workpiece is moved, the dicing blade 40 cuts the cutting object backward with respect to the cutting direction (movement direction) 44 of the wiring board 20. Rotate. Since the down cut method shown in FIG. 23 rotates so as to hold the cutting region of the wiring substrate 20 to the fixing jig 41, the wiring substrate 20 is easier to fix than the upper cut method. For this reason, in this Embodiment, the down cut system is employ | adopted.

  Further, at the time of cutting, the wiring substrate 20 is cut while spraying (supplying) the cutting fluid 45 onto the dicing blade 40. The cutting liquid 45 is used as a lubricating liquid for improving the lubricity during cutting, as a cleaning liquid for discharging cutting waste generated during cutting to the outside, and for the dicing blade 40 and the wiring board 20 due to frictional heat during cutting. It is used as a coolant that suppresses temperature rise.

  Further, as a method of sequentially cutting along the dicing region 20c, a method of moving the dicing blade 40 as well as a method of moving the dicing blade 40 as shown in FIG. A method of moving both can be used. However, since the cutting can be performed with higher accuracy when the position of the rotating body is fixed and cut than when the rotating body such as the dicing blade 40 is moved, the fixing jig is used in the present embodiment. 41, a method of moving the wiring board 20 in the cutting direction 44 is employed.

  Further, in the singulation process using a rotary blade such as the dicing blade 40, the periphery of the area where the workpiece is cut during the cutting process (the dicing area 20c in the present embodiment) is firmly fixed. It is necessary. In addition, in order to prevent the separated semiconductor device from being scattered around, it is necessary to fix the semiconductor device for each device region 20a of the wiring substrate that is the object to be cut.

  Therefore, in the present embodiment, cutting is performed by the dicing blade 40 (see FIG. 22) in a state in which the wiring substrate 20 that is an object to be cut is fixed on the fixing jig 41 shown in FIG.

  A plurality of recesses 41 b are formed on the upper surface 41 a of the fixing jig 41 (placement surface of the wiring board 20) at a position overlapping the sealing resin 4 formed on the wiring board 20. The recess 41b is a recess for accommodating (embedding) each of the plurality of sealing resins 4 formed on the wiring board 20 shown in FIG. Therefore, the upper surface 41a of the fixing jig 41 corresponds to the number of sealing resins 4 arranged on the fixing jig 41 at one time (that is, the number of device regions 20a of the wiring board 20 shown in FIG. 9). A plurality of recesses 41b are formed. In the present embodiment, an example in which the wiring board 20 having 16 device regions 20a (see FIG. 9) is arranged is shown, so that 16 recesses 41b are formed as shown in FIG.

  Further, the shape of the recess 41 b is formed following the shape of the sealing resin 4. Specifically, as shown in FIG. 24, the planar shape of the recess 41b forms a substantially quadrangle (quadrangle) along the planar shape of the sealing resin 4 (see FIG. 19), and the size thereof is the sealing resin. 4 is larger than the planar shape. Further, as shown in FIG. 22, the depth of the recess 41 b is set to be equal to or higher than the height of the sealing resin 4.

  The plurality of recesses 41b are formed separately from each other, and a protrusion 41c is formed between adjacent recesses 41b. In addition, a groove 41d into which a dicing blade 40 cut from the wiring board 20 is inserted is formed at each convex portion 41c, specifically, at a position overlapping the dicing area 20c of the wiring board 20 fixed to the fixing jig 41. That is, the fixing jig 41 accommodates the plurality of sealing resins 4 formed on the wiring substrate 20 in the plurality of recesses 41 b, and the upper surface (pressing surface, support surface) 41 e of the recess 41 b and the wiring substrate 20. The wiring board 20 is supported (fixed) by bringing the surface 10a into contact therewith. In the present embodiment, as shown in FIG. 22, the wiring board 20 is turned upside down with the fixing jig 41 so that the surface 10 a side on which the sealing resin 4 is formed faces downward. It is fixed. In the manufacturing process of the BGA type semiconductor device as in the present embodiment, the solder balls 5 can be efficiently formed by forming the solder balls 5 before the singulation process. However, if the back surface 10b side of the wiring board 20 on which the solder balls 5 are formed is fixed downward, the solder balls 5 are damaged in the singulation process, which causes a decrease in electrical reliability.

  The fixing jig 41 is made of, for example, hard rubber, and a vent hole (intake hole) 41f is formed in each recess 41b. The plurality of ventilation holes 41f are, for example, an intake such as a vacuum pump (not shown) through an air passage (gas passage, exhaust passage) 41g formed in a table (base plate) 42 that supports the fixing jig 41. Connected to the device. For this reason, as shown in FIG. 22, when the wiring board 20 is arranged on the fixing jig 41 and sucked from the plurality of vent holes 41f, the surface 10a of the wiring board 20 and the convex part 41c (specifically, the convex part 41c) The upper surface 41e) is in close contact, and the wiring board 20 can be fixed by suction. The convex portion 41c extends along the contour of the concave portion 41b, and a groove portion 41d is formed at the approximate center of the convex portion 41c. The groove 41d also extends along the contour of the recess 41b.

  In the singulation process of the present embodiment, the wiring board 20 is fixed (adsorption fixing) on the fixing jig 41 described above, and for example, while the dicing blade 40 is rotated in the rotation direction 43 shown in FIG. The fixing jig 41 to which the substrate 20 is fixed is moved in the cutting direction 44. Therefore, as shown in FIG. 22, by fixing the wiring board 20 so that the dicing region 20c of the wiring board 20 and the groove 41d overlap each other, the dicing blade 40 penetrates into the groove 41d, and the wiring board 20 Can be cut off. Moreover, since the convex part 41c is arrange | positioned so that it may extend along the dicing area | region 20c of the wiring board 20, the periphery of the dicing area | region 20c can be firmly fixed at the time of the cutting process by the dicing blade 40. FIG. That is, the surface 10a of the wiring board 20 (a part of the surface (peripheral part) in the device region 20a) is brought into contact with (or supported by) the upper surface 41e of the fixing jig 41 (specifically, the convex portion 41c). ) And the surface of the dicing region 20c (in this embodiment, the upper surface 14a of the insulating layer 14) is fixed in a state where it is not brought into contact with (or not supported by) the fixing jig 41. In this state, the dicing blade 40 is inserted into the groove 41d formed on the upper surface 41e side of the fixing jig 41 so as to extend along the dicing region 20c, and the back surface (external electrode (external connection terminal)) in the dicing region 20c. The dicing blade 40 is rotated into the groove portion 41d formed on the upper surface 41e side of the fixing jig 41 from the surface where the wiring board is formed, and the wiring board is divided.

  Further, in the present embodiment, as shown in FIG. 24, a vent hole 41f is formed in each recess 41b. In other words, the vent hole 41f is formed for each device region 20a of the wiring board 20 shown in FIG. That is, as shown in FIG. 22, each device region 20a of the wiring board 20 can be fixed, so that the separated semiconductor device 1 (see FIG. 1) can be prevented from being scattered around. .

<Outline and issues of the individualization process of the comparative example>
However, the inventors of the present application have examined that when the wiring substrate 20 disposed on the fixing jig 41 is cut using a dicing blade having a side-surface orthogonal shape in which the front end surface of the peripheral edge is substantially orthogonal to both side surfaces. It was found that defects occurred. 68 is an enlarged cross-sectional view showing a singulation process as a first comparative example of the present embodiment, and FIGS. 69, 70, and 71 are the lines JJ and KK in FIG. 68, respectively. FIG.

  The singulation process of the first comparative example shown in FIGS. 68 to 71 is the same as the singulation process of the present embodiment except for the tip shape of the dicing blade. The dicing blade 100 of the first comparative example has a side surface orthogonal shape (hereinafter simply referred to as a side surface orthogonal shape) in which the tip surface 100a is substantially orthogonal to both side surfaces 100b. The dicing blade 100 having a ring shape is manufactured as follows, for example. First, one solid made of metal and formed in a cylindrical shape is prepared. A plurality of dicing blades are obtained by slicing the solid. For this reason, unless the tip surface 100a is particularly processed, the side surface is orthogonal as shown in FIGS.

  In general, if the dicing blade is used, the cut surface of the dicing blade is worn out, and therefore, the dicing blade must be replaced when the wear proceeds to some extent. Therefore, in order to reduce the manufacturing cost of the dicing blade, the dicing blade is manufactured with as few manufacturing steps as possible as described above.

  However, it has been found that when the wiring substrate 20 is cut by the dicing blade 100 having the tip surface 100a orthogonal to the side surface, a string-like (band-like) foreign matter 101 is generated as shown in FIG. The string-like foreign matter 101 is made of a constituent material of the workpiece (for example, in this comparative example, the insulating layer 14 of the wiring board 20). The foreign substance 101 has a cross-sectional shape with a thickness of about 20 μm to 30 μm and a width that is the same as the width of the dicing blade 100 (for example, about 200 μm to 300 μm), and a shape that extends long in a string shape (band shape). It has become. Further, the length of the foreign matter 101 was the same as the length along the cutting direction of the cut wiring board 20 in the longest thing. Further, when the generated foreign matter 101 was taken out and observed, the appearance was wound in a coil shape.

  When the long foreign substance 101 is generated in such a string shape, the foreign substance 101 remains in the fixing jig 41 (for example, in the groove 41d) even after the separated semiconductor device is taken out from the fixing jig 41. When the foreign substance 101 is sandwiched between the wiring board 20 to be cut next and the fixing jig 41, the wiring board 20 cannot be firmly fixed to the fixing jig 41. For example, if it is sandwiched between the upper surface 41e of the convex portion 41c and the surface 10a of the wiring board 20, a gap serving as a leak source is generated around the foreign material 101, which causes a suction failure. Further, for example, when the foreign substance 101 is interposed between the wiring board 20 and the fixing jig 41, the position of the wiring board 20 may be shifted. Then, due to these, for example, a cutting defect such as damage to the wiring board 20 due to vibration during cutting processing occurs.

  As a result of examination of the shape and physical properties of the foreign matter 101 by the inventor of the present application, it is considered that the foreign matter 101 was formed as follows.

  In the singulation process, as shown in FIGS. 69 to 71, the dicing blade 100 is pressed and cutting is sequentially performed from the back surface 10 b side to the front surface 10 a side of the wiring substrate 20. Therefore, a pressing force from the dicing blade 100 is applied to the wiring board 20 during the cutting process.

  In the singulation process, the wiring board 20 is moved and cut while rotating the dicing blade 100, which is a thin plate having a substantially circular outer shape, so that the JJ line, KK line, The progress of cutting differs for each cross section (region) along the line LL. For example, in the cross section (region) shown in FIG. 69, since cutting has just started, an uncut region remains on the wiring board 20 (insulating layer 14), which is a workpiece. On the other hand, in the cross section (region) shown in FIG. 71, the dicing blade 100 penetrates the wiring board 20 (insulating layer 14).

  Here, the stress (downward stress) due to the pressing force from the dicing blade 100 whose tip surface 100a is orthogonal to the side surface is concentrated on the end portion (M portion shown in FIGS. 69 and 70) of the cutting region. As shown in FIG. 69, in the region where the thickness of the uncut wiring substrate 20 (insulating layer 14) is sufficiently thick, the fracture is not caused by the stress concentrated on the end of the cutting region, and the cutting is performed. Can do. However, as shown in FIG. 70, in the region where the thickness of the uncut wiring substrate 20 (insulating layer 14) is thin (for example, about 20 μm to 30 μm in this comparative example), the end of the cutting region is stressed. It cannot withstand and breaks. At this time, since the stress from the dicing blade 100 is applied substantially evenly to both ends of the cutting region, both ends of the cutting region break at substantially the same timing. In this embodiment, as described above, the down-cut method is adopted. However, the down-cut method rotates in a direction in which the wiring board 20 is pressed toward the fixing jig 41. Breaks easily.

  Then, as shown in FIG. 71, the uncut region 102 after the both end portions are broken is pushed downward (in the groove portion 41d) without being cut, and the string shape shown in FIG. A (band-like) foreign material 101 is formed. In addition, since the foreign matter 101 is made of a material (for example, a prepreg material) constituting the insulating layer 14 of the wiring board 20, if a very strong force such as stress from the dicing blade 100 is not applied, destruction (brittle failure) It is hard to do. That is, the foreign material 101 pushed down is difficult to be cut in the middle, and when the fixing jig 41 is moved in the cutting direction 44 shown in FIG. 68, the foreign material 101 is formed longer. For this reason, the longest thing among the foreign materials 101 becomes a length comparable to the length along the cutting direction (for example, the cutting direction 44 shown in FIG. 68) of the cut | disconnected wiring board 20. FIG.

  Further, as described above, in order to cut the wiring substrate 20, it is necessary to use a dicing blade having a width wider than that of the dicing blade used in the semiconductor chip preparation step. Therefore, the width of the foreign material 101 is about 200 μm to 300 μm. Become wider.

  Next, a comparative example will be described in which a dicing blade 100 whose tip is orthogonal to the side surface is used to cut a wiring board on which a batch mold type sealing resin is formed. 72 is an enlarged cross-sectional view showing a singulation process as a second comparative example of the present embodiment, and FIGS. 73 and 74 are enlarged cross-sectional views taken along lines NN and PP of FIG. 72, respectively. FIG.

  72 to 74, the first comparative example shown in FIGS. 68 to 71 is the same as that shown in FIGS. 68 to 71 except that the collective sealing resin 103 is formed on the surface 10a side of the wiring board 20. This is the same as the individualization step of the comparative example.

  In the singulation process as the second comparative example, the collective sealing resin 103 is formed on the surface 10a side of the wiring board 20. The collective sealing resin 103 is a sealing body that arranges a plurality of device regions 20a in one cavity and collectively seals the plurality of device regions 20a in the above-described sealing step. For this reason, in the second comparative example, the collective sealing resin 103 is also formed in the dicing region 20c.

  When the wiring substrate 20 is fixed on the fixing jig 41 and the singulation process is performed, the first comparative example can be performed even if cutting is performed using the dicing blade 100 whose tip shape is orthogonal to the side surface. The string-like foreign matter 101 (see FIG. 68) as described in FIG.

  First, as shown in FIG. 73, in the region where the thickness of the uncut wiring board 20 (insulating layer 14) is thin (about 20 μm to 30 μm), as in the first comparative example, Stress concentrates at the end (M portion in FIG. 73). However, in the second comparative example, the collective sealing resin 103 is disposed in the lower layer of the wiring board 20, and the dicing region 20 c of the wiring board 20 is supported by the collective sealing resin 103. For this reason, even if stress concentrates on the end of the cutting region, no breakage occurs and the wiring board 20 can be completely cut.

  Next, as shown in FIG. 74, in the region where the uncut batch sealing resin 103 is thin (about 20 μm to 30 μm), the end of the cutting region of the batch sealing resin 103 (FIG. 74). Stress concentrates on the M part). For this reason, the edge part of a cutting process area | region fractures | ruptures, and a part of uncut batch sealing resin 103 may become the foreign material 104 shown in FIG.

  However, the foreign substance 104 shown in FIG. 72 is made of a material constituting the collective sealing resin 103 (for example, a material obtained by adding a filler such as silica to an epoxy thermosetting resin), and will be described in the first comparative example. Compared to the string-like foreign material 101 (see FIG. 68), it is brittle (low brittle fracture resistance). In general, the material used for the sealing resin needs to fill in a narrow gap such as a wire in the sealing step, and therefore requires fluidity before curing. On the other hand, the insulating layer of the wiring board is required to have strength as a base material for supporting the package. For this reason, the material constituting the insulating layer of the wiring board is less susceptible to brittle fracture (higher brittle fracture resistance) than the material constituting the sealing resin. Also in this embodiment, the insulating layer 14 of the wiring board 20 shown in FIG. 22 is less susceptible to brittle fracture than the sealing resin 4 (high brittle fracture resistance). When the degree of brittle fracture resistance of the insulating layer 14 and the sealing resin 4 is shown by using the bending strength as an index, the bending strength of the insulating layer 14 is, for example, about 500 MPa to 800 MPa. On the other hand, the bending strength of the sealing resin 4 and the collective sealing resin 103 shown in FIG. 72 is, for example, 0.1 MPa to 0.15 MPa. That is, the insulating layer 14 has a bending strength 1000 times or more higher than that of the sealing resin 4 shown in FIG. 22 or the collective sealing resin 103 shown in FIG. For this reason, the foreign material 101 (refer FIG. 68) resulting from the insulating layer 14 is harder to carry out a brittle fracture than the foreign material 104 (refer FIG. 72) resulting from the package sealing resin 103 (refer FIG. 72). Therefore, the foreign matter 104, which is a thinned portion of the collective sealing resin 103 shown in FIG. 72, is finely cut as shown in FIG. 72 by, for example, an impact during cutting, which is the first comparative example. The foreign object 101 does not have a long connected shape.

  As shown in FIG. 72, the finely cut foreign matter 104 falls into the groove 41d, so that it is difficult to get caught between the wiring board 20 to be cut next and the fixing jig 41 as in the first comparative example. . Further, the foreign matter 104 in the groove 41d can be easily removed in a cleaning process described later. Further, even if the foreign matter 104 is sandwiched between the wiring board 20 and the fixing jig 41, the foreign substance 104 is broken by the fixing force (adsorption force) when fixing the wiring board 20, so that in the first comparative example, It does not cause the cutting failure as described.

  Further, it has been described that the semiconductor wafer is cut by the dicing blade in the above-described semiconductor chip preparation step. However, since the semiconductor wafer is also fragile as compared with the insulating layer 14 of the wiring substrate 20 shown in FIG. 22, even if the semiconductor wafer is cut with a dicing blade, long string-like foreign matters are not generated. For example, the bending strength of the semiconductor chip 2 shown in FIG. 21 is about 75 MPa to 85 MPa.

  That is, the problem that the cutting failure described in the first comparative example occurs is that a hollow space such as a groove 41d is formed on the lower surface side of the dicing region 20c of the wiring substrate 20 (on the surface 10a side of the wiring substrate 20 shown in FIG. 69). In this state, it was found that this is a problem that occurs when the wiring board 20 having high brittle fracture resistance is cut.

  Further, it has been found that the occurrence of the string-like foreign material 101 shown in FIG. 68 can be prevented by preventing the both ends of the cutting region of the workpiece from being broken by stress.

<Individualization step of this embodiment>
Based on the problems described in the first and second comparative examples described above, the individualization process of the present embodiment will be described. 26 is an enlarged cross-sectional view of the dicing blade shown in FIG.

  As shown in FIG. 26, the dicing blade 40 of the present embodiment has a tapered surface (inclined surface) 40a intersecting the side surface 40b at the tip (cutting surface side) of the peripheral edge. The angle θ1 formed by the side surface 40b and the tapered surface 40a is larger than 90 degrees, for example, 135 degrees in the present embodiment. Specifically, the dicing blade 40 of the present embodiment has tapered surfaces 40a formed from both side surfaces 40b toward the opposite side surface 40b (double-sided tapered structure). The tapered surfaces 40a intersect each other in the middle of both side surfaces 40b. In other words, the dicing blade 40 has a plane-symmetric structure with the center plane in the width direction as an axis. For this reason, the front-end | tip (vertex 40c) of the peripheral part of the dicing blade 40 is located in the approximate center of the width direction of the dicing blade 40, and has the projection shape formed of the two taper surfaces 40a. Further, the angle θ1 formed by each tapered surface 40a and the side surface 40b is 135 degrees in the present embodiment. By cutting the wiring board 20 using the dicing blade 40 having the tapered surface 40a formed at the tip in this way, the occurrence of the string-like foreign matter 101 (see FIG. 68) described in the first comparative example is prevented. be able to. The reason will be described below. 27 is an enlarged cross-sectional view of a Q portion in FIG. 23, and FIGS. 28, 29, and 30 are enlarged cross-sectional views of the RR line, the SS line, and the TT line in FIG. 27, respectively.

  First, as shown in FIG. 28, in the region immediately before the apex 40c where the two tapered surfaces 40a intersect each other reaches the upper surface 14a of the insulating layer 14 of the wiring board 20 (for example, about 20 μm to 30 μm from the upper surface 14a), cutting is performed. Stress concentrates at the end of the processing region (M portion in FIG. 28) and in the vicinity of the apex 40c where the tapered surface 40a intersects. However, the insulating layer 14 still has a sufficient thickness (for example, about 150 μm to 200 μm) at the end portion (M portion) of the cutting region. Further, since the stress from the dicing blade 40 is applied in an oblique direction (a direction orthogonal to the tapered surface 40a) by forming the tapered surface 40a, a downward component (that is, a component that causes the insulating layer 14 to break). ) Is smaller than in the case of the first comparative example. Therefore, in this region, the uncut region is hardly broken as described in the first comparative example. Moreover, even if it is a case where it fractures | ruptures in the vertex 40c vicinity which the taper surface 40a crosses, the fracture | rupture part is one place. Further, since the end portion (M portion) of the cutting region is firmly fixed, the broken portion does not become the string-like foreign material 101 shown in FIG. 68, and cutting can be performed continuously.

  Next, as shown in FIG. 29, in the region where the thickness of the end portion (M portion in FIG. 29) of the cutting region is, for example, about 20 μm to 30 μm, stress concentrates on this end portion. However, in the region shown in FIG. 29, since the tip (vertex 40c) of the dicing blade 40 has already reached the lower side of the upper surface 14a of the insulating layer 14, the stress concentrated on the end is compared with the first comparison. Compared to the case of FIG. 70 described in the example, it is significantly smaller. Further, as described above, since the stress applied to the end portion is applied in an oblique direction (a direction orthogonal to the tapered surface 40a), the downward component (the component causing the fracture of the insulating layer 14) is further reduced. For this reason, also in this region, it is possible to prevent the uncut region from breaking as described in the first comparative example.

  Then, as shown in FIG. 30, the wiring substrate 20 can be cut by cutting until the side surface 40 b of the dicing blade 40 penetrates the upper surface 14 a of the insulating layer 14.

  As described above, in the present embodiment, by using the dicing blade 40 having the tapered surface 40a, it is possible to prevent the uncut region from being broken, so that the string-like foreign matter described in the first comparative example is generated. It is possible to cut the top surface 14a of the insulating layer 14 without making it.

  When all the dicing regions (dicing lines) 20c surrounding the device region 20a are cut, the device regions of the wiring board 20 are separated into pieces, and a plurality of semiconductor devices 1 shown in FIG. 1 can be obtained. At this time, each semiconductor device 1 is in a state of being fixed to the fixing jig 41 shown in FIG.

<Tip shape of dicing blade>
Next, a preferable aspect of the tip shape of the dicing blade will be described including modifications and comparative examples. FIG. 31 is an enlarged cross-sectional view showing a state where the dicing blade shown in FIG. 26 is deformed due to wear. FIGS. 32 and 33 are first and second modifications of the dicing blade shown in FIG. 26, respectively. FIG. 75 is an enlarged cross-sectional view showing a state where the dicing blade shown in FIG. 69 is deformed due to wear.

  As described above, in this embodiment, the tapered surface 40a is provided on the tip surface (cut surface) of the dicing blade 40 to prevent the uncut region from being broken. Therefore, it is preferable that the taper surface 40a intersects the side surface 40b.

  From the viewpoint of preventing breakage of the uncut region, the plane of the wiring board 20 shown in FIGS. 27 to 29 (for example, the lower surface 14b and the upper surface 14a of the insulating layer 14) and the taper of the dicing blade 40 shown in FIG. The angle θ2 formed by the surface 40a is preferably as large as possible. In the present embodiment, as shown in FIGS. 27 to 29, an angle such that the side surface 40 b of the dicing blade 40 is substantially orthogonal to the plane of the wiring board 20 (for example, the lower surface 14 b and the upper surface 14 a of the insulating layer 14). The tip is brought into contact with (entrance angle). For this reason, in other words, increasing the angle θ2, it is preferable to increase the angle θ1 formed by the tapered surface 40a and the side surface 40b. This is because when the thickness of a part of the cutting region is reduced, the thickness of the end where stress is concentrated is sufficiently increased. Moreover, the downward stress applied to the uncut region can be reduced by increasing the angle θ2.

  According to the study by the present inventor, it has been found that if the angle θ2 is larger than 40 degrees, it is possible to prevent the occurrence of the string-like foreign matter described in the first comparative example. In other words, the angle θ1 formed by the tapered surface 40a and the side surface 40b is preferably larger than 130 degrees. In the present embodiment, even when the intrusion angle of the dicing blade 40 is slightly shifted due to accuracy, the angle θ2 is set to be greater than 40 degrees, so that the angle θ1 is set to 135 degrees and the angle θ2 is set to 45 degrees.

  On the other hand, if the angle θ2 is extremely large (too close to 90 degrees), the dicing blade 40 is worn heavily during cutting, and the replacement frequency increases. Further, the tip portion of the dicing blade 40 is damaged during the cutting process, causing a cutting failure. From the viewpoint of suppressing such wear and damage of the dicing blade 40, the angle θ2 is preferably less than 60 degrees, in other words, the angle θ1 is preferably less than 150 degrees.

  By the way, in general, a dicing blade is worn by use. And the greater the stress during cutting, the greater the degree of wear. Therefore, for example, in the case of the dicing blade 100 having the tip surface of the side-orthogonal shape shown in FIG. 69 described as the first comparative example, by using the tip as in the curved surface 100c shown in FIG. The end of the surface 100a is worn and becomes a curved shape in an arc. However, even when the inventor cuts the wiring board 20 of the present embodiment using the dicing blade 100 having both ends of the tip end surface 100a curved in an arc as shown in FIG. It has been confirmed that the string-like foreign matter 101 as shown in 68 occurs frequently. That is, in the dicing blade 100 having the curved surface 100c formed by abrasion when cutting the wiring board 20 as shown in FIG. 75, the occurrence of the string-like foreign matter 101 (see FIG. 68) cannot be prevented. This is considered because stress concentrates on an arbitrary point in the cutting region of the wiring board 20 that contacts the curved surface 100c, and both ends of the uncut region break.

  On the other hand, the tapered surface 40a of the dicing blade 40 of the present embodiment has a flatness equivalent to that of the side surface 40b. When the flat tapered surface 40a is used in this way, the position where the stress concentrates in the uncut region can be controlled to be, for example, around the M portion shown in FIG. 28 and the apex 40c of the dicing blade 40. That is, it is possible to prevent any two places in the uncut region from breaking at substantially the same timing. Therefore, the generation of the string-like foreign substance 101 shown in FIG. 68 can be prevented. However, as described above, in the dicing blade 40, a plurality of abrasive grains made of, for example, diamond are fixed to the outer periphery of the thin plate (base material), and the plurality of abrasive grains scrape off the workpiece to be cut. . For this reason, the surface of the taper surface 40a is an uneven surface in which a plurality of abrasive grains are exposed microscopically. That the tapered surface 40a is a flat surface does not exclude the fact that the plurality of abrasive grains have microscopic irregularities due to exposure from the base material.

  Further, the dicing blade 40 of the present embodiment is also worn by use. When the cutting surface of the dicing blade 40 is worn, for example, as shown in FIG. 31, both end portions of the tapered surface 40a where stress is concentrated during cutting (the end portion intersecting the side surface 40b and the two tapered surfaces 40a intersect). From the apex 40c), it is sequentially deformed and curved by wear. However, the inventor of the present application has a string-like shape shown in FIG. 68 in the range where the width W1 of the curved surface 40d where the apex 40c where the two tapered surfaces 40a intersect is curved due to wear is smaller than the width W2 of each tapered surface 40a. The knowledge that the foreign material 101 does not occur has been obtained. In other words, if the width W1 of the curved surface 40d is set to one third or less of the entire width of the dicing blade 40, the occurrence of the string-like foreign material 101 shown in FIG. 68 can be prevented. Accordingly, if the dicing blade 40 is worn out and the width of the curved surface 40d where the apex 40c where the two taper surfaces 40a intersect is curved is more than one third, the new dicing blade 40 is replaced. Generation of the string-like foreign matter 101 shown in 68 can be prevented or suppressed.

  Furthermore, by applying the above knowledge, as shown in the dicing blade 50 shown in FIG. 32, a side orthogonal surface 40e facing the plane of the workpiece may be provided between the two tapered surfaces 40a. In this case, if the width W1 of the side orthogonal surface 40e is narrower than the width W2 of each tapered surface 40a, in other words, if the width W1 of the side orthogonal surface 40e is less than or equal to one third of the total width of the dicing blade 40. 68, the occurrence of the string-like foreign matter 101 shown in FIG. 68 can be prevented. That is, even in the case of the dicing blade 50 having a tip surface (for example, the side surface orthogonal surface 40e) intersecting the taper surface between the two taper surfaces 40a, the width W1 of the side surface orthogonal surface 40e is set to the full width of the dicing blade 40. If it is set to 1/3 or less of this, generation | occurrence | production of the string-like foreign material 101 shown in FIG. 68 can be prevented.

  Further, from the viewpoint of suppressing the occurrence of the string-like foreign material 101 shown in FIG. 68, it is only necessary to prevent the both ends of the uncut region from breaking at substantially the same timing. For example, the dicing blade 51 shown in FIG. As described above, a structure having one tapered surface 51a extending from one side surface 40b of the dicing blade 51 toward the other side surface 40b can also be adopted (single-sided tapered structure). Although not shown, as a modification of the dicing blade 40 shown in FIG. 26, a structure (surface asymmetric structure) in which the apex 40c at which the two tapered surfaces 40a intersect each other is arranged close to one of the side surfaces 40b. You can also However, in these dicing blades having a surface asymmetric structure, the stress applied to the workpiece during cutting is not uniform. For this reason, from the viewpoint of applying the same cutting stress to each device region 20a of the wiring board 20 and reducing the variation for each device region 20a, the dicing blades 40, 50 having the plane-symmetric structure shown in FIGS. Is preferably used.

<Washing, drying, pick-up process>
34 is an enlarged cross-sectional view showing a cleaning process after cutting the wiring board shown in FIG.

  Next, as a cleaning process, with the semiconductor devices 1 separated into individual pieces fixed to the fixing jig 41, a cleaning liquid (cleaning water) 52 is supplied to remove foreign matters and dirt that could not be removed during the cutting process. Remove. Although the cleaning method is not particularly limited, in this embodiment, water is sprayed from the back surface 10b side of the wiring board 20 for cleaning. The cleaning liquid 52 sprayed onto the wiring board 20 also enters the groove 41d of the fixing jig 41, and the cutting waste remaining in the groove 41d can be washed away at this time.

  Here, when the string-like foreign matter 101 shown in FIG. 68 remains in the groove 41d shown in FIG. 34, the foreign matter 101 has a long length and has a shape wound in a coil shape. Even if a part of the foreign matter 101 comes out of the groove 41d, it is difficult to completely remove the foreign matter 101 from the groove 41d. Further, from the viewpoint of ensuring the strength to support the wiring board 20, the width of the groove 41d is as narrow as several hundred microns, so it is difficult to scrape out foreign matter in the groove 41d without damaging the wiring board 20 after cutting. is there. If the foreign matter 101 remains even after the cleaning process, it causes a suction failure when the separated semiconductor device is taken out in the pick-up process for taking out the individual semiconductor devices after washing and drying. Further, when a part of the foreign matter 101 remains on the fixing jig 41, the foreign matter 101 is sandwiched between the wiring substrate 20 to be cut next and the fixing jig 41, which causes a cutting failure.

  On the other hand, in the present embodiment, even if the cutting waste remains in the groove 41d of the fixed jig 41 after the cutting, the cutting waste is short in length and can be washed away by the cleaning liquid 52. I can do it. Therefore, it is possible to prevent poor suction due to residual foreign matter and cutting failure.

  Following the cleaning process, a drying process is performed. In the drying process, moisture adhering to the semiconductor device in the cleaning process is dried.

  Subsequent to the drying step, the dried semiconductor device 1 is taken out from the fixing jig 41. FIG. 35 is an enlarged cross-sectional view showing a state in which the separated semiconductor device is taken out from the fixing jig shown in FIG.

  In this step, for example, as shown in FIG. 34, each semiconductor device 1 (specifically, the back surface 10b side of the wiring board 10) is sucked and held by the suction jig 53, and the semiconductor device 1 is fixed and fixed. Remove from tool 41. At this time, if a part of the string-like foreign material 101 shown in FIG. 68 is sandwiched between the suction jig 53 and the semiconductor device 1, it causes a suction failure. Since foreign substances such as cutting waste can be removed in the cleaning step, this can be prevented.

  Each semiconductor device 1 picked up in this process is transported to the next process (for example, an inspection process) while being held by the suction jig 53 or stored in a tray (not shown). Then, necessary inspections and tests such as appearance inspection are performed, and the semiconductor device 1 shown in FIG. 1 is completed.

  In the present embodiment, the cleaning process, the drying process, and the pick-up process have been described as processes included in the singulation process, but these can also be considered as independent processes performed after the singulation process. .

(Embodiment 2)
In the first embodiment, the semiconductor device 1 having a structure in which the bonding leads 11 exposed from the insulating film 16 are sealed with the sealing resin 4 on the surface 10a of the wiring substrate 10 has been described. However, the method for manufacturing a semiconductor device described in the first embodiment can also be applied to a method for manufacturing a semiconductor device having a structure different from that of the semiconductor device 1.

  For example, recently, a POP (Package on Package) type semiconductor device in which another semiconductor device (semiconductor package) is stacked on a semiconductor device (semiconductor package) has been studied. In this embodiment, a semiconductor device disposed on the lower side of a POP type semiconductor device and a manufacturing process thereof will be described. In the present embodiment, the description of the same points as in the first embodiment is omitted except for the differences described below. 36 is a plan view showing a modification of the semiconductor device shown in FIG. 3 described in the first embodiment, FIG. 37 is a sectional view taken along the line U-U in FIG. 36, and FIG. 38 is shown in FIG. It is an expanded sectional view of the W section.

  The semiconductor device 70 shown in FIGS. 36 and 37 is the same as that of the first embodiment shown in FIGS. 3 and 4 in that a plurality of lands 72 are exposed from the sealing resin 4 on the surface 10a of the wiring board 71. Different from the semiconductor device 1. The plurality of lands 72 are terminals for an external interface for arranging an electronic device such as a wiring board or a semiconductor device on the upper stage of the semiconductor device 70 and electrically connecting the electronic device and the semiconductor device 70. . A package in which a plurality of semiconductor devices or electronic devices are stacked and electrically connected to each other as described above is called a POP type semiconductor device, and the plurality of semiconductor devices are mounted on a mounting substrate (not shown). ) There is an advantage that the mounting area can be reduced as compared with the case where they are arranged side by side. For example, a memory chip (semiconductor chip) 74 in which a memory circuit such as a DRAM or a flash memory is formed is mounted on an upper semiconductor device (memory package) 73 shown in FIG. 37, and a lower semiconductor device (controller package) is mounted. ) 70 is mounted with a semiconductor chip 2 which is a controller chip for controlling the memory chip, and a plurality of solder balls (joining material, inter-substrate joining material) 75 joined to a plurality of lands (electrodes, electrode pads, terminals) 72. These can be electrically connected to each other through a system. Then, the mounting area can be reduced by stacking the semiconductor device 73 on which the memory chip 74 is mounted and the semiconductor device 70 on which the controller chip is mounted.

  In addition, as an aspect different from the POP type in which a system is configured by electrically connecting a plurality of semiconductor chips, a plurality of semiconductor chips are stacked on a wiring board and electrically connected to one semiconductor package. There is also a system in package (SIP) type semiconductor device that constitutes a system. However, in the POP type semiconductor device, the upper side semiconductor device and the lower side semiconductor device 70 can be manufactured separately and then connected to each other, so that the system amount is smaller than that of the SIP type semiconductor device.・ It can flexibly cope with a variety of products.

  The plurality of lands 72 included in the semiconductor device 70 of the present embodiment, which is the lower package of this POP type semiconductor device, are electrically connected to the plurality of bonding leads 11 via the wiring 12 of the wiring substrate 71. Yes. Thus, the upper semiconductor device 73 (memory chip 74) and the lower semiconductor device 70 (semiconductor chip 2) can be electrically connected to form a system. The plurality of lands 72 are electrically connected to the plurality of lands 13 formed on the back surface 10 b side (on the lower surface 14 b of the insulating layer 14) of the wiring board 71 via the wirings 12 and 15 of the wiring board 71. ing. Thereby, the upper semiconductor device 73 (memory chip 74) can be electrically connected to an external device.

  Specifically, as shown in FIG. 38, the wiring board 71 according to the present embodiment includes, for example, a plurality of (in FIG. 38, a front wiring layer, a back wiring layer, and two inner wiring layers manufactured by a build-up method. A multilayer wiring board having four wiring layers). The insulating layer 14 that electrically insulates the wiring layers includes, for example, an insulating layer (core layer) 14d made of a prepreg obtained by impregnating glass fiber or carbon fiber with a resin, and an upper surface 14e and a lower surface 14f of the insulating layer 14d. The insulating layers 14g and 14h are disposed so as to cover each other and are made of a thermosetting resin such as epoxy that does not contain glass fibers and is cured. Thus, even when a resin material not containing glass fibers is used as the insulating layers 14g and 14h, the brittle fracture resistance is higher than that of the semiconductor chip 2 and the sealing resin 4. The bending strength values of the insulating layers 14g and 14h are smaller than the bending strength of the insulating layer 14d serving as the core layer, but larger than the bending strength of the semiconductor chip 2 and the sealing resin 4. Therefore, when a foreign matter is generated due to the insulating layer 14g, the foreign matter is likely to be a long string like the foreign matter 101 shown in FIG. In the present embodiment, the insulating layers 14g and 14h that do not include glass fibers are used. However, the insulating layers 14g and 14h may include glass fibers. In this case, the values of the bending strength of the insulating layers 14g and 14h are substantially equal to the bending strength of the insulating layer 14d serving as the core layer.

  In this embodiment, since the wiring substrate has four wiring layers, the upper surface of the insulating layer 14g is the upper surface 14a of the insulating layer 14, and the lower surface of the insulating layer 14h is the lower surface 14b of the insulating layer 14. The insulating layers 14g and 14h are insulating layers arranged to insulate the inner wiring layer from the front or back wiring layer, and are thinner than the insulating layer 14d. This is to prevent the overall thickness of the wiring board 71 from increasing. In the present embodiment, for example, the thickness of the insulating layer 14d is 200 μm, whereas the thickness of the insulating layers 14g and 14h is 30 μm. Note that the insulating film 16 that covers the front surface wiring layer and the insulating film 17 that covers the back surface wiring layer are thinner than the insulating layers 14g and 14h, and in this embodiment, for example, 15 μm.

  A plurality of wirings 12 are formed in each wiring layer, and each wiring is connected via a wiring (in-via wiring, interlayer wiring) 15 in a via (hole) 15a penetrating each insulating layer 14d, 14g, 14h. Layer wirings 12 are electrically connected. Specifically, a wiring (uppermost layer wiring) 12a is formed in the surface wiring layer, and is electrically connected to the wiring 12d formed in the second wiring layer via the wiring 15 formed in the insulating layer 14g. Has been. The wiring 12d is electrically connected to the wiring 12e formed in the third wiring layer via the wiring 15 formed in the insulating layer 14d. The wiring 12e is electrically connected to the wiring 12b formed on the back wiring layer via the wiring 15 formed on the insulating layer 14h. Further, bonding leads 11 and lands 72 are formed on the front surface wiring layer, and lands 13 are formed on the back surface wiring layer, and are electrically connected via wirings 12a and 12b. That is, the plurality of bonding leads 11 and the plurality of lands 72 are electrically connected via the wirings 12 and 15 of the wiring board 71.

  Further, as shown in FIG. 36, the plurality of lands 72 are arranged outside the plurality of bonding leads 11 in a plan view and exposed from the sealing resin 4. As shown in FIG. 38, the insulating film 16 covering the upper surface 14a of the insulating layer 14 of the wiring board 71 is formed with an opening 16c at a position overlapping the land 72, and a part of the land 72 is formed in the opening 16c. The insulating film 16 is exposed.

<Problems and solutions when cutting a wiring board having a plurality of wiring layers>
Here, when a wiring board having a plurality of wiring layers such as the wiring board 71 is cut by applying the singulation process of the first comparative example described in the first embodiment, the first embodiment. The string-like foreign matter is more likely to be generated than the wiring board 20 described in the above.

  In the wiring board 71 having a plurality of wiring layers, the insulating layer 14 that insulates between the wiring layers also has a multilayer structure. Specifically, as shown in FIG. 38, an insulating layer 14g having a thickness smaller than that of the insulating layer 14d is laminated on the upper surface 14e of the insulating layer 14d serving as the core layer.

  In the case of the wiring board 71 in which insulating layers having different thicknesses are laminated in this way, the cutting resistance when cutting with a dicing blade is different between the insulating layer 14d and the insulating layer 14g. That is, the cutting resistance of the insulating layer 14g is smaller than that of the thick insulating layer 14d. Further, as in the present embodiment, when the insulating layer 14d that is the core layer includes glass fibers and the insulating layer 14g does not include glass fibers, the difference in cutting resistance further increases.

  However, as described in the above embodiment, when a workpiece is cut while rotating a dicing blade, which is a thin plate having a substantially circular outer shape, for each cross section (region) (for example, J- The progress of the cutting process differs for each cross section (region) along the line J, KK, and LL. That is, the insulating layers 14d and 14g having different cutting resistances are simultaneously cut. In this case, the strength with which the dicing blade is pressed against the wiring board 71 needs to be matched with the one having the higher cutting resistance (insulating layer 14d). This is to prevent vibration during cutting and cutting defects.

  For this reason, a pressing force more than necessary is applied from the dicing blade to the insulating layer 14g having a cutting resistance smaller than that of the insulating layer 14d. When a pressing force more than necessary is applied, stress concentrates on both ends of the cutting region of the insulating layer 14g and breaks more easily than in the first embodiment.

  Therefore, in this embodiment, as shown in FIGS. 39 to 42, the dicing blade 40 described in the first embodiment is used to form the wiring board 76 (a number corresponding to the wiring board 20 described in the first embodiment). The substrate is cut. 39 is an enlarged cross-sectional view showing the singulation process of the present embodiment, and FIGS. 40, 41, and 42 are enlargements of the XX line, the YY line, and the ZZ line of FIG. 39, respectively. It is sectional drawing. 39 is an enlarged cross-sectional view corresponding to FIG. 27 described in the first embodiment.

  First, as shown in FIG. 39, in the region where the apex 40c where the two tapered surfaces 40a intersect each other exceeds the upper surface 14e of the insulating layer 14d of the wiring board 20 and reaches the insulating layer 14g, the end of the cutting region ( The stress concentrates in the M portion in FIG. However, since most of the tapered surface 40a of the dicing blade 40 is in contact with the insulating layer 14d at this time, the stress generated in the insulating layer 14g is suppressed to be lower than when the dicing blade 100 shown in FIG. 68 is used. be able to. In addition, as described in the first embodiment, the stress from the dicing blade 40 is applied in an oblique direction (a direction orthogonal to the tapered surface 40a) by forming the tapered surface 40a, so that a downward component (that is, a downward component) , The component causing the breakage of the insulating layer 14g) is smaller than in the case of the first comparative example. Therefore, in this region, the uncut region is hardly broken as described in the first comparative example. Moreover, even if it is a case where it fractures | ruptures in the vertex 40c vicinity which the taper surface 40a crosses, the fracture | rupture part is one place. Further, since the end portion (M portion) of the cutting region is firmly fixed, the broken portion does not become the string-like foreign material 101 shown in FIG. 68, and cutting can be performed continuously.

  Next, as shown in FIG. 41, in the region where the end portion (M portion in FIG. 41) of the cutting region reaches the insulating layer 14g, stress concentrates on this end portion. Then, the insulating layer 14g having a cutting resistance lower than that of the insulating layer 14d is cut while being pressed by the dicing blade 40 with a strong pressing force. However, in the region shown in FIG. 41, since the tip (vertex 40c) of the dicing blade 40 has already reached the lower side of the upper surface 14a of the insulating layer 14 (insulating layer 14g), the stress concentrated on the end is It is much smaller than when the dicing blade 100 shown in FIG. 68 is used. Further, as described above, since the stress applied to the end portion is applied in an oblique direction (a direction orthogonal to the tapered surface 40a), the downward component (the component causing the fracture of the insulating layer 14g) is further reduced. For this reason, also in this area | region, the fracture | rupture of the uncut area | region which was demonstrated in the said Embodiment 1 can be prevented.

  Then, as shown in FIG. 42, the side surface 40b of the dicing blade 40 is cut until it penetrates the upper surface 14a of the insulating layer 14g, so that the insulating layer 14 does not generate the string-like foreign material 101 shown in FIG. The top surface 14a can be cut.

  As described above, in the present embodiment, the dicing blade 40 having the taper surface 40a is used to explain the wiring board 76 in which the insulating layers 14d and 14g having different thicknesses are stacked in the first embodiment. The wiring board 76 can be cut without generating the string-like foreign matter. Further, since the insulating layer 14d includes glass fibers and the insulating layer 14g does not include glass fibers, the string-like foreign matter described in the first embodiment can be removed even when the difference in cutting resistance between the two is large. The wiring board 76 can be cut without generating it.

  In addition, about the preferable shape of the front-end | tip shape of a dicing blade, the aspect demonstrated in the said Embodiment 1 can be applied as it is. The following is a brief description while avoiding repeated detailed description.

  First, it is preferable that the taper surface 40a intersects the side surface 40b.

  Further, from the viewpoint of reliably preventing breakage of the uncut region, it is preferable to make the angle θ1 formed by the tapered surface 40a and the side surface 40b of the dicing blade 40 shown in FIG. 26 larger than 130 degrees. In other words, the angle θ2 formed by the plane of the wiring board (for example, the lower surface 14b or the upper surface 14a of the insulating layer 14) and the tapered surface 40a of the dicing blade 40 is preferably larger than 40 degrees. Further, even when the intrusion angle of the dicing blade 40 is slightly shifted due to accuracy, it is particularly preferable that the angle θ1 is 135 degrees or more and the angle θ2 is 45 degrees or more in order to make the angle θ2 larger than 40 degrees.

  Further, from the viewpoint of reducing the replacement frequency of the dicing blade 40 and suppressing damage to the dicing blade 40 during the cutting process, the angle θ2 is preferably less than 60 degrees, in other words, the angle θ1 is preferably less than 150 degrees. .

  Further, from the viewpoint of reliably preventing breakage of the uncut region, the tapered surface 40a of the dicing blade 40 has a flatness higher than that of the curved surface formed by wear, particularly preferably the same flatness as the side surface 40b. It is preferable.

  As a modification, for example, as shown in FIG. 31, a portion between both side surfaces 40b may be a curved surface 40d. Furthermore, as shown in FIG. 32, a side surface orthogonal surface 40e facing the plane of the workpiece may be provided between the two tapered surfaces 40a. In this case, if the width W1 of the curved surface 40d shown in FIG. 31 or the side surface orthogonal surface 40e shown in FIG. 32 is smaller than the width W2 of each tapered surface 40a, the string-like foreign material 101 shown in FIG. It can be prevented or suppressed.

  Further, from the viewpoint of suppressing the generation of the string-like foreign substance 101 shown in FIG. 68, for example, as in the dicing blade 51 shown in FIG. 33, the dicing blade 51 extends from one side surface 40b toward the other side surface 40b. A structure having a single tapered surface 51a (a single-sided taper structure or a plane asymmetric structure) can also be used. However, from the viewpoint of reducing the variation of each device region 20a by applying the same cutting stress to each device region 20a of the wiring board 76, the plane-symmetrical dicing blades 40 and 50 shown in FIGS. It is preferable to use it.

<Problems and Solution for Cutting a Wiring Substrate with Exposed Land on the Front Side>
As shown in FIG. 38, in the manufacturing process of the semiconductor device in which a plurality of lands 72 are exposed on the surface 10a of the wiring board 71, the following problems are further encountered in the singulation process described in the first embodiment. have. That is, when the string-like foreign material 101 shown in FIG. 68 is generated, the exposed land 72 is contaminated in the individualization step, and the semiconductor device 70 shown in FIG. This causes a conduction failure.

  When the string-like foreign substance 101 shown in FIG. 68 is generated in the first embodiment, a part of the foreign substance 101 is easily caught between the wiring board 20 shown in FIG. 69 and the convex part 41c of the fixing jig 41, for example. I have already explained that. It has also been described that when the foreign matter 101 is sandwiched, a gap is generated between the wiring board 20 and the convex portion 41c.

  Here, in the singulation step, the operation is performed while supplying (spraying) the cutting fluid 45 shown in FIG. 22 and the cleaning fluid 52 shown in FIG. 34 toward the wiring board 20. Therefore, if there is a gap between the wiring board 20 and the fixing jig, the cutting fluid 45 shown in FIG. 22 and the cleaning liquid 52 shown in FIG. 34 enter the concave portion 41b of the fixing jig from the gap. When this is applied to the wiring substrate 71 of the present embodiment shown in FIG. 38, for example, the cutting fluid 45 that has entered the recess 41b shown in FIG. 22 is exposed in the recess 41b from the insulating film 16 shown in FIG. 72 is contaminated.

  On the other hand, according to the present embodiment, as described above, the wiring board 76 (see FIG. 42) can be cut without generating the string-like foreign matter 101 (see FIG. 68). Therefore, it is possible to prevent a gap from being generated between the wiring board 76 and the convex portion 41 c of the fixing jig 41. As a result, even if the cutting fluid 45 shown in FIG. 22 or the cleaning fluid 52 shown in FIG. 34 is used, contamination of the land 72 can be prevented.

  As described above, according to the present embodiment, in addition to the effects described in the first embodiment, the contamination of the plurality of lands 72 exposed from the sealing resin 4 on the surface 10a of the wiring board 71 is further prevented. Can do.

(Embodiment 3)
In the first and second embodiments, the mode in which the semiconductor chip 2 is mounted on the wiring substrate 71 by the face-up mounting method has been described. However, it can also be applied to a semiconductor device in which a semiconductor chip is mounted by a face-down mounting method. FIG. 43 is a plan view showing a modification of the semiconductor device shown in FIG. 36 described in the second embodiment, and FIG. 44 is a sectional view taken along the line Aa-Aa in FIG.

  The semiconductor device 80 shown in FIGS. 43 and 44 is a semiconductor device disposed on the lower side of the POP type semiconductor device, like the semiconductor device 70 described in the second embodiment. In the semiconductor device 80, the semiconductor chip 2 is mounted in a state where the main surface 2 a of the semiconductor chip 2 faces the surface 10 a of the wiring substrate 81. The semiconductor chip 2 and the wiring board 81 are electrically connected by flip chip connection. That is, a plurality of bump electrodes (projection electrodes, conductive members) 83 are joined to a plurality of pads 2c formed on the main surface 2a, and are formed at positions facing the pads 2c via the bump electrodes 83. The plurality of bonding leads (terminals, bonding pads) 84 are electrically connected to each other. The bonding lead 84 is the same as the bonding lead 11 described in the first and second embodiments except that the bonding lead 84 is disposed at a position facing the pad 2c of the semiconductor chip 2 (that is, in the chip mounting region). The description to be omitted is omitted.

  Further, an underfill resin (sealing resin, sealing body) 85 is filled between the main surface 2a of the semiconductor chip 2 and the surface 10a of the wiring substrate 81, and a plurality of pads 2c and a plurality of bumps of the semiconductor chip 2 are filled. The electrode 83 and the plurality of bonding leads 84 are sealed. On the other hand, the underfill resin 85 is not disposed on the back surface 2b side of the semiconductor chip 2 and is exposed. The plurality of lands 72 are also exposed from the underfill resin 85. As described above, when the flip chip connection is performed, the back surface 2b of the semiconductor chip 2 can be exposed, so that the package height can be made lower (thinner) than that of the semiconductor device 70 described in the second embodiment. .

  Further, by reducing the package height of the semiconductor device 80, the size of the solder ball (bonding material, bonding material between substrates) 86 that is electrically connected to the upper semiconductor device 73 is the same as that of the second embodiment. It can be made smaller than the solder ball 75 described. As a result, the exposed area of the land 72 can also be reduced. Further, in the case of the face-down mounting method, since the bonding lead 84 is disposed in the chip mounting area on which the semiconductor chip 2 is mounted, a large space outside the chip mounting area can be secured. Therefore, more lands 72 can be arranged than the semiconductor device 70 described in the second embodiment. That is, the number of terminals for electrically connecting the semiconductor devices can be increased. For example, FIG. 43 shows an example in which the lands 72 are arranged in a plurality of rows (two rows in FIG. 43) along the outer periphery of the surface 10a of the wiring board 81.

  In the semiconductor device 80 shown in FIGS. 43 and 44, the surface 10 a of the wiring substrate 81 is exposed around the semiconductor chip 2. The underfill resin 85 is made of, for example, a thermosetting resin such as an epoxy resin, and is effective by performing a heat treatment after filling. However, similar to the sealing resin 4 described in the first embodiment, since it is necessary to embed in a narrow gap between the plurality of bump electrodes 83, the cured underfill resin 85 is used as the insulating layer of the wiring substrate 81. It is more brittle than 14. In other words, the insulating layer 14 of the wiring board 81 has higher brittle fracture resistance than the underfill 85. Further, the wiring board 81 is a wiring board in which a plurality of insulating layers are laminated, similarly to the wiring board 71 described in the second embodiment. Therefore, there arises a problem that the string-like foreign substance 101 shown in FIG. 68 described in the first and second embodiments is generated in the singulation process when the semiconductor device 80 is manufactured. However, this can be prevented by using the dicing blade 40 (see FIGS. 26 and 31), the dicing blade 50 (see FIG. 32), or the dicing blade 51 (see FIG. 33) described in the first embodiment. be able to.

  In the semiconductor device 80, the land 72 is exposed on the surface 10 a of the wiring board 81. Therefore, the problem that the land 72 is contaminated occurs in the singulation process as described in the second embodiment. However, as described above, since the occurrence of the string-like foreign matter 101 (see FIG. 68) can be prevented, contamination of the land 72 can also be prevented.

(Embodiment 4)
In the first to third embodiments, the embodiment applied to the semiconductor device in which the semiconductor chip is mounted on the wiring board has been described. In the present embodiment, an embodiment applied to a manufacturing method of a lead frame mounting type semiconductor device using a lead frame as a substrate on which a semiconductor chip is mounted will be described. In the present embodiment, differences from the first embodiment will be mainly described, and a duplicate description will be omitted.

  Lead frame mounting type semiconductor devices can be classified as follows according to the arrangement of leads serving as external terminals of a package (semiconductor device). There is a semiconductor device called QFP (Quad Flat Package) in which a plurality of leads protrude from four side surfaces of a sealing resin having a quadrangular planar shape. In addition, there is a semiconductor device called SOP (Small Outline Package) in which a plurality of leads protrude from two long side surfaces facing each other among the four side surfaces of the sealing resin having a substantially rectangular planar shape. . Further, there are semiconductor devices called QFN (Quad Flat Non-leaded) and SON (Small Outline Non-leaded) in which a plurality of leads are exposed from the lower surface of the sealing resin as a modification of QFP or SOP. In the present embodiment, a QFN (semiconductor device) 90 shown in FIGS. 45 to 48 will be described as an example of a lead frame mounting type semiconductor device. 45 is a plan view showing the surface of the semiconductor device of the present embodiment, and FIG. 46 is a plan view showing the back surface of the semiconductor device shown in FIG. FIG. 47 is a plan view showing the internal structure of the surface side of the semiconductor device shown in FIG. FIG. 48 is a cross-sectional view taken along the line Ab-Ab in FIG. 47, the position of the sealing resin 4 shown in FIG. 45 is indicated by a two-dot chain line.

<Structure of QFN>
First, the configuration of the QFN (semiconductor device) 90 according to the present embodiment will be described with reference to FIGS. As shown in FIGS. 47 and 48, the QFN 90 of the present embodiment includes a die pad (chip mounting portion) 91 and a semiconductor chip 2 mounted on the die pad 91 via an adhesive 6. The QFN 90 also includes a plurality of wires (conductive) that electrically connect a plurality of leads (terminals) 92 disposed around the semiconductor chip 2, a plurality of pads 2 c of the semiconductor chip 2, and a plurality of leads 92. Sex member 3). The QFN 90 includes a sealing resin 4 that seals the semiconductor chip 2, the plurality of wires 3, and the plurality of leads 92. A plurality of suspension leads 93 are connected to the die pad 91.

  As shown in FIG. 45, the planar shape of the sealing resin (sealing body) 4 is a quadrilateral (a square with chamfered corners). As shown in FIG. 46, a plurality of leads 92 that are external terminals of the QFN 90 are arranged along each side of the sealing resin 4 on the lower surface side of the sealing resin 4. As shown in FIG. 45, in this embodiment, a part (outer lead portion) of each of the plurality of leads 92 is also exposed on the upper surface side of the sealing resin 4. In the present embodiment, the lower surface 91b side of the die pad 91 is also exposed from the sealing resin 4 as shown in FIG. The die pad 91, the plurality of leads 92, and the plurality of suspension leads 93 are each made of a metal material, and are made of, for example, copper (Cu) in the present embodiment. Specifically, a thin plated conductor film (not shown) made of, for example, nickel (Ni) is formed on the surface of a base material made of copper (Cu). In addition, exterior plating films (solder films) 91c and 92c made of, for example, solder are formed on the exposed portions of the die pad 91 and the plurality of leads 92 from the sealing resin 4, respectively. In particular, by forming the exterior plating film 92c on the exposed portion of the lead 92, the connectivity (wetting property) when the QFN 90 is mounted on a mounting substrate (not shown) can be improved.

  47 and 48, in the QFN 90, the semiconductor chip 2 is mounted on the upper surface (front surface) 91a of the die pad (chip mounting surface) 91. The semiconductor chip 2 is mounted with an adhesive 6 in a state where the back surface (second main surface) 2b faces the top surface 91a of the die pad 91. That is, by a so-called face-up mounting method in which the opposite surface (back surface 2b) of the main surface (first main surface) 2a on which the plurality of pads 2c are formed is opposed to the upper surface (front surface, chip mounting surface) 91a of the die pad 91. It is installed. One of the plurality of wires 3 is connected to the plurality of pads 2 c, respectively, and the other is connected to each of the plurality of leads 92.

<Manufacturing method of QFN>
Next, a manufacturing process of QFN 90 shown in FIGS. 45 to 48 will be described. The QFN 90 is manufactured along the assembly flow shown in FIG. 49 is an explanatory diagram showing an assembly flow of the semiconductor device shown in FIGS. 45 to 48.

1. Lead frame preparation process;
First, as a preparation step (S1) shown in FIG. 49, a lead frame (substrate) 94 as shown in FIG. 50 is prepared. 50 is a plan view showing the overall structure of the lead frame prepared in the lead frame preparation step shown in FIG. 49, and FIG. 51 is an enlarged plan view of the portion Ac in FIG.

  As shown in FIG. 50, the lead frame 94 prepared in this step includes a plurality of device regions 20a inside a frame portion (frame body) 20b. Specifically, a plurality of device regions 20a are arranged in a matrix. The number of device regions 20a is not limited to the mode shown in FIG. 50. For example, FIG. 50 includes 24 device regions 20a arranged in 3 rows × 8 columns.

  Each device region 20a corresponds to one QFN 90 shown in FIG. 1, and is formed with the die pad 91, the plurality of leads 92, and the suspension leads 93 described with reference to FIGS. Further, around each device region 20a (between adjacent device regions of the plurality of device regions 20a), dicing is a region in which the lead frame 94 is to be cut in the singulation step (S7) shown in FIG. A region (dicing line) 20c is arranged. As shown in FIG. 50, the dicing region 20c is arranged so as to surround each device region 20a between the adjacent device regions 20a and between the frame portion 20b and the device region 20a.

  As shown in FIG. 51, the plurality of leads 92 are connected by a dam bar (tie bar, dam portion) 95 arranged along the dicing region 20c. The dam bar 95 is formed integrally with the plurality of leads 92 and the plurality of suspension leads 93, and is connected to the frame portion 20b shown in FIG. The dam bar 95 is disposed in the dicing region 20c, and each of the plurality of leads 92 disposed to face each other via the dam bar 95 is connected to the dam bar 95 disposed therebetween. Until the individualization step (S7) shown in FIG. 49, the plurality of leads 92 and the plurality of suspension leads 93 (and the die pad 91 connected to the suspension leads 93) are supported by the frame portion 20b via the dam bar 95. The In the sealing step (S5) shown in FIG. 49, the dam bar 95 functions as a dam portion that prevents the sealing resin from leaking out.

2. Semiconductor chip preparation process;
Further, as the semiconductor chip preparation step (S2) shown in FIG. 49, the semiconductor chip 2 shown in FIGS. 47 and 48 is prepared. In this step, for example, a semiconductor wafer made of a plurality of semiconductor elements and a wiring layer electrically connected thereto is prepared on the main surface side of a semiconductor wafer made of silicon (not shown). Thereafter, a dicing blade is run along the dicing line of the semiconductor wafer (not shown) to cut the semiconductor wafer, and a plurality of semiconductor chips 2 shown in FIGS. 47 and 48 are obtained.

3. Die bonding process;
Next, the die bonding step (S3) shown in FIG. 49 will be described. 52 is an enlarged plan view showing a state in which a semiconductor chip is mounted on the lead frame shown in FIG. 51, and FIG. 53 is an enlarged cross-sectional view taken along the line Ad-Ad shown in FIG. In this step, the semiconductor chip 2 is mounted (adhered) on the die pad 91 (chip mounting step). As shown in FIG. 53, in the present embodiment, the semiconductor chip 2 is mounted on the die pad 91 via the adhesive 6 so that the back surface 2b of the semiconductor chip 2 faces the upper surface 91a of the die pad 91 (face-up mounting). Since the other points are the same as those of the first embodiment, a duplicate description is omitted.

4). Wire bonding process;
Next, the wire bonding step (S4) shown in FIG. 49 will be described. 54 is an enlarged plan view showing a state in which a plurality of pads of the semiconductor chip shown in FIG. 52 and a plurality of leads of the lead frame are electrically connected by wire bonding, and FIG. 55 is a plurality of semiconductor chips shown in FIG. It is an expanded sectional view which shows the state which electrically connected the several lead of the pad and the lead frame by wire bonding. In this step, as shown in FIGS. 54 and 55, a plurality of pads 2c formed on the main surface 2a of the semiconductor chip 2 and a plurality of leads 92 of the lead frame 94 are respectively connected via a plurality of wires 3. Connect electrically. In the present embodiment, wire bonding is performed by a so-called positive bonding method in which the pads 2c of the semiconductor chip 2 are on the first bond side and the plurality of leads 92 of the lead frame 94 are on the second bond side. The lead 92 is electrically connected. Since the other points are the same as those of the first embodiment, a duplicate description is omitted.

5. Sealing step;
Next, the sealing step (S5) shown in FIG. 49 will be described. 56 is an enlarged plan view showing a state in which a sealing resin is formed in each device region of the lead frame shown in FIG. 54. FIG. 57 is a state in which a sealing resin is formed in each device region of the lead frame shown in FIG. FIG. In this step, the semiconductor chip 2, the plurality of wires 3, and the plurality of leads 92 shown in FIGS. 54 and 55 are sealed with the sealing resin 4a as shown in FIGS. 56 and 57, and the plurality of device regions 20a. The sealing resin 4 is formed on the surface of each. Further, in this step, the surface of the lead frame 94 in the dicing region 20c (the upper surface (surface) 95a of the dam bar 95 shown in FIG. 56) and the upper surface (surface) 92a of a portion of the lead 92 on the dam bar 95 side are exposed. Forming the resin 4. Specifically, in the sealing process, the dicing region 20c can be exposed as a clamp region, for example, as in the first embodiment, the cavity can be formed by the top gate method. When the sealing resin 4a is supplied into 31b, the sealing resin 4a is filled in the gaps around the cavity 31b and around the cavity 31b, so that the region surrounded by the lead 92 and the dam bar 95 around the cavity 31b. In this step, the in-dam resin 4d is formed, and in this step, the lower surface (back surface) 91b of the die pad 91 is formed. The sealing resin 4 is formed so that the lower surface (rear surface) 92b of the lead 92 is exposed from the sealing resin 4. The other points are the same as those in the first embodiment, and the description of the first embodiment. In the present embodiment, the description can be omitted because the wiring board 20 can be replaced with the lead frame 94. Strictly speaking, the wiring board 20 described in the first embodiment and the lead frame 94 of the present embodiment are the same. Since the number of device regions 20a is different, the number of cavities 31b is different correspondingly, that is, in the present embodiment, the upper mold 31 has 24 cavities 31b.

6). Plating process;
Next, as a plating step (S6) shown in FIG. 49, an exterior plating film made of, for example, solder is formed on the exposed portions (outer lead portions) of the plurality of lead frames 94 exposed from the sealing resin 4 shown in FIG. In this step, the lead frame 94, which is a workpiece to be plated, is placed in a plating tank (not shown) containing a plating solution (not shown), and, for example, an exterior plating film is formed by electrolytic plating. . According to this electrolytic plating method, the exterior conductor film can be collectively formed in the region exposed from the sealing resin 4. Therefore, for example, the outer plating film 91c and the outer plating film 92c shown in FIG. 48 are collectively formed in this step. The exterior plating films 91c and 92c of this embodiment are made of so-called lead-free solder that does not substantially contain Pb (lead). For example, only Sn (tin), Sn (tin) -Bi (bismuth), or Sn (Tin) -Ag (silver) -Cu (Cu). Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHs (Restriction of Hazardous Substances) directive. For this reason, the plating solution used in this plating step contains a metal salt such as Sn ²⁺ or Bi ³⁺ . In this embodiment, Sn—Bi alloyed metal plating is used as an example of lead-free solder plating, but Bi can be replaced with a metal such as Cu or Ag.

7). Individualization step;
Next, the singulation process (S7) shown in FIG. 49 will be described. 58 is an enlarged cross-sectional view showing a modification to FIG. 22, and FIG. 59 is an enlarged cross-sectional view showing a modification to FIG. 60, 61, and 62 are enlarged cross-sectional views showing modifications to FIGS. 28, 29, and 30, respectively.

  In the individualization step, the wiring board 20 is cut (divided) along the dicing area (dicing line) 20c using a dicing blade (rotating blade) 40, and is separated into individual device areas 20a. As another method of dividing the lead frame 94 into pieces, there is a method of dividing into pieces using a cutting punch and a die (support base) (pressing method). When a large number of device regions 20a are arranged in one lead frame 94 as in the present embodiment, each device region 20a is separated by the singulation method using the dicing blade 40 rather than the press working method. It can be singulated in a short time. Moreover, since the space of the dicing area 20c can be reduced, the number of products that can be obtained from one lead frame 94 can be increased.

  In the present embodiment, as shown in FIG. 58, the dicing blade 40 is attached to the lead frame 94 in a state where the lead frame 94 having the plurality of sealing resins 4 formed on the surface 94a side is fixed on the fixing jig 41. And run along the dicing region 20c from the back surface 94b side of the substrate. As shown in FIG. 58, in this step, dicing is performed in a state where the surface 94a in the dicing region 20c is not supported. That is, as in the first embodiment, the lead frame 94 is divided by the jig dicing method. In this step, the dicing blade 40 is disposed on the back side of the lead frame 94 for the following reason. First, in the individualization step, when the lead 92 is cut, burrs may occur in the cut cross section. By cutting from the back surface 94b side to the front surface 94a side of the lead frame 94, the burrs are formed in the lead 92. It can suppress protruding to the lower surface 92b side. Since the lower surface 92b of the lead 92 serves as a mounting surface when the QFN 90 (see FIG. 48) is mounted on a mounting board (not shown), if a burr is not projected on the mounting surface side, a short circuit failure or the like during mounting may be prevented. Can be suppressed. Further, in the singulation process, cutting is performed with the lead frame 94 fixed, but by suppressing the upper surface 92a side of the lead 92 as shown in FIG. For example, it can suppress that an exterior plating film etc. are damaged.

  The structure of the dicing blade 40, the rotating direction of the dicing blade 40, the method of moving the dicing blade 40 along the dicing area 20c, and the detailed structure of the fixing jig 41 have already been described in the first embodiment. The overlapping description is omitted. Further, although not shown in FIG. 58, at the time of cutting, the lead frame 94 is cut while spraying (supplying) the cutting fluid 45 shown in FIG. 22 onto the dicing blade 40 as in the first embodiment. It is.

  Here, similarly to FIGS. 68 to 71 described as the comparative example in the first embodiment, when the dicing blade 100 having a tip having a side surface orthogonal shape is used, the object to be cut is a lead as in the present embodiment. It was found that the string-like foreign material 101 (see FIG. 68) is generated even when the metal plate is used like the frame 94. In the case of the present embodiment, the string-like foreign matter 101 is made of a constituent material of the workpiece (for example, an exterior plating film made of a copper material, a nickel film, and solder constituting the lead frame 94). Moreover, the thickness of the foreign material 101 is about 20 μm to 30 μm, the width is the same as the width of the dicing blade 100, and the shape extends long in a string shape (band shape). Moreover, cutting traces (linear traces) remain along the longitudinal direction (the direction in which the dicing region 20c extends) on one surface of the string-like foreign material 101, and exterior plating is provided on the opposite surface. The film remains. That is, it was found that the phenomenon described as the comparative example in the first embodiment also occurred in the lead frame 94.

  In order to cut the lead frame 94, it is necessary to use a dicing blade 40 that is harder than the lead frame 94. For this reason, as described with reference to FIGS. 69 to 71 in the first embodiment, the stress (downward stress) due to the pressing force from the dicing blade 100 whose tip surface 100a is orthogonal to the side surface is in the cutting region. It concentrates on the end part (M part shown in FIGS. 69 and 70). For this reason, it is considered that the end portion of the cutting region is broken and the uncut region is pushed down before the entire central portion of the cutting region is cut. Further, the metal plate (copper material) constituting the lead frame 94 is less likely to undergo brittle fracture (high brittle fracture resistance) than the material constituting the sealing resin 4. In other words, the sealing resin 4 is more fragile than the lead frame 94. For this reason, it is thought that the uncut area | region pushed down became the string-like foreign material 101 as shown in FIG.

  Incidentally, in the present embodiment, as shown in FIG. 60, the width of the dicing blade 40 is larger than the width of the dam bar 95. When the width of the dicing blade 40 is narrower than the width of the dam bar 95, the plurality of leads 92 cannot be divided unless two or more rows are cut in the direction in which one dicing region 20c extends. On the other hand, according to the present embodiment, by making the width of the dicing blade 40 thicker than the width of the dam bar 95, the center of the dam bar 95 (center with respect to the width direction) and the center of the dicing blade 40 (center with respect to the width direction). If aligned and cut, the plurality of leads 92 connected to both sides of the dam bar 95 can be separated from each other by cutting one row in the direction in which one dicing region 20c extends. Here, aligning the center of the dam bar 95 with the center of the dicing blade 40 means that both side surfaces 40b of the dicing blade 40 are arranged closer to the device region 20a than the side surfaces of the dam bar 95. Therefore, the center position of the dam bar 95 and the center position of the dicing blade 40 are not limited to the same.

  Thus, if the width of the dicing blade 40 is made larger than the width of the dam bar 95, it is advantageous in that the number of times of cutting by the dicing blade 40 can be reduced. When the width of the dicing blade 100 shown in FIG. 6 is larger than the width of the dam bar 95 shown in FIG. 60, it has been found that string-like foreign matters are more likely to be generated. The string-like foreign matter is likely to occur when cutting a portion where the constituent members of the lead frame 94 continuously extend. As shown in FIG. 56 described in the sealing step, in the case of the lead frame 94, the in-dam resin 4d is formed in a region surrounded by the leads 92 and the dam bar 95. When the width of the dicing blade 100 is larger than the width of the dam bar 95 shown in FIG. 60, the end portion of the dicing blade 100 is formed by alternately cutting a part of the lead 92 and a part of the resin 4d in the dam. become. Thus, when cutting the dam bar 95 extending in a strip shape (continuously), when both ends of the dicing blade 100 alternately cut a part of the lead 92 and a part of the resin 4d in the dam, String-like foreign matter is likely to occur. In other words, when the width of the dicing blade 100 shown in FIGS. 69 to 71 is larger than the width of the dam bar 95 shown in FIG. 60, a part of the surface 94a side of the dam bar 95 is pushed down in an uncut state, The string-like foreign material 101 is likely to be generated.

  As described above, it is particularly preferable to use the dicing blade 40 described in the first embodiment as a method for suppressing the generation of the string-like foreign material 101 when the lead frame 94 is singulated.

  First, as shown in FIG. 60, in the region immediately before the apex 40c where the two tapered surfaces 40a intersect each other reaches the surface 94a of the lead frame 94, the end of the cutting region (M portion in FIG. 28), and Stress concentrates in the vicinity of the vertex 40c where the tapered surfaces 40a intersect. However, the lead 92 of the lead frame 94 still has a sufficient thickness at the end portion (M portion) of the cutting region. Further, since the stress from the dicing blade 40 is applied in an oblique direction (a direction orthogonal to the tapered surface 40a) by forming the tapered surface 40a, the downward component becomes small. Therefore, in this region, the uncut region is hardly broken.

  Next, as shown in FIG. 61, in the region where the thickness of the end portion (M portion in FIG. 61) of the cutting region is, for example, about 20 μm to 30 μm, stress concentrates on this end portion. However, in the region shown in FIG. 61, since the tip (vertex 40c) of the dicing blade 40 has already reached the lower side of the surface 94a of the lead frame 94, the stress concentrated on the end is small. In addition, in the region shown in FIG. 61, the dam bar 95 (see FIG. 65) that is likely to become a string-like foreign substance 101 is almost cut, so that it is difficult to be pushed down in an uncut state.

  Then, as shown in FIG. 62, the lead frame 94 can be cut by cutting until the side surface 40b of the dicing blade 40 penetrates the surface 94a of the lead frame 94. At this time, the leads 92 connected to both sides of the dam bar 95 (see FIG. 60) are separated and become independent members.

  As described above, in the present embodiment, by using the dicing blade 40 having the tapered surface 40a, it is possible to prevent breakage of the uncut region, so that the surface of the lead frame 94 can be generated without generating string-like foreign matter. Cutting up to 94a is possible. When all the dicing areas (dicing lines) 20c surrounding the device area 20a are cut, the device areas 20a of the lead frame 94 are separated into pieces, and a plurality of QFNs 90 shown in FIGS. 45 to 48 can be obtained.

  As a modification of the dicing blade 40 shown in FIGS. 58 to 62, the preferred mode described in the first embodiment and various modifications can be applied. Hereinafter, a particularly preferable aspect in the present embodiment will be described.

  As shown in FIG. 31, from both ends of the tapered surface 40a where stress is concentrated at the time of cutting (ends intersecting the side surface 40b and the apex 40c where the two tapered surfaces 40a intersect), deformation is sequentially caused by wear, The case where it curves is demonstrated. In this case, the width W1 of the curved surface 40d in which the apex 40c where the two tapered surfaces 40a intersect is curved due to wear is preferably smaller than the width of the dam bar 95 (see FIG. 60). Thereby, the dam bar 95 can be cut first.

  Furthermore, when the side surface orthogonal surface 40e facing the plane of the workpiece is provided between the two tapered surfaces 40a as in the dicing blade 50 shown in FIG. 32, the width W1 of the side surface orthogonal surface 40e. However, it is preferable that the width of the dam bar 95 (see FIG. 60) is narrower.

  Next, each process described in the section <Washing, drying, and pick-up process> in the first embodiment is performed, but since it can be performed in the same manner as in the first embodiment, a duplicate description is omitted.

(Embodiment 5)
In the fourth embodiment, the embodiment in which dicing is performed in a state where the surface side of the lead frame is fixed by a fixing jig has been described. In the present embodiment, as a modification of the fourth embodiment, an embodiment will be described in which dicing is performed in a state where the upper surface of the sealing resin is fixed using an adhesive tape called a dicing tape. In the present embodiment, differences from the fourth embodiment will be mainly described, and a duplicate description will be omitted. FIG. 63 is a cross-sectional view showing a modification to FIG.

  The difference between the QFN 90 shown in FIG. 48 and the QFN 96 shown in FIG. 63 is that a part of the side surface of the sealing resin 4 is cut and the lead 92 does not protrude from the side surface of the sealing resin 4. In the QFN 96, the protruding portion of the lead 92 is cut together with a part of the sealing resin 4 in the individualization step. Therefore, the QFN 96 is a semiconductor device that is smaller (smaller in planar size) than the QFN 90 shown in FIG.

  Next, a method for manufacturing QFN 96 will be described focusing on differences from the fourth embodiment. Specifically, the manufacturing method of QFN 96 is the same as the manufacturing method of QFN 90 described in the fourth embodiment except for the sealing step (S5) and the individualization step (S7). However, in the present embodiment, a part of the side surface of the sealing resin 4 is cut in the singulation step (S7), so that the distance between the adjacent device regions 20a is made even closer than in the fourth embodiment. Can do. For this reason, the arrangement space of the device region 20a can be made efficient.

  Next, a difference between the sealing step (S5) of the present embodiment and the fourth embodiment will be described. 64 is an enlarged plan view showing a modification to FIG. 56, and FIG. 65 is an enlarged cross-sectional view along the line Af-Af in FIG. As shown in FIG. 65, in the sealing process of the present embodiment, a so-called side gate method in which a gate portion is provided on a part of the side surface of the cavity 31b and the sealing resin 4a is supplied from the side surface side of the cavity 31b. Thus, the sealing resin 4 is formed. In the side gate method, the structure of the molding die 30 can be simplified as compared with the top gate method, so that the resin sealing device can be downsized. In addition, by simplifying the structure, the molding die 30 can be easily maintained. Moreover, since the flow path of the sealing resin 4a can be simplified, the amount of the sealing resin 4a used can be reduced.

  When the resin sealing is performed by the side gate method, the sealing resin 4a is supplied from the runner portion 31d shown in FIG. 65 via the gate portion 31c disposed on the side surface of the cavity 31b. When the cavity 31b in the first row is filled with the sealing resin 4a, the second through the gate part 31c (the gate part between the cavities is called a through gate) disposed between the adjacent cavities 31b. The sealing resin 4a is supplied to the cavity 31b in the row. As described above, in the side gate method, the sealing resin 4a is sequentially supplied into the plurality of cavities 31b connected by the gate portion 31c. For this reason, when the sealing process is completed, as shown in FIG. 64, the gate resin 4b is formed between the adjacent device regions 20a. Here, as shown in FIG. 57 described in the fourth embodiment, when the cavity 31b is arranged so as not to cover the dicing region 20c, the gate resin 4b shown in FIG. Will remain. Therefore, in the fourth embodiment, the top gate method in which the gate resin 4b is formed on the cavity 31b is applied. On the other hand, in the present embodiment, as shown in FIG. 65, the cavity 31b is arranged so as to cover a part of the dicing region 20c. That is, the gate resin 4b is removed in the singulation process. Therefore, the gate resin 4b does not remain in the completed product QFN96 shown in FIG. For this reason, in the present embodiment, a side gate method that is advantageous in terms of downsizing the resin sealing device, ease of maintenance, or reducing the amount of sealing resin 4a used is applied. Since the other details of the sealing process are the same as those in the fourth embodiment, a duplicate description is omitted.

  Next, the difference from the fourth embodiment will be described with respect to the individualization step (S7) of the present embodiment. 66 is an enlarged cross-sectional view showing a modification to FIG. 58, and FIG. 67 is an enlarged cross-sectional view showing a modification to FIG. FIG. 76 is an enlarged cross-sectional view showing a comparative example in which the lead frame 94 shown in FIG. 67 is cut using the dicing blade shown in FIGS. As shown in FIG. 66, in the singulation process of the present embodiment, the fixing jig 41 described in the fourth embodiment is not used, and a film material 97 called dicing tape is used instead of the sealing resin 4. The lead frame 94 is fixed by adhering to the upper surface. If the distance between the adjacent device regions 20a is reduced as in the present embodiment, a space for arranging the convex portions 41c as shown in FIG. 58 cannot be secured. For this reason, in this embodiment, the dicing blade 40 is run from the back surface 94b side in a state where the lead frame 94 is fixed by adhering the film material 97 to the sealing resin 4. In the present embodiment, since the film material 97 is not bonded to the back surface side of the lead frame 94, a paste material or an adhesive (not shown) disposed on the bonding surface of the film material 97 is mounted on the mounting surface of the lead 92. Adhesion to the lower surface (back surface) 92b, which is the mounting surface, can be prevented. Thus, even when the film material 97 is stuck and fixed to the upper surface 4c of the sealing resin 4, the space between the surface 94a and the film material 97 in the dicing area 20c is a hollow space, and the dicing area 20c The point of performing the cutting process in a state where the surface 94a is not supported is the same as in the fourth embodiment.

  Moreover, in the individualization process of this Embodiment, as shown in FIG. 66, a part of side surface inclined with respect to the upper surface 4c of the sealing resin 4 is in the dicing region 20c (in other words, in the cutting region). Has been placed. That is, in this embodiment, together with the dam bar 95, part of the lead 92 on the dam bar 95 side and part of the side surface of the sealing resin 4 are cut. In this case, as shown in FIG. 76, a part of the sealing resin 4 remains immediately below the end portion (M portion) of the cutting region. However, according to the study by the present inventor, when cutting is performed using a dicing blade 100 whose tip surface 100a is orthogonal to the side surface as shown in FIG. 76, a string mainly made of a metal material constituting the lead frame 94 is used. It was found that a foreign material was easily generated. This is considered to be due to the following reason. That is, as shown in FIG. 76, when the lead frame 94 is thinned by cutting, breakage due to stress concentration tends to occur at the end of the cutting region as in the fourth embodiment. At this time, a part of the sealing resin 4 is present just below the end of the cutting region, but the sealing resin 4 is more fragile than the constituent material of the lead frame 94. Moreover, since the dicing area 20c of the lead frame 94 made of a metal material is cut, an excessive pressing force is applied to the sealing resin 4 in the cutting area. For this reason, as shown in FIG. 76, as long as a part of the side surface of the sealing resin 4 remains slightly, the breakage cannot be suppressed, and eventually the string-like foreign matter as in the fourth embodiment. Is considered to occur.

  From the viewpoint of suppressing the occurrence of such string-like foreign matters, when the lead frame 94 is fixed by the film material 97 or when a part of the side surface of the sealing resin 4 is cut as in the present embodiment. However, as shown in FIGS. 66 and 67, the method using the dicing blade 40 is effective. In addition, since the effect | action at the time of using the dicing blade 40 is the same as that of the said Embodiment 4, the overlapping description is abbreviate | omitted. Moreover, as a modification of the dicing blade 40, the preferred mode described in the fourth embodiment and various modifications can be applied.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to third embodiments, the wiring substrate 20 in which the insulating films 16 and 17 in the dicing region 20c and the wiring 12 (feeding line 12c) in the dicing region 20c have been removed in advance has been described. However, this process can be omitted when there is no need to remove the wiring 12, for example, when the power supply line 12c is not formed. In this case, the surface 10a of the dicing region 20c is covered with the insulating film 16 in the individualization step described above. Since the insulating film 16 has a lower brittle fracture resistance than the material constituting the insulating layer 14, when a foreign material derived only from the insulating film 16 is generated, the foreign material is unlikely to be a long string. However, since the brittle fracture resistance of the insulating film 16 is low, even if the insulating film 16 of about 20 μm, for example, is formed on the upper surface 14a of the insulating layer 14 shown in FIG. Foreign matter 101 is generated. Accordingly, this can be prevented by using the dicing blade 40 (see FIGS. 26 and 31), the dicing blade 50 (see FIG. 32), or the dicing blade 51 (see FIG. 33) described in the first embodiment. can do.

  Further, for example, in the first to fifth embodiments, the aspect of performing the cutting process while supplying the cutting fluid 45 to the dicing blade in the cutting process has been described, but the cutting process is performed without supplying the cutting liquid. It can also be applied to the case where Even if the cutting fluid is not supplied, cutting waste is generated. Therefore, there is a concern that the chip mounting surface side of the wiring board is contaminated by the cutting waste, but the technique described in the first to fifth embodiments is used. By applying this, this can be prevented or suppressed.

  For example, in the third embodiment, a POP type semiconductor device has been described as an example of a face-down mounting type semiconductor device. However, a semiconductor device that employs the face-down mounting method is not limited to a semiconductor device having a stacked structure, and can be applied to, for example, a single-layer type semiconductor device as described in the first embodiment.

  Further, for example, in the first embodiment, the wiring board 10 having two wiring layers, and in the second and third embodiments, the wiring boards 71 and 81 which are multilayer wiring boards having four wiring layers are taken as examples. explained. However, the number of wiring layers can be selected according to the planar size of the semiconductor device and the number of terminals. For example, the wiring board 10 may be a multilayer wiring board having four or more wiring layers. The wiring boards 71 and 81 may be wiring boards having two wiring layers.

  In the fourth embodiment and the fifth embodiment, QFN has been described as an example of a lead frame mounting type semiconductor device. However, the present invention can also be applied to, for example, SON.

  The present invention is applicable to a semiconductor device that cuts a substrate on which a semiconductor chip is mounted with a dicing blade.

1, 70, 73, 80 Semiconductor device 2 Semiconductor chip 2a Main surface (first main surface)
2b Back surface (second main surface)
2c Pad 3 Wire (conductive member)
4 Sealing resin (sealing body)
4a Sealing resin 4b Gate resin (resin in the gate)
4c Upper surface 4d Resin in dam 5 Solder ball (solder material)
6 Adhesive 10, 71, 81 Wiring board (board)
10a Front surface 10b Back surface 10c Chip mounting area 10d Exposed portion 11 Bonding leads 12, 12d, 12e Wiring 12a Wiring (uppermost layer wiring)
12b wiring (lowermost layer wiring)
12c Feed line 13 Land (terminal, electrode)
14 Insulating layer (core layer)
14a Upper surface 14b Lower surface 14c Side surface 14d Insulating layer (core layer)
14e upper surface 14f lower surface 14g, 14h insulating layer 15 wiring (wiring in via, interlayer wiring)
15a Via (hole)
16, 17 Insulating film (solder resist film, protective film)
16a, 17a Opening 16b, 17b Opening groove 16c Opening 20 Wiring board (board)
20a Device region 20b Frame portion 20c Dicing region (dicing line)
30 Molding die 31 Upper die 31a Lower surface 31b Cavity 31c Gate portion 31d Runner portion 32 Lower die 32a Upper surface 40, 50, 51, 100 Dicing blade (rotary blade)
40a, 51a Tapered surface 40b Side surface 40c Vertex 40d Curved surface 40e Side surface orthogonal surface 41 Fixing jig 41a Upper surface 41b Recessed portion (recessed portion, groove portion)
41c Convex (wall)
41d Groove 41e Upper surface (pressing surface, support surface)
41f Ventilation hole 41g Air passage 42 Table (base plate)
43 Rotating direction 44 Cutting direction 45 Cutting fluid 52 Cleaning fluid 53 Suction jig 72 Land (electrode, electrode pad, terminal)
74 Memory chip (semiconductor chip)
75, 86 Solder balls (bonding material, bonding material between substrates)
76 Wiring board 83 Bump electrode (conductive member)
84 Bonding lead 85 Underfill resin (sealing resin, sealing body)
90, 96 QFN (semiconductor device)
91 Die pad (chip mounting part)
91a Top surface (surface, chip mounting surface)
91b Bottom (back)
91c, 92c Exterior plating film 92 Lead (terminal)
92a Top surface (surface)
93 Suspended lead 94 Lead frame (substrate)
94a Surface (upper surface)
94b Back (bottom)
95 Dam Bar (Tie Bar, Dam Section)
95a Upper surface (surface)
97 Film material (dicing tape)
100a Front end surface 100b Side surface 100c Curved surface 101 Foreign material 102 Region 103 Collective sealing resin 104 Foreign material W1 Width W2 Width θ1 Angle θ2 Angle

Claims (33)

A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a wiring board including a plurality of device regions and a dicing region provided between adjacent device regions of the plurality of device regions;
(B) A semiconductor chip having a first main surface, a plurality of electrodes formed on the first main surface, and a second main surface opposite to the first main surface, in each of the plurality of device regions. Mounting on the surface;
(C) electrically connecting the plurality of electrodes of the semiconductor chip and the plurality of first terminals formed on the surface of the wiring board through a plurality of conductive members;
(D) The semiconductor chip, the plurality of conductive members, and the plurality of first terminals are made of resin so that a part of the surface in each of the plurality of device regions and the surface in the dicing region are exposed. Sealing and forming a sealing body on the surface of each of the plurality of device regions;
(E) In a state where the part of the surface in each of the plurality of device regions is supported by the upper surface of a fixing jig and the surface in the dicing region is not supported, a rotating blade is used to form the dicing region. Dividing the wiring board along the line;
here,
Each of the plurality of device regions is
An insulating layer having the upper surface and a lower surface opposite to the upper surface;
The plurality of first terminals formed on the upper surface of the insulating layer;
A plurality of first wirings formed on the upper surface of the insulating layer and electrically connected to the plurality of first terminals;
A first insulating film formed on the upper surface of the insulating layer such that the plurality of first terminals are exposed and the plurality of first wirings are covered;
A plurality of lands formed on the lower surface of the insulating layer;
A plurality of second wirings formed on the lower surface of the insulating layer and electrically connected to the plurality of lands, respectively;
A second insulating film formed on the lower surface of the insulating layer so that the plurality of lands are exposed and the plurality of second wirings are covered;
A hole formed from one surface side of the upper surface and the lower surface toward the other surface side;
A third wiring formed inside the hole and electrically connecting the first wiring and the second wiring;
Have
An inclined surface is formed at the tip of the rotary blade,
The angle formed by the inclined surface and the side surface of the rotary blade is greater than 90 degrees. In claim 1,
The method for manufacturing a semiconductor device, wherein the sealing body formed in the step (d) is more fragile than the insulating layer of the wiring board. In claim 2,
A method of manufacturing a semiconductor device, wherein a plurality of external connection terminals are formed on the plurality of lands after the step (d) and before the step (e). In claim 3,
The fixing jig is
A plurality of recesses that respectively accommodate the plurality of sealing bodies formed on the wiring board, a convex portion formed between the plurality of concave portions, and a groove portion formed between the convex portions,
In the step (e),
In each of the plurality of device regions, the wiring substrate is adsorbed and fixed so that the part of the surface exposed from the sealing body and the surface of the dicing region face the upper surface of the convex portion. Thus, a cutting method is performed by moving one or both of the rotary blade and the wiring board along the groove. In claim 4,
In the step (e),
A method of manufacturing a semiconductor device, wherein the rotary blade is inserted and cut into the groove of the fixing jig. In claim 5,
An angle formed by the inclined surface and the side surface of the rotary blade is greater than 130 degrees. In claim 6,
An angle formed by the inclined surface and the side surface of the rotary blade is less than 150 degrees. In claim 7,
The method of manufacturing a semiconductor device, wherein the first insulating film is removed in the dicing region of the wiring board. In claim 8,
In the step (e),
The method of manufacturing a semiconductor device, wherein the rotary blade rotates from the back surface of the wiring board toward the front surface. In claim 1,
At the tip of the rotary blade,
A first inclined surface formed from the first side surface toward the second side surface located on the opposite side of the first side surface;
A method for manufacturing a semiconductor device, comprising: a second inclined surface formed from the second side surface toward the first side surface. In claim 10,
The first and second inclined surfaces are:
A method of manufacturing a semiconductor device, wherein the semiconductor devices cross each other in the middle of the first and second side surfaces. In claim 10,
The rotary blade is
A tip surface intersecting the first and second inclined surfaces is provided between the first and second inclined surfaces, and the width of the tip surface is the width of the first inclined surface and the first A method of manufacturing a semiconductor device, wherein the width is smaller than the width of the inclined surface. In claim 1,
The insulating layer of the wiring board is
A first insulating layer having an upper surface and a lower surface;
And a second insulating layer stacked on the upper surface side of the first insulating layer. In claim 13,
The method of manufacturing a semiconductor device, wherein the second insulating layer is thinner than the first insulating layer. In claim 13,
The first insulating layer includes glass fiber,
The method for manufacturing a semiconductor device, wherein the second insulating layer does not contain glass fiber. A method for manufacturing a semiconductor device comprising the following steps:
(A) preparing a wiring board including a plurality of device regions and a dicing region provided between adjacent device regions of the plurality of device regions;
(B) A semiconductor chip having a first main surface, a plurality of electrodes formed on the first main surface, and a second main surface opposite to the first main surface, in each of the plurality of device regions. Mounting on the surface and electrically connecting the plurality of electrodes of the semiconductor chip and the plurality of first terminals formed on the surface of the wiring substrate through a plurality of conductive members;
(C) Rotating in a state where a part of the surface of the wiring board located around the semiconductor chip in each of the plurality of device regions is supported by the upper surface of the fixing jig and the surface in the dicing region is not supported Dividing the wiring board along the dicing region using a blade;
here,
Each of the plurality of device regions is
An insulating layer having the upper surface and a lower surface opposite to the upper surface;
The plurality of first terminals formed on the upper surface of the insulating layer;
A plurality of first wirings formed on the upper surface of the insulating layer and electrically connected to the plurality of first terminals;
A first insulating film formed on the upper surface of the insulating layer such that the plurality of first terminals are exposed and the plurality of first wirings are covered;
A plurality of lands formed on the lower surface of the insulating layer;
A plurality of second wirings formed on the lower surface of the insulating layer and electrically connected to the plurality of lands, respectively;
A second insulating film formed on the lower surface of the insulating layer so that the plurality of lands are exposed and the plurality of second wirings are covered;
A hole formed from one surface side of the upper surface and the lower surface toward the other surface side;
A third wiring formed inside the hole and electrically connecting the first wiring and the second wiring;
Have
An inclined surface is formed at the tip of the rotary blade,
The angle formed by the inclined surface and the side surface of the rotary blade is greater than 90 degrees. In claim 16,
In the step (b), after electrically connecting the plurality of electrodes and the plurality of first terminals of the wiring board, respectively, the first main surface of the semiconductor chip and the surface of the wiring board A step of supplying a sealing resin between and sealing the first main surface side of the semiconductor chip,
The method of manufacturing a semiconductor device, wherein the sealing resin is more fragile than the insulating layer of the wiring board. In claim 17,
A method of manufacturing a semiconductor device, wherein a plurality of external connection terminals are formed on the plurality of lands after the step (b) and before the step (c). In claim 18,
The fixing jig is
A plurality of recesses that respectively accommodate a plurality of sealing bodies formed on the wiring board, a protrusion formed between the plurality of recesses, and a groove formed between the protrusions,
In the step (c),
In each of the plurality of device regions, a part of the surface exposed from the sealing body, and the wiring substrate is sucked and fixed so that the surface in the dicing region faces the upper surface of the convex portion. A method of manufacturing a semiconductor device, wherein cutting is performed by moving one or both of the rotary blade and the wiring board along the groove. In claim 19,
In the step (c),
A method of manufacturing a semiconductor device, wherein the rotary blade is inserted and cut into the groove of the fixing jig. In claim 20,
An angle formed by the inclined surface and the side surface of the rotary blade is greater than 130 degrees. In claim 21,
An angle formed by the inclined surface and the side surface of the rotary blade is less than 150 degrees. In claim 22,
The method of manufacturing a semiconductor device, wherein the first insulating film is removed in the dicing region of the wiring board. In claim 23,
In the step (c),
The method of manufacturing a semiconductor device, wherein the rotary blade rotates from the back surface of the wiring board toward the front surface. A method for manufacturing a semiconductor device comprising the following steps:
(A) Formed on each of the front surface, the back surface opposite to the front surface, a plurality of device regions, a dicing region provided between adjacent device regions of the plurality of device regions, and the plurality of device regions Preparing a lead frame having a plurality of leads disposed around the chip mounting portion in each of the chip mounting portion and the plurality of device regions;
(B) A semiconductor chip having a first main surface, a plurality of electrodes formed on the first main surface, and a second main surface opposite to the first main surface, in each of the plurality of device regions. Mounting on the chip mounting portion;
(C) electrically connecting the plurality of electrodes of the semiconductor chip and the plurality of leads of the lead frame via a plurality of conductive members;
(D) The semiconductor chip, the plurality of conductive members, and the plurality of leads are sealed with resin so that a surface of the lead frame in the dicing region is exposed, and sealed in each of the plurality of device regions. Forming a stop;
(E) Running a rotary blade from the back surface side of the lead frame in a state of supporting a part of the surface in each of the sealing body or the plurality of device regions and not supporting the surface in the dicing region. Dividing the lead frame along the dicing area;
here,
An inclined surface is formed at the tip of the rotary blade,
The angle formed by the inclined surface and the side surface of the rotary blade is greater than 90 degrees. In claim 25,
The method of manufacturing a semiconductor device, wherein the rotary blade is harder than the lead frame. In claim 26,
The method for manufacturing a semiconductor device, wherein the sealing body formed in the step (d) is more fragile than the lead frame. In claim 27,
An angle formed by the inclined surface and the side surface of the rotary blade is greater than 130 degrees. In claim 28,
An angle formed by the inclined surface and the side surface of the rotary blade is less than 150 degrees. In claim 25,
At the tip of the rotary blade,
A first inclined surface formed from the first side surface toward the second side surface located on the opposite side of the first side surface;
A method for manufacturing a semiconductor device, comprising: a second inclined surface formed from the second side surface toward the first side surface. In claim 30,
The first and second inclined surfaces are:
A method of manufacturing a semiconductor device, wherein the semiconductor devices cross each other in the middle of the first and second side surfaces. In claim 31,
In the dicing region of the lead frame prepared in the step (a), a dam portion extending along the dicing region is disposed,
Among the plurality of leads formed in each of the plurality of device regions, the plurality of leads disposed to face each other via the dam portion are connected to the dam portion, respectively.
In the step (e), the dicing region is cut using the rotary blade having a width wider than the dam portion. In claim 32,
The rotary blade is
Between the first and second inclined surfaces, there is a tip surface that intersects the first and second inclined surfaces, and the width of the tip surface is narrower than the width of the dam part, A method for manufacturing a semiconductor device.

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