JP2011204856A - Nonvolatile semiconductor memory device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve stress resistance of a memory cell array.SOLUTION: A local selection gate electrode CSG partially selects memory cell transistors MT (for example, memory cell transistors MTto MT) and then can make other memory cell transistors MT (for example, memory cell transistors MTto MT) unselected, so that a high voltage need not be applied to the memory cell transistors MT having been made unselected.

Description

  The present invention relates to a nonvolatile semiconductor memory device having a stacked memory cell structure and a method for manufacturing the same.

  As this type of nonvolatile semiconductor memory device, a stacked memory cell structure has been proposed (see, for example, Patent Documents 1 to 5). According to these technical ideas described in Patent Documents 1 to 5, a cell unit structure of a NAND flash memory is configured by sequentially stacking memory cells on a semiconductor substrate.

  For example, in the technical idea described in Patent Document 1, a first stacked body in which a plurality of first gate electrodes included in a plurality of first memory cells are stacked via an insulating layer, and a plurality of second memories. A second stacked body in which a plurality of second gate electrodes included in the cell are stacked via an insulating layer, and provided on the side surfaces of the first and second stacked bodies, respectively, and the charge storage layer is provided inside And the first pillar provided on the side surface of the first gate insulating film, and the first pillar provided on the side surface of the second gate insulating film. A first semiconductor layer including a second pillar electrically connected; a first selection transistor connected in series to the first memory cell and provided on the first pillar; And a second selection transistor connected in series to the memory cell and provided on the second pillar. It is configured by including a Njisuta.

  However, since it is necessary to frequently apply a voltage to each word line connecting the memory cell structure at the time of programming or / and reading, the stress applied to each memory cell increases, resulting in poor stress resistance of the memory cell array. .

JP 2007-317874 A JP 2008-159699 A JP 2009-224574 A JP 2009-224633 A JP 2009-146554 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device having improved stress resistance of a memory cell array and a method for manufacturing the same.

  One aspect of the present invention is a semiconductor substrate in which a first active region is formed on a surface layer, and a local cell group selection gate electrode formed on the first active region of the semiconductor substrate via a gate insulating film, A local cell group selection gate electrode in which a first active region is located on both sides; a stacked body in which a plurality of memory cell gate electrodes are stacked on the local cell group selection gate electrode via an insulating film; and the local cell A plurality of memory cells in a second active region that contacts the first active region located on both sides of the group selection gate electrode, on at least one side of one side, the upper side, or the other side of the stacked body; It is characterized by comprising a second active region that is structurally continuously formed facing the gate electrode, and a charge storage layer located between the opposed second active region and the plurality of memory cell gate electrodes.

  Another aspect of the present invention includes a selection gate transistor formed between a bit line and a source line, a plurality of local cell group selection gate transistors electrically connected between the pair of selection gate transistors, and the local A plurality of local memory cell transistors connected in parallel to the cell group selection gate transistor, and a plurality of local memory cell transistors corresponding to the plurality of local cell group selection gate transistors, respectively, and a pair of selection gate transistors And a control circuit for electrically selecting / deselecting the local memory cell transistor by controlling on / off of the local cell group selection gate transistor. Yes.

  Another aspect of the present invention is a laminate in which a plurality of insulating layers and conductive films for memory cell gate electrodes are repeatedly stacked on a semiconductor substrate via a conductive film for a gate insulating film and a local cell group selection gate electrode. And forming the bottom layer of the plurality of stacked bodies as a local cell group selection gate electrode by dividing the stacked body into a plurality of parts and exposing the side walls of the plurality of stacked bodies. Forming a diffusion layer constituting a first active region on the surface layer of the semiconductor substrate on both sides of the plurality of stacked bodies, and forming a charge storage layer along the side walls of the plurality of stacked bodies And a step of forming a semiconductor layer serving as a second active region on the outer wall surface of the charge storage layer and on the top surfaces of the plurality of stacked bodies, the memory cell gate sandwiching the charge storage layer Opposite the electrode It is characterized by comprising a step of forming a semiconductor layer to be in contact with the upper surface of the diffusion layer with.

  According to the present invention, the stress resistance of the memory cell array can be improved.

1 is a block diagram schematically showing an electrical configuration of a nonvolatile semiconductor memory device according to an embodiment of the present invention. Circuit diagram schematically showing electrical connection relationship of cell units in memory cell region Circuit diagram showing electrical configuration of cell unit A plan view schematically showing the structure of the select gate electrode in the memory cell region Sectional drawing which shows typically the cross-sectional structure which follows the AA line of FIG. 4 of a cell unit. Sectional drawing which shows typically the cross-sectional structure which follows the BB line of FIG. 4 of a cell unit. Explanatory diagram of cell unit applied voltage at the time of writing / reading / erasing Schematic diagram showing one manufacturing stage (1) Schematic diagram showing one manufacturing stage (Part 2) Schematic diagram showing one manufacturing stage (Part 3) Schematic diagram showing one manufacturing stage (Part 4) Schematic diagram showing one manufacturing stage (Part 5) Schematic diagram showing one manufacturing stage (Part 6) Schematic diagram showing one manufacturing stage (Part 7) Schematic diagram showing one manufacturing stage (Part 8) Schematic diagram showing one manufacturing stage (No. 9) Schematic diagram showing one manufacturing stage (No. 10) Schematic diagram showing one manufacturing stage (Part 11) Schematic diagram showing one manufacturing stage (No. 12) Schematic diagram showing one manufacturing stage (Part 13)

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 schematically shows an electrical configuration of a NAND flash memory device 1 as a nonvolatile semiconductor memory device using a block diagram.

  As shown in FIG. 1, a flash memory device 1 includes a memory cell array Ar configured by arranging a large number of memory cell transistors MT in a matrix, and read processing / reading of each memory cell transistor MT of the memory cell array Ar. And a peripheral circuit PC for performing write / erase processing. The memory cell array Ar is configured in the memory cell region M, and the peripheral circuit PC is configured in the peripheral region of the memory cell region M.

  As shown in FIG. 1, the peripheral circuit PC is configured by connecting a control circuit CC, a row drive circuit RD electrically connected to the control circuit CC, a column drive circuit CD, and a sense amplifier circuit SA. Has been. The control circuit CC transmits a control signal to the row driving circuit RD and the column driving circuit CD, and performs writing / reading / erasing of each memory cell transistor MT constituting the memory cell array Ar.

  First, the basic electrical configuration of the entire memory cell array will be described with reference to FIG. FIG. 2 schematically shows the electrical connection relationship of the cell units in the memory cell array. As shown in FIG. 2, the memory cell array Ar in the memory cell region M is configured by arranging a large number of cell units UC (NAND cell units).

  These cell units UC constitute one block Bj by being arranged in parallel in a predetermined column (n columns) in the arrangement direction of the bit lines BL. The memory cell array Ar is configured by arranging one block Bj in a plurality of columns (z columns) in the bit line BL direction.

FIG. 2 shows the electrical connection relationship of the select gate electrodes in the cell unit in the memory cell array. The cell unit UC includes a selection gate transistor STD connected to a bit line BL (BL ₀ ... BL _n-1 ) extending in the column direction, a selection gate transistor STS connected to a source line CSL, and the two ( And a plurality of local cell group selection gate transistors CSGT (CSGT _{0 to} CSGT ₇ : hereinafter, local selection transistors) connected in series between a plurality of selection gate transistors STD-STS.

  The select gate transistors STD of the plurality of cell units UC are electrically connected by their select gate electrodes SGD. The select gate transistors STS of the plurality of cell units UC arranged in the row direction are electrically connected by their select gate electrodes SGS.

Further, the local selection gate transistors CSGT of the plurality of cell units UC arranged in the row direction are electrically connected by their local cell group selection gate electrodes CSG (CSG ₀ ... CSG _n−1 : hereinafter, local selection gate electrodes). It is connected.

The selection gate transistors STS of the plurality of cell units UC arranged in the row direction have their sources connected to the source line CSL. The sense amplifier SA shown in FIG. 1 is connected to the bit lines BL (BL _{0 to} BL _n−1 ), and is connected to a latch circuit that temporarily stores the data when reading the data.

  The present embodiment is characterized by the electrical configuration and structure of each cell unit UC. Hereinafter, an electrical configuration of one cell unit UC will be described in detail with reference to FIG. FIG. 3 shows an electrical configuration of the cell unit UC. An electrical configuration having the same function as that of the electrical configuration shown in FIG.

The cell unit UC includes a plurality of memory cell transistors MT (MT ₀ ... MT _m−1 ) connected in series (for example, m = 2 to the power k = 64) between two select gate transistors STD-STS. Comprising.

Memory cell transistors MT of the cell units UC arranged in the row direction (MT ₀ ~MT _m-1), respectively, electrically connected the gate electrode by a word line _{WL (WL 0 ~WL m-1} ) Has been. Note that the word lines WL (WL _{0 to} WL _m−1 ) are simplified in FIG. 3, but are formed to extend in the row direction (X direction) shown in FIG.

As shown in FIG. 3, one cell unit UC includes selection gate transistors STD and STS, local selection transistors CSGT (CSGT _{0 to} CSGT ₇ ), memory cell transistors MT (MT _{0 to} MT _m-1 ), and dummy transistors. DM (DM _{0 to} DM ₁₅ ) and a plurality of mutual interference suppressing dummy gate electrodes IDG and IDG ₂ are included.

The local selection transistor CSGT is provided in a number (for example, 8) which is a divisor of the number (for example, 64) of the memory cell transistors MT for one cell unit UC. In the present embodiment, the local selection transistor CSGT _b (where b is 0 to 7) is provided corresponding to the memory cell transistors MT _b × _{8 to} MT _b × _{8 + 7} .

The local selection transistor CSGT _b is connected to both ends of memory cell transistors MT _b × _{8 to} MT _b × _{8 + 7} (local memory cell transistors) whose sources / drains are connected in series. Thus, the local selection transistor CSGT _b and the memory cell transistor _{MT b × 8 ~MT b × 8} + 7 are connected in parallel, the control circuit CC to turn on the local selection transistors CSG _b, the corresponding memory cell transistors MT _b X _{8 to} MT _b x _{8 + 7} can be deselected. That is, these local selection transistors CSG _b enable selection / non-selection of the corresponding memory cell transistors MT _b × _{8 to} MT _b × _{8 + 7} .

The dummy transistors DM _{0 to} DM ₇ are provided corresponding to the selection gate transistors STD. These dummy transistors DM _{0 to} DM ₇ are provided to maintain the periodicity of the lithography process, and do not function electrically in the cell unit UC. Similarly, the dummy transistor DM ₈ to dm ₁₅ are provided corresponding to the selected gate transistor STS. These dummy transistors DM ₈ to dm ₁₅ also intended to be provided to hold the periodicity of the lithographic process, not electrically functional in the cell unit UC.

  FIG. 4 schematically shows a part of the planar structure of the cell unit. 5 schematically shows a cross-sectional structure of the cell unit by a sectional view taken along the line AA in FIG. 4, and FIG. 6 schematically shows a sectional view taken along the line BB in FIG. Show.

As shown in FIG. 4, local cell group selection gate electrodes CSG _{0 to} CSG ₇ (hereinafter abbreviated as local selection gate electrode CSG) are configured to intersect with active region 1e (see FIGS. 5 and 6 described later). Yes. The selection gate electrodes SGD and SGS are configured to intersect the active region 1e, and are provided in parallel with the local selection gate electrode CSG.

  As shown in FIG. 5, a plurality (ten pieces) of the stacked bodies 2 are provided on the semiconductor substrate 1. The laminate 2 is composed of laminates having substantially the same structure. The reason why the stacked body 2 having the same structure is formed is to keep the periodicity as much as possible, and thus the structure can be miniaturized in the Y direction while facilitating pattern formation accompanying the lithography process.

  The stacked body 2 has a structure in which a conductive layer 4 is formed on a gate insulating film 3 and a plurality of conductive layers are stacked on the conductive layer 4 with an insulating layer interposed therebetween. Specifically, the stacked body 2 includes an insulating layer 5, a conductive layer 6, an insulating layer 7, a conductive layer 8, an insulating layer 9, a conductive layer 10, an insulating layer 11, a conductive layer 12, an insulating layer on the conductive layer 4. The layer 13, the conductive layer 14, the insulating layer 15, the conductive layer 16, and the insulating layer 17 are formed in this order.

The conductive layer 4 constitutes select gate electrodes SGD and SGS and a local select gate electrode CSG. Conductive layer 6 constitutes dummy gate electrode IDG. The conductive layers (8, 10, 12, 14) constitute the memory cell gate electrode MG (MG _{0 to} MG ₆₃ ). Conductive layer 16 constitute a dummy gate electrode IDG _2.

  A pair of conductive layers (6, 8, 10, 12, 14, 16) and insulating layers (7, 9, 11, 13, 15, 17) are separated from each other in the plane direction of the Y direction in each laminate 2. Is formed. One of the pair of conductive layers (6, 8, 10, 12, 14, 16) is formed flush with one side surface of the conductive layer 4, and the pair of conductive layers (6, 8, 10, 12, 14, 16) is formed flush with the other side surface of the conductive layer 4. The conductive layer 4 is formed to have a width more than twice that of the other conductive layers (6, 8, 10, 12, 14, 16) positioned above, and the thickness of the conductive layer 4 is different from that of other conductive layers. It is formed thicker than the layers (6, 8, 10, 12, 14, 16).

  The local selection gate electrode CSG and the memory cell gate electrode MG are both formed vertically. The conductive layer 4 constituting each select gate electrode SGD, SGS, CSG is formed to have a film thickness larger than that of the other conductive layers (8, 10, 12, 14) constituting the memory cell gate electrode MG. Therefore, the gate lengths of the selection gate transistors STD, STS, and CSGT are set larger than the gate length of the memory cell transistor MT. This is to improve the cut-off characteristics of the select gate transistors STD, STS, and CSGT. The selection gate electrodes SGD and SGS and the local selection gate electrode CSG also function in a horizontal type with the surface layer of the semiconductor substrate 1 as the active region 1e.

  The respective conductive layers (4, 6, 8, 10, 12, 14, 16) are extended in parallel to each other in the depth direction (X direction) in FIG. In the cross section shown in FIG. 5, the conductive layers (6, 8, 10, 12, 14, 16) are planarly formed in the formation region of the local selection gate electrode CSG.

  The pair of conductive layers 4 includes a silicon film (conductive film) 4a and a silicide layer 4b, respectively. Each of the pair of conductive layers 6 includes a silicon layer 6a and a silicide layer 6b, and the silicide layers 6b are disposed to face each other. Each of the pair of conductive layers 8 includes a silicon layer 8a and a silicide layer 8b, and the silicide layer 8b is disposed so as to face the conductive layer 8. Each of the pair of conductive layers 10 includes a silicon layer 10a and a silicide layer 10b, and the silicide layers 10b are disposed to face each other.

  Each of the pair of conductive layers 12 includes a silicon layer 12a and a silicide layer 12b, and the silicide layers 12b are disposed to face each other. Each of the pair of conductive layers 14 includes a silicon layer 14a and a silicide layer 14b, and the silicide layers 14b are disposed to face each other. Each of the pair of conductive layers 16 includes a silicon layer 16a and a silicide layer 16b, and the silicide layers 16b are disposed to face each other.

  The charge trap stacked film 18 is formed so as to cover the stacked body 2. The charge trap laminated film 18 extends in the vertical direction along one side surface of the conductive layer 4 and the side surface of one conductive layer (6, 8, 10, 12, 14, 16). The charge trap laminated film 18 extends in the vertical direction along the other side surface of the conductive layer 4 and the side surfaces of the other pair of conductive layers (6, 8, 10, 12, 14, 16).

  The charge trap laminated film 18 is formed in the order of the insulating film, the charge trapping film, and the insulating film from the right side to the outside of the conductive layer (4, 6, 8, 10, 12, 14, 16). A charge trapping film is sandwiched between insulating films. The charge trap film is formed of, for example, a silicon nitride film, and the insulating film sandwiching the charge trap film is formed of, for example, a silicon oxide film. That is, an ONO film (a laminated film made of an oxide film, a nitride film, and an oxide film) is used for the charge trap laminated film 18. The charge trap laminated film 18 particularly functions as a charge storage layer that traps and stores charges (electrons) in, for example, an intermediate layer (for example, a silicon nitride film).

  A diffusion layer 1c serving as a source / drain is formed on both sides of the local selection gate electrode CSG and on both sides of the selection gate electrodes SGD and SGS. A bit line contact CB is formed immediately above the diffusion layer 1c beside the selection gate electrode SGD, and a bit line BL is formed on the bit line contact CB. A source line contact CS is formed immediately above the diffusion layer 1c beside the selection gate electrode SGS.

  The n − semiconductor layer 22 is continuously formed to face each memory cell gate electrode MG across the left side, the upper side, and the right side of each stacked body 2. The n − semiconductor layer 22 is formed so as to cover the stacked body 2 and the charge trap stacked film 18, but is partially cut off at a position above the select gate electrodes SGD and SGS. Specifically, the n − semiconductor layer 22 is formed so as to be structurally partly in contact with the upper surface of the semiconductor substrate 1 with which the bit line contact CB contacts.

  The n − semiconductor layer 22 is formed continuously across the upper surface and the side surface of the plurality of stacked bodies 2, and is formed along the outer surface of the charge trap stacked film 18 in contact with the plurality of stacked bodies 2. The n − semiconductor layer 22 is formed so as to be partly structurally in contact with the upper surface of the semiconductor substrate 1 with which the source line contact CS is in contact. The sidewall film along which the n − semiconductor layer 22 extends along the sidewall of the stacked body 2 is formed thicker than the n − semiconductor layer 22 positioned above the stacked body 2 and the n − semiconductor layer 22 along the semiconductor substrate 1.

  This is for forming the original functional film after forming the n-semiconductor layer 22a once for improving the reliability as will be described later, and the n-semiconductor layer 22 functions as a second active region. The diffusion layer 1c is formed on the surface layer of the semiconductor substrate 1 between the plurality of stacked bodies 2, and the n− semiconductor layer 22 is configured in contact with the upper surface of the diffusion layer 1c.

  Here, the thickness of the conductive layer constituting each gate electrode and the thickness of the insulating layer interposed between the conductive layers will be described. Regarding the thickness relationship of the conductive layer, the conductive layer 16 is thinner than the conductive layer 4, and the conductive layers (6, 8, 10, 12, 14) are formed thinner than the conductive layer 16. The conductive layers 6, 8, 10, 12, and 14 are formed to have substantially the same thickness. Regarding the relationship of the thickness of the insulating film, the insulating films (5, 7, 15, 17) are formed thicker than the insulating films (9, 11, 13).

Therefore, the distance between the dummy gate electrode IDG and the memory cell gate electrode MG is longer than the distance between the memory cell gate electrodes MG and MG. This is because the local selection gate electrode CSG and the memory cell gate electrode MG are preferably separated as much as possible in order to secure a withstand voltage characteristic, and the memory cell gate electrode MG (for example, MG ₃ , MG ₄ ) located at the upper end and its The n-semiconductor layer 22 positioned above may be separated as much as possible in order to secure a withstand voltage characteristic. The n-semiconductor layer 22 functions as a channel and a second active region. While ensuring good charge transfer characteristics flowing through the n-semiconductor layer 22, the distance between the gate electrodes CSG-MG and the gate electrode MG and above the gate electrode MG It is preferable that the distance between the n − semiconductor layer 22 positioned is separated.

  FIG. 6 schematically shows a cross-sectional structure taken along line BB in FIG. As shown in FIG. 6, wells (n-well 1 a and p-well 1 b from the deep layer side toward the surface layer) are formed in the surface layer of a semiconductor substrate (for example, a p-type silicon substrate) 1. An element isolation trench 1d is formed in the p-well 1b on the surface layer of the semiconductor substrate 1, and an element isolation film 23 is formed in the element isolation trench 1d. The element isolation film 23 is made of, for example, a silicon oxide film. The upper surface of the element isolation film 23 is located below the upper surface of the semiconductor substrate 1.

  The upper surface of the semiconductor substrate 1 is configured such that a portion that becomes an active region 1 e (corresponding to a first active region) protrudes above the upper surface of the element isolation film 23. The active region 1e of the semiconductor substrate 1 is covered with a gate insulating film 3 on the upper surface and side surfaces thereof, and a local selection gate electrode CSG is formed over this.

The electrical configuration includes the following characteristic configuration. That is, as shown in the electrical configuration of FIG. 3 and the cross-sectional structure of FIG. 5, the memory cell gate electrode MG is located above the local selection gate electrode CSG and arranged in an inverted U shape. The memory cell gate electrodes MG (eg, between MG _{0 to} MG ₃ and MG _{4 to} MG ₇ ) are set at the same interval. With this configuration, the characteristics of the memory cell transistors MT adjacent to each other can be kept substantially the same.

A dummy gate electrode IDG is formed between the memory cell gate electrode MG and the local selection gate electrode CSG. The dummy gate electrode IDG is provided between the local selection gate electrode CSG (for example, CSGT ₀ ) and the memory cell gate electrode MG (for example, MG ₀ , MG ₇ ), so that the local selection gate electrode CSG is provided. In addition, the electric field interaction generated when the voltages applied to the memory cell gate electrode MG are different from each other can be alleviated as much as possible to reduce external noise.

In addition, the dummy gate electrode IDG receives a predetermined voltage from the control circuit CC so that the dummy gate electrode IDG can stably charge through the n − semiconductor layer 22 facing the side surfaces of the local selection gate electrode CSG and the memory cell gate electrode MG _0. Can be moved.

  Furthermore, since the distance between the dummy gate electrode IDG and the memory cell gate electrode MG adjacent above the dummy gate electrode IDG is set to be longer than the distance between the plurality of memory cell gate electrodes MG, The charge transfer characteristics flowing in the n − semiconductor layer 22 can be stabilized while maintaining

Since the dummy gate electrode IDG ₂ is formed so as to be interposed between the memory cell gate electrode MG (MG ₃ , MG ₄ ) located at the upper end of the stacked body 2 and the n− semiconductor layer 22 extending over the memory cell gate electrode MG (MG ₃ , MG ₄ ). Stable through the n-semiconductor layer 22 over the stacked body 2 while suppressing the influence of the electric field applied from the memory cell gate electrode MG (MG ₃ , MG ₄ ) to the n-semiconductor layer 22 over the body 2 as much as possible. Thus, the charge can be moved.

The distance between the conductive layer 16 of the dummy gate electrode IDG _{2 and} the conductive layer 14 of the memory cell gate electrode MG located therebelow is set to be longer than the distance between the plurality of memory cell gate electrodes MG-MG. Therefore, the charge transfer characteristic flowing in the n − semiconductor layer 22 can be stabilized while maintaining the breakdown voltage characteristic.

FIG. 7 shows voltages applied to the respective electrical configurations during the write operation / read operation / erase operation of the memory cell. For example, if you write / read data to the memory cell transistors MT ₄ via the word line WL _4, also be described as an example a case where the block erase.

As shown in FIG. 7, in the writing process, the control circuit CC applies the on voltage VSG to the local selection gate electrodes CSG _{1 to} CSG ₇ and applies the on voltage VSG to the selection gate electrodes SGD and SGS. ₀ V as an off voltage is applied to the local selection gate electrode CSG0. Then, a channel is formed between both sides of the diffusion layer 1c-1c of the local selection gate electrode CSG ₁ ~CSG _7.

Further, the control circuit CC applies the write voltage Vpgm as a high voltage to the write select word line WL ₄ while applying a pass voltage Vpass to the non-write the selected word line _{WL 0 ~WL 3, WL 5 ~WL} 7 .

In this case, since the local selection gate electrode CSG ₀ is turned off, the semiconductor region that becomes a substantially active region at the time of data writing is the n − semiconductor layer 22 covered with the stacked body 2 including the local selection gate electrode CSG _0. (Second active region), the selection gate electrode STD, the local selection gate electrodes CSG _{1 to} CSG ₇ , and the surface layer region (first active region 1 e) of the semiconductor substrate 1 on both sides. That is, charges are injected into the charge storage layer 20 in which the conductive layer 14 (word line WL ₄ ) is sandwiched between the n− semiconductor layer 21 and data can be written.

In the read process, the control circuit CC applies the on-voltage VSG to the local selection gate electrodes CSG _{1 to} CSG ₇ and the on-voltage VSG to the selection gate electrodes SGD and SGS, and the local selection gate electrode CSG _0. 0 V which is an off-voltage is applied to. Then, a channel is formed between both sides of the diffusion layer 1c-1c of the local selection gate electrode CSG ₁ ~CSG _7.

The control circuit CC applies the read target voltage Vwl (<Vread) to the read target word line WL ₄ while applying the read voltage Vread to the non-read selected word lines WL _{0 to} WL ₃ , WL _{5 to} WL ₇ . In this case, since the local selection gate electrode CSG ₀ is off, the semiconductor region that becomes a substantially active region at the time of data reading is covered with the stacked body 2 including the local selection gate electrode CSG ₀ in the same manner as described above. The semiconductor layer 22 (second active region), the selection gate electrode STD, the local selection gate electrodes CSG _{1 to} CSG ₇ , and the surface layer region (first active region 1 e) of the semiconductor substrate 1 on both sides.

Since the control circuit CC applies the read target voltage Vwl to the read target word line WL ₄ and applies the read voltage Vread to the other word lines WL _{0 to} WL ₃ and WL _{5 to} WL ₇ , the read target word line WL _The degree of voltage drop in the active region changes due to the influence of the charge accumulated in the charge accumulation layer 20 near ₄ . The control circuit CC can read the data stored in the memory cell transistor MT ₄ by detecting the degree of voltage drop near the read target word line WL ₄ .

During the erasing process, the control circuit CC applies the voltage shown in FIG. 7 (Flg is floating, Vera is the erasing voltage) to the p-well 1b. Since the control circuit CC sets the applied potentials of the local selection gate electrodes CSG _{1 to} CSG _{7 in} a floating state, the charge accumulated in the charge trap stacked film 18 is released through the n− semiconductor layer 22 and the p well 1b. Become.

  The manufacturing method of the said structure is demonstrated referring FIGS. 8-20. In the following description of the manufacturing method, various peripheral transistors TrP such as a high-voltage transistor and a low-voltage transistor in the row driving circuit RD are also formed at the same time. In the following description, parts having the same functions as the reference numerals assigned to the respective structural films in the above description will be described with the same or similar reference numerals.

  In the following description, the drawing with (a) shows the cross section of the selection gate electrode SGD, the local cell group selection gate electrode CSG and the structure above it, and the drawing with (b) shows the local selection gate electrode. The cross-sectional structure along the CSG and the word line WL is shown, and the drawing with (c) schematically shows the structural cross-section of the peripheral transistor TrP.

  First, as shown in FIG. 8, after an n well 1a and a p well 1b are formed in order on the surface layer of the semiconductor substrate 1, an element isolation groove 1d is formed in the semiconductor substrate 1, and an element isolation film is formed in the element isolation groove 1d. 23 is embedded and formed. In this case, the upper surface of the element isolation film 23 may be formed flush with the upper surface of the semiconductor substrate 1, or even if the upper surface is formed so as to protrude upward from the upper surface of the semiconductor substrate 1, it is positioned below the upper surface. You may form so that it may do.

  Next, as shown in FIGS. 9A to 9C, a gate insulating film 3a is formed of a silicon oxide film on the upper surface of the semiconductor substrate 1, and then, for example, amorphous silicon is deposited. Then, a silicon film (conductive film) 4a is deposited.

  This silicon film 4a (lowermost conductive film) is, for example, thicker than silicon films (6a, 8a, 10a, 12a, 14a: conductive films) to be formed later, and serves as a base layer for the local selection transistor CSGT and selection gate electrodes SGD, SGS. It is formed. Next, an insulating film (5a, 7a, 9a, 11a, 13a, 15a, 17a) and a silicon film (6a, 8a, 10a, 12a) serving as a base layer of the memory cell gate electrode MG are formed on the upper surface of the silicon film 4a. 14a) are alternately stacked by, for example, the CVD method.

  Next, as shown in FIGS. 10A to 10C, silicon films (6a, 8a, 10a, 12a, 14a), insulating films (5a, 7a, 9a, 11a, 13a, 15a, 17a) The stacked body 2a is divided in the direction crossing the word line WL direction along the word line WL direction so as to expose the side walls of the plurality of stacked bodies 2a.

  Next, as shown in FIGS. 11A to 11C, a protective film 24 is formed along the side walls of the plurality of stacked bodies 2a. The protective film 24 is preferably formed of an oxide film or a silicon nitride film.

  Next, as shown in FIGS. 12A to 12C, n-type impurities are ion-implanted on both sides of the plurality of stacked bodies 2a. In this impurity introduction region, the diffusion layer 1c is formed by a subsequent heat treatment.

  Next, as shown in FIG. 13A to FIG. 13C, lithography and anisotropic etching are performed to form a hole 25 in a groove shape for each of the protective film 24 and the plurality of stacked bodies 2a. Form. The hole 25 is formed until reaching the upper surface of the silicon layer 4a.

  Next, as shown in FIGS. 14A to 14C, a metal (for example, platinum, palladium, cobalt, nickel, etc.) is formed in the hole 25 and heat-treated, so that each silicon film (4a, The silicide layers (4b, 6b, 8b, 10b, 12b, 14b, 16b) of the metal are formed on the exposed portions of the side surfaces of 6a, 8a, 10a, 12a, 14a, 16a), and excess metal is removed.

  Next, as shown in FIGS. 15A to 15C, the interlayer insulating film 20 is embedded in the hole 25 and laminated on the upper surface of the protective film 24 and between the plurality of stacked bodies 2 a. A part of the extra interlayer insulating film 20 is removed. At this time, the interlayer insulating film 20 remains in a spacer shape on both sides of each stacked body 2a. Next, the interlayer insulating film 20 and the protective film 24 are peeled off. A wet etching process is applied to the peeling process. In this case, a part of the upper part of the interlayer insulating film 20 is removed.

  Next, as shown in FIGS. 16A to 16C, the charge trap laminated film 18 is formed so as to cover the laminated body 2a along the side surface and the upper surface of the laminated body 2a. In this case, for example, a CVD method, an ALD method, or the like is applied to sequentially form a silicon oxide film, a silicon nitride film, and a silicon oxide film, thereby forming the charge trap stack film 18.

  Next, as shown in FIGS. 17A to 17C, an n − semiconductor layer 22a is once deposited on the charge trap stacked film 18 for improving reliability, and the n − semiconductor layer 22a is formed, for example, An upper surface of the diffusion layer 1c of the semiconductor substrate 1 located on both sides of the stacked body 2 is exposed by performing an anisotropic etching process by the RIE method.

  Next, as shown in FIGS. 18A to 18C, the n − semiconductor layer 22 is stacked as an original functional film on the n − semiconductor layer 22a by, for example, the CVD method. Then, the n − semiconductor layer 22 contacts the upper surface of the diffusion layer 1 c of the semiconductor substrate 1 exposed.

  Next, as shown in FIGS. 19A to 19C, the n − semiconductor layer 22 is selectively etched using a lithography method and an RIE method. This etching region includes a division region between the cell units UC, a formation region on the bit line contact CB side from the upper central portion of the selection gate electrode SGD of the cell unit UC, and a source line from the upper central portion of the selection gate electrode SGS. A formation region on the contact CS side. In this region, the n − semiconductor layer 22 is removed.

FIG. 19D schematically shows a cross section of the divided region of each stacked body 2 along the word line WL direction.
When the above-described steps are applied, the element isolation film 23 is embedded in the semiconductor substrate 1, and after several steps, the n-semiconductor layer 22 is deposited and the n-semiconductor layer 22 is patterned. As shown in FIG. 19D, misalignment may occur between the diffusion layer 1 c and the n − semiconductor layer 22. However, when the upper surface of the element isolation film 23 is lower than the upper surface of the diffusion layer 1c, the n-semiconductor layer 22 and the upper side surface of the diffusion layer 1c come into contact with each other, so that the contact area can be enlarged and contact is made. Resistance can be reduced.

  Next, after depositing an interlayer insulating film (not shown) on the structure, as shown in FIGS. 20A to 20C, a through hole is formed in the formation region of the bit line contact CB and the diffusion layer 1c. A through hole is formed to communicate with the upper surface of the peripheral gate electrode (conductive film 4) in the peripheral circuit region. Thereafter, the via plug CP of the peripheral circuit is formed in the through hole so as to contact the bit line contact CB, the source line contact CS, and the upper part of the gate electrode (conductive film 4) of the transistor TrP in the peripheral circuit PC region. In this manner, the cell unit UC and the peripheral transistor TrP in the peripheral circuit region can be formed. Since the subsequent steps are not related to the characteristic part of the present embodiment, the description thereof is omitted.

According to the present embodiment, since a plurality of memory cell gate electrodes MG can be stacked in the formation region of the local selection gate electrode CSG, the degree of integration in the planar direction can be improved. Further, the local selection gate electrode CSG is controlled to be turned on / off from the peripheral circuit PC, so that a channel is formed through the first active region on the surface layer of the semiconductor substrate 1 and the n − semiconductor layer 22 covering the stacked body 2. The local cell group memory cell transistors (MT _{0 to} MT ₇ , MT _{8 to} MT ₁₅ , MT _{16 to} MT ₂₃ , MT _{24 to} MT ₃₁ , MT _{32 to} MT ₃₉ are divided into the case where a channel is formed through two active regions. , MT _{40 to} MT ₄₇ , MT _{48 to} MT ₅₅ , MT _{56 to} MT ₆₃ ) can be selectively controlled.

Therefore, when the local selection gate electrode CSG partially selects the memory cell transistor MT (for example, the memory cell transistors MT _{0 to} MT ₇ ), other memory cell transistors MT (for example, the memory cell transistors MT _{8 to} MT ₆₃ ) Can be brought into a non-selected state, and it is not necessary to apply a high voltage to the gate electrode (word line WL) of the memory cell transistor MT in the non-selected state. Therefore, it is not necessary to apply an unnecessary write voltage, read voltage, etc. to the non-selected memory cell gate electrode MG every time, and for example, the number of rewritable times during writing can be substantially increased. Various problems of program disturb and read disturb can be dealt with, and the stress resistance of the memory cell array Ar can be improved.

  A plurality of local selection gate electrodes CSG are provided between a pair of selection gate electrodes SGD-SGS. Above each local selection gate electrode CSG, gate electrodes MG of a plurality of memory cell transistors MT having the same structure are spaced apart. Since it is formed in an inverted U shape, structural periodicity can be maintained in the Y direction. Thereby, the pattern periodicity by lithography can be ensured as much as possible during manufacturing, and the degree of integration can be improved.

Since the gate electrodes of the dummy transistors DM (DM _{0 to} DM ₇ , DM _{8 to} DM ₁₅ ) are also configured above the select gate electrodes SGD and SGS with the same structure as the structures above the local select gate electrodes CSG. The periodicity of the structure can be maintained in the Y direction, the pattern periodicity by lithography can be ensured as much as possible, and the degree of integration can be improved.

  In addition, the peripheral transistor TrP has a gate electrode that has substantially the same potential by electrically connecting the conductive layers (4, 6, 8, 10, 12, 14, 16) of the stacked body 2 with the contact plug CP. It is prepared for. For this reason, when the structure of the memory cell region M is formed, the peripheral transistor TrP in the peripheral circuit region can be formed by applying substantially the same process, leading to a reduction in the number of manufacturing processes.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.
Although the embodiment in which the distance between the gate electrodes MG-IDG and IDG ₂ -MG is set longer than the distance between the gate electrodes MG-MG has been shown, the insulating layers (5, 7, 9, 11, 13, 15 and 17) may be appropriately set to the same film thickness, and the distance between the gate electrodes may be set to the same distance. Thereby, the charge transfer characteristics of the semiconductor layer 22 opposed between the gate electrodes MG-MG, MG-IDG, and IDG ₂ -MG can be made the same.

The diffusion layer 1c between the local selection gate electrodes CSG-CSG may not be formed. The diffusion layer 1c is preferably formed as needed because the carrier mobility increases. You may apply to the form which formed the diffused layer in the vertical direction side of each memory cell gate electrode MG. The dummy transistor DM may be provided as necessary. The dummy gate electrodes IDG and IDG ₂ are preferably provided as necessary.

In the drawings, 1 is a semiconductor substrate, 2 is a laminate, 3 is a gate insulating film, 4, 6, 8, 10, 12, 14, and 16 are conductive layers, 5, 7, 9, 11, 13, 15, and 17 are Insulating layer, 18 is a charge trap laminated film (charge storage layer), 20 is an interlayer insulating film (buried insulating film), 22 and 22a are n-semiconductor layers (second active regions), 24 is a protective film, MG is a memory Cell gate electrode, MT is a memory cell transistor (local memory cell transistor), SGD and SGS are selection gate electrodes, DM is a dummy transistor, CSG is a local cell group selection gate electrode, IDG and IDG ₂ are dummy gate electrodes, and CSGT is local A cell group selection gate transistor is shown.

Claims (5)

A semiconductor substrate having a first active region formed on a surface layer;
A local cell group selection gate electrode formed on the first active region of the semiconductor substrate via a gate insulating film, the local cell group selection gate electrode having the first active region located on both sides;
A stacked body in which a plurality of memory cell gate electrodes are stacked via an insulating film directly above the local cell group selection gate electrode;
A second active region in contact with the first active region located on both sides of the local cell group selection gate electrode, wherein the plurality of at least one surface on one side, upper side, or other side of the stacked body; A second active region structurally continuously formed opposite to the memory cell gate electrode of
A non-volatile semiconductor memory device comprising: the opposed second active region and a charge storage layer located between a plurality of memory cell gate electrodes. A pair of select gate electrodes,
A plurality of the local cell group selection gate electrodes are provided between the pair of selection gate electrodes,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cell gate electrodes are arranged in an inverted U shape with the same structure above the plurality of local cell group selection gate electrodes. The pair of selection gate electrodes is formed by the same structure as the local cell group selection gate electrode,
On the pair of select gate electrodes, the gate electrodes of the dummy transistors are arranged corresponding to the plurality of memory cell gate electrodes in the same structure as the structure above the plurality of local cell group select gate electrodes. The nonvolatile semiconductor memory device according to claim 1 or 2. A pair of select gate transistors formed between a bit line and a source line, a plurality of local cell group select gate transistors electrically connected between the pair of select gate transistors, and a parallel connection to the local cell group select gate transistors A plurality of local memory cell transistors, and the plurality of local memory cell transistors corresponding to the plurality of local cell group selection gate transistors, respectively, and configured to be selectable by a pair of selection gate transistors With units,
A non-volatile semiconductor memory device comprising: a control circuit which enables electrical selection / non-selection of the local memory cell transistor by controlling on / off of the local cell group selection gate transistor. Forming a stacked body by repeatedly laminating an insulating layer and a conductive film for a memory cell gate electrode through a conductive film for a gate insulating film and a local cell group selection gate electrode on a semiconductor substrate;
A step of forming the lowermost conductive film in the plurality of stacked bodies as a local cell group selection gate electrode by dividing the stacked body into a plurality of parts and exposing sidewalls of the plurality of stacked bodies;
Forming a diffusion layer constituting a first active region in a surface layer of the semiconductor substrate on both sides of the plurality of stacked bodies;
Forming a charge storage layer along the side walls of the plurality of stacks;
Forming a semiconductor layer serving as a second active region on the outer wall surface of the charge storage layer and on the top surfaces of the plurality of stacked bodies, and facing the memory cell gate electrode with the charge storage layer interposed therebetween And forming a semiconductor layer in contact with the upper surface of the diffusion layer;
A method for manufacturing a nonvolatile semiconductor memory device, comprising:

Images