JP2011135731A - Driver of switching element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem of flow of overcurrents, when operating a charging switching element 30 that turns on the power switching element Sw by opening/closing between a power source 20 and the gate of a power switching element Sw. <P>SOLUTION: A charging switching element 30 is turned on, while a terminal (a) of a selecting circuit 24 is selected, when the power switching element Sw is turned on. Then, it is determined whether there is an overcurrent flowing in the power switching element Sw by a comparator 48 based on the amount of voltage drop of a resistor 44 by an output current of a sense terminal St. When there is no overcurrent flowing, a b-terminal of the selecting circuit 24 is selected to switch a gate application voltage from a voltage V1 of the power source 20 to a voltage of V1+V2, in serial connection of power sources 20 and 22. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage application means for applying a voltage for turning on the switching element to a conduction control terminal of a voltage control type switching element, and an opening / closing operation for opening and closing between the voltage application means and the conduction control terminal. And a switching element driving device that drives the switching element by operating the opening / closing means.

  As this type of driving device, for example, as shown in Patent Document 1 below, a driving device having a pair of power supplies for generating a voltage to be applied to the gate to turn on the IGBT constituting the inverter has been proposed. As a result, when the IGBT is turned on, a voltage is first applied to the gate using a low voltage of a pair of power supplies to turn on the IGBT. Next, the voltage applied to the gate is increased using a high-voltage one of the pair of power supplies. Thereby, when the short circuit of an upper and lower arm arises, it can avoid suitably that an overcurrent flows with the ON operation of IGBT. Further, when there is no possibility of overcurrent flowing, the conduction loss can be quickly reduced by increasing the gate voltage.

JP 2009-71956 A

  However, in the case of the above device, there is a problem that when a voltage is applied to the gate using the higher voltage of the pair of power supplies, a current flows from the higher voltage to the lower voltage. On the other hand, in the above device, the current flow is avoided by providing a diode. However, in this case, there is a problem that the gate voltage is not stabilized due to fluctuations in the voltage drop amount of the diode.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to apply voltage application means for applying a voltage for turning on the switching element to the conduction control terminal of the voltage-controlled switching element. And an opening / closing means for opening and closing between the voltage application means and the conduction control terminal, and when the switching element is driven by operating the opening / closing means, the voltage applied to the conduction control terminal can be varied more appropriately. It is an object of the present invention to provide a driving device for a switching element that can be set.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  According to the first aspect of the present invention, voltage application means for applying a voltage for turning on the switching element to the conduction control terminal of the voltage-controlled switching element, and between the voltage application means and the conduction control terminal In the switching element driving device that drives the switching element by operating the opening and closing means, the voltage applying means includes a plurality of voltage generating means, an output terminal of the switching element, and And variable means for variably setting the number of the voltage generating means connected in series between the conduction control terminals.

  In the said invention, the voltage applied to a conduction control terminal can be changed by changing the number of the voltage generation means connected in series. For this reason, the voltage applied to the conduction control terminal can be variably set more appropriately.

  According to a second aspect of the present invention, in the first aspect of the invention, by operating the variable means, the voltage connected in series during the switching process period of the switching state from the OFF state to the ON state of the switching element. It is further characterized by further comprising an increase operation means for increasing the number of generation means.

  In the above invention, the potential difference of the conduction control terminal with respect to the potential of the output terminal can be changed by increasing the number of voltage generating means.

  According to a third aspect of the present invention, in the first or second aspect of the invention, the voltage applied to the conduction control terminal when the switching element is switched from the off state to the on state by operating the variable means. The variable means is configured to switch to the second voltage on the on-state side rather than the first voltage after setting the first voltage on the on-state side from the threshold voltage at which the switching element switches from the off-state to the on-state. It further comprises voltage changing means for operation.

  In the above invention, when switching the switching state, the voltage applied to the conduction control terminal can be made different between before and after the transition to the mirror period.

  According to a fourth aspect of the invention, in the third aspect of the invention, the voltage changing means switches from the first voltage to the second voltage after a mirror period of the switching element.

  According to a fifth aspect of the present invention, in the third aspect of the present invention, the voltage changing unit is configured to provide a delay signal indicating a timing delayed with respect to a timing at which the operation signal of the switching element is instructed to switch to the ON state. A delay signal generating means for generating is provided, and the switching is performed based on the delay signal.

  In the above invention, the switching process from the first voltage to the second voltage can be performed at an appropriate timing by referring to the delay signal to perform the switching process.

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the delay signal generation means generates the delay signal with the operation signal as an input.

  In the said invention, a delay signal can be produced | generated appropriately.

  The invention according to claim 7 is the invention according to claim 6, further comprising overcurrent determining means for determining whether or not the current flowing through the switching element becomes excessively large, and the delay time by the delay signal is It is set to be longer than the time required for the overcurrent determination by the overcurrent determination means.

  When the output terminal of the switching element is connected to a low-potential member with an abnormally low impedance, an overcurrent flows at the moment when the switching element is turned on. However, a certain amount of processing time (time required for determination of overcurrent by the overcurrent determination unit) is required until the overcurrent determination unit determines that this overcurrent has flowed. If the first voltage is switched to the second voltage before this determination, the current flowing through the switching element further increases, which may reduce the reliability of the switching element. In the above invention, in view of this point, the delay time of the delay signal is set as the above setting.

  According to an eighth aspect of the present invention, in the seventh aspect of the invention, when the overcurrent determination unit determines that the current flowing through the switching element is excessively large, the prohibition unit prohibits the switching by the switching unit. It is further provided with the feature.

  In the above invention, by prohibiting switching when an overcurrent flows, it is possible to avoid a further increase in the current flowing through the switching element.

  According to a ninth aspect of the present invention, in the invention according to any one of the fifth to eighth aspects, the delay time until the delayed timing is determined from the switching command timing to turn on the switching element. Of the mirror period, the time is assumed to be required before the end of the mirror period.

  According to the above invention, the loss of the switching element can be reduced.

  According to a tenth aspect of the present invention, in the invention according to any one of the fifth to eighth aspects, the delay time until the delayed timing is determined from the switching command timing to turn on the switching element. It is set to a time that is assumed to be required until the end timing of the mirror period.

  When the rate of change of the current flowing through the switching element is large, a large surge is generated by an inductor (such as a parasitic inductor) that exists in the current flow path. In order to reduce this surge, it is desirable to suppress the voltage change rate of the conduction control terminal until the end of the mirror period. However, when the change rate of the voltage at the conduction control terminal is small, the loss in switching the switching state increases. In the above invention, in view of this point, the loss can be reduced as much as possible while suppressing the surge by performing the switching process with the end of the mirror period of the switching element.

  According to an eleventh aspect of the present invention, in the invention according to the third or fourth aspect, the voltage changing means includes end detecting means for detecting the end of the mirror period of the switching element, and the end of the mirror period is detected. Thus, the first voltage is switched to the second voltage.

  When the rate of change of the current flowing through the switching element is large, a large surge is generated by an inductor (such as a parasitic inductor) that exists in the current flow path. In order to reduce this surge, it is desirable to suppress the voltage change rate of the conduction control terminal until the end of the mirror period. However, when the change rate of the voltage at the conduction control terminal is small, the loss in switching the switching state increases. In the above invention, in view of this point, it is possible to reduce the loss as much as possible while suppressing the surge by performing the switching process by detecting the end of the mirror period of the switching element.

  The invention according to a twelfth aspect is the invention according to any one of the fifth to tenth aspects, wherein the voltage changing means includes end detection means for detecting the end of a mirror period of the switching element, and the delay signal. The switching is performed when the delay time specified by the elapse of time and the end of the mirror period is detected.

  When the rate of change of the current flowing through the switching element is large, a large surge is generated by an inductor (such as a parasitic inductor) that exists in the current flow path. In order to reduce this surge, it is desirable to suppress the voltage change rate of the conduction control terminal until the end of the mirror period. However, when the change rate of the voltage at the conduction control terminal is small, the loss in switching the switching state increases. In the above invention, in view of this point, the loss can be reduced as much as possible while suppressing the surge by performing the switching process based on the detection of the end of the mirror period of the switching element.

  According to a thirteenth aspect of the invention, in the invention of the eleventh or twelfth aspect, the end detection means includes a comparison means for comparing a voltage of the conduction control terminal with an end determination voltage, and the comparison result of the comparison means is obtained. A signal indicating a result of detection of the end of the mirror period is used.

  The invention according to claim 14 is the invention according to claim 13, further comprising temperature detection means for detecting the temperature of the switching element, wherein the end detection means is the end according to the temperature detected by the temperature detection means. The determination voltage is variably set.

  The voltage of the conduction control terminal in the mirror period has temperature dependence. In the above invention, in view of this point, it is possible to set the end determination voltage according to a value assumed as the voltage of the mirror period at the current temperature.

  According to a fifteenth aspect of the invention, in the invention of the eleventh or twelfth aspect, the end detection means includes means for detecting a change in voltage of the conduction control terminal, and the mirror is detected based on detection of the change. It is characterized by detecting the end of the period.

  In the mirror period, the change rate of the voltage of the conduction control terminal is greatly reduced. For this reason, at the end of the mirror period, the change rate of the voltage of the conduction control terminal greatly increases. In the above invention, paying attention to this point, the end of the mirror period is detected.

  The invention according to claim 16 is the invention according to any one of claims 1 to 15, wherein the voltage applying means sets the switching element to the off state rather than a threshold voltage at which the switching element switches from the off state to the on state. Pre-voltage generation means for generating a pre-voltage that is a voltage-side voltage; and post-voltage generation means for generating a post-voltage that is a voltage-side voltage that is in the ON state with respect to the threshold voltage; A plurality of opening / closing means for opening / closing between the conduction control terminal and the voltage applying means, and when the switching state of the switching element is switched from the OFF state to the ON state, After realizing the connection state between the voltage generation means and the conduction control terminal, the state is switched to the connection state between the post voltage generation means and the conduction control terminal. And a resistance value when connecting the pre-voltage generation means and the conduction control terminal is smaller than a resistance value when connecting the post-voltage generation means and the conduction control terminal. .

  In the above invention, the rate of increase of the voltage before the voltage of the conduction control terminal reaches the threshold voltage can be increased.

  A seventeenth aspect of the present invention is the power conversion device according to any one of the first to sixteenth aspects, wherein the switching element includes a series connection body of a high potential side switching element and a low potential side switching element. It is a switching element constituting the series connection body in a circuit.

  In the above invention, when both the high-potential side switching element and the low-potential side switching element are turned on, an excessive current may flow through them. However, even in this case, the amount of current can be limited as long as the voltage applied to the conduction control terminal is lower than the maximum voltage for turning on. For this reason, the above invention has particularly great utility value of the variable means.

1 is a system configuration diagram according to a first embodiment. FIG. The circuit diagram which shows the circuit structure of the drive unit concerning the embodiment. The circuit diagram which shows one Example of the switching circuit concerning the embodiment. The circuit diagram which shows the circuit structural example of the delay circuit concerning the embodiment. The time chart which shows the ON operation aspect of the power switching element concerning the embodiment. The time chart which shows the ON operation aspect of the power switching element concerning 2nd Embodiment. The time chart which shows the ON operation aspect of the power switching element concerning 3rd Embodiment. The circuit diagram which shows the circuit structure of the drive unit concerning 4th Embodiment. The time chart which shows the ON operation aspect of the power switching element concerning the embodiment. The circuit diagram which shows the circuit structure of the drive unit concerning 5th Embodiment. The circuit diagram which shows the circuit structure of the drive unit concerning 6th Embodiment. The time chart which shows the ON operation aspect of the power switching element concerning the embodiment. The circuit diagram which shows the circuit structure of the drive unit concerning 7th Embodiment. The time chart which shows the ON operation aspect of the power switching element concerning the embodiment. The time chart which shows the ON operation aspect of the power switching element concerning 8th Embodiment. The circuit diagram which shows the circuit structure of the drive unit concerning 9th Embodiment. The time chart which shows the ON operation aspect of the power switching element concerning the embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a drive device for a power switching element according to the present invention is applied to a hybrid vehicle will be described with reference to the drawings.

  FIG. 1 shows the system configuration of this embodiment. As shown in the figure, a motor generator 10 as an in-vehicle main machine is connected to a high voltage battery 12 via an inverter IV and a converter CV. The inverter IV is configured by connecting three series-connected bodies of a power switching element Swp on the high potential side and a power switching element Swn on the low potential side in parallel. A connection point between each power switching element Swp and power switching element Swn is connected to each phase of motor generator 10. Further, converter CV includes capacitor C, a series connection body of power switching element Swp on the high potential side and power switching element Swn on the low potential side, a connection point of power switching element Swp and power switching element Swn, and high voltage battery 12. And a reactor L that connects the two.

  Between the input / output terminals (between collector and emitter) of the high potential side power switching element Swp and the low potential side power switching element Swn, there is a high potential side freewheel diode FDp and a low potential side freewheel diode. The cathode and anode of FDn are connected. In particular, in the present embodiment, the high potential side power switching element Swp and the high potential side freewheel diode FDp are formed adjacent to each other on the same semiconductor substrate, and the low potential side power switching element Swn and the low potential side power switching element Swd The free wheel diodes FDn on the side are formed adjacent to the same semiconductor substrate. Examples of such semiconductor devices include those described in “RC-IGBT for motor control Hideki Takahashi, et al., 7 (315) Mitsubishi Electric Technical Report, Vol 81, No. 5, 2007”.

  The drive unit DU is connected to the conduction control terminals (gates) of the power switching elements Swp and Swn constituting the inverter IV. Thereby, the power switching elements Swp and Swn are driven by the control device 16 using the low voltage battery 14 as a power source via the drive unit DU. The control device 16 controls operation signals gup, gvp, gwp for operating the power switching elements Swp for the U phase, V phase, and W phase of the inverter IV based on detection values of various sensors (not shown), and power switching. Operation signals gn, gvn, and gwn for operating the element Swn are generated and output. Further, operation signals gcp and gcn for operating the power switching elements Swp and Swn of the converter CV are generated and output. Thereby, the power switching elements Swp and Swn are operated by the control device 16 via the drive unit DU.

  Note that the high voltage system including the inverter IV and the converter CV and the low voltage system including the control device 16 are insulated by an insulating means such as a photocoupler (not shown), and the operation signal is high via the insulating means. Output to the voltage system.

  The power switching elements Swp and Swn are both constituted by insulated gate bipolar transistors (IGBT). The power switching elements Swp and Swn include a sense terminal St that outputs a minute current having a correlation with a current flowing between the input terminal and the output terminal.

  FIG. 2 shows a circuit configuration of the drive unit DU according to the present embodiment. In the following description, the power switching elements Swp and Swn are collectively referred to as the power switching element Sw, and the free wheel diodes FDp and FDn are collectively referred to as the free wheel diode FD. The operation signals gup, gvp, gwp, gcp, gun, gvn, gwn, and gcn are collectively referred to as an operation signal g.

  As shown in the figure, the drive unit DU includes a power source 20 that uses a predetermined voltage V1 as an output voltage, and a power source 22 that uses a predetermined voltage V2 as an output voltage. In the figure, the power sources 20 and 22 are indicated by symbols of batteries, but actually, the power source 20 may be a capacitor or the like constituting a floating power source. These power supplies 20 and 22 can be connected in series by a switching circuit 24. That is, in the switching circuit 24, the power sources 20 and 22 can be connected in series by selecting the b terminal side, while the power source 20 can be disconnected from the power source 22 by selecting the a terminal. Here, since both the a terminal of the switching circuit 24 and the negative electrode of the power source 22 are connected to the output terminal (emitter) of the power switching element Sw, when the a terminal is selected by the switching circuit 24 The positive potential of the power supply 20 is higher than the emitter potential by “V1”, while it is higher by “V1 + V2” when the b terminal is selected.

  FIG. 3 shows a circuit example of the switching circuit 24. In FIG. 3, the switching circuit 24 includes a series connection body of an N-channel MOS field effect transistor (switching element 24 a) and a P-channel MOS field effect transistor (switching element 24 b). The negative terminal of the power source 22 is connected to the output terminal of the switching element 24a, the positive terminal of the power source 22 is connected to the input terminal of the switching element 24b, and the negative terminal of the power source 20 is connected to the connection point of the switching elements 24a and 24b. .

  The high voltage of the power source 20 is applied to the conduction control terminal (gate) of the power switching element Sw through the charging switching element 30 and the charging resistor 32 as a linear element. Further, the gate charge is discharged through the discharge resistor 34 and the discharge switching element 36 as linear elements. Here, the gate is connected to the emitter of the power switching element Sw via the discharging resistor 34 and the discharging switching element 36.

  On the other hand, the control unit 40 receives the operation signal g and operates the charging switching element 30 and the discharging switching element 36 based on the operation signal g to drive the power switching element Sw. Specifically, in the present embodiment, when the operation signal g becomes an on operation command, the charging switching element 30 is turned on and the discharging switching element 36 is turned off. Further, when the operation signal becomes an off operation command, the charging switching element 30 is turned off and the discharging switching element 36 is turned on.

  Here, in the process of switching the power switching element Sw from the off state to the on state, first, the switching circuit 24 selects the a terminal and switches to the b terminal in the middle. As a result, the gate application voltage can be increased during the switching of the switching state from the off state to the on state. A predetermined delay time that defines this switching is set by the delay circuit 50. The delay circuit 50 is a circuit that receives the operation signal g and generates a delay signal DL that indicates a timing delayed by a predetermined delay time with respect to the timing at which the operation signal g is instructed to switch to the on operation. For example, the circuit shown in FIG. 4 may be used.

  FIG. 4A is a delay circuit composed of a resistor 50b and a capacitor 50a. When the operation signal g as an input signal becomes logic “H”, the voltage of the capacitor 50a gradually increases, and logic “H”. When a predetermined delay time elapses to a voltage value corresponding to. FIG. 4B shows a structure in which a diode 50c having a forward direction from the output side to the input side in the configuration of FIG. 4A is connected in parallel to the resistor 50b. According to this configuration, although there is a delay from when the operation signal g changes to logic “H” until the output signal of the delay circuit 50 changes to logic “H”, the operation signal g changes to logic “L”. There is almost no delay before the output signal of the delay circuit 50 changes to logic “L” after the change. FIG. 4 (c) shows a case where a voltage of a power source 50f is applied to both ends of a series connection body of a resistor 50b and a capacitor 50a, a switching element 50d is provided so as to bypass the capacitor 50a, and an inverter is provided at the gate thereof. A logic inversion signal of the operation signal g by 50e is applied. Here, the inverter e is for turning off the switching element 50d when the operation signal g becomes logic “H”. Even with this configuration, the operation signal g changes to logic “L” although there is a delay after the operation signal g changes to logic “H” until the output signal of the delay circuit 50 changes to logic “H”. After that, there is almost no delay until the output signal of the delay circuit 50 changes to logic “L”.

  The delay time of the delay circuit 50 is set longer than the time required until the period (mirror period) in which the rising speed of the gate voltage is once greatly decreased in the transition period from the OFF state to the ON state of the switching state. . However, in the present embodiment, even when the delay time has elapsed, when the overcurrent flows through the power switching element Sw, the switching circuit 24 is not switched. The configuration for realizing this is as follows.

  A series connection body of resistors 42 and 44 is connected between the sense terminal St and the emitter of the power switching element Sw, and a non-inverting input terminal of the comparator 48 is connected to the connection point. The reference voltage Vref of the reference power supply 46 is applied to the inverting input terminal of the comparator 48. Here, the reference voltage Vref is set according to a lower limit value (threshold current) at which it is determined that the current flowing through the power switching element Sw is excessively large. Thereby, the comparator 48 can determine whether or not the current flowing through the power switching element Sw is equal to or higher than the threshold current by using the voltage drop of the resistors 42 and 44 due to the output current of the sense terminal St.

  The output signal of the comparator 48 is logically inverted by the inverter 54 and then taken into the AND circuit 52. The AND circuit 52 generates a logical product signal of the delay signal DL output from the delay circuit 50 and the signal output from the inverter 54, and outputs the logical product signal to the control unit 40. The control unit 40 switches the switching circuit 24 from the selection state of the a terminal to the selection state of the b terminal when the output signal of the AND circuit 52 becomes logic “H”. As a result, in the control unit 40, the logical product of the fact that the predetermined delay time has elapsed from the timing when the operation signal g commands the on operation and that the current exceeding the threshold current does not flow through the power switching element Sw is true. In some cases, the switching circuit 24 is switched from the selected state of the a terminal to the selected state of the b terminal.

  FIG. 5 shows a driving process of the power switching element Sw according to the present embodiment, comparing a normal case (case 1) and an overcurrent detected case (case 2). Specifically, FIG. 5A shows the transition of the gate voltage Vge, FIG. 5B shows the transition of the operating state of the charging switching element 30, and FIG. 5C shows the operation of the switching circuit 24. FIG. 5D shows the transition of the output signal of the comparator 48, and FIG. 5E shows the transition of the delay signal DL.

  As illustrated, when the operation signal g is switched to the on operation command, the charging switching element 30 is turned on in a state where the terminal a of the switching circuit 24 is selected. As a result, the gate voltage Vge converges to the voltage V1 of the power supply 20. This voltage V1 is set to be equal to or higher than a threshold voltage Vth at which the power switching element Sw is switched on. Therefore, in the case 1, when the gate voltage reaches the threshold voltage Vth, it shifts to the mirror period, and the rising speed of the gate voltage becomes small so as to be negligible compared with before the mirror period. After the elapse of the period, the voltage converges to V1. Thereafter, as the delay time Td elapses, the switching circuit 24 is switched to the selection state of the b terminal, so that the gate voltage Vge rises to the voltage “V1 + V2”.

  On the other hand, in the case 2, the gate voltage Vge rises at once to the voltage V1. In this case, since the output signal of the comparator 48 becomes logic “H” and overcurrent is detected, the switching circuit 24 is maintained in the selected state of the a terminal even when the delay time Td elapses, and the selection of the b terminal is performed. Do not switch to state. The delay time Td is set to be longer than the time Ti required for determination of overcurrent by the overcurrent determination means configured with the comparator 48. In the figure, the time Ti is described as the time required for the output of the comparator 48 to be inverted to the logic “H”, but this time Ti is precisely the output signal of the comparator 48 being the logic “H”. Is the time until the influence is reflected in the AND circuit 52 via the inverter 54. The threshold current for determining the overcurrent is set to be equal to or less than the maximum current that can flow through the power switching element Sw when the gate voltage becomes the voltage V1.

  Thereby, when an overcurrent flows, the current flowing through the power switching element Sw can be limited by limiting the gate voltage to the voltage V1. Incidentally, the maximum current that can flow through the power switching element Sw when the gate voltage becomes the voltage “V1 + V2” is a large current that cannot maintain the reliability of the power switching element Sw, and is particularly sufficiently larger than the threshold current. . Nevertheless, the reason why the gate application voltage is increased to the voltage “V1 + V2” is that the conduction loss when the power switching element Sw is turned on becomes smaller as the gate voltage Vge increases. However, when the gate applied voltage is increased to the voltage “V1 + V2” at a stretch, the current flowing through the power switching element Sw becomes excessively large (the gate voltage becomes the voltage “V1 + V2”) under an abnormal situation where an overcurrent flows. In some cases, the maximum current that can be passed through the power switching element Sw). This is because the operating speed of the overcurrent determination means is limited. For this reason, it is necessary to select a power switching element Sw that can withstand at least the large current during the period until it is determined that the overcurrent flows by the overcurrent determination means and the fail-safe process is performed. The element Sw is increased in size.

  In particular, in the case where the power switching element Sw and the free wheel diode FD are formed adjacent to each other on the same semiconductor substrate, the conduction loss of the power switching element Sw tends to increase, so the thickness between the emitter and the collector is large. However, in this case, since resistance to heat is reduced, the allowable current that can be passed through the power switching element Sw is reduced. For this reason, when selecting a device that can withstand a large current for a time until the fail-safe process is performed, a demand for increasing the surface area of the power switching element Sw becomes particularly large.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) When switching the power switching element Sw to the ON state, the switching circuit 24 is switched from the selection state of the a terminal to the selection state of the b terminal. Thereby, the gate applied voltage can be changed stepwise. In particular, the gate voltage Vge in the selected state of the terminal a can be limited to the voltage V1 of the power supply 20.

  (2) The gate applied voltage “V1” in the selected state of the a terminal of the switching circuit 24 is set higher than the voltage at which the power switching element Sw is turned on (voltage at the end of the mirror period). As a result, when the switching state is switched to the on state, the gate application voltage can be made different between before and after the transition to the mirror period.

  (3) After the end of the mirror period of the power switching element Sw, the switching circuit 24 is switched from the selected state of the a terminal to the selected state of the b terminal. As a result, when the switching state is switched to the on state, the gate application voltage can be made different between before and after the transition to the mirror period.

  (4) A delay circuit 50 that generates a delay signal DL that indicates a timing delayed with respect to a timing at which the operation signal g of the power switching element Sw is instructed to be switched on is provided, and the switching circuit 24 is based on the delay signal DL. The selected state of the a terminal was switched to the selected state of the b terminal. Thereby, the switching process can be performed at an appropriate timing.

  (5) The delay circuit 50 is a circuit that receives the operation signal g and generates the delay signal DL. Thereby, the delay signal DL can be appropriately generated.

  (6) The delay time Td by the delay signal DL is set to be longer than the time required for the overcurrent determination by the overcurrent determination means (comparator 48 or the like). Thereby, it is possible to switch from the selection state of the a terminal of the switching circuit 24 to the selection state of the b terminal after waiting for the determination of the presence or absence of overcurrent.

  (7) When an overcurrent is detected, switching from the selection state of the a terminal of the switching circuit 24 to the selection state of the b terminal is prohibited. Thereby, it can avoid that the electric current which flows through the power switching element Sw increases further.

  (8) Power switching that constitutes the series connection body in the power conversion circuit (inverter IV) including the series connection body of the high-potential side power switching element Swp and the low-potential side power switching element Swn as the drive target of the drive unit DU Elements Swp and Swn were used. In this case, when a situation occurs in which both the high-potential side power switching element Swp and the low-potential side power switching element Swn are turned on, an excessive current may flow through them. The utility value is particularly great.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the present embodiment, the switching circuit 24 is switched from the selection state of the a terminal to the selection state of the b terminal during the mirror period of the power switching element Sw. Thereby, the loss due to the current flowing through the power switching element Sw is reduced. That is, when the gate voltage Vge converges on the voltage V1 of the power source 20 after the end of the mirror period, the loss becomes larger than when the gate application voltage is set to the voltage V1 + V2 after the end of the mirror period. Therefore, by performing the switching in the middle of the mirror period, the gate voltage Vge quickly rises toward the voltage V1 + V2 after the end of the mirror period, and the loss can be reduced.

  FIG. 6 shows a drive process (particularly during normal operation) of the power switching element Sw according to the present embodiment. 6A to FIG. 6D correspond to the previous FIG. 5A to FIG. 5D. In the mirror period shown in the figure, the rising speed of the gate voltage Vge is negligibly small compared to before the mirror period and after the mirror period, but actually, as shown in the enlarged lower part in the figure, the gate voltage Vge is rising. The rising speed is increased by switching from the selection state of the a terminal of the switching circuit 24 to the selection state of the b terminal.

  The switching timing can be set by adjusting the circuit time constant of the delay circuit 50 or the like.

  According to the present embodiment described above, in addition to the effects (1), (2), (4) to (8) of the first embodiment, the following effects can be obtained. Become.

  (9) The delay time Td due to the delay signal DL is set to a time that is assumed to be required from the switching command timing to turn on the power switching element Sw to the timing before the end of the mirror period in the mirror period. . Thereby, the loss of the power switching element Sw can be reduced.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the present embodiment, the switching circuit 24 is switched from the selected state of the a terminal to the selected state of the b terminal at the end timing of the mirror period of the power switching element Sw. As a result, loss due to current flowing through the power switching element Sw is reduced while suppressing an increase in surge. FIG. 7 shows a drive process (particularly during normal operation) of the power switching element Sw according to the present embodiment. 7A to 7D correspond to the previous FIGS. 5A to 5D.

  That is, in the second embodiment, as shown in FIG. 6, the gate voltage Vge is changed by switching the switching circuit 24 from the selection state of the a terminal to the selection state of the b terminal in the middle of the mirror period. Ascending speed increases. As a result, the rate of change of the current flowing through the power switching element Sw increases, which may result in a surge. On the other hand, by making the switching at the end of the mirror period, the loss of the power switching element Sw is reduced as much as possible while suppressing the surge.

  The switching timing can be set by adjusting the circuit time constant of the delay circuit 50 or the like.

  According to the present embodiment described above, in addition to the effects (1), (2), (4) to (8) of the first embodiment, the following effects can be obtained. Become.

  (10) The delay time Td of the delay signal DL is set to a time that is assumed to be required from the ON operation command timing of the power switching element Sw to the end timing of the mirror period. Thereby, loss can be reduced as much as possible while suppressing surge.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 8 shows a circuit configuration of the drive unit DU according to the present embodiment. In FIG. 8, members corresponding to those shown in FIG. 2 are given the same reference numerals for the sake of convenience.

  In the present embodiment, the end of the mirror period is determined using the gate voltage Vge as an input, and based on this, switching from the selected state of the a terminal to the selected state of the b terminal is performed. That is, in the present embodiment, the comparator 60 is provided, the gate voltage Vge is applied to the non-inverting input terminal, and the inverting input terminal is slightly higher than the voltage Vth when the power switching element Sw is turned on by the power source 62. An end detection voltage Vm is applied. Then, the AND circuit 52 generates a logical product signal of the delay signal DL, the output signal of the inverter 54, and the output signal of the comparator 60, and outputs the logical product signal to the control unit 40. As a result, in the control unit 40, the delay time Td elapses from the timing at which the operation signal g is switched to the on command, the overcurrent is not detected, and the gate voltage Vge becomes equal to or higher than the end detection voltage Vm. The above switching is performed when the logical product of and becomes true. Here, the delay time Td is detected by an overcurrent determination unit configured to include a comparator 48 or the like when an overcurrent flows through the power switching element Sw from the timing when the operation signal g is switched to the ON operation command. It is set to a time that is not less than the time Ti required for the mirror period and shorter than the time required for the end of the mirror period.

  FIG. 9 shows a driving process of the power switching element Sw according to the present embodiment, comparing a normal case (case 1) and a case where an overcurrent is detected (case 2). 9A to 9D correspond to the previous FIGS. 5A to 5D, and FIG. 9E shows the transition of the delay signal DL.

  As shown in the figure, in the normal state, the mirror period ends and the gate voltage Vge becomes equal to or higher than the end detection voltage Vm, so that the switching state from the selection state of the a terminal of the switching circuit 24 to the selection state of the b terminal is switched. Made. On the other hand, when an overcurrent flows, the above switching is not performed, and the current flowing through the power switching element Sw is limited to a current that can be flowed by the voltage V1 of the power supply 20.

  According to the present embodiment described above, in addition to the effects (1), (2), (4) to (8) of the first embodiment, the following effects can be obtained. Become.

  (11) The switching is performed by detecting the end of the mirror period of the power switching element Sw and detecting the end of the mirror period. Thereby, loss can be reduced as much as possible while suppressing surge.

  (12) The above switching is performed when the delay time Td defined by the delay signal DL elapses and the end of the mirror period is detected. As a result, even if the gate voltage Vge becomes equal to or higher than the end detection voltage Vm before it is determined that the overcurrent has flowed in a situation where the overcurrent flows due to the power switching element Sw being switched to the ON state, the switching is not performed. Can be avoided.

(Fifth embodiment)
Hereinafter, the fifth embodiment will be described with reference to the drawings with a focus on differences from the fourth embodiment.

  In the present embodiment, the end detection voltage Vm for determining the end of the mirror period is variably set according to the temperature of the power switching element Sw. This is a setting in view of the fact that the threshold voltage Vth at which the power switching element Sw is switched on varies with temperature.

  FIG. 10 shows a circuit configuration of the drive unit DU according to the present embodiment. In FIG. 10, members corresponding to those shown in FIG. 8 are given the same reference numerals for convenience. As shown in the figure, the power source 62a variably sets the end detection voltage Vm based on a temperature detection signal from a temperature sensitive diode SD that is disposed near the power switching element Sw and detects its temperature. As a result, the end detection voltage Vm is set to a value that is slightly larger than the value that the power switching element Sw actually switches to the on state according to the temperature detection value of the power switching element Sw.

  According to the present embodiment described above, in addition to the effects (1), (2), (4) to (8) of the first embodiment, the following effects can be obtained. Become.

  (13) The end detection voltage Vm is variably set according to the temperature of the power switching element Sw. Thereby, the end detection voltage Vm can be set according to a value assumed as the gate voltage Vge in the mirror period at the current temperature. Therefore, the end of the mirror period can be detected more quickly than when the end detection voltage Vm is a fixed value.

(Sixth embodiment)
Hereinafter, the sixth embodiment will be described with reference to the drawings with a focus on differences from the fourth embodiment.

  In the present embodiment, the end of the mirror period is detected based on detection of a change in the gate voltage Vge.

  FIG. 11 shows a circuit configuration of the drive unit DU according to the present embodiment. In FIG. 11, members corresponding to those shown in FIG. 2 are given the same reference numerals for convenience. As shown in the figure, the present embodiment includes a differentiating circuit 74 that receives a gate voltage Vge as input and differentiates it. The differentiating circuit 74 can be constituted by, for example, an RC circuit. The output of the differentiating circuit 74 (the changing speed of the gate voltage Vge) is applied to the non-inverting input terminal of the comparator 70, and the voltage Vd of the power source 72 is applied to the inverting input terminal of the comparator 70. Here, the voltage Vd is set to a value that can make the output value of the comparator 70 different between the output value of the differentiating circuit 74 other than the mirror period and the output value of the differentiating circuit 74 in the mirror period. Then, the AND circuit 52 outputs a logical product signal of the delay signal DL, the output signal of the inverter 54, and the output signal of the comparator 70 to the control unit 40. Thereby, in the control unit 40, the delay time Td elapses from the timing at which the operation signal g is switched to the ON operation command, the overcurrent does not flow, and the rising speed of the gate voltage Vge becomes a predetermined value or more. When the logical product of is true, the switching circuit 24 is switched from the selected state of the a terminal to the selected state of the b terminal. Note that the delay time Td defined by the delay signal DL is not less than the time required from the timing when the operation signal g is switched to the ON operation command to the timing when the operation signal g shifts to the mirror period and not more than the time required until the end timing of the mirror period. Set to

  FIG. 12 shows a driving process of the power switching element Sw according to the present embodiment. 12A to 12C correspond to the previous FIGS. 5A to 5C, and FIG. 12D shows the transition of the output signal of the comparator 70. FIG. 12 (e) shows the transition of the delay signal DL.

  As shown in the figure, the operation signal g is switched to an on operation command, and the charging switching element 30 is turned on, whereby the gate voltage Vge increases. Thereby, the comparator 70 outputs a signal indicating that the change rate of the gate voltage Vge is larger than that due to the mirror period, but in this case, the delay time Td specified by the delay signal DL does not elapse. There is no switching. Thereafter, although the delay time Td specified by the delay signal DL elapses in the middle of the mirror period, the comparator 70 outputs a signal indicating that the change rate of the gate voltage Vge is due to the mirror period. The above switching is not performed. Thereafter, the comparator 70 outputs a signal indicating that the change rate of the gate voltage Vge is higher than that due to the mirror period, whereby the switching is performed.

  According to the present embodiment described above, in addition to the effects (1), (2), (4) to (8) of the first embodiment, the following effects can be obtained. Become.

  (14) The end of the mirror period is detected based on the detection of the change in the gate voltage Vge. Thereby, the end of the mirror period can be accurately detected.

(Seventh embodiment)
Hereinafter, the seventh embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 13 shows a circuit configuration of the drive unit DU according to the present embodiment. In FIG. 13, members corresponding to those shown in FIG. 2 are given the same reference numerals for convenience. As illustrated, in this embodiment, in addition to the switching circuit 24 that connects the power supply 20 and the power supply 22 in series, a switching circuit 84 that connects the power supply 86 of the voltage V3 and the power supply 22 in series is provided. Here, the switching circuit 84 connects the negative electrode of the power source 22 to the emitter of the power switching element Sw by selecting the a terminal, while the negative terminal of the power source 22 is connected to the emitter of the power source 86 by selecting the b terminal. Connect to the positive electrode. Note that the negative electrode of the power source 86 is connected to the negative electrode of the power switching element Sw. In the present embodiment, the voltage V1 of the power supply 20 is set to a value smaller than the threshold voltage Vth for switching the power switching element Sw from the off state to the on state.

  In the present embodiment, a charging switching element 80 and a charging resistor 82 are further connected in parallel to the charging switching element 30 and the charging resistor 32. Here, the resistance value R2 of the charging resistor 82 is smaller than the resistance value R1 of the charging resistor 32.

  FIG. 14 shows a driving process of the power switching element Sw according to the present embodiment. 14 (a) and 14 (b) correspond to FIGS. 5 (a) and 5 (b), and FIG. 14 (c) shows how the charging switching element 80 is operated. FIG. 14 (d) shows the transition of the operation mode of the switching circuit 24, and FIG. 14 (e) shows the transition of the operation mode of the switching circuit 84.

  As shown in the figure, in accordance with the ON operation command, the charging switching element 80 is switched to the ON state in a state where both the switching circuit 24 and the switching circuit 84 are in the selected state of the a terminal. As a result, the gate voltage Vge rises to the voltage V1 of the power supply 20. In addition, the rate of voltage increase increases because the resistance value R2 of the charging resistor 82 is small. Then, after the gate voltage Vge becomes the voltage V1, the switching circuit 24 is switched to the selection state of the b terminal, the charging switching element 80 is turned off, and the charging switching element 30 is turned on. As a result, the gate voltage Vge rises to the voltage “V1 + V2” via the threshold voltage Vth. Then, after the timing when the gate voltage Vge becomes the voltage “V1 + V2”, the switching circuit 84 is switched to the selection state of the b terminal. As a result, the gate voltage Vge rises to the voltage “V1 + V2 + V3”.

  The switching circuit 24 may be switched from the selected state of the a terminal to the selected state of the b terminal based on a delay signal of a delay circuit having the same configuration as the delay circuit 50 described above. Further, the turning-off operation of the charging switching element 80 and the turning-on operation of the charging switching element 30 may be performed based on this delay signal. Furthermore, the switching circuit 84 can be switched from the selected state of the a terminal to the selected state of the b terminal using the delay circuit 50 or the like of the first embodiment.

  According to the present embodiment described above, in addition to the effects (1), (2), (4) to (8) of the first embodiment, the following effects can be obtained. Become.

  (15) As a path bypassing the charging resistor 32, a path including the charging switching element 80 and the charging resistor 82 is provided, and the voltage V1 applied to the gate when using this path is set to be equal to or lower than the threshold voltage Vth. . Thereby, the switching speed from the off state to the on state can be increased while suppressing noise such as surge.

(Eighth embodiment)
Hereinafter, the eighth embodiment will be described with reference to the drawings with a focus on differences from the previous seventh embodiment.

  FIG. 15 shows a driving process of the power switching element Sw according to the present embodiment. 15A to 15E correspond to the previous FIGS. 14A to 14E.

  As shown in the figure, in the present embodiment, both the charging switching element 30 and the charging switching element 80 are turned on in response to the ON operation command, and the charging switching element after the time when the gate voltage Vge becomes the voltage V1. 80 is turned off. Thereby, the period during which the gate voltage Vge is raised to the voltage V1 can be further reduced. However, when such control is performed, the resistance value R2 of the charging resistor 82 may not be smaller than the resistance value R1 of the charging resistor 32. This is because the resistance value of the parallel circuit of the charging resistor 32 and the charging resistor 82 is smaller than the resistance value of the charging resistor 32.

(Ninth embodiment)
Hereinafter, the ninth embodiment will be described with reference to the drawings with a focus on differences from the eighth embodiment.

  FIG. 16 shows a circuit configuration of the drive unit DU according to the present embodiment. In FIG. 16, members corresponding to those shown in FIG. 13 are given the same reference numerals for convenience. As shown in the figure, in the present embodiment, the switching circuit 90 connects the negative terminal of the power source 20 to the a terminal that connects to the emitter of the power switching element Sw, the b terminal that connects to the positive terminal of the power source 22, and the positive terminal of the power source 86. c terminal is provided.

  FIG. 17 shows a driving process of the power switching element Sw according to the present embodiment. 17A to 17C correspond to FIGS. 14A to 14C, and FIG. 17D shows the transition of the operation mode of the switching circuit 90. Indicates.

  As illustrated, in the present embodiment, in response to the ON operation command, the charging switching element 30 and the charging switching element 80 are turned ON in a state where the switching circuit 90 is in the selected state of the terminal a. Thereafter, after the time point when the gate voltage Vge reaches the voltage V1, the switching circuit 90 is switched to the selection state of the b terminal. Then, after the time when the gate voltage Vge exceeds the threshold voltage Vth, the switching circuit 90 is switched to the selection state of the c terminal.

(Other embodiments)
The above embodiments may be implemented with the following modifications.
<About delay signal generation means>
The delay signal generating means is not limited to means for receiving the operation signal g and delaying it. For example, a timer that performs a timing operation triggered by the operation signal g becoming an ON command signal may be provided, and a timing at which the value of the timer exceeds a threshold value may be specified.
<Voltage changing means>
The voltage changing means is not limited to the one provided with the delay circuit 50. For example, the delay circuit 50 may be omitted in the fourth and fifth embodiments. Further, in the previous sixth embodiment, the delay circuit 50 is omitted, and the end of the mirror period is terminated based on the fact that the output of the comparator 60 becomes logic “H” twice after the operation signal g becomes the ON command signal. Means for detecting may be configured.
<About overcurrent judgment means>
The overcurrent determination means is not limited to means for determining the presence or absence of overcurrent by comparing the voltage drop amount of the shunt resistor due to a minute current at the sense terminal St of the power switching element Sw and the reference voltage Vref. For example, the amount of voltage drop between the input terminal and output terminal of the power switching element Sw is used as a parameter correlated with the current flowing through the power switching element Sw, and this value is compared with a threshold value to determine the presence or absence of overcurrent. It may be a means to do.
<About switching elements to be driven>
The IGBT to be driven is not limited to one that constitutes a semiconductor device provided with a free wheel diode provided on the same semiconductor substrate as that connected in reverse parallel to the IGBT. Further, the field effect transistor is not limited to the IGBT, and may be a field effect transistor such as a super junction MOS field effect transistor or a MOS field effect transistor formed of silicon carbide (SiC). Note that when a MOS field effect transistor is employed as a driving target, not only an N-channel transistor but also a P-channel transistor may be used. In the case of a P-channel transistor, the potential of the conduction control terminal is further brought closer to the potential side of the output terminal by reducing the number of voltage generating means connected in series during the switching process period from the off state to the on state. You may do it.

  However, the process of reducing the potential difference between the conduction control terminal and the output terminal may be performed by increasing the number of voltage generation means connected in series. This can be realized by connecting the positive or negative electrodes of the voltage generating means connected in series.

Further, the power switching element to be driven is not limited to that constituting the inverter IV or the converter CV. At this time, the present invention is not limited to the configuration including a series connection body of the power switching element Swp on the high potential side and the power switching element Swn on the low potential side.
<Regarding charging switching element and charging resistor>
The charging switching element and the charging resistor are not limited to those constituting a single or pair of electrical paths. For example, three or more electrical paths may be configured. At this time, the period during which the resistance value of the electrical path for charging is reduced is not limited to before the mirror period, but may be a period after the end of the mirror period.
<Other>
The seventh embodiment may be changed by changing the ninth embodiment with respect to the eighth embodiment.

  40: control unit, 48: comparator, 50: delay circuit, Sw: power switching element, DU: drive unit.

Claims (17)

Voltage application means for applying a voltage for turning on the switching element to the conduction control terminal of the voltage-controlled switching element, and opening / closing means for opening and closing between the voltage application means and the conduction control terminal In the switching element drive device for driving the switching element by operating the opening and closing means,
The voltage application means includes a plurality of voltage generation means and variable means for variably setting the number of the voltage generation means connected in series between the output terminal of the switching element and the conduction control terminal. Switching device drive device.   Further comprising an increasing operation means for increasing the number of voltage generating means connected in series during the switching process period of the switching state of the switching element from the OFF state to the ON state by operating the variable means. The driving device for a switching element according to claim 1.   By operating the variable means, when the switching element is switched from the off state to the on state, the voltage applied to the conduction control terminal is more than the threshold voltage at which the switching element switches from the off state to the on state. 3. The apparatus further comprises voltage changing means for operating the variable means so that the first voltage on the state side is switched to the second voltage on the on state side rather than the first voltage. The switching element drive device described.   4. The switching element driving device according to claim 3, wherein the voltage changing means switches from the first voltage to the second voltage after a mirror period of the switching element.   The voltage changing unit includes a delay signal generating unit that generates a delay signal that indicates a timing delayed with respect to a timing at which the operation signal of the switching element is instructed to switch to an ON state, and the switching based on the delay signal The switching element driving device according to claim 3, wherein:   6. The switching element driving apparatus according to claim 5, wherein the delay signal generating means generates the delay signal by using the operation signal as an input. Overcurrent determination means for determining whether or not the current flowing through the switching element becomes excessively large;
7. The switching element driving device according to claim 6, wherein a delay time by the delay signal is set to be equal to or longer than a time required for the overcurrent determination by the overcurrent determination means.   The switching element according to claim 7, further comprising a prohibiting unit that prohibits the switching by the voltage changing unit when the overcurrent determining unit determines that the current flowing through the switching element becomes excessively large. Drive device.   The delay time until the delayed timing is assumed to be the time required from the switching command timing to turn on the switching element to the timing before the end of the mirror period of the mirror period of the switching element. The switching element driving device according to claim 5, wherein the switching element driving device is set.   The delay time until the delayed timing is set to a time that is assumed to be required from the switching command timing to turn on the switching element to the end timing of the mirror period of the switching element. The driving device for a switching element according to any one of claims 5 to 8.   The voltage changing means includes end detection means for detecting the end of a mirror period of the switching element, and switches from the first voltage to the second voltage when the end of the mirror period is detected. The switching element drive device according to claim 3 or 4.   The voltage changing means includes end detection means for detecting the end of a mirror period of the switching element, and the switching is performed when a delay time defined by the delay signal has elapsed and the end of the mirror period is detected. The switching element drive device according to claim 5, wherein:   The end detection means includes comparison means for comparing the voltage of the conduction control terminal with the end determination voltage, and the comparison result of the comparison means is a signal indicating the detection result of the presence or absence of the end of the mirror period. The drive device for a switching element according to claim 11 or 12. Comprising temperature detecting means for detecting the temperature of the switching element;
14. The switching element driving device according to claim 13, wherein the end detection unit variably sets the end determination voltage in accordance with a temperature detected by the temperature detection unit.   13. The end detection means includes means for detecting a change in voltage of the conduction control terminal, and detects the end of the mirror period based on the change being detected. Switching device drive device. The voltage applying unit includes: a pre-voltage generating unit that generates a pre-voltage that is a voltage on a voltage side of the switching element from a threshold voltage at which the switching element is switched from an off state to an on state; A post voltage generation means for generating a post voltage that is a voltage on the voltage side to be in a state;
The opening / closing means includes a plurality of opening / closing means for opening / closing between the conduction control terminal and the voltage applying means,
When switching the switching state of the switching element from the off state to the on state, the post voltage generation unit is operated after the opening / closing unit is operated to realize the connection state between the pre-voltage generation unit and the conduction control terminal. Further comprising means for switching to a connection state with the conduction control terminal,
16. The resistance value at the time of connection between the pre-voltage generation means and the conduction control terminal is smaller than the resistance value at the time of connection between the post voltage generation means and the conduction control terminal. The switching element drive device according to any one of the above.   The switching element is a switching element constituting the series connection body in a power conversion circuit including a series connection body of a high potential side switching element and a low potential side switching element. The switching element driving device according to any one of the preceding claims.

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