JP2011134416A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain data reliability even when a threshold voltage distribution width is expanded. <P>SOLUTION: After a predetermined temporary write voltage is applied to a memory cell MC, the writing speed of the memory cell MC is determined (S1 and S2). Then, threshold voltage sorting processing corresponding to the writing speed is executed (S3 to S5), and threshold voltage adjustment processing is executed according to write data (S6 to S9). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device including electrically rewritable memory cells.

  Non-volatile semiconductor memory devices (NAND flash memory, etc.) are being applied to handle large-capacity data such as moving images in portable device applications, for example. In order to handle a large amount of data, it is necessary to miniaturize elements and reduce design rules, and further, it is an indispensable technique to increase the speed of data writing.

  In order to solve this type of problem, for example, the technical idea of Patent Document 1 is provided. According to the technical idea described in Patent Document 1, identification data for performing write speed verification and classifying memory cells into a first cell group and a second cell group having a write speed slower than that of the first cell group. And the first cell group and the second cell group are alternately electrically written under different write conditions. When this technical idea is applied, data writing can be speeded up.

  By the way, when the element is miniaturized, the element characteristics of the memory cell include, for example, the amount of impurity implantation during the ion implantation process, the variation in gate length and gate width and the film thickness of other element components, and the amount of etching processing. It varies greatly depending on factors.

  For this reason, variations in element characteristics among the memory cells occur, and an increase in the threshold distribution width due to a large number of memory cells is inevitable. When the threshold distribution width is enlarged, the operation speed is reduced, the memory cell selection / non-selection ratio is lowered, and self-field variation and proximity effect variation are caused. Therefore, even if the technical idea of Patent Document 1 is applied, the reliability of stored data is poor.

JP 2007-4861 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can maintain data reliability even when the threshold voltage distribution width is expanded.

  According to one embodiment of the present invention, data is written and erased by adjusting a memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arrayed and a threshold voltage of the plurality of memory cells in the memory cell array A control circuit, wherein the control circuit determines a write speed of the memory cell, and each of the memory cells in a plurality of threshold voltage regions corresponding to a plurality of memory cell groups sorted based on the speed determination result. Data is written by adjusting a threshold voltage according to write data.

  According to one embodiment of the present invention, data reliability can be maintained even when the threshold voltage distribution width is increased.

The block diagram which shows the electric constitution in 1st Embodiment of this invention. Partial circuit diagram of the memory cell array A longitudinal sectional view showing a schematic structure of a NAND cell unit Explanatory diagram schematically showing the relationship between the threshold voltage distribution and the number of memory cells Explanatory drawing which shows roughly the threshold voltage distribution of the memory cell in the erased state A flowchart showing a schematic flow of data writing processing Explanatory drawing which shows threshold voltage distribution of many memory cells A flowchart showing a schematic flow of data reading processing The flowchart which shows schematically the flow of the erasure | elimination process in 2nd Embodiment of this invention.

(First embodiment)
A first embodiment in which a nonvolatile semiconductor memory device of the present invention is applied to a NAND flash memory device will be described with reference to FIGS. In the following description in the drawings, the same or similar parts are denoted by the same or similar reference numerals.

  FIG. 1 is a schematic block diagram showing an electrical configuration of a NAND flash memory device. As shown in FIG. 1, the flash memory device 1 includes a memory cell array Ar having a large number (a plurality) of memory cells MC for storing data. Data stored in the memory cell MC is configured to be erasable / written / read out.

  In the memory cell array Ar, a plurality of bit lines BL, a plurality of word lines WL, and a common source line CSL are configured, and each memory cell MC is planarly connected to the bit lines BL and the word lines WL. It is located in the intersection area. A cache memory CM and a sense amplifier circuit SA / PB are formed around the memory cell array Ar, and these are used for writing / reading the memory cells MC in the memory cell array Ar.

  In addition, the flash memory device 1 includes a control circuit 2, an address register 3, a word line control circuit 4, a bit line control circuit 5, an input / output buffer 6, and the like. In addition, a voltage generation circuit for applying a high voltage to the word line WL and a defective block determination circuit for determining whether or not a block to be read are defective blocks are provided. The control circuit 2 is connected to the control terminal CONT, and is provided as a block that mainly controls the operations of the blocks 3 to 6.

  The input / output buffer 6 is connected to the input / output terminal I / O, and inputs / outputs data via the input / output signal pin I / O in accordance with control from the control circuit 2. The input / output buffer 6 is provided as a buffer for temporarily storing data when data is input / output.

  The address register 3 stores the address data when it is detected that the address data is input to the input / output buffer 6 in response to a control signal from the control circuit 2. The word line control circuit 4 selects the word line WL by the row decoder 4 a, and the bit line control circuit 5 selects the bit line BL by the column decoder 5. Thereby, the memory cell MC in the memory cell array Ar can be specified. The word line control circuit 4 is a circuit for controlling the voltage applied to the word line WL, and the bit line control circuit 5 is provided as a circuit for controlling and detecting the voltage of the bit line BL.

FIG. 2 shows an electrical configuration of a part of the memory cell array and its peripheral blocks.
As shown in FIG. 2, the memory cell array Ar includes a plurality of blocks B (B _{0 to} B _j-1 ). The plurality of blocks B are arranged in the column direction (Y direction), and each block B is configured by a plurality of NAND cell units UC (UC _{0 to} UC _n-1 ) arranged in the row direction (X direction). ing. Bit lines BL (BL _{0 to} BL _n-1 ) are provided corresponding to the NAND cell units UC (UC _{0 to} UC _n-1 ), and the bit lines BL (BL _{0 to} BL _n-1 ) are respectively provided. Stretched in the row direction.

  One NAND cell unit UC includes two select gate transistors STD and STS, and a plurality of transistors connected in series by sharing adjacent source / drain regions between these select gate transistors STD and STS. (For example, 32) memory cells MC (memory cell transistors). The selection gate transistor STD has its drain connected to the bit line BL, and the selection gate transistor STS has its source connected to the source line CSL.

The memory cells MC are commonly connected by connecting their control gate electrodes CG (see FIG. 3 to be described later) with word lines WL (WL _{0 to} WL _m−1 ). The select gate transistors STD are connected in common by connecting their gate electrodes SGD (see FIG. 3 to be described later) with a select gate line SGLD. Further, the select gate transistors STS are connected in common by connecting their gate electrodes SGS (see FIG. 3 described later) with a select gate line SGLS. These selection gate lines SGLD and SGLS are provided for each block B.

  FIG. 3 schematically shows the structure of the cell unit. As shown in FIG. 3, an n well 7 a and a p well 7 b are sequentially formed on the surface layer of the semiconductor substrate 7. A selection gate electrode SGD of the selection gate transistor STD is formed on the p well 7b via the gate insulating film 8. In addition, the selection gate SGS of the selection gate transistor STS is formed on the p-well region 7b via the gate insulating film 8 so as to be separated from the formation region of the selection gate electrode SGD in a plan view. On the semiconductor substrate 7b between the select gate electrodes SGD-SGS, a plurality of gate electrodes MG of the memory cells MC are formed via the gate insulating film 8. The gate electrode MG has a structure in which the inter-gate insulating film 9 is sandwiched between the floating gate electrode FG and the control gate electrode CG (word line WL).

  Impurity diffusion layers 7c serving as source / drain regions are formed on the surface layer of the semiconductor substrate 7 between the gate electrodes MG-MG, between the gate electrode MG and the selection gate electrode SGD, and between the gate electrode MG and the selection gate electrode SGS. Is formed.

  An impurity diffusion layer 7d for source line contact is formed on the surface layer of the semiconductor substrate 7 on one side of the selection gate electrode SGS. A source line CSL is electrically connected on the impurity diffusion layer 7d. On the surface layer of the semiconductor substrate 7 on one side of the selection gate electrode SGD, an impurity diffusion layer 7d for bit line contact is formed.

  Each memory cell MC includes a floating gate electrode FG, and stores data of four or more values (multi-value: for example, 2-bit data) corresponding to the electron injection amount of the floating gate electrode FG. In this embodiment, the memory cells MC connected in the row direction by one word line WL constitute one page. One page as a unit may be provided such that the memory cells MC corresponding to the even-numbered pit lines BL and the memory cells MC corresponding to the odd-numbered bit lines BL each constitute one page. Data is configured to be writable / readable for each page.

  The cache memory CM shown in FIG. 1 has a structure similar to that of the memory cell array Ar, and is configured to store a smaller number of bits than the number of bits stored per memory cell in the memory cell array Ar. This is because the cache memory CM places importance on the writing / reading speed. In the present embodiment, the cache memory CM stores, for example, binary data (1-bit data). In the cache memory CM, the structure of the cell unit UC is prepared for a plurality of blocks B, and data is temporarily input from the outside via the input / output buffer 6, and then the sense amplifier circuit SA / PB writes to the memory cell array Ar.

  As shown in FIG. 2, a sense amplifier circuit SA / PB is connected to the bit line BL in the memory cell array Ar. The sense amplifier circuit SA / PB includes a voltage sensing circuit SA for the bit line BL and a data storage circuit PB. Although not shown, the voltage sensing circuit SA and the data storage circuit PB are arranged for one page in the row direction. Each data storage circuit PB has a function of holding data read from the memory cell MC and a function of holding write data of the memory cell MC.

  Here, a writing method of the NAND flash memory device 1 of the binary storage method will be schematically described. In the binary NAND flash memory device 1, the threshold voltage of one memory cell MC is adjusted to any one of two voltage distributions, whereby one memory cell MC is converted to four-value data (“1”). , “0”).

FIG. 4 shows the relationship between the threshold voltage distribution of the memory cells MC and the number of memory cells MC in the memory cell array Ar.
In FIG. 4, A distribution to B distribution indicate threshold voltage distributions corresponding to binary data (“1”, “0”), respectively. The E distribution indicates a threshold voltage distribution after binary data is erased from a block, and no data is assigned in this embodiment.

These A distribution to B distribution are set in advance different from each other, and the E distribution, the A distribution, and the B distribution are set apart from each other so as to obtain a high threshold voltage distribution in this order in advance.
Specifically, the upper limit value Veh of the E distribution is set to a voltage value lower than the lower limit value Val of the A distribution. The lower limit value Vbl of the B distribution is set to a voltage value higher than the upper limit value Vah of the A distribution. The voltage distributions of these A distribution to B distribution are set so as to be separated from each other in anticipation of a predetermined margin voltage.

  In FIG. 4, Va indicates a voltage applied to the selected word line WL for reading binary data, and Vread is applied to an unselected word line WL in the NAND cell unit UC when reading data. The voltage indicates the voltage that makes the memory cell MC conductive regardless of the data value stored in the memory cell MC.

A threshold voltage distribution of all the memory cells MC from when the data in the memory cell MC reaches the multi-value final write state will be described.
As shown in FIG. 5, an erased state in which all memory cells MC are adjusted within one threshold voltage distribution (E distribution) is considered. Even in the erased state, the erase threshold voltage distribution of all the memory cells MC has a predetermined threshold voltage width.

  FIG. 6 is a schematic flowchart showing the flow of the writing process from the erased state to the final written state. Control circuits 2, 4, and 5 (hereinafter referred to as control circuit 2 and the like) perform the writing process shown in FIG. 6 for each page on each memory cell MC. The writing process includes a temporary writing process for determining a writing speed (S1 to S2), a threshold voltage sorting process according to the writing speed (S3 to S5), and a threshold voltage adjusting process for adjusting the magnitude according to writing data. (Final writing process: S6 to S9).

First, the control circuit 2 or the like performs a program (S1) by applying a predetermined temporary write voltage to the memory cell MC (word line WL) for a predetermined time, for example, in order to perform a temporary write process for writing speed determination. after rising adjust the threshold voltage Vth of all the memory cells MC by, by applying a read voltage V ₀ which for speed determination to determine the writing speed by reading (S2). Thus, the reason for performing the temporary writing process is that the rising speed of the threshold voltage Vth of the memory cell MC differs depending on a large number of memory cells MC.

FIG. 7A schematically shows a threshold voltage distribution by a large number of memory cells MC at this time. As shown in FIG. 7A, the distribution X ₀ of the threshold voltage Vth of the large number of memory cells MC after the temporary writing process tends to be greatly widened although it can be made narrower than the erase distribution E. This is because the device characteristics of the memory cell MC vary greatly due to factors such as the amount of impurity implantation during the ion implantation process, variations in the gate length, gate width, film thickness of other device components, and the amount of etching processing. This is because the write speeds of the large number of memory cells MC differ from each other.

The read voltage V ₀ for speed determination is a voltage set in advance according to the write voltage and the application time in step S1, and when sorting into two types (less than a predetermined speed and above a predetermined speed), The threshold voltage distribution X ₀ is set in advance to be an intermediate voltage (for example, an average value) between the maximum voltage and the minimum voltage. When the threshold voltage Vth is lower than the read voltage V ₀ , the writing speed is classified as less than a predetermined speed, and when the threshold voltage Vth is equal to or higher than the read voltage V ₀ , the writing speed is classified as a predetermined speed or higher. Note that the writing speed of a large number of memory cells MC may be classified into three or more types.

  Returning to FIG. 6, after determining the writing speed (S1, S2), the control circuit 2 or the like performs a threshold voltage sorting process according to the writing speed (S3 to S5). Specifically, the control circuit 2 or the like applies a verify voltage according to the write speed after programming (S3) by applying a predetermined write voltage according to the write speed to the word line WL for a predetermined time. (S4) and repeat from step S3 until the verify process is OK (S5: YES).

FIG. 7B schematically shows the threshold voltage distribution by the large number of memory cells MC at this time. As described above, when a large number of memory cells MC are separated into two types of high-speed and low-speed write speeds, as shown in FIG. For MC, the threshold voltage Vth is distributed and adjusted to a relatively low distribution A ₁ by shortening the writing time or applying the word line WL with a reduced voltage.

On the other hand, the control circuit 2 or the like applies the threshold voltage Vth to the memory cell MC having a high writing speed by extending the writing time or increasing the voltage applied to the word line WL. Are adjusted to a relatively high distribution B ₁ . These distributions A ₁ and B ₁ are set to be voltage distributions separated from each other, but both distributions A ₁ and B ₁ are both narrower than the threshold voltage distribution X ₀ .

  Returning to FIG. 6, the control circuit 2 or the like loads data from the cache memory CM to the data storage circuit PB constituting the sense amplifier circuit SA / PB (S6), and then applies a predetermined write voltage to the word line WL. Thus, programming is performed (S7), a verify voltage corresponding to the writing speed and data is applied (S8), and the process is repeated from step S7 until the verify process is OK (S9).

FIG. 7C schematically shows the threshold voltage distribution by the large number of memory cells MC at this time. As shown in FIG. 7 (c), the the like control circuit 2, the step S7 by the threshold voltage Vth is increased adjusted threshold voltage Vth of the memory cell MC which is adjusted to the distribution A ₁ at step S3~S5 The threshold voltage distribution is adjusted to one of A ₁₁ and A ₁₂ . That is, the control circuit 2 or the like adjusts the threshold voltage Vth of the memory cell MC whose writing speed is relatively slow to one of the threshold voltage distributions A ₁₁ and A ₁₂ .

Conversely, such a control circuit 2, by the threshold voltage Vth is increased adjusted threshold voltage Vth of the memory cell MC which is adjusted to the distribution B ₁ at step S3 to S5, the threshold voltage distribution B ₁₁ in step S7, adjusted to either B _12. That is, the control circuit 2 or the like adjusts the threshold voltage Vth of the memory cell MC having a relatively high writing speed to one of the threshold voltage distributions B ₁₁ and B ₁₂ .

As shown in FIG. 7C, these threshold voltage distributions A ₁₁ , A ₁₂ , B ₁₁ , B ₁₂ are separated from each other and become higher in this order. In this way, each memory cell MC has its threshold voltage Vth adjusted to any one of the four threshold voltage distributions A ₁₁ , A ₁₂ , B ₁₁ , and B ₁₂ , thereby allowing one bit (binary). ) Is memorized.

FIG. 8 is a flowchart showing a flow when reading the stored data of the memory cell MC. As described above, the threshold voltage Vth of each memory cell MC is adjusted within any one of the four threshold voltage distributions A ₁₁ , A ₁₂ , B ₁₁ , B ₁₂ . As shown in FIG. 8, at the time of data reading, a reading process for determining the writing speed is performed (T1), and then a reading process corresponding to the data is performed (T2).

Specifically, like the control circuit 2 sets a voltage lower than the lower limit of the high distribution B ₁₁ than the upper limit value of the distribution A12 as a read voltage Vref, the threshold voltage Vth by applying the read voltage Vref is It is determined whether it is lower than the read voltage Vref or higher than the read voltage Vref.

When it is determined that the control circuit 2 or the like is lower than the read voltage Vref, the control circuit 2 determines that it belongs to either distribution A ₁₁ or A ₁₂ and is higher than the upper limit value of the distribution A _11. A voltage set lower than the lower limit of ₁₂ is set as the read voltage Va and read. Thereby, the control circuit 2 and the like can read the stored data by determining which voltage in the distribution A ₁₁ or the distribution A _{12 the} threshold voltage Vth is.

Conversely, like the control circuit 2 determines that belong to the one of the distribution of the distribution B ₁₁ or B ₁₂ when it is determined that the read voltage Vref or higher, higher distribution than the upper limit value of the distribution B ₁₁ B ₁₂ A voltage set lower than the lower limit value is set as the read voltage Vb and read. As a result, the control circuit 2 and the like can read the stored data by determining which of the distributions B ₁₁ and B ₁₂ is the threshold voltage Vth.

  According to the present embodiment, the control circuit 2 and the like determine the writing speed of each memory cell MC, and a plurality of threshold voltage regions (corresponding to a plurality of memory cell MC groups sorted based on the speed determination result) Data is written by adjusting the threshold voltage Vth of the memory cell MC in accordance with the write data in the threshold voltage region Vd1 lower than Vref and the threshold voltage region Vd2 equal to or higher than Vref.

Specifically, when the control circuit 2 or the like stores binary data in the memory cell MC, for the memory cell MC having a low writing speed, two threshold voltage distributions are generated according to the data in the threshold voltage region Vd1. Adjustments are made within A ₁₁ and A ₁₂ . Conversely, the control circuit 2 or the like adjusts the two threshold voltage distributions B ₁₁ and B ₁₂ in accordance with the data in the threshold voltage region Vd2 for the memory cell MC having a high writing speed. Therefore, even if the threshold distribution width of a large number of memory cells MC is expanded, binary data can be obtained by adjusting the threshold voltage Vth to any one of the total four voltage distributions A ₁₁ , A ₁₂ , B ₁₁ , B ₁₂ . Can maintain the reliability of data.
In addition, since the memory cell MC of its own stores a flag corresponding to the writing speed, it can be configured without providing a separate storage area.

  When reading data from the memory cell MC, the control circuit 2 or the like sets the boundary voltage between the plurality of threshold voltage regions Vd1 and Vd2 as the read voltage Vref, and the threshold value in any threshold voltage region Vd1 or Vd2 After determining whether or not the voltage is Vth, the read voltages Va and Vb are set in the determined threshold voltage regions Vd1 and Vd2, respectively, and data is read, so that data can be read regardless of whether the writing speed is slow or slow.

Before adjusting the threshold voltage Vth of the memory cell MC in each of the two (plurality) threshold voltage regions Vd1 and Vd2, the control circuit 2 or the like has two (the threshold voltage) according to the writing speed of the memory cell MC. Since the voltage distributions A ₁ and B ₁ in the same number as the regions Vd1 and Vd2) are distributed and adjusted, the threshold voltage Vth can be adjusted according to variations in individual memory cell characteristics.

The control circuit 2 or the like has the memory cell MC whose write speed is less than the predetermined speed for the memory cell MC whose threshold voltage Vth is lower than the predetermined read voltage V ₀ after the predetermined temporary write voltage is applied to the memory cell MC. Memory cell in which the threshold voltage Vth after the predetermined temporary write voltage is applied to the memory cell MC is equal to or higher than the predetermined read voltage V ₀ Since MC is classified from the memory cell MC whose writing speed is equal to or higher than a predetermined speed and is distributed and adjusted to a threshold voltage region higher than the predetermined voltage Vx or Vref, the threshold value is set according to the variation in the characteristics of the individual memory cells MC. The voltage Vth can be adjusted.

(Second Embodiment)
FIG. 9 shows a second embodiment of the present invention. The difference from the previous embodiment is that the threshold voltage of each memory cell is distributed according to the writing speed of the memory cell when data is erased. It is in the place of adjustment. The same parts as those of the above-described embodiment are denoted by the same reference numerals and description thereof is omitted, and different parts will be described below.

  FIG. 9 is a flowchart showing the flow of the erasing process. In the NAND flash memory device 1, an erasing process is performed for each block B (U2). In the present embodiment, before performing the process of step U2, the reading process for determining the writing speed shown in step T1 is performed (U1).

Specifically, the control circuit 2 or the like sets a voltage higher than the upper limit value of the distribution A ₁₂ and lower than the lower limit value of the distribution B ₁₁ as the read voltage Vref, and the threshold voltage Vth of the memory cell MC is set to the read voltage Vref. Or lower than the read voltage Vref. This makes it possible to determine whether the writing speed of the target memory cell MC is fast or slow.

  Then, the control circuit 2 and the like perform a block erase process in step U2, and then perform a threshold voltage sorting process corresponding to the writing speed (U3 to U5). Specifically, the control circuit 2 or the like applies a verify voltage corresponding to the writing speed after programming (U3) by applying a predetermined writing voltage corresponding to the writing speed to the word line WL for a predetermined time. (U4) and repeat from step U3 until the verify process is OK (U5: YES). The erasure process is completed by repeating the processes in steps U3 to U5 over all pages (U6). That is, in the present embodiment, when performing the erasing process, the threshold voltage sorting process according to the writing speed is performed.

  Then, when the data writing process is performed, the control circuit 2 and the like can write the data only by performing the threshold voltage adjustment process (S6 to S9) described in the above embodiment. It can be carried out.

  As described above, according to the present embodiment, the threshold voltage Vth of each memory cell MC is allocated and adjusted in advance when erasing the data of the memory cell MC. When performing the writing process, the process can be performed quickly.

(Other embodiments)
The present invention is not limited to the above embodiment, and for example, the following modifications or expansions are possible.

  In the above-described embodiment, binary writing has been described. However, the present invention can be applied to writing of three values, four values, or more. In this case, the threshold voltage Vth of the memory cell MC may be adjusted in accordance with the ternary and quaternary data in the two threshold voltage regions Vd1 and Vd2, or three or more threshold voltage regions may be set. The threshold voltage Vth of the memory cell MC may be adjusted in accordance with the ternary or quaternary data in the setting area.

  Although applied to the NAND flash memory device 1, it can be applied to other nonvolatile semiconductor memory devices. Although the embodiment in which no data is assigned to the E distribution is shown, the present invention can also be applied to an embodiment in which data is assigned to the E distribution. Further, the present invention can be applied to an embodiment in which the E distribution and the A distribution overlap each other.

  Within the range of conditions described in the above-described embodiment, an equivalent effect can be achieved by appropriately selecting conditions. The above embodiment includes various embodiments, and is described in the column of the problem to be solved by the invention even if some of the constituent elements are deleted from all the constituent elements shown in the above embodiment. In the case where the problem can be solved and the effects described in the column of the effect of the invention can be obtained, the configuration requirements from which the configuration requirements are deleted can be applied as the invention.

  In the drawings, 1 is a flash memory device (nonvolatile semiconductor memory device), 2 is a control circuit, 4 is a word line control circuit (control circuit), 5 is a bit line control circuit (control circuit), MC is a memory cell, Ar is 1 shows a memory cell array.

Claims (5)

A memory cell array in which a plurality of electrically rewritable nonvolatile memory cells are arranged;
A control circuit for writing and erasing data by adjusting threshold voltages of a plurality of memory cells in the memory cell array;
The control circuit determines the write speed of the memory cell, and sets the threshold voltage of the memory cell as write data in a plurality of threshold voltage regions corresponding to a plurality of memory cell groups sorted based on the speed determination result, respectively. A nonvolatile semiconductor memory device, wherein data is written by adjusting accordingly.   When the data of the memory cell is read, the control circuit sets a boundary voltage of the plurality of threshold voltage regions as a read voltage, and is a threshold voltage in any threshold voltage region of the plurality of threshold voltage regions. 2. The nonvolatile semiconductor memory device according to claim 1, wherein after the determination, the read voltage is set in the determined threshold voltage region and the data is read.   The control circuit adjusts the write speed of the memory cell so that the number of threshold voltage distributions is equal to the number of threshold voltage regions before adjusting the threshold voltage of the memory cell in each of the plurality of threshold voltage regions. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage of the memory cell is distributed and adjusted accordingly.   The control circuit discriminates a memory cell having a threshold voltage lower than a predetermined read voltage after a predetermined temporary write voltage is applied to the memory cell from a memory cell having a write speed lower than a predetermined speed, and the predetermined voltage or less. A memory cell whose threshold voltage is equal to or higher than a predetermined read voltage after applying a predetermined temporary write voltage to the memory cell and having a write speed equal to or higher than the predetermined speed 4. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is classified and adjusted to a threshold voltage region higher than the predetermined voltage.   5. The control circuit according to claim 1, wherein the control circuit distributes and adjusts a threshold voltage of each memory cell according to a writing speed of the memory cell when erasing data of the memory cell. The nonvolatile semiconductor memory device described.

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