JP2011129616A - Semiconductor device - Google Patents

Abstract

A semiconductor device in which reverse bias breakdown voltage characteristics of a MOSFET are stable is provided.
A semiconductor device includes an FET cell region (active region) in which a vertical MOSFET having a source electrode is formed on a surface of a semiconductor substrate, and a distance from the source electrode on the surface of the semiconductor substrate. A channel stopper region 22 (channel stop region) having an EQR electrode 101 to be provided. The EQR electrode 101 is formed so that the inter-electrode distance d between the source electrode 11 and the EQR electrode 101 is partially smaller than the other portions.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an EQR (Equivalent Potential Ring) structure on the outer periphery of a chip.

  As this type of technology, Patent Document 1 discloses a semiconductor device having an EQR (Equivalent Potential Ring) structure that functions as a channel stopper.

JP-A-9-32282

  An example of the semiconductor device disclosed in Patent Document 1 will be described with reference to FIG.

  This semiconductor device is an N-channel vertical MOSFET having an EQR structure. FIG. 5A is a cross-sectional view of the end portion of the chip. FIG. 5B is a plan view of the chip.

  In FIG. 5, 1 is an N + type silicon substrate, 2 is an N− type epitaxial layer, 3 is a field insulating film, 4 is a P type base region, 5 is an N + type source region, 6 is a gate oxide film, and 7 is a gate electrode. , 8 is an interlayer insulating film, 9 is an EQR diffusion region, 10 is an EQR electrode, 11 is a source electrode, 21 is an FET cell region (active region), 22 is a channel stopper region (channel stop region), GP is a gate pad, GF Is a gate finger.

  As shown in FIG. 5A, a channel stopper region 22 is provided on the outer periphery of the chip outside the FET cell region 21.

  In the channel stopper region 22, an N + type EQR diffusion region 9 serving as a channel stopper is provided.

  On the EQR diffusion region 9, an EQR electrode 10 made of, for example, aluminum as a low resistance metal, a part of which is directly connected to the EQR diffusion region 9 is disposed.

  The EQR electrode 10 serves to make the EQR diffusion region 9 the same potential over the entire area.

  The EQR electrode 10 is at the same potential as the drain (N + type silicon substrate 1).

  This is because the front surface side and the back surface side are electrically connected via the chip side surface due to processing distortion when the wafer is diced and divided into chips.

  An outline of the manufacturing process of such a MOSFET will be described below.

  First, an N− type epitaxial layer 2 is formed on an N + silicon substrate 1.

  Next, after the field oxide film 3 is formed on the entire surface of the substrate, the field oxide film 3 in the FET cell region 21 is removed. At this time, the channel stopper region 22 remains covered with the field oxide film 3.

  Thereafter, the gate insulating film 6 is formed in the FET cell region 21, polysilicon is deposited thereon, phosphorus is diffused, and the resistance value of the polysilicon is lowered.

  Thereafter, patterning is performed using a photolithography technique to form the gate electrode 7.

  Next, boron is ion-implanted into the N − -type epitaxial layer 2 in a self-aligned manner with the gate electrode 7, thermal diffusion is performed, and a P-type base region 4 is formed.

  Thereafter, a resist is applied and patterning is performed so as to open the channel stopper region 22, and the field oxide film 3 in the channel stopper region 22 is removed.

  Subsequently, arsenic is ion-implanted and thermal diffusion is performed to form the N + source region 5 in the FET cell region 21 and simultaneously form the N + type EQR diffusion region 9 in the channel stopper region 22.

  Thereafter, an interlayer insulating film 8 is formed by the CVD method, and then a contact is opened in the interlayer insulating film 8.

  Then, aluminum is deposited on the substrate surface by vapor deposition or sputtering.

  Next, a resist mask having a predetermined pattern is formed, and the source electrode 11 connected to the source region 5, the EQR electrode 10 connected to the EQR diffusion region 9, and the gate pad portion and the gate finger portion are simultaneously patterned.

  In this way, the N + type EQR diffusion region 9 of the channel stopper region 22 is provided so as to surround the FET cell region 21, and the EQR electrode 10 connected thereto is arranged around.

  Due to the presence of the channel stopper region 22, the withstand voltage characteristic between the source and the drain when the reverse bias is applied becomes stable.

  Next, an example of electrode arrangement on the surface of the semiconductor chip will be described with reference to FIG.

  As shown in FIG. 5B, a rectangular source electrode 11 is arranged at the center of the chip so as to cover the FET cell region.

  The gate finger GF extending from the gate pad GP is disposed so as to cross the source electrode 11. Note that the gate electrode 7 shown in FIG. 5A is connected to the gate finger GF at a portion not shown.

  A striped EQR electrode 10 is arranged on the outer periphery of the chip so as to surround the source electrode 11 while being separated from the source electrode 11 by a predetermined distance.

  However, the MOSFET as described above has the following problems. This will be described with reference to FIG. 6A is a cross-sectional view of the chip, and FIG. 6B is a plan view of the chip. In FIG. 6, 15 is a movable ion, and 16 is a depletion layer.

  In general, the surface of a semiconductor device is covered with a sealing material in order to prevent damage and corrosion. As the sealing material, various resins such as epoxy resin, silicon gel, and the like are used. These sealing materials contain movable charges such as impurity ions. These movable charges move in the sealing material in accordance with the bias state with respect to the semiconductor device. As described above, when the movable charge in the encapsulant moves, the charge distribution changes, so that the behavior of the charge in each semiconductor region is affected and the characteristics of the semiconductor device are also changed.

  Specifically, as shown in FIGS. 6A and 6B, the surface of the interlayer insulating film 8 exposed between the EQR electrode 10 and the source electrode 11 has movable ions 15 (external movable charges) entering from the outside. ) Was scattered.

  Unlike the fixed charges in the oxide film that do not move, the movable ions 15 move relatively easily on the surface of the interlayer insulating film 8.

  The movable ions 15 are unevenly distributed at the indefinite position on the surface of the interlayer insulating film 8, and as a result, the end position of the depletion layer 16 fluctuates as indicated by a broken line in FIG. FIG. 6A illustrates three end positions using broken lines. This variation in the termination position of the depletion layer 16 causes the breakdown voltage characteristics of the MOSFET to vary. Here, the breakdown voltage characteristics of the MOSFET mean the reverse bias breakdown voltage characteristics between the source and the drain when a reverse bias is applied.

  In particular, when the protective film (polyimide film) on the chip surface is omitted for cost reduction or the like, contamination due to mobile ions contained in the exterior epoxy resin becomes more prominent, and the withstand voltage characteristics of the MOSFET are further increased between products. The result was inconsistent.

  In order to solve the above problems, according to a first aspect of the present invention, a semiconductor device configured as follows is provided. That is, the semiconductor device includes an active region in which a vertical MOSFET having a source electrode on the surface of a semiconductor substrate is formed, a channel stop region having an EQR electrode formed on the surface of the semiconductor substrate at a distance from the source electrode, And at least one of the source electrode and the EQR electrode is formed such that an inter-electrode distance between the source electrode and the EQR electrode is partially smaller than the other portions.

  According to the present invention, since the lines of electric force formed between the electrodes are partially dense, the external movable charge existing between the electrodes is one of the source electrode and the EQR electrode. Will be strongly attracted to. That is, since the external movable charge existing between the electrodes is removed, the termination position of the depletion layer formed in the semiconductor substrate is stabilized when a reverse bias is applied, and as a result, the reverse bias withstand voltage characteristic of the MOSFET is stable. Will do. And since the reverse bias withstand voltage characteristic of MOSFET is stabilized, the variation in the lifetime between semiconductor devices is suppressed.

Chip plan view and cross-sectional view of a semiconductor device according to an embodiment of the present invention Illustration of density distribution of electric field lines Sectional drawing of the semiconductor device which concerns on the 1st and 2nd modification Partially enlarged perspective view of a semiconductor device according to a third modification Sectional view and chip plan view of end portion of semiconductor device of Patent Document 1 FIG. 6 is a diagram similar to FIG.

  An embodiment of the semiconductor device 100 of the present invention will be described with reference to FIG.

  The semiconductor device 100 is an N-channel vertical MOSFET having an EQR structure.

  FIG. 1A is a plan view of a chip (semiconductor device). FIG. 1B is a cross-sectional view of the outer periphery of the chip of FIG. The same parts as those in FIG. 5 and FIG. In FIG. 1, 101 is an EQR electrode, 101a is a straight pattern portion of the EQR electrode (lower portion of the EQR electrode, first layer), 101b is an uneven pattern portion of the EQR electrode (upper portion of the EQR electrode, uneven pattern, 2 layers). The drain electrode on the back surface of the chip is omitted.

  The difference from the MOSFET of Patent Document 1 described above is that the pattern of the EQR electrode is different.

  The EQR electrode 101 of the present embodiment is a combination of a straight pattern portion 101a that is a lower portion of the EQR electrode and a concavo-convex pattern portion 101b that is an upper portion (surface side portion) of the EQR electrode. In other words, the concavo-convex pattern portion 101b is provided on the straight pattern portion 101a.

  In other words, the EQR electrode 101 is such that the inter-electrode distance d between the source electrode 11 and the EQR electrode 101 (see also FIG. 1B and FIG. 2) is smaller in part than in other parts. It is formed. Further, as shown in the perspective view of FIG. 1A, the EQR electrode 101 includes a straight pattern portion 101a as a first layer that maintains the inter-electrode distance d constant, a semiconductor substrate surface e, and a straight pattern portion. And an uneven pattern portion 101b as a second layer which is formed on the opposite side across 101a and which makes the inter-electrode distance d partially smaller than the other portions. Here, the semiconductor substrate surface e means the surface of the semiconductor substrate 200 composed of the N + type silicon substrate 1 and the N− type epitaxial layer 2. Similar to Patent Document 1, a source electrode 11 and an EQR electrode 101 are formed on the surface e of the semiconductor substrate. The EQR electrode 101 is formed with a distance d (distance) between the source electrode 11 and the electrode. Further, the EQR electrode 101 is provided with a concavo-convex pattern portion 101b (a concavo-convex pattern) that makes the inter-electrode distance d partially smaller than the other portions. As shown in the perspective view of FIG. 1A, the uneven pattern portion 101b is formed so as to include a triangular planar shape that gradually narrows between the electrodes.

  By providing the concavo-convex pattern portion 101b, as shown in FIG. 2, the electric force lines 105 shown by broken lines are densely gathered at the edge portion 300a of the convex pattern 300, and the electric field strength is increased in the vicinity thereof. This makes it easier to remove the movable ions 15 than when the lines of electric force 105 are evenly distributed.

  The straight pattern portion 101a is provided across the entire outer periphery of the chip in parallel with the source electrode 11 while being electrically connected to the N + type EQR diffusion region 9.

  The straight pattern portion 101a serves to stabilize the entire EQR diffusion region 9 at the same potential.

  As shown in FIG. 2, the concavo-convex pattern portion 101b is provided with a convex pattern 300 in a plan view at a constant pitch, for example, a triangular shape.

  When the uneven pattern portion 101b is provided on the EQR electrode 101 in this way, electric lines of force are concentrated on the edge portion 300a of the convex pattern 300 as shown in FIG. FIG. 2 shows electric lines of force when the source electrode side is at a high potential and the EQR electrode side is at a low potential. In the opposite case, the same effect can be obtained simply by reversing the direction of the arrow of the electric lines of force.

  A strong electric field strength is obtained in the vicinity of the convex pattern 300, and the mobile ions 15 can be easily removed.

  The movable ions 15 having a negative charge are moved away from the EQR electrode 101 and attracted to the source electrode 11 to be removed.

  On the contrary, the movable ions 15 having a positive charge are attracted to the EQR electrode 101 side and absorbed and removed.

  As described above, by providing the EQR electrode 101 with the concavo-convex pattern portion 101b where electric lines of force are concentrated, the distribution of the electric lines of force 105 is made strong (dense / dense), and mobile ions are generated at a portion where the electric field strength is strong (dense portion). 15 is effectively removed. Note that the movable ions 15 having a charge different from that of the EQR electrode 101 are attracted to the EQR electrode 101 and absorbed and removed. On the other hand, the movable ions 15 having the same sign as the EQR electrode 101 are moved away from the EQR electrode 101 and absorbed and removed by the source electrode 11. By effectively removing the movable ions 15 in this manner, the variation in the termination position of the depletion layer 16 (see also FIG. 6A) is eliminated, and as a result, the breakdown voltage is stabilized.

  In this way, the movable ions 15 existing in the dense region of the electric lines of force 105 are attracted to the one electrode 11 and 101 and removed. The movable ions 15 existing in the sparse region of the electric lines of force 105 are first moved to the dense region of the electric lines of force 105 by the action of electromagnetic force, and then one of the electrodes 11 and 101 (electrodes having a different sign from the ions). ) To be removed.

  In this way, the movable ions 15 on the surface of the interlayer insulating film 8 are removed, the termination position of the depletion layer 16 (see also FIG. 6A) is not changed, and the breakdown voltage of the MOSFET is stabilized.

  The resistance component of the EQR electrode 101 is slightly increased by the provision of the concave / convex pattern portion 101b, but there is no problem by adjusting the arrangement pitch and thickness of the convex pattern 300.

  Next, a method for manufacturing the semiconductor device 100 will be described.

  Only differences from the method of manufacturing the semiconductor device 100 described in Patent Document 1 will be described.

  First, after a predetermined metal is attached to the entire surface of the chip, the electrodes 101, 11, GP, and GF are simultaneously formed using a photolithography method and etching. The resist mask pattern of the EQR electrode 101 used at this time is the mask pattern of the straight pattern portion 101b.

  Thereafter, the concavo-convex pattern portion 101b of the EQR electrode 101 is formed by photolithography and etching. The resist mask pattern used at this time is a mask pattern in which only the concavo-convex pattern portion 101b is opened.

(Summary)
(1) As described above, in the present embodiment, the semiconductor device 100 is configured as follows. That is, the semiconductor device 100 is formed on the semiconductor substrate surface e with the FET cell region 21 (active region) where the vertical MOSFET having the source electrode 11 is formed, and on the semiconductor substrate surface e with a distance from the source electrode 11. A channel stopper region 22 (channel stop region) having an EQR electrode 101. The EQR electrode 101 is formed so that the inter-electrode distance d between the source electrode 11 and the EQR electrode 101 is partially smaller than the other portions. According to the above configuration, since the electric lines of force 105 formed between the electrodes are partially dense, the movable ions 15 (external movable charges) existing between the electrodes are separated from the source electrode 11 and the EQR. It is strongly attracted to either one of the electrodes 101. That is, since the movable ions 15 existing between the electrodes are removed, the termination position of the depletion layer 16 formed in the semiconductor substrate 200 is stabilized when a reverse bias is applied. As a result, the reverse bias withstand voltage characteristic of the MOSFET is improved. It will be stable. Since the reverse bias withstand voltage characteristics of the MOSFET are stabilized, variations in lifetime between the semiconductor devices 100 can be suppressed.

  In the above embodiment, the EQR electrode 101 is formed such that the inter-electrode distance d between the source electrode 11 and the EQR electrode 101 is partially smaller than the other portions. The source electrode 11 may be formed such that the inter-electrode distance d between the source electrode 11 and the EQR electrode 101 is partly smaller than the other part. In short, if the inter-electrode distance d is partly smaller than the other parts, the shape of both the source electrode 11 and the EQR electrode 101 is changed regardless of the shape of the source electrode 11 or the EQR electrode 101. You can choose to change the

(2) In the above embodiment, the EQR electrode 101 is opposite to the straight pattern portion 101a (first layer) that maintains the inter-electrode distance d constant, and the semiconductor substrate surface e and the straight pattern portion 101a. And a concavo-convex pattern portion 101b (second layer) which is formed on the side and which makes the inter-electrode distance d partly smaller than the other portions. According to the above configuration, the function of partially concentrating the electric lines of force 105 formed between the electrodes and the function as a channel stop provided in the channel stopper region 22 can be achieved without problems.

  In the above embodiment, the EQR electrode 101 is configured to include the straight pattern portion 101a and the concavo-convex pattern portion 101b. Instead, the source electrode 11 includes a pattern corresponding to the straight pattern portion 101a, and A pattern corresponding to the concavo-convex pattern portion 101b may be included.

(3) Moreover, in the said embodiment, the uneven | corrugated pattern part 101b (uneven | corrugated pattern) which makes the said electrode distance d partially smaller than another part in the EQR electrode 101 is formed. According to the above configuration, the electric lines of force 105 formed between the electrodes can be partially concentrated with a simple configuration.

  Of course, a concavo-convex pattern corresponding to the concavo-convex pattern portion 101b may be formed on the source electrode 11.

(4) Moreover, in the said embodiment, the uneven | corrugated pattern part 101b is formed including the triangular planar shape which narrows gradually toward the said electrode.

  Although a preferred embodiment of the present invention has been described above, the above embodiment can be implemented with the following modifications.

(First modification)
As the configuration of the channel stopper region 22, instead of adopting the EQR structure illustrated in FIG. 1B, for example, as shown in FIG. 3A, an N + type EQR diffusion region 9 has a P-type base. An EQR structure including a polysilicon electrode 17 disposed inside the region 14 and connected to the EQR electrode 101 may be employed.

(Second modification)
Further, as shown in FIG. 3B, the above-mentioned electric lines of force are also concentrated in the semiconductor device 100 having a structure including a plurality of guard rings GR for relaxing the electric field concentration in order to obtain a high breakdown voltage characteristic (for example, 600 V). Thus, a technique for removing the movable ions 15 can be applied.

(Third Modification)
Further, as shown in FIG. 4, the concave / convex pattern portion 101 b may be formed to include a square planar shape extending between the electrodes. Also in this case, the EQR electrode 101 includes a convex pattern 301, and the convex pattern 301 has an edge portion 301a for partially concentrating the lines of electric force 105. Furthermore, as long as the electric lines of force 105 formed between the source electrode 11 and the EQR electrode 101 are partially concentrated, the shape is not limited to the shape illustrated in FIG. The shape can be adopted.

  The surface of such a high breakdown voltage semiconductor device 100 is usually covered with a polyimide film (not shown) as a protective film, but this protective film is omitted for the purpose of cost reduction. Since the mobile ions 15 can easily enter from the exterior epoxy resin, the above-described effect of removing the mobile ions 15 is particularly expected.

(Appendix 1)
The semiconductor device includes a semiconductor layer in which a cell region composed of a plurality of FET cells is formed, an annular diffusion region as a channel stopper disposed so as to surround the cell region in the semiconductor layer, and an annular diffusion on the annular diffusion region. It is good also as providing the EQR (equipotential ring) electrode superimposed and electrically connected with the area | region, and providing the uneven | corrugated pattern part 101b (the electric lines of force are concentrated) in the pattern of the EQR electrode 101.

(Appendix 2)
The uneven pattern portion 101 b may be provided on the surface layer of the EQR electrode 101.

(Appendix 3)
The uneven pattern portion 101b may be a pattern having a triangular shape.

(Appendix 4)
The uneven pattern portion 101b may be a pattern having a rectangular shape.

11 Source electrode 21 FET cell region 22 Channel stopper region 101 EQR electrode 101a Straight pattern portion 101b Uneven pattern portion 100 Semiconductor device 200 Semiconductor substrate

Claims (5)

An active region in which a vertical MOSFET having a source electrode is formed on the surface of a semiconductor substrate;
A channel stop region having an EQR electrode formed on the surface of the semiconductor substrate at a distance from the source electrode;
With
At least one of the source electrode and the EQR electrode is formed such that an interelectrode distance between the source electrode and the EQR electrode is partially smaller than the other portions.
Semiconductor device. The semiconductor device according to claim 1,
At least one of the source electrode and the EQR electrode is
A first layer for maintaining a constant distance between the electrodes;
A second layer formed on the opposite side across the surface of the semiconductor substrate and the first layer, wherein the distance between the electrodes is partly smaller than the other part;
Composed of,
Semiconductor device. The semiconductor device according to claim 1 or 2,
At least one of the source electrode and the EQR electrode is formed with a concavo-convex pattern that makes the inter-electrode distance between the source electrode and the EQR electrode partially smaller than the other portions.
Semiconductor device. The semiconductor device according to claim 3,
The concavo-convex pattern is formed to include a triangular planar shape that gradually narrows between the electrodes.
Semiconductor device. The semiconductor device according to claim 3 or 4, wherein
The concavo-convex pattern is formed to include a rectangular planar shape extending between the electrodes.
Semiconductor device.

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