JP2011123184A - Display device, method for producing display device, and method for driving display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which reduces the number of data lines and in which relative luminance difference among display elements of the same kind is hard to occur among display element groups. <P>SOLUTION: The display element group includes a first display element, a second display element, and a third display element, and each includes a driving circuit and a current driving-type light emission part. One source/drain region of writing transistors of the first display element and the second display element is connected to a first data line, and one source/drain region of a writing transistor of the third display element is connected to a second data line. A gate electrode of the writing transistor of the first display element is connected to a first scanning line, the gate electrode of the writing transistor of the second display element is connected to a second scanning line, and the gate electrode of the writing transistor of the third display element is connected to either the first scanning line or the second scanning line. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device, a display device manufacturing method, and a display device driving method. More specifically, the present invention relates to a display device including a display element having a drive circuit and a current-driven light emitting unit, a method for manufacturing the display device, and a method for driving the display device.

  A display element having a current-driven light emitting unit and a display device including the display element are well known. For example, a display element provided with an organic electroluminescence light emitting unit using electroluminescence of an organic material has been attracting attention as a display element capable of emitting light with high luminance by low voltage direct current drive.

  Similar to the liquid crystal display device, a simple matrix method and an active matrix method are well known as a driving method in a display device including a display element having a current-driven light-emitting portion. The active matrix method has a disadvantage that the structure is complicated, but has an advantage that the luminance of the image can be increased. A display element that is driven by an active matrix system and has a current-driven light emitting unit includes a drive circuit for driving the light emitting unit in addition to the light emitting unit.

  3B of Japanese Patent Application Laid-Open No. 2007-310311 (Patent Document 1) includes a light emitting element (light emitting unit) 3D, a sampling transistor (writing transistor) 3A, a driving transistor (driving transistor) 3B, and a storage capacitor ( A pixel circuit (display element) 101 including a capacitor portion 3C is disclosed, and a display device including the pixel circuit 101 is disclosed in FIG. 3A. The display device includes a scanning line WSL arranged for each row of pixel circuits 101 and a signal line (data line) DTL arranged for each column of pixel circuits 101. A control signal (scanning signal) is supplied from the main scanner (scanning circuit) 104 to the scanning line WSL, and a video signal and various reference voltages are supplied from the signal selector (signal output circuit) 103 to the signal line DTL. .

JP 2007-310311 A

  In the display device shown in FIG. 3A of Patent Document 1, a data line is provided for each column of display elements, and a scanning line is provided for each row of display elements. A scanning signal for controlling the conduction state and non-conduction state of the writing transistor is supplied to the scanning line. The scanning circuit that supplies the scanning signal can be constituted by a relatively simple circuit such as a shift register. On the other hand, a video signal for controlling the luminance gradation of the display element, various reference voltages, and the like are supplied to the data line. Therefore, the signal output circuit for supplying a signal to the data line is composed of a D / A converter, an amplifier, and the like, and has a larger circuit scale and higher cost than the scanning circuit. As the number of data lines in the display device increases, the circuit scale of the signal output circuit increases and the cost also increases.

  If the data lines are shared by a plurality of columns of display elements, the number of data lines can be reduced, and as a result, the circuit scale of the signal output circuit can be reduced. Therefore, a display device having a configuration in which data lines are shared between two adjacent display elements and the number of data lines is halved can be considered. In the display device having this configuration, the conduction state and the non-conduction state of the writing transistor in the row composed of the display elements cannot be uniformly controlled, and two scanning lines are required for each row composed of the display elements. Become. Although the number of scanning lines is doubled and the scale of the scanning circuit is increased, it is disadvantageous, but overall, the cost of the signal output circuit can be reduced by reducing the number of data lines. The benefits are great.

FIG. 16 shows a schematic circuit diagram in the case where the data lines are shared in two adjacent display elements. Each display element constitutes a so-called sub-pixel, and one pixel is constituted by a display element group DG composed of three display elements. One pixel is arranged in the direction in which the first scanning line SCL1 and the second scanning line SCL2 extend, the first display element (red light emitting subpixel), the second display element (green light emitting subpixel), and the third display element. It is composed of three display elements (blue light emitting subpixels). Three data lines DTL _A , DTL _B and DTL _C are arranged for every two pixels.

In the left display element group DG ₁ shown in FIG. 16, one source / drain region of the write transistor TR _W of the first display element and the second display element is connected to the data line DTL _A , and One source / drain region of the write transistor TR _W of the display element and the first display element of the adjacent display element group DG ₂ is connected to the data line DTL _B. In the display element group DG _2, one source / drain regions of the write transistor TR _W of the second display device and the third display element is connected to the data line DTL _C. The gate electrode of the write transistor TR _W in six display elements constituting the two pixels, to the first scan line SCL1 second scan line SCL2, are connected alternately. In the configuration in which the data lines are shared by two columns of adjacent display elements, the connection pattern described above is repeated for each of the two display element groups. Note that the symbol PS2 is a common feeder line for all the display elements.

Here, in the configuration in which the data lines are shared by two adjacent display elements and the number of data lines is halved, the driving transistor TR _D is directed from one source / drain region to the other source / drain region. It will be described that the direction is not constant in the same kind of display element. FIG. 17 is a diagram corresponding to FIG. 16, and is a schematic plan view of a layout of a drive circuit including a write transistor TR _W and a drive transistor TR _D constituting a display element. In FIG. 17, the light-emitting portion ELP is not shown, and in order to clarify the configuration of various wirings, electrodes, etc., the portion made of the first metal layer is hatched, and the second portion The portion composed of the metal layer is roughly shaded. The portion of the semiconductor layer constituting the channel formation region and the source / drain region of the transistor is indicated by a broken line.

Here, the power supply line PS1 side of the driving transistor TR _D is simply referred to as a drain region, and the other is simply referred to as a source region. In FIG. 17, the drain region and the source region are represented by a symbol D and a symbol S, respectively. Direction from the drain region of the driving transistor TR _D in the first display element in the source region, in the display element group DG ₁ is -X direction in the + X direction, the display element group DG _2. The direction from the drain region to the source region of the driving transistor TR _D in the second display element is the −X direction in the display element group DG ₁ and the + X direction in the display element group DG ₂ . Direction from the drain region of the driving transistor TR _D in the third display element to the source region, in the display element group DG ₁ is -X direction in the + X direction, the display element group DG _2.

A difference in the direction from one source / drain region to the other source / drain region of the driving transistor TR _D constituting the display element may cause a difference in characteristics of the driving circuit. For example, in the annealing process in the manufacturing process of the display device, the pattern of temperature rise and temperature drop in the drive transistor TR _D varies depending on the difference in direction from one source / drain region to the other source / drain region. In the layout of the drive circuit as shown in FIG. 17, the inventors have a relative luminance difference between the display elements of the same type in the display element groups, and the bright and dark lines extending in the Y direction shown in FIG. The phenomenon of being visually recognized is confirmed.

  Accordingly, an object of the present invention is to reduce the number of data lines and to make it difficult for relative luminance differences to occur between display elements of the same type among display element groups, and a method for manufacturing such a display apparatus, Another object is to provide a method for driving such a display device.

To achieve the above object, the display device of the present invention, the display device manufactured by the method of manufacturing the display device of the present invention, and the display device used for the method of driving the display device of the present invention,
N pieces in a first direction, M pieces in a second direction different from the first direction, and a total of N × M pieces, which are arranged in a two-dimensional matrix, are respectively a first display element and a second display element. And a display element group including a third display element,
A first scan line and a second scan line provided for each column of N display element groups arranged along the first direction and extending in the first direction; and
A first data line and a second data line provided in each column of M display element groups arranged along the second direction and extending in the second direction;
Each of the first display element, the second display element, and the third display element includes a drive circuit and a current-driven light emitting unit.
The driving circuit includes a gate electrode, a channel formation region, a write transistor having one source / drain region and the other source / drain region, and a gate electrode connected to the other source / drain region of the write transistor, a channel formation region A drive transistor having one source / drain region and the other source / drain region,
The light emitting part is electrically connected to the other source / drain region of the driving transistor,
In the display element group, the first display element, the second display element, and the third display element are arranged along the first direction, and one of the write transistors of the first display element and the second display element. The source / drain region is connected to the first data line, one source / drain region of the write transistor of the third display element is connected to the second data line, and the gate electrode of the write transistor of the first display element Is connected to the first scan line, the gate electrode of the write transistor of the second display element is connected to the second scan line, and the gate electrode of the write transistor of the third display element is connected to the first scan line and the second scan line. Connected to one of the scan lines,
The direction from one source / drain region of the drive transistor constituting the first display element toward the other source / drain region is constant in the display element group,
The direction from one source / drain region of the driving transistor constituting the second display element to the other source / drain region is constant in the display element group,
In the display device, the direction from one source / drain region of the driving transistor constituting the third display element toward the other source / drain region is constant among the display element groups.

  In the display device manufacturing method of the present invention, a driving transistor and a writing transistor each including a thin film transistor are provided, and then scanning with a laser beam is performed so that a channel forming region, one source / drain region, and the other source of the driving transistor are scanned. And a semiconductor layer constituting the / drain region, a channel formation region of the writing transistor, one source / drain region, and a semiconductor layer constituting the other source / drain region are annealed.

And the drive method of the display apparatus of this invention for achieving said objective is as follows.
A first scanning signal and a second scanning signal whose periods do not overlap each other are applied to the first scanning line and the second scanning line, respectively, so that the first display element is based on the first scanning signal. The writing transistor is turned on, the first video signal is applied from the first data line to the gate electrode of the driving transistor, and in the second display element, the writing transistor is turned on based on the second scanning signal. A second video signal is applied from one data line to the gate electrode of the driving transistor. In the third display element, when the gate electrode of the driving transistor is connected to the first scanning line, the first scanning signal is output. Accordingly, when the gate electrode of the driving transistor is connected to the second scanning line, the writing transistor is turned on based on the second scanning signal, and the third video signal is driven from the second data line. A driving method for a display device that performs a writing process to be applied to the gate electrode of the transistor.

  In the display device of the present invention, the display element group includes the first display element, the second display element, and the third display element, and 2 for every M display element groups arranged along the second direction. A data line of books is arranged. Therefore, the number of data lines can be reduced by a third compared to the conventional configuration in which data lines are arranged for each column of display elements. Further, the direction from one source / drain region of the drive transistor to the other source / drain region of the display transistor of the same type is constant in the display element groups. Therefore, a difference in the direction from one source / drain region to the other source / drain region of the driving transistor does not cause a relative luminance difference between display elements of the same type in the display element groups. According to the method for manufacturing a display device of the present invention, the direction from one source / drain region of the drive transistor to the other source / drain region of the drive transistor in the same kind of display element is constant between the display element groups. In the display element, annealing is performed under the same conditions. Further, according to the driving method of the display device of the present invention, the writing process can be performed without any trouble even if the data lines are shared.

FIG. 1 is a conceptual diagram of a display device according to the first embodiment. FIG. 2 is an equivalent circuit diagram of the display element group. FIG. 3 is a diagram corresponding to FIG. 2, and is a schematic plan view of a layout of a drive circuit including a write transistor and a drive transistor constituting the display element. FIG. 4 is a schematic partial cross-sectional view of the display device taken along the line AA in FIG. FIG. 5 is a schematic plan view for explaining the arrangement of various components in the region corresponding to the display element group. FIG. 6 is a schematic plan view for explaining the arrangement of various components in the region corresponding to the display element group, following FIG. 5. FIG. 7 is a schematic plan view for explaining the arrangement of various components in the region corresponding to the display element group, following FIG. 6. 8A to 8D are schematic plan views for explaining modifications of the arrangement of the first display element, the second display element, and the third display element that constitute the display element group. is there. FIGS. 9A to 9D illustrate modifications of the arrangement of the first display element, the second display element, and the third display element that constitute the display element group, following FIG. 8D. It is a typical top view for this. FIG. 10 is a schematic circuit diagram of the first display element, the second display element, and the third display element that constitute the display pixel group in the m-th row and the n-th column. FIG. 11 is a schematic diagram of various timings in the driving method of the display device according to the first embodiment. FIG. 12 is a schematic diagram of a timing chart for explaining the operation of the third display element in the display pixel group in the m-th row and the n-th column. FIGS. 13A to 13F are diagrams schematically showing the conductive state / non-conductive state of each transistor constituting the driving circuit of the third display element. FIGS. 14A to 14F are diagrams schematically showing a conduction state / non-conduction state of each transistor included in the driving circuit of the third display element, following FIG. 13F. FIG. 15 is an equivalent circuit diagram of a display element including a drive circuit. FIG. 16 is a schematic circuit diagram in the case where data lines are shared in two adjacent display elements. FIG. 17 is a diagram corresponding to FIG. 16, and is a schematic plan view of a layout of a drive circuit including a write transistor and a drive transistor constituting the display element.

Hereinafter, the present invention will be described based on examples with reference to the drawings. However, the present invention is not limited to the examples, and various numerical values and materials in the examples are examples. The description will be given in the following order.
1. 1. General description of the display device of the present invention, the method of manufacturing the display device of the present invention, and the driving method of the display device of the present invention Example 1

[Description of the Display Device of the Present Invention, the Method of Manufacturing the Display Device of the Present Invention, and the Driving Method of the Display Device of the Present Invention]
The display device of the present invention, the display device manufactured by the method of manufacturing the display device of the present invention, and the display device used in the driving method of the display device of the present invention (hereinafter collectively referred to simply as the present invention) In some cases, the first display element, the second display element, and the third display element constituting the display element group are respectively a red light emission sub-pixel and a green light emission sub-pixel. A color display configuration corresponding to the pixel and the blue light emitting subpixel can be employed. The correspondence relationship between each display element and the light emission color is not limited to this, and can be set as appropriate according to the design of the display device. The combination of the emission colors of the first display element and the second display element is not limited to the above example.

  In the display device of the present invention, the method of manufacturing the display device of the present invention, and the method of driving the display device of the present invention (hereinafter, these may be collectively referred to simply as the present invention), “A direction from one source / drain region to the other source / drain region of a driving transistor constituting one display element” is a direction as a vector. Similarly, “from one source / drain region of the driving transistor constituting the second display element to the other source / drain region” and “from one source / drain region of the driving transistor constituting the third display element” The direction toward the other source / drain region is also a direction as a vector.

  In the display device or the like of the present invention, one source / drain region of the writing transistor of the first display element and the second display element is connected to the first data line, and one source / drain of the writing transistor of the third display element. The region is connected to the second data line. In the display element group, the direction from one source / drain region of the driving transistor constituting the first display element to the other source / drain region and one source / drain of the driving transistor constituting the second display element. The direction from the drain region to the other source / drain region may be different.

  In the display device or the like of the present invention having the preferred configuration described above, in the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the first display element, and the second display element One source / drain region and the other source / drain region of the drive transistor constituting the transistor may be arranged point-symmetrically. The display device having this configuration may be referred to as the display device of the first aspect. In this case, in the display element group, the driving circuit of the first display element and the driving circuit of the second display element can be arranged symmetrically.

  Alternatively, in the display device or the like of the present invention having the preferred configuration described above, in the display element group, one source / drain region and the other source / drain region of the drive transistor constituting the first display element, One source / drain region and the other source / drain region of the driving transistor constituting the two-display element can be arranged in line symmetry. The display device having this configuration may be referred to as a display device according to the second aspect. In this case, the display element group may have a configuration in which the drive circuit of the first display element and the drive circuit of the second display element are arranged in line symmetry.

  In the display device and the like of the present invention including the various preferable configurations described above, the gate electrode of the write transistor of the third display element can be connected to the second scan line, or alternatively The gate electrode of the writing transistor of the third display element can be connected to the first scanning line.

  In the display device according to the first aspect, the configuration in which the gate electrode of the write transistor of the third display element is connected to the second scanning line is referred to as the display device according to the first aspect, and the write transistor of the third display element A configuration in which the gate electrode is connected to the first scanning line may be referred to as a display device according to the 1B mode. In the display device of the second aspect, the configuration in which the gate electrode of the writing transistor of the third display element is connected to the second scanning line is referred to as the display device of the second A aspect, and the writing of the third display element is performed. A structure in which the gate electrode of the transistor is connected to the first scan line may be referred to as a display device of the mode 2B.

  In the configuration in which the gate electrode of the writing transistor of the third display element is connected to the second scanning line, in the display element group, one source / drain region of the driving transistor constituting the third display element and the other The source / drain region and one source / drain region and the other source / drain region of the driving transistor constituting the second display element may be arranged in translational symmetry. In this case, the display element group may have a configuration in which the drive circuit for the third display element and the drive circuit for the second display element are arranged in translational symmetry.

  Alternatively, in the configuration in which the gate electrode of the writing transistor of the third display element is connected to the second scanning line, in the display element group, one source / drain region of the driving transistor constituting the third display element The other source / drain region and the one source / drain region and the other source / drain region of the driving transistor constituting the second display element may be arranged in line symmetry. In this case, the display element group may have a configuration in which the drive circuit for the third display element and the drive circuit for the second display element are arranged in line symmetry.

  In the configuration in which the gate electrode of the writing transistor of the third display element is connected to the first scanning line, in the display element group, one source / drain region of the driving transistor constituting the third display element and the other The source / drain region and one source / drain region and the other source / drain region of the driving transistor constituting the first display element may be arranged in translational symmetry. In this case, the display element group may have a configuration in which the drive circuit for the third display element and the drive circuit for the first display element are arranged in translational symmetry.

  Alternatively, in the configuration in which the gate electrode of the writing transistor of the third display element is connected to the first scanning line, in the display element group, one source / drain region of the driving transistor constituting the third display element The other source / drain region and the one source / drain region and the other source / drain region of the driving transistor constituting the first display element may be arranged in line symmetry. In this case, the display element group may have a configuration in which the drive circuit of the third display element and the drive circuit of the first display element are arranged in line symmetry.

  In the display device and the like of the present invention including the various preferable configurations described above, the display device is provided for each column of N display element groups arranged along the first direction, and the first direction. In the display element group, one source / drain region of the drive transistor of the first display element, the second display element, and the third display element is connected to the power supply line. It can be configured.

  In the manufacturing method of the display device of the present invention including the various preferable configurations described above, for example, annealing may be performed by irradiating a spot-like or rectangular laser beam while scanning in one direction. it can. As the laser light source, a known laser light source such as a gas laser, a solid-state laser, or a semiconductor laser can be used. The laser light source may be pulsed oscillation or continuous oscillation. The wavelength of the laser light may be appropriately selected according to the design of the display device. The scanning direction of the laser beam is not particularly limited. For example, it may be the first direction or the second direction. Furthermore, it may be configured to scan in another direction different from the first direction and the second direction.

  In the display device and the like of the present invention including the various preferable configurations described above, the drive transistor and the write transistor constituting the drive circuit can be configured by thin film transistors (TFTs). For example, the driving transistor and the writing transistor can be formed of n-channel thin film transistors. Note that the drive transistor and the write transistor may have the same conductivity type or different conductivity types. For example, the driving transistor may be an n-channel thin film transistor, and the writing transistor may be a p-channel thin film transistor. The thin film transistor may be a bottom gate type (reverse stagger type) or a top gate type (forward stagger type). The driving transistor and the writing transistor may be an enhancement type or a depletion type. The structure of the thin film transistor is not particularly limited.

  The semiconductor layer (semiconductor thin film) constituting the source / drain region and the channel formation region of the thin film transistor can be made of a known semiconductor material such as amorphous silicon or polysilicon. The semiconductor layer can be formed by a known method such as a physical vapor deposition method (PVD method) exemplified by a vacuum evaporation method or a sputtering method, or various chemical vapor deposition methods (CVD methods). A semiconductor layer made of amorphous silicon or polysilicon can be formed on a support by, for example, a plasma CVD method (PECVD method) or the like.

  In an n-channel thin film transistor, an LDD structure (Lightly Doped Drain structure) may be formed. The LDD structure may be formed asymmetrically. For example, a large current flows through the driving transistor when the display element emits light. Therefore, when the driving transistor is composed of an n-channel thin film transistor, an LDD structure can be formed only on one source / drain region side that becomes the drain region side when the light emitting portion emits light.

  In the display device driving method of the present invention, the first scanning signal and the second scanning signal whose periods do not overlap each other are applied to the first scanning line and the second scanning line, respectively. The order of applying the first scanning signal and the second scanning signal is not particularly limited. The configuration may be such that the second scan signal is applied after the first scan signal is applied, or the first scan signal is applied after the second scan signal is applied.

In the display device driving method of the present invention including the various preferable configurations described above, the display device is provided for each column of N display element groups arranged along the first direction. A feed line extending in the direction of 1;
In the display element group, one source / drain region of the drive transistor of the first display element, the second display element, and the third display element is connected to the power supply line,
Prior to the first scanning signal and the second scanning signal, the third scanning signal is applied to the first scanning line and the second scanning line, and the writing transistors of the first display element, the second display element, and the third display element are made conductive. As a state, in the first display element and the second display element, a reference voltage is applied from the first data line to the gate electrode of the driving transistor, and in the third display element, the reference voltage is applied from the second data line. Is applied to the gate electrode of the driving transistor, and a predetermined driving voltage is applied from the feeder line to one of the source / drain regions of the driving transistors of the first display element, the second display element, and the third display element. A threshold voltage capacitor that changes the potential of the other source / drain region of the driving transistor of the one display element, the second display element, and the third display element toward a potential obtained by subtracting the threshold voltage of the driving transistor from the reference voltage. It may be configured to perform the cell processing.

  In this case, in the driving method of the display device of the present invention, the driving voltage is applied to one source / drain region of the driving transistor of the first display element, the second display element, and the third display element. Thus, the writing process can be performed to change the potential of the other source / drain region of the driving transistor of the first display element, the second display element, and the third display element.

In the display device and the like of the present invention including the various preferable configurations described above, the drive circuit is connected to one electrode connected to the other source / drain region of the drive transistor and to the gate electrode of the drive transistor. It is possible to adopt a configuration further including a capacitor having the other electrode. And in the driving method of the display device of the present invention including the various preferred configurations described above,
In the first display element, a voltage corresponding to the first video signal is held in the capacitor unit by the writing process, and application of the first video signal to the gate electrode of the driving transistor is stopped, thereby A current corresponding to the value of the held voltage flows to the light emitting part through the driving transistor, and the light emitting part emits light,
In the second display element, a voltage corresponding to the second video signal is held in the capacitor unit by the writing process, and application of the second video signal to the gate electrode of the driving transistor is stopped, thereby A current corresponding to the value of the held voltage flows to the light emitting part through the driving transistor, and the light emitting part emits light,
In the third display element, a voltage corresponding to the third video signal is held in the capacitor unit by the writing process, and application of the third video signal to the gate electrode of the driving transistor is stopped, thereby A current in accordance with the value of the held voltage can flow through the driving transistor to the light emitting unit so that the light emitting unit emits light.

  In the present invention, “point symmetry” includes not only strictly point symmetry but also substantially point symmetry, and “line symmetry” means not only strictly line symmetry but substantially Includes the case of line symmetry. The “translational symmetry” includes not only strictly translational symmetry but also substantially translational symmetry. For example, it is conceivable that the sizes of the drive transistors and the like in the first display element, the second display element, and the third display element are different in design due to the difference in the light emission efficiency of the light emitting unit. Is acceptable. In addition, the presence of various variations caused in the design or manufacture of display elements and display devices is allowed.

  The conditions shown in the various expressions in this specification are satisfied not only when the expression is strictly mathematically established but also when the expression is substantially satisfied. Regarding the establishment of the expression, the existence of various variations that occur in the design or manufacture of the display element or the display device is allowed.

  In the driving method of the display device of the present invention, when the potential of the other source / drain region of the driving transistor reaches the potential obtained by subtracting the threshold voltage of the driving transistor from the reference voltage by the threshold voltage canceling process, the driving transistor It becomes a non-conductive state. On the other hand, when the potential of the other source / drain region of the driving transistor does not reach the potential obtained by subtracting the threshold voltage of the driving transistor from the reference voltage, the driving transistor is not turned off. In the present invention, as a result of the threshold voltage canceling process, the driving transistor is not necessarily required to be in a non-conductive state.

  As described above, the display device can have a color display configuration. Note that the display element group may further include one type or a plurality of types of display elements. For example, one set of display elements that emit white light to increase brightness, one set of display elements that emit complementary colors to expand the color reproduction range, and yellow to expand the color reproduction range. One set including a display element that emits light, and one set including a display element that emits yellow and cyan in order to expand the color reproduction range can also be configured.

  As values of pixels (pixels) of the display device, VGA (640, 480), S-VGA (800, 600), XGA (1024, 768), APRC (1152, 900), S-XGA (1280, 1024), U-XGA (1600, 1200), HD-TV (1920, 1080), Q-XGA (2048, 1536), (1920, 1035), (720, 480), (1280, 960), etc. Although some of the resolutions can be exemplified, the present invention is not limited to these values.

  Examples of the current-driven light emitting unit include an organic electroluminescence light emitting unit, an inorganic electroluminescence light emitting unit, an LED light emitting unit, and a semiconductor laser light emitting unit. From the viewpoint of configuring a flat display device for color display, among these, the configuration in which the light emitting section is composed of an organic electroluminescence light emitting section is preferable. The organic electroluminescence light emitting unit may be a so-called top emission type or a bottom emission type.

  The configuration and structure of the light emitting unit can be a known configuration and structure. For example, when the light emitting part is composed of an organic electroluminescence light emitting part, it can be composed of an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, a cathode electrode, and the like. These can be provided by a known method using a known material.

  The capacitor portion constituting the drive circuit can be composed of one electrode, the other electrode, and a dielectric layer sandwiched between these electrodes. The above-described transistors and capacitors that constitute the drive circuit are formed in a certain plane (for example, formed on a support), and the light-emitting portion is a transistor that constitutes the drive circuit via an interlayer insulating layer, for example. And formed above the capacitor portion. In addition, the other source / drain region of the driving transistor is connected to one end of the light emitting unit (an anode electrode or the like provided in the light emitting unit) via, for example, a contact hole.

  Various electrodes and wirings such as a gate electrode, an electrode constituting a capacitor portion, a first scanning line, a second scanning line, a first data line, a second data line, and a feeder line constituting a display device are well known. It can be formed by a known method such as a PVD method or a CVD method using a conductive material. For example, after forming a metal layer (metal thin film), these can be provided based on a photolithography technique, an etching technique, and the like. In the display device, various circuits such as a power supply unit, a scanning circuit, and a signal output circuit, which will be described later, can be configured using known circuit elements.

As a constituent material of a support or a substrate described later, high strain point glass, soda glass (Na ₂ O · CaO · SiO ₂ ), borosilicate glass (Na ₂ O · B ₂ O ₃ · SiO ₂ ), forsterite (2MgO・ In addition to glass materials such as SiO ₂ ) and lead glass (Na ₂ O · PbO · SiO ₂ ), flexible polymer materials such as polyethersulfone (PES), polyimide, polycarbonate (PC), polyethylene A polymer material exemplified by terephthalate (PET) can be exemplified. Various coatings may be applied to the surface of the support or the substrate. The constituent materials of the support and the substrate may be the same or different. When a support body and a substrate made of a plastic material having flexibility are used, a display device having flexibility can be configured.

  In two source / drain regions of one transistor, the term “one source / drain region” may be used to mean a source / drain region connected to the power supply side. In addition, the transistor being in a conductive state means a state in which a channel is formed in a channel formation region between the source / drain regions. It does not matter whether current flows from one source / drain region of the transistor to the other source / drain region. On the other hand, the transistor being in a non-conductive state means a state in which no channel is formed between the source / drain regions. Further, the source / drain regions can be made of polysilicon containing impurities, amorphous silicon, or the like.

  In the timing chart used in the following description, the length of the horizontal axis (time length) indicating each period is a schematic one and does not indicate the ratio of the time length of each period. The same applies to the vertical axis. The waveform shape in the timing chart is also schematic.

  Example 1 relates to a display device of the present invention, a method for manufacturing the display device of the present invention, and a method for driving the display device of the present invention.

A conceptual diagram of the display device of Example 1 is shown in FIG. 1, and an equivalent circuit diagram of the display element group is shown in FIG. The display device according to the first embodiment includes N pieces in the first direction (X direction in the figure), M pieces in the second direction (Y direction in the figure) different from the first direction, and a total of N × M pieces. Arranged in a two-dimensional matrix, each includes a display element group DG including a first display element 10 ₁ , a second display element 10 _2, and a third display element 10 ₃ . The first scanning line SCL1 and the second scanning line SCL2, which are provided for each column of N display element groups DG arranged along the first direction and extend in the first direction, and the second A first data line DTL1 and a second data line DTL2 are provided for each column of M display element groups DG arranged along the direction and extend in the second direction. The first scanning line SCL1 and the second scanning line SCL2 are connected to the scanning circuit 101, and the first data line DTL1 and the second data line DTL2 are connected to the signal output circuit 102. The display device further includes a power supply line PS1 connected to the power supply unit 100 and provided for each column including N display element groups DG arranged along the first direction and extending in the first direction. .

Although FIG. 1 shows a 2 × 3 display element group DG, this is merely an example. The display element group DG located in the m-th row (where m = 1, 2,..., M) and the n-th column (where n = 1, 2,..., N) is referred to as (n , M) The display element group DG or the display element group DG _{(n, m)} . FIG. 2 shows an equivalent circuit diagram of the (n, m) th and (n + 1, m) th display element groups DG.

As shown in FIG. 2, each of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ includes a drive circuit 11 and a current drive type light emitting unit ELP. The drive circuit 11 includes a gate electrode, a channel formation region, a write transistor TR _W having one source / drain region and the other source / drain region, and a gate connected to the other source / drain region of the write transistor TR _W. A drive transistor TR _D having an electrode, a channel formation region, one source / drain region and the other source / drain region is provided. In addition, the structure provided with another transistor may be sufficient.

The light emitting section ELP is electrically connected to the other of the source / drain area of the driving transistor TR _D. More specifically, the other source / drain region of the drive transistor TR _D is connected to one end (specifically, an anode electrode) of the light emitting unit ELP. Incidentally, for example, via another transistor or the like, the other source / drain region of the drive transistor TR _D and the light emission unit ELP may be a configuration that is connected.

Drive circuit 11, and the other source / drain region connected to one electrode of the driving transistor TR _D, and further includes a capacitor C ₁ and a second electrode connected to the gate electrode of the driving transistor TR _D Yes. As will be described later with reference to FIG. 4, the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ include a drive circuit 11 and a light emitting unit ELP connected to the drive circuit 11. It has a laminated structure. The light emitting part ELP is composed of an organic electroluminescence light emitting part. The capacity of the light emitting part ELP is represented by the symbol C _EL .

In the display element group DG, the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ are arranged in the first direction (X direction). Each display element 10 constitutes a so-called sub-pixel, and one pixel is constituted by a display element group DG composed of three display elements 10. The first display element 10 ₁ red light-emitting sub-pixel, the second display element 10 ₂ green light-emitting sub-pixel, the third display element 10 ₃ constituting a blue light-emitting sub-pixel. The display device of the first embodiment is a color display device including a plurality of display element groups DG (for example, N × M = 640 × 480).

In the (n, m) th display element group DG, one source / drain region of the first display element 10 ₁ and the second display element 10 ₂ of the write transistor TR _W is the n-th first It is connected to the data line DTL1 _n, one source / drain region of the third display element 10 ₃ of the write transistor TR _W is connected to the n-th second data line DTL2 _n. The gate electrode of the first display element 10 ₁ of the write transistor TR _W is connected to the m-th first scan line of SCL1 _m, the gate electrode of the second display element 10 ₂ of the write transistor TR _W is the m It is connected to th second scan line SCL2 _m. The gate electrode of the write transistor TR _W of the third display element 10 ₃ is either the m-th first scanning line SCL1 _{m or} the second scanning line SCL2 _m (in the first embodiment, the second scanning line). SCL2 _m ). One source / drain region of the drive transistor TR _D of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ is connected to the _mth feeder line PS1 _m .

  The other end of the light emitting unit ELP (specifically, the cathode electrode) is connected to the second power supply line PS2. The second power supply line PS2 is common to all the display elements 10. In FIG. 1, the illustration of the feeder line PS2 is omitted.

A predetermined voltage V _Cat described later is applied from the second feeder line PS2 to the cathode electrode of the light emitting unit ELP. Further, a threshold voltage required for light emission of the light emitting unit ELP is set to V _th-EL described later. That is, when a voltage equal to or higher than V _th-EL is applied between the anode electrode and the cathode electrode of the light emitting unit ELP, the light emitting unit ELP emits light.

  The light emitting unit ELP has a known configuration and structure including, for example, an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode electrode. The power supply unit 100, the scanning circuit 101, the signal output circuit 102, the first scanning line SCL1, the second scanning line SCL2, the first data line DTL1, the second data line DTL2, the feed line PS1, and the second feed line PS2. The configuration or structure can be a known configuration or structure.

Here, in the light emitting state of the display element 10, the driving transistor TR _D is set to a voltage so as to operate in the saturation region, and is driven so that the drain current I _ds flows according to the following formula (1). In the light emission state of the display device 10, one source / drain region of the driving transistor TR _D works as a drain region, the other source / drain region acts as a source region. In the following description, one source / drain region of the drive transistor TR _D may be simply referred to as a drain region, and the other source / drain region may be simply referred to as a source region. still,
μ: effective mobility L: channel length W: channel width V _gs : potential difference between gate electrode and source region V _th : threshold voltage C _ox : (relative permittivity of gate insulating layer) x (vacuum dielectric) Rate) / (thickness of gate insulating layer)
k≡ (1/2) ・ (W / L) ・ C _ox
And

I _ds = k · μ · (V _gs −V _th ) ² (1)

When the drain current I _ds flows through the light emitting unit ELP, the light emitting unit ELP of the display element 10 emits light. Furthermore, the light emission state (luminance) in the light emitting portion ELP of the display element 10 is controlled by the magnitude of the drain current I _ds .

A predetermined voltage is applied to one source / drain region of the write transistor TR _W from the first data line DTL1 or the second data line DTL2 based on the operation of the signal output circuit 102. Specifically, a video signal (drive signal, luminance signal) V _Sig for controlling luminance in the light emitting unit ELP and a reference voltage V _Ofs described later are supplied from the signal output circuit 102. Conductive state / nonconductive state of the writing transistor TR _W, the write transistor TR _W scanning signal from the first scan line SCL1 and second scan lines SCL2 connected to the gate electrode of, specifically, from the scanning circuit 101 Controlled by a scanning signal.

FIG. 3 is a diagram corresponding to FIG. 2, and is a schematic diagram of the layout of the drive circuit 11 including the write transistor TR _W and the drive transistor TR _D constituting the display element 10 provided on the support 20 described later. It is a top view. FIG. 4 is a schematic partial cross-sectional view of the display device taken along the line AA in FIG. 3, the gate insulating layer 32, the wiring 39 (corresponding to the second power supply line PS2), the interlayer insulating layer 40, the contact hole 55, and the interlayer insulating layer 40 shown in FIG. Illustration of various components was omitted.

As shown in FIG. 3, in each display element group DG, a first display element 10 ₁ is arranged on the −X direction side, a second display element 10 ₂ is arranged in the center, and a third display element 10 ₃ is arranged on the + X direction side. Has been. The first scanning line SCL1 is arranged on the + Y direction side and the second scanning line SCL2 is on the −Y direction side with respect to the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ . It is arranged. In other words, the display element group DG is disposed between the first scanning line SCL1 and the second scanning line SCL2. The first data line DTL1 are arranged between the ₂ first display element 10 ₁ and the second display element 10, the second data line DTL2 between the second display element 10 ₂ and the third display element 10 ₃ It is arranged in. For the first display element 10 _1, and the arrangement of the second display element 10 ₂ and the third display element 10 _3, the first display device 10 _1, the second display element 10 ₂ and the third display element 10 ₃ in a display device group DG The arrangement of the first scanning line SCL1, the second scanning line SCL2, and the first data line DTL1 and the second data line DTL2 is constant in the display element group DG.

As shown in FIG. 4, the transistors TR _D and TR _W and the capacitor C ₁ constituting the drive circuit 11 are formed on the support 20, and the light emitting unit ELP is connected to the drive circuit via the interlayer insulating layer 40, for example. 11 are formed above the transistors TR _D and TR _W and the capacitor C ₁ . The other source / drain region of the driving transistor TR _D is connected to an anode electrode provided in the light emitting unit ELP through a contact hole.

More specifically, the drive transistor TR _D includes a gate electrode 31, a gate insulating layer 32, source / drain regions 35 and 35 provided in the semiconductor layer 33, and a semiconductor layer between the source / drain regions 35 and 35. The portion 33 is constituted by the corresponding channel forming region 34. On the other hand, the capacitor portion C ₁ includes the other electrode 36, a dielectric layer composed of the extending portion of the gate insulating layer 32, and one electrode 37. The gate electrode 31, a part of the gate insulating layer 32, and the other electrode 36 constituting the capacitor portion C ₁ are formed on the support 20. Note that the write transistor TR _W not shown in FIG. 4 is also composed of a semiconductor layer, a gate insulating layer, a gate electrode, and the like, as described above.

  The gate electrode 31 and the other electrode 36 are composed of the first metal layer shown in FIG. Although not shown in FIG. 4, a part of the first data line DTL1 and a part of the second data line DTL2 are also composed of the first metal layer shown in FIG. One electrode 37 and a later-described wiring 38 (corresponding to the feeder line PS1) are composed of the second metal layer shown in FIG. Although not shown in FIG. 4, a part of the first data line DTL1 and a part of the second data line DTL2 are composed of the second metal layer shown in FIG.

One source / drain region 35 of the driving transistor TR _D is connected to the wiring 38, and the other source / drain region 35 is connected to one electrode 37. The drive transistor TR _{D, the} capacitor C _{1, and the} like are covered with an interlayer insulating layer 40, and an anode electrode 51, a hole transport layer, a light emitting layer, an electron transport layer, and a cathode electrode 53 are formed on the interlayer insulating layer 40. A light emitting unit ELP is provided. In the drawing, the hole transport layer, the light emitting layer, and the electron transport layer are represented by one layer 52. A second interlayer insulating layer 54 is provided on the portion of the interlayer insulating layer 40 where the light emitting part ELP is not provided, and the transparent substrate 21 is disposed on the second interlayer insulating layer 54 and the cathode electrode 53. The light emitted from the light emitting layer passes through the substrate 21 and is emitted to the outside. The one electrode 37 and the anode electrode 51 are connected by a contact hole provided in the interlayer insulating layer 40. In addition, the cathode electrode 53 is connected to the wiring 39 (second wiring) provided on the extended portion of the gate insulating layer 32 through the contact holes 56 and 55 provided in the second interlayer insulating layer 54 and the interlayer insulating layer 40. (Corresponding to the feeder line PS2).

In the display device group DG constitutes a direction from one of the source / drain region of the drive transistor TR _D that constitute the first display device 10 ₁ to the other source / drain region, the second display element 10 ₂ The direction is different from one source / drain region of the driving transistor TR _D toward the other source / drain region. As shown in FIG. 3, a direction from one of the source / drain region of the drive transistor TR _D that constitute the first display device 10 ₁ to the other source / drain region is a + X direction. Direction from one of the source / drain region of the drive transistor TR _D that constitutes the second display device 10 ₂ to the other source / drain region is the -X direction.

In the display device group DG, the drive transistor TR constituting the one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitute the first display device 10 _1, the second display element 10 ₂ One source / drain region and the other source / drain region of _D are arranged point-symmetrically. More specifically, in the display device group DG has a first display element 10 ₁ of the driving circuit 11 and the second display element 10 _{and second} driving circuit 11 are arranged in point symmetry.

As described above, the gate electrode of the third display element 10 ₃ of the write transistor TR _W is connected to the second scan line SCL2. The display device of Example 1 shown in FIG. 3 is the display device of the first aspect, more specifically, the display device of the first A aspect. In the display device group DG, the drive transistor TR constituting the one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitutes the third display element 10 _3, the second display element 10 ₂ One source / drain region and the other source / drain region of _D are arranged in translational symmetry. More specifically, in the display element group DG, the drive circuit 11 of the third display element 10 _{3 and} the drive circuit 11 of the second display element 10 ₂ are arranged in translational symmetry.

The direction of the drive transistor TR _D is different between the first display element 10 ₁ and the second display element 10 ₂ , but from one source / drain region of the drive transistor TR _D constituting the first display element 10 ₁ to the other source. The direction toward the drain region is constant in the + X direction between the display element groups DG. Direction from one of the source / drain region of the drive transistor TR _D that constitutes the second display device 10 ₂ to the other source / drain region is constant -X direction in the mutual display element group DG. Direction toward the driving transistor TR one of the source / drain regions other source / drain region of the _D constituting the third display element 10 ₃ is constant -X direction in the mutual display element group DG. In the first embodiment, the arrangement of the components of the drive circuit 11 in the same type of display element 10 is constant among the display element groups DG.

Therefore, unlike the configuration shown in FIG. 17, the drive circuit in the same kind of display element 10 is different depending on the direction from one source / drain region to the other source / drain region of the drive transistor TR _D constituting the display element 10. The phenomenon that a difference occurs in the characteristics of 11 basically does not occur.

A method for manufacturing the display device of Example 1 will be described with reference to FIGS. 4, 5, 6, and 7. After a first metal layer made of, for example, molybdenum (Mo) is formed on the entire surface of the support 20 by sputtering, the gate electrodes 31 and 31A, the other electrode 36, A part of the first data line DTL1 and a part of the second data line DTL2 are formed (see FIG. 5). Here, in FIG. 5, in order to clarify the portion of the first metal layer left on the support 20, the portion of the first metal layer is hatched. Note that the gate electrode of the write transistor TR _W is denoted by reference numeral 31A.

Next, a gate insulating layer 32 made of, for example, silicon oxide is formed on the entire surface by PECVD. Thereafter, a semiconductor layer made of, for example, amorphous silicon is formed on the gate insulating layer 32 using PECVD, and then the entire surface of the semiconductor layer is polysiliconized by a known annealing process. Next, after an impurity is implanted into the semiconductor layer corresponding to the writing transistor and the driving transistor by a well-known method, unnecessary portions of the semiconductor layer are removed based on the photolithography technique and the etching technique to obtain semiconductor layers 33 and 33A. (See FIG. 6). The semiconductor layer constituting the write transistor TR _W is represented by reference numeral 33A in FIG. 6 and 7, in order to clarify the positional relationship between the semiconductor layers 33 and 33A and the patterned first metal layer, the illustration of the gate insulating layer 32 is omitted, and the semiconductor layers 33 and 33A are omitted. The outline of 33A is indicated by a broken line.

  Thereafter, a portion of the gate insulating layer 32 (extension portion thereof) corresponding to a region where the connection portion (excluding the connection portion with ELP) shown in FIG. 3 is provided is removed based on the photolithography technique and the etching technique, and then After a second metal layer made of, for example, aluminum (Al) is formed on the entire surface by sputtering, one electrode 37, the feed line PS1, the first scan line SCL1, the first scan line SCL1, the first scan line SCL1, Two scanning lines SCL2, a portion of the remaining first data line DTL1, and a portion of the remaining second data line DTL2 are formed (see FIG. 7). Here, in FIG. 7, in order to clarify the portion of the second metal layer left on the support 20, the portion of the second metal layer is marked with a rough oblique line.

The first data line DTL1 and second data lines DTL2 extends its part, is connected to one of source / drain regions of the write transistor TR _W. Note that the wiring that connects the other source / drain region of the write transistor TR _W and the other electrode 36 is also formed of the second metal layer. Feeder line PS1 extends its part, one of the source / drain regions of the driving transistor TR _D is connected to (the drain region, represented by the symbol D). One electrode 37 is connected to the other source / drain region (source region, represented by symbol S) of the drive transistor TR _D. Through the above steps, the write transistor TR _W and the drive transistor TR _D that form the drive circuit 11 and the capacitor C ₁ can be provided on the support 20.

Next, the support 20 including the drive circuit 11 is irradiated with a spot-like laser beam and scanned in the X direction, whereby the channel formation region, one source / drain region, and the other source / drain of the drive transistor TR _D are scanned. An annealing process is performed on the semiconductor layer 33 constituting the drain region and the semiconductor layer 33A constituting the channel formation region of the write transistor TR _W , one source / drain region, and the other source / drain region (see FIG. 7). ). As a result, the crystallinity deterioration of the semiconductor layer due to various processes such as impurity implantation can be recovered.

For example, the temperature of an electrode, wiring, or the like composed of the second metal layer also rises due to laser irradiation. For this reason, the pattern of temperature increase / decrease in the semiconductor layers 33 and 33A is affected by the size of the area of the wiring connected to the source / drain region. In particular, in the driving transistor TR _D , the electrode 37 having a relatively large area that constitutes the capacitor portion is connected to the source region side. Therefore, in the annealing process, depending on whether the laser is irradiated from the electrode 37 side toward the drain region (D) side or the electrode 37 side laser is irradiated from the drain region (D) side, This produces a relative difference in properties.

However, in the display element 10 of the same type, the direction from one source / drain region of the drive transistor TR _{D to} the other source / drain region is constant in the display element group DG. More specifically, the arrangement of the components of the drive circuit 11 in the same type of display element 10 is constant among the display element groups DG. Therefore, a phenomenon that a difference occurs in the characteristics of the drive transistor TR _D due to the annealing process and a difference in characteristics occurs in the drive circuit 11 of the display element 10 of the same type does not basically occur.

  Thereafter, an interlayer insulating layer 40 made of, for example, silicon oxide or silicon nitride is formed by PECVD, and then contact holes and the like are appropriately formed by a known method. Next, film formation and patterning are performed by a known method to form light emitting portions ELP arranged in a matrix. And after making the support body 20 and the board | substrate 21 which passed through the said process oppose and sealing a periphery, it connects with an external circuit, for example, and a display apparatus can be obtained.

In the above description, the display device group DG between the first scan line SCL1 and second scan lines SCL2 are arranged, the gate electrode of the third display element 10 ₃ of the write transistor TR _W is the second scanning line SCL2 In addition, the second data line DTL2 is arranged between the second display element 10 ₂ and the third display element 10 ₃ . The arrangement relationship of the display elements 10 shown in FIG. 3 is schematically shown in FIG.

In the first embodiment, the first scanning line SCL1 and the like can take various arrangements. First, with respect to FIG. 8A, the arrangement relationship of the display element 10 when the second data line DTL2 is arranged between the third display element 10 ₃ and the adjacent display element group DG is schematically shown. This is shown in FIG. A display device of this configuration, is a display device of the aspect of the 1A, in the display element group DG, of one of the source / drain regions and the other of the drive transistor TR _D that constitutes the third display element 10 ₃ and source / drain regions, and one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitutes the second display element 10 ₂ is disposed in a line symmetry. In the display device group DG includes a drive circuit 11 of the third display element 10 ₃ and the second display element 10 _{and second} driving circuit 11 are arranged in line symmetry.

8 to (A), the arrangement of the display device 10 in the case of connecting the gate electrode of the third display element 10 ₃ of the write transistor TR _W to the first scan line SCL1, and schematically 8 (C ). The display device having this configuration is the display device according to the 1B mode. In the display device group DG, the drive transistor TR constituting the one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitutes the third display element 10 _3, the first display element 10 ₁ One source / drain region and the other source / drain region of _D are arranged in line symmetry. In the display device group DG includes a drive circuit 11 of the third display element 10 ₃ and the first display element 10 ₁ of the driving circuit 11 are arranged in line symmetry.

8 to (C), the second data line DTL2, the arrangement of the display element 10 when disposed between the display element group DG adjacent to the third display element 10 _3, schematically 8 (D). The display device having this configuration is also the display device of the mode 1B. In the display element group DG, one source / drain region and the other source of the driving transistor TR _D constituting the third display element 10 ₃ are included. / drain regions, and one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitute the first display element 10 ₁ is disposed in a translational symmetry. In the display device group DG includes a drive circuit 11 of the third display element 10 ₃ and the first display element 10 ₁ of the driving circuit 11 are arranged in translational symmetry.

  Next, with reference to (A) to (D) of FIG. 9, for example, an arrangement relationship when the second scanning line SCL2 is arranged on the first scanning line SCL1 side will be described.

FIG. 9A schematically shows an arrangement relationship when the second scanning line SCL2 is arranged on the first scanning line SCL1 side in FIG. In the display device group DG, the drive transistor TR constituting the one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitute the first display device 10 _1, the second display element 10 ₂ One source / drain region and the other source / drain region of _D are arranged in line symmetry. In the display device group DG has a first display element 10 ₁ of the driving circuit 11 and the second display element 10 _{and second} driving circuit 11 are arranged in line symmetry. The same applies to (B) to (D) of FIG. 9 described later. The display device having this configuration is the display device of the second aspect, more specifically, the display device of the second A aspect.

The gate electrode of the write transistor TR _W of the third display element 10 ₃ is connected to the second scanning line SCL2, and in the display element group DG, one of the drive transistors TR _D constituting the third display element 10 _3. and source / drain regions and the other of the source / drain regions of the one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitutes the second display element 10 ₂ is disposed in the translational symmetry Yes. In the display element group DG, the drive circuit 11 of the third display element 10 _{3 and} the drive circuit 11 of the second display element 10 ₂ are arranged in translational symmetry.

9 to (A), the second data line DTL2, the arrangement of the display element 10 when disposed between the display element group DG adjacent to the third display element 10 _3, schematically 9 (B). A display device of this configuration, is a display device of the aspect of the 2A, in the display element group DG, of one of the source / drain regions and the other of the drive transistor TR _D that constitutes the third display element 10 ₃ and source / drain regions, and one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitutes the second display element 10 ₂ is disposed in a line symmetry. In the display device group DG includes a drive circuit 11 of the third display element 10 ₃ and the second display element 10 _{and second} driving circuit 11 are arranged in line symmetry.

9 to (A), the arrangement of the display device 10 in the case of connecting the gate electrode of the third display element 10 ₃ of the write transistor TR _W to the first scan line SCL1, schematically in FIG. 9 (C ). The display device having this configuration is the display device according to the 2B mode. In the display device group DG, the drive transistor TR constituting the one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitutes the third display element 10 _3, the first display element 10 ₁ One source / drain region and the other source / drain region of _D are arranged in line symmetry. In the display device group DG includes a drive circuit 11 of the third display element 10 ₃ and the first display element 10 ₁ of the driving circuit 11 are arranged in line symmetry.

9C schematically shows the arrangement relationship of the display elements 10 when the second data line DTL2 is arranged between the third display element 10 ₃ and the adjacent display element group DG. (D). A display device of this configuration, is a display device of the aspect of the 2B, in the display element group DG, of one of the source / drain regions and the other of the drive transistor TR _D that constitutes the third display element 10 ₃ and source / drain regions, and one of the source / drain regions and the other of the source / drain region of the drive transistor TR _D that constitute the first display element 10 ₁ is disposed in a translational symmetry. In the display device group DG includes a drive circuit 11 of the third display element 10 ₃ and the first display element 10 ₁ of the driving circuit 11 are arranged in translational symmetry.

In the display device according to the first embodiment, the display element group DG includes the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ , and M arranged along the second direction. Two data lines are arranged for each display element group DG. Therefore, the number of data lines can be reduced by one third compared to the conventional configuration in which data lines are arranged for each column of display elements 10.

  Next, a driving method of the display device according to the first embodiment (hereinafter simply referred to as a driving method according to the first embodiment) will be described. As described above, the display device includes N × M pixels arranged in a two-dimensional matrix. The display frame rate is FR (times / second). The display elements 10 constituting each of N pixels (3 × N subpixels) arranged in the m-th row are driven simultaneously. In other words, in the N display element groups DG arranged along the first direction, the light emission / non-light emission timing is controlled in units of rows to which they belong. The scanning period per line when the display device is line-sequentially scanned in units of rows, more specifically, one horizontal scanning period (so-called 1H) is less than (1 / FR) × (1 / M) seconds. .

  In the following description, the voltage or potential value is as follows. However, this is merely a value for explanation, and is not limited to these values.

V _Sig : Video signal for controlling the luminance in the light emitting part ELP: 1 volt (black display) to 8 volt (white display)
V _CC-H : Drive voltage for causing current to flow through the light _- emitting portion ELP ... 20 volts V _CC-L : Second node initialization voltage ... -10 volts V _Ofs : Potential of the gate electrode of the drive transistor TR _D Reference voltage for initializing (the potential of the first node ND ₁ )... 0 volt V _th : threshold voltage of the drive transistor TR _D ... 3 volt V _Cat : applied to the cathode electrode of the light emitting unit ELP Voltage: 0 V V _th-EL : Threshold voltage of light emitting part ELP: 3 V

FIG. 10 is an equivalent circuit diagram of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ constituting the (n, m) th display element group DG. In the respective drive circuits 11, the driving transistor TR to the gate electrode of the _D is connected to the write transistor TR _W other source / drain region and the other electrode of the capacitor C ₁ of the driving transistor TR _D The gate electrode constitutes the first node ND ₁ . The other source / drain region of the driving transistor TR _D is connected to one electrode of the capacitor C ₁ and one end (specifically, an anode electrode) of the light emitting unit ELP, and the other source / drain region of the driving transistor TR _{D is connected to} the other source / drain region. source / drain regions constitute a second node ND _2.

  First, the outline of the writing process for the (n, m) th display element group DG will be described. The operation in the overall driving method will be described in detail later with reference to FIG.

FIG. 11 is a schematic diagram of various timings in the driving method of the first embodiment. Since the first display element 10 ₁ and the second display element 10 ₂ are both connected to the first data line DTL1 _n, the first display element 10 ₁ and the second display element 10 _2, respectively, and different from the period Therefore, it is necessary to apply a predetermined video signal V _Sig from the first data line DTL1 _n . Therefore, the first data line DTL1 _n, 1 during the horizontal scanning period, the reference voltage V _Ofs, the video signal corresponding to the first display element 10 ₁ (first video signal), and the second display element 10 ₂ A video signal (second video signal) corresponding to is sequentially applied. On the other hand, the reference voltage V _Ofs and the video signal corresponding to the third display element 10 ₃ (third video signal) are sequentially applied to the second data line DTL2 _n within one horizontal scanning period. Note that the period in which the second video signal is applied is synchronized with the period in which the third video signal is applied. While applying the second video signal to the first data line DTL1 _n, subsequently applying a reference voltage V _Ofs to the second data line DTL2 _n.

The first video signal, the second video signal, and the third video signal corresponding to the (n, m) th display element group DG are respectively converted into a video signal V _{Sig_ [m, 1]} and a video signal V _{Sig_ [m, 2]} is represented as a video signal V _{Sig_ [m, 3]} . A first scanning signal and a second scanning signal whose periods do not overlap each other are applied to the first scanning line SCL1 _m and the second scanning line SCL2 _m , respectively. Specifically, in [Period-TP (2) ₆ ] shown in FIG. 11, the first scanning signal is applied to the first scanning line SCL1 _m to be high level, and in [Period-TP (2) ₇ ], the second scanning line SCL2 _m by applying a second scan signal to the high level. In [Period -TP (2) ₆ ], the potential of the first data line DTL1 _n is the video signal V _{Sig — [m, 1]} . In [Period -TP (2) ₇ ], the potential of the first data line DTL1 _n is the video signal V _{Sig_ [m, 2]} , and the potential of the second data line DTL2 _n is the video signal V _{Sig_ [m. , 3]} .

In the first display device 10 _1, the conducting state the write transistor TR _W in based on the first scan signal [Period -TP (2) _6], the video signal V _{Sig_} from the first data line DTL1 _{n [m , 1]} is applied to the gate electrode of the driving transistor TR _D. In the second display element 10 _2, the write transistor TR _W is made conductive in on the basis of the second scan signal [Period -TP (2) _7], the video signal V _{Sig_} from the first data line DTL1 _{n [m , 1]} is applied to the gate electrode of the driving transistor TR _D. In the third display element 10 _3, the gate electrode of the driving transistor TR _D is connected to the second scan line SCL2 _m, writing in based on the second scanning signal [Period -TP (2) _7] the transistor TR _W is made conductive, is applied from the second data line DTL2 _n video signal V _{Sig_ [m, 3]} to the gate electrode of the driving transistor TR _D. Thereby, the writing process is completed.

The outline of the writing process has been described for the (n, m) th display element group DG. In the driving method of the first embodiment, various processes are performed before the writing process. The operations of the display elements 10 constituting the (n, m) th display element group DG are basically the same operations except that the period for performing the writing process is different. Hereinafter, basically, the (n, m) Notice the third display element 10 ₃ constituting th display element group DG, the operation thereof will be described in detail.

Figure 12 is a schematic diagram of a timing chart for explaining the (n, m) th third operation of the display device 10 ₃ in the display pixel group DG. FIGS. 13A to 13F are diagrams schematically showing the conductive state / non-conductive state of each of the transistors constituting the drive circuit 11 of the third display element 10 ₃ . (A) to (F) is 14, subsequent to (F) in FIG. 13, schematically shows a conductive state / nonconductive state of the transistor constituting the driving circuit 11 of the third display element 10 ₃ It is.

[Period -TP (2) ₋₁ ] (see FIGS. 12 and 13A)
This [period-TP (2) ₋₁ ] is, for example, an operation in the previous display frame, and is a period in which the (n, m) th display element group DG is in a light emitting state after the completion of various previous processes. is there. That is, the drain current I ′ _ds based on the formula (5 ′) described later flows through the light emitting portion ELP in the third display element 10 ₃ constituting the (n, m) th display element group DG. The luminance of the third display element 10 ₃ constituting the (n, m) th display element group DG is a value corresponding to the drain current I ′ _ds . Here, the write transistor TR _W is in a non-conductive state, and the drive transistor TR _D is in a conductive state. The light emission state of the (n, m) th display element group DG is continued until just before the start of the horizontal scanning period of the display element group DG arranged in the (m + m ′) th row.

As described above, the reference voltage V _Ofs and the video signal V _Sig are applied to the first data line DTL1 _n and the second data line DTL2 _n corresponding to each horizontal scanning period. However, since the write transistor TR _W is in a non-conducting state, even _if the potential (voltage) of the second data line DTL2 _n changes in [period -TP (2) ₋₁ ], the first node ND ₁ and the second node The potential of the node ND ₂ does not change (actually, a potential change due to electrostatic coupling such as parasitic capacitance may occur, but these can usually be ignored). The same applies to [period-TP (2) ₀ ] described later.

[Period-TP (2) ₀ ] to [Period-TP (2) ₅ ] shown in FIG. 12 are from the end of the light emission state after completion of the previous various processes to immediately before the next writing process is performed. Is the operation period. In [Period -TP (2) ₀ ] to [Period -TP (2) ₅ ], the (n, m) th display element group DG is in a non-light emitting state in principle. As shown in FIG. 12, [Period-TP (2) ₅ ], [Period-TP (2) ₆ ] and [Period-TP (2) ₇ ] are included in the m-th horizontal scanning period H _m. .

In the driving method of the first embodiment, the third scanning signal is applied to the first scanning line SCL1 and the second scanning line SCL2 prior to the first scanning signal and the second scanning signal, and the first display element 10 ₁ , In the first display element 10 ₁ and the second display element 10 ₂ , the reference voltage V is applied from the first data line DTL1 _{n by} setting the write transistor TR _W of the second display element 10 ₂ and the third display element 10 ₃ to the conductive state. the _Ofs is applied to the gate electrode of the driving transistor TR _D, in the third display element 10 _3, the reference voltage V _Ofs from the second data line DTL2 _n is applied to the gate electrode of the driving transistor TR _D, the feeder line PS1 A predetermined driving voltage V _CC-H is applied to one source / drain region of the driving transistor TR _D of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ , thereby 1 display element 10 _1, the first Threshold changing towards the potential obtained by subtracting the threshold voltage V _th of the display device 10 ₂ and the third display element 10 ₃ of the driving transistor TR _D of the other source / drain region potential reference voltage V _Ofs from the driving transistor TR _D in Performs voltage cancellation processing.

In the first embodiment, the threshold voltage canceling process is performed in a plurality of horizontal scanning periods, more specifically, in the (m−1) th horizontal scanning period H _m−1 and the mth horizontal scanning period H _m . However, the present invention is not limited to this.

In FIG. 11, a period in which the potentials of the first data line DTL1 _n and the second data line DTL2 _n are both the reference voltage V _Ofs is referred to as an initialization period. [Period-TP (2) ₁ ] coincides with the initialization period in the (m−2) th horizontal scanning period H _m−2 , and [Period−TP (2) ₃ ] corresponds to (m−1). ) th match in the initialization period in the horizontal scanning period H _m-1, [period -TP (2) _5] is a match in the initialization period in the m-th horizontal scanning period H _m. In the first embodiment, the third scanning signal is applied to the first scanning line SCL1 _m and the second scanning line SCL2 _m in each period described above.

Next, with reference to FIG. 12 and the like, operations in each period of [Period-TP (2) ₀ ] to [Period-TP (2) ₈ ] will be described.

[Period -TP (2) ₀ ] (see FIGS. 12 and 13B)
This [period-TP (2) ₀ ] is, for example, an operation from the previous display frame to the current display frame. That is, this [period-TP (2) ₀ ] is the (m−3) th in the current display frame from the beginning of the (m + m ′) th horizontal scanning period H _{m + m ′} in the previous display frame. This is the period up to the horizontal scanning period. In this [period-TP (2) ₀ ], the (n, m) th display element group DG is in a non-light emitting state in principle. At the beginning of [Period-TP (2) ₀ ], the voltage supplied from the power supply unit 100 to the power supply line PS1 _m is switched from the drive voltage V _CC-H to the second node initialization voltage V _CC-L . As a result, the potential of the second node ND ₂ drops to V _CC-L , a reverse voltage is applied between the anode electrode and the cathode electrode of the light emitting unit ELP, and the light emitting unit ELP enters a non-light emitting state. In addition, the potential of the floating first node ND ₁ (the gate electrode of the drive transistor TR _D ) is also lowered so as to follow the potential drop of the second node ND ₂ .

[Period -TP (2) ₁ ] (see FIGS. 12 and 13C)
Then, the (m−2) th horizontal scanning period H _m−2 in the current display frame starts.

In this [Period-TP (2) ₁ ], the third scanning signal is applied to the first scanning line SCL1 _m and the second scanning line SCL2 _m , and the first display element 10 ₁ , the second display element 10 _2, 3 The writing transistor TR _W of the display element 10 ₃ is brought into a conducting state. The voltage applied from the signal output circuit 102 to the first data line DTL1 _n and the second data line DTL2 _n is the reference voltage V _Ofs . (Initialization period). As a result, the potential of the first node ND ₁ becomes V _Ofs (0 volts). Since the second node initialization voltage V _CC-L is applied to the second node ND ₂ from the power supply line PS1 _m based on the operation of the power supply unit 100, the potential of the second node ND ₂ is V _CC-L (− 10 volts).

The first node ND ₁ and the potential difference between the second node ND ₂ is 10 volts, the threshold voltage V _th of the driving transistor TR _D because it is 3 volts, the driving transistor TR _D is conductive. The potential difference between the second node ND ₂ and the cathode electrode provided in the light emitting unit ELP is −10 volts, and does not exceed the threshold voltage V _th−EL of the light emitting unit ELP. Thereby, the preprocessing for initializing the potential of the first node ND _{1 and} the potential of the second node ND ₂ is completed.

[Period -TP (2) ₂ ] (see FIGS. 12 and 13D)
In this [period-TP (2) ₂ ], since the third scanning signal is not applied, the writing transistors TR _W of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ are in a non-conductive state. It becomes. The potentials of the first node ND ₁ and the second node ND ₂ basically maintain the previous state.

[Period -TP (2) ₃ ] (see FIGS. 12 and 13 (E) and (F))
In this [period-TP (2) ₃ ], the first threshold voltage canceling process is performed. By applying the third scanning signal for the second time, the write transistors TR _W of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ are turned on. The voltage applied from the signal output circuit 102 to the first data line DTL1 _n and the second data line DTL2 _n is the reference voltage V _Ofs . The potential of the first node ND ₁ is V _Ofs (0 volts).

Next, the voltage supplied from the power supply unit 100 to the power supply line PS1 _m is switched from the voltage V _CC-L to the drive voltage V _CC-H . As a result, the potential of the first node ND ₁ does not change (V _Ofs = 0 is maintained), but the second node ND moves toward the potential obtained by subtracting the threshold voltage V _th of the drive transistor TR _D from the reference voltage V _Ofs. The potential of ₂ changes. That is, the potential of the second node ND ₂ increases.

If this [period-TP (2) ₃ ] is sufficiently long, the potential difference between the gate electrode of the driving transistor TR _D and the other source / drain region reaches V _th , and the driving transistor TR _D becomes non-conductive. . That is, the potential of the second node ND ₂ approaches (V _Ofs -V _th), and finally becomes (V _Ofs -V _th). However, in the example shown in FIG. 12, the length of [Period -TP (2) ₃ ] is insufficient to change the potential of the second node ND ₂ sufficiently, and [Period -TP (2) ₃ ], the potential of the second node ND ₂ reaches a certain potential V ₁ that satisfies the relationship of V _CC-L <V ₁ <(V _Ofs −V _th ).

[Period -TP (2) ₄ ] (see FIGS. 12 and 14A)
In this [period-TP (2) ₄ ], since the third scanning signal is not applied, the writing transistors TR _W of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ are in the non-conductive state. It becomes. As a result, the first node ND ₁ is in a floating state.

Since the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _D , the potential of the second node ND ₂ rises from the potential V ₁ to a certain potential V ₂ . . On the other hand, since the gate electrode of the driving transistor TR _D is in a floating state and the capacitance portion C ₁ exists, a bootstrap operation occurs on the gate electrode of the driving transistor TR _D. Therefore, the potential of the first node ND ₁ rises following the potential change of the second node ND ₂ .

As a premise of the operation in the next [period-TP (2) ₅ ], the potential of the second node ND ₂ is lower than (V _Ofs −V _th ) at the beginning of [period-TP (2) ₅ ]. Necessary. The length of [Period -TP (2) ₄ ] is basically determined so as to satisfy the condition of V ₂ <(V _Ofs−L −V _th ).

[Period -TP (2) ₅ ] (see FIGS. 12 and 14B)
In this [period-TP (2) ₃ ], the second threshold voltage canceling process is performed. By applying the third scanning signal for the third time, the writing transistors TR _W of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ are turned on. The voltage applied from the signal output circuit 102 to the first data line DTL1 _n and the second data line DTL2 _n is the reference voltage V _Ofs . The potential of the first node ND ₁ becomes V _Ofs (0 volt) again from the potential increased by the bootstrap operation.

Here, the value of the capacitor C ₁ is set as a value c _1, and the value of the capacitor C _EL of the light emitting unit ELP is set as a value c _EL . The value of the parasitic capacitance between the gate electrode of the driving transistor TR _D and the other source / drain region is defined as c _gs . If the capacitance value between the first node ND ₁ and the second node ND ₂ is represented by the symbol c _A , c _A = c ₁ + c _gs . In addition, if a capacitance value between the second node ND ₂ and the second power supply line PS2 is represented by a symbol c _B , c _B = c _EL . Note that both ends of the light emitting section ELP, although additional capacity portion may have a configuration that is connected in parallel, in which case, further capacitance value of the additional capacitance portion to c _B is added.

When the potential of the first node ND ₁ changes, the potential between the first node ND ₁ and the second node ND ₂ also changes. That is, the charge based on the change in the potential of the first node ND ₁ is caused by the capacitance value between the first node ND ₁ and the second node ND ₂ , the second node ND _2, and the second feeder line PS 2. Sorted according to the capacity value between them. However, if the value c _b (= c _EL ) is sufficiently larger than the value c _A (= c ₁ + c _gs ), the change in the potential of the second node ND ₂ is small. In general, the value c _EL of the capacitance C _EL of the light emitting unit ELP is larger than the value c ₁ of the capacitance unit C ₁ and the parasitic capacitance value c _{gs of the} driving transistor TR _D. Hereinafter, the description will be made without considering the potential change of the second node ND ₂ caused by the potential change of the first node ND ₁ . In the drive timing chart shown in FIG. 12, the potential change of the second node ND ₂ caused by the potential change of the first node ND ₁ is shown without considering.

Since the power supply unit 100 driving transistor TR one of the source / drain regions to the drive voltage V _CC-H for _D is applied, towards the potential obtained by subtracting the threshold voltage V _th of the driving transistor TR _D from the reference voltage V _Ofs The potential of the second node ND ₂ changes. That is, the potential of the second node ND ₂ rises from the potential V ₂ and changes toward the potential obtained by subtracting the threshold voltage V _th of the driving transistor TR _D from the reference voltage V _Ofs . When the potential difference between the gate electrode of the driving transistor TR _D and the other source / drain region reaches V _th , the driving transistor TR _D becomes non-conductive. In this state, the potential of the second node ND ₂ is approximately (V _Ofs −V _th ). Here, if the following formula (2) is guaranteed, in other words, if the potential is selected and determined so as to satisfy the formula (2), the light emitting unit ELP does not emit light.

(V _Ofs −V _th ) <(V _th−EL + V _Cat ) (2)

In this [period-TP (2) ₅ ], the potential of the second node ND ₂ is finally (V _Ofs −V _th ). That is, the potential of the second node ND ₂ is determined depending only on the threshold voltage V _th of the driving transistor TR _D and the reference voltage V _Ofs . And it is unrelated to the threshold voltage V _{th-EL of} the light emitting unit ELP.

[Period -TP (2) ₆ ] (see FIGS. 12 and 14D)
The writing process described above is performed in [Period-TP (2) ₆ ] and [Period-TP (2) ₇ ] described later. Although not shown in FIGS. 12 and 14, as shown in FIG. 11, in the first display element 10 _1, the [period -TP (2) _6], the first based on the first scan signal The video signal V _{Sig_ [m, 1]} is applied from the data line DTL1 _n to the gate electrode of the write transistor TR _W.

On the other hand, the scanning signal is not applied to the second scanning line SCL2 _m during [period-TP (2) ₆ ]. During the [period-TP (2) ₆ ], in the second display element 10 ₂ and the third display element 10 ₃ , the writing transistor TR _W is in a non-conducting state. If the driving transistor TR _D reaches the non-conducting state in [Period -TP (2) ₅ ], the potentials of the first node ND ₁ and the second node ND ₂ do not change substantially. If the drive transistor TR _D does not reach the non-conducting state in the threshold voltage cancel process performed in [Period-TP (2) ₅ ], a bootstrap operation occurs in [Period-TP (2) ₆ ], The potentials of the first node ND ₁ and the second node ND ₂ slightly increase.

[Period -TP (2) ₇ ] (see FIGS. 12 and 14E)
In this [period-TP (2) ₇ ], the writing transistors TR _W of the second display element 10 ₂ and the third display element 10 ₃ are turned on based on the second scanning signal of the second scanning line SCL2 _m . . Then, although not shown in FIGS. 12 and 14, in the second display element 10 _2, the video signal V _{Sig_} to the gate electrode of the writing transistor TR _W from the first data line DTL1 _{n [m, 2]} a Apply. In the third display element 10 ₃ , the video signal V _{Sig — [m, 3]} is applied from the second data line DTL2 _n to the gate electrode of the write transistor TR _W.

In the above-mentioned writing process, in a state where the drive voltage V _CC-H to one source / drain region of the driving transistor TR _D from the power supply unit 100 is applied, the video signal to the gate electrode of the driving transistor TR _{D Apply} V _Sig . Therefore, as shown in FIG. 12, in the third display element 10 ₃ potential of the second node ND ₂ is changed in the period -TP (2) _7]. The amount of increase in potential (ΔV shown in FIG. 12) will be described later. Although not shown, the second display element 10 ₂ and the second node ND ₂ in the potential is changed in the period -TP (2) _7], the first display element 10 ₁ [Period -TP (2) ₆ ], the potential of the second node ND ₂ changes.

When potential V _g of the gate electrode of the driving transistor TR _D (the first node ND _1), the potential of the other of the source / drain regions of the driving transistor TR _D (the second node ND ₂₎ was V _s, the above-described If the increase in the potential of the two-node ND ₂ is not taken into consideration, the values of V _g and V _s are as follows. The potential difference between the first node ND ₁ and the second node ND ₂ , that is, the potential difference V _gs between the gate electrode of the driving transistor TR _{D and} the other source / drain region serving as the source region is expressed by the following equation (3). Can be represented.

V _g = V _{Sig_ [m, 3]}
V _s ≈V _Ofs −V _th
V _gs ≒ V _{Sig_ [m, 3]} -(V _Ofs- V _th ) (3)

That is, V _gs obtained in the writing process on the driving transistor TR _D is the video signal V _{Sig — [m, 3]} for controlling the luminance in the light emitting unit ELP, the threshold voltage V _th of the driving transistor TR _D , and the reference It depends only on the voltage V _Ofs . And it is unrelated to the threshold voltage V _{th-EL of} the light emitting unit ELP.

Next, the increase in potential (ΔV) of the second node ND ₂ described above will be described. In the driving method of the first embodiment described above, the driving voltage V _{CC is} applied to one source / drain region of the driving transistor TR _D of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 _3. Performs write processing with _-H applied. Thereby, the mobility correction process for changing the potential of the other source / drain region of the drive transistor TR _D of the first display element 10 ₁ , the second display element 10 _2, and the third display element 10 ₃ is also performed.

When the driving transistor TR _D is made of a thin film transistor or the like, it is difficult to avoid variations in mobility μ between transistors. Therefore, even if the video signal V _Sig having the same value is applied to the gate electrodes of the plurality of drive transistors TR _D having different mobility μ, the drain current I _ds flowing through the drive transistor TR _D having the high mobility μ and the movement A difference is generated between the drain current I _ds flowing through the driving transistor TR _D having a small degree μ. And when such a difference arises, the uniformity (uniformity) of the screen of a display apparatus will be impaired.

In the drive method described above, the video signal V V is applied to the gate electrode of the drive transistor TR _D while the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _{D. Sig} is applied. For this reason, as shown in FIG. 12, the potential of the second node ND ₂ rises in the writing process. If the value of the mobility μ of the driving transistor TR _D is large, the increase amount [Delta] V (potential correction value) of the potential of the other of the source / drain regions of the driving transistor TR _D (i.e., the potential of the second node ND ₂₎ increases . Conversely, when the value of mobility μ of the drive transistor TR _D is small, the rise amount ΔV of the potential of the other source / drain region of the drive transistor TR _D becomes small. Here, the potential difference V _gs between the gate electrode of the driving transistor TR _{D and} the other source / drain region serving as the source region is transformed from the equation (3) into the following equation (4).

V _gs ≈V _{Sig — [m, 3]} − (V _Ofs −V _th ) −ΔV (4)

Note that the length of the period of the second scanning signal for writing the video signal may be determined according to the design of the display element and the display device. Further, the length of the period of the second scanning signal is such that the potential (V _Ofs −V _th + ΔV) in the other source / drain region of the driving transistor TR _D at this time satisfies the following expression (2 ′). Assume that it has been decided. The first scanning signal is the same as described above.

In the third display element 10 ₃ , the light emitting unit ELP does not emit light in [Period -TP (2) ₇ ]. By this mobility correction processing, the variation of the coefficient k (≡ (1/2) · (W / L) · C _ox ) is also corrected at the same time.

In the second display element 10 _2, except that replaced the video signal V _{Sig_} the _{[m, 3]} and the video signal V _{Sig_ [m, 2]} are the same as described above. In the first display device 10 _1, replaced video signal V _{Sig_ the m, 3]} and the video signal _{V Sig_ [m, 1],} [ Period -TP (2) _7] the period -TP (2) ₆ ] is the same as described above, except that

(V _Ofs −V _th + ΔV) <(V _th−EL + V _Cat ) (2 ′)

[Period -TP (2) ₈ ] (see FIGS. 12 and 14E)
The state where the drive voltage V _CC-H is applied from the power supply unit 100 to one source / drain region of the drive transistor TR _D is maintained. In the third display element 10 ₃ , a voltage corresponding to the third video signal is held in the capacitor C ₁ by the writing process. Since the application of the second scanning signal is finished, the writing transistor TR _W is turned off. Accordingly, when the _{application of} the third video signal V _{Sig_ [m, 3]} to the gate electrode of the driving transistor TR _D is stopped, a current corresponding to the value of the voltage held in the capacitor C ₁ is changed to the driving transistor TR. _The light emitting part emits light through _D through the light emitting part ELP.

In the second display element 10 _2, except that replaced the video signal V _{Sig_} the _{[m, 3]} and the video signal V _{Sig_ [m, 2]} are the same as described above. In the first display device 10 _1, replaced video signal V _{Sig_} the _{[m, 3]} and the video signal V _{Sig_ [m, 1],} is that the starting operation described above from the Period -TP (2) _7] Other than that, the operation is similar.

The operation of the third display element 10 ₃ will be described more specifically. The drive voltage V _CC-H is applied to one source / drain region of the drive transistor TR _D from the power supply unit 100, and the first node ND ₁ is electrically connected to the first data line DTL1 _n. Is disconnected. Accordingly, the potential of the second node ND ₂ increases.

Here, as described above, the gate electrode of the drive transistor TR _D is in a floating state, and since the capacitor portion C ₁ exists, the same phenomenon as that in the so-called bootstrap circuit occurs in the gate electrode of the drive transistor TR _D. As a result, the potential of the first node ND ₁ also rises. As a result, the potential difference V _gs between the gate electrode of the driving transistor TR _{D and} the other source / drain region serving as the source region maintains the value of the equation (4).

Further, since the potential of the second node ND ₂ rises and exceeds (V _th−EL + V _Cat ), the light emitting unit ELP starts to emit light (see FIG. 14F). At this time, since the current flowing through the light emitting unit ELP is the drain current I _ds flowing from the drain region to the source region of the driving transistor TR _D , it can be expressed by Expression (1). Here, from the formulas (1) and (4), the formula (1) can be transformed into the following formula (5).

I _ds = k · μ · (V _{Sig — [m, 3]} −V _Ofs −ΔV) ² (5)

Therefore, the current I _ds flowing through the light emitting unit ELP is driven from the value of the video signal V _{Sig_ [m, 3]} for controlling the luminance in the light emitting unit ELP when the reference voltage V _Ofs is set to 0 volt. This is proportional to the square of the value obtained by subtracting the value of the potential correction value ΔV caused by the mobility μ of the transistor TR _D. Stated words, current I _ds flowing through the light emitting section ELP, the threshold voltage V _th-EL of the luminescence part ELP, and does not depend on the threshold voltage V _th of the driving transistor TR _D. That is, the light emitting quantity of the light emitting portion ELP (luminance), the influence of the threshold voltage V _th-EL of the luminescence part ELP, and not affected by the threshold voltage V _th of the driving transistor TR _D. The luminance of the display element 10 constituting the (n, m) th is a value corresponding to the current _Ids .

In addition, since the potential correction value ΔV increases as the driving transistor TR _D has a higher mobility μ, the value of V _{gs on} the left side of Equation (4) decreases. Thus, in the formula (5), even larger value of the mobility μ _{is, (V Sig_ [m, 3} ] -V Ofs -ΔV) 2 value decreases a result, the variation of the mobility μ of the driving transistor TR _D ( Furthermore, the variation in the drain current I _ds due to the variation in k) can be corrected. As a result, it is possible to correct the luminance variation of the light emitting unit ELP caused by the variation in mobility μ (further, the variation in k).

The light emitting state of the light emitting unit ELP is continued until the (m + m′−1) th horizontal scanning period. The end of the (m + m′−1) th horizontal scanning period corresponds to the end of [period-TP (2) ₋₁ ]. Here, “m ′” satisfies a relationship of 1 <m ′ <M and is a predetermined value in the display device. In other words, the light emitting unit ELP is driven from the start of [Period -TP (2) ₈ ] to immediately before the (m + m ′)-th horizontal scanning period H _{m + m ′} , and this period becomes the light emission period. Incidentally, strictly speaking, in the first display device 10 _1, the beginning of [Period -TP (2) _7] the beginning of the emission period.

  As mentioned above, although this invention was demonstrated based on the preferable Example, this invention is not limited to this Example. The configuration and structure of the display device described in the embodiments, the steps of the manufacturing method of the display device, and the steps of the driving method of the display device are examples, and can be changed as appropriate.

In addition, as illustrated in FIG. 15, the driving circuit 11 configuring the display element 10 may include a transistor (first transistor TR ₁ ) connected to the first node ND ₁ . In the first transistor TR ₁ , the reference voltage V _Ofs is applied to one source / drain region, and the other source / drain region is connected to the first node ND ₁ . A control signal from the first transistor control circuit 103 is applied to the gate electrode of the first transistor TR ₂ via the first transistor control line AZ1 to control the conduction state / non-conduction state of the first transistor TR ₁ . Thereby, the potential of the first node ND ₁ can be set. In addition, it can also be set as the structure provided with another transistor.

In the first embodiment, the driving transistor TR _D has been described as an n-channel type. In the case where the driving transistor TR _D is a p-channel transistor, the connection may be made by replacing the anode electrode and the cathode electrode of the light emitting unit ELP. In this configuration, since the direction in which the drain current flows changes, the value of the voltage applied to the power supply line or the like may be changed as appropriate.

TR _W: writing transistor, TR _D: driving transistor, TR _1: first transistor, C _1: capacitance unit, ELP: organic electroluminescence light emitting unit, C _EL: light emitting unit ELP capacitance, ND ₁ ... First node, ND ₂ ... Second node, SCL 1... First scanning line, SCL 2... Second scanning line, DTL 1. ... second data line, PS1 ... feed line, PS2 ... second feed line, AZ1 ... first transistor control line, DG ... display element group, 10 ₁ ... first Display element, 10 _2, second display element, 10 _3, third display element, 11, drive circuit, 20, support, 21, substrate, 31, gate electrode, 32 ... Gate insulating layer, 33 ... Semiconductor layer, 34 ... Channel formation region 35, 35 ... source / drain regions, 36 ... other electrode, 37 ... one electrode, 38 ... wiring, 39 ... wiring, 40 ... interlayer insulation layer, 51 ... Anode electrode, 52... Hole transport layer, light emitting layer and electron transport layer, 53... Cathode electrode, 54... Second interlayer insulating layer, 55, 56. Power supply unit, 101 ... scanning circuit, 102 ... signal output circuit, 103 ... first transistor control circuit

Claims (14)

N pieces in a first direction, M pieces in a second direction different from the first direction, and a total of N × M pieces, which are arranged in a two-dimensional matrix, are respectively a first display element and a second display element. And a display element group including a third display element,
A first scan line and a second scan line provided for each column of N display element groups arranged along the first direction and extending in the first direction; and
A first data line and a second data line provided in each column of M display element groups arranged along the second direction and extending in the second direction;
Each of the first display element, the second display element, and the third display element includes a drive circuit and a current-driven light emitting unit.
The driving circuit includes a gate electrode, a channel formation region, a write transistor having one source / drain region and the other source / drain region, and a gate electrode connected to the other source / drain region of the write transistor, a channel formation region A drive transistor having one source / drain region and the other source / drain region,
The light emitting part is electrically connected to the other source / drain region of the driving transistor,
In the display element group, the first display element, the second display element, and the third display element are arranged along the first direction, and one of the write transistors of the first display element and the second display element. The source / drain region is connected to the first data line, one source / drain region of the write transistor of the third display element is connected to the second data line, and the gate electrode of the write transistor of the first display element Is connected to the first scan line, the gate electrode of the write transistor of the second display element is connected to the second scan line, and the gate electrode of the write transistor of the third display element is connected to the first scan line and the second scan line. Connected to one of the scan lines,
The direction from one source / drain region of the drive transistor constituting the first display element toward the other source / drain region is constant in the display element group,
The direction from one source / drain region of the driving transistor constituting the second display element to the other source / drain region is constant in the display element group,
A display device in which a direction from one source / drain region to the other source / drain region of the driving transistor constituting the third display element is constant among the display element groups.   In the display element group, the direction from one source / drain region of the driving transistor constituting the first display element to the other source / drain region and one source / drain of the driving transistor constituting the second display element. The display device according to claim 1, wherein the direction is different from the direction from the drain region toward the other source / drain region.   In the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the first display element, and one source / drain region of the driving transistor constituting the second display element, and 3. The display device according to claim 2, wherein the other source / drain regions are arranged point-symmetrically.   In the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the first display element, and one source / drain region of the driving transistor constituting the second display element, and 3. The display device according to claim 2, wherein the other source / drain regions are arranged in line symmetry. The gate electrode of the write transistor of the third display element is connected to the second scanning line,
In the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the third display element, and one source / drain region of the driving transistor constituting the second display element, and The display device according to claim 1, wherein the other source / drain region is arranged in translational symmetry. The gate electrode of the write transistor of the third display element is connected to the second scanning line,
In the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the third display element, and one source / drain region of the driving transistor constituting the second display element, and The display device according to claim 1, wherein the other source / drain region is arranged in line symmetry. The gate electrode of the write transistor of the third display element is connected to the first scanning line,
In the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the third display element, and one source / drain region of the driving transistor constituting the first display element, and The display device according to claim 1, wherein the other source / drain region is arranged in translational symmetry. The gate electrode of the write transistor of the third display element is connected to the first scanning line,
In the display element group, one source / drain region and the other source / drain region of the driving transistor constituting the third display element, and one source / drain region of the driving transistor constituting the first display element, and The display device according to claim 1, wherein the other source / drain region is arranged in line symmetry. The display device further includes a power supply line provided for each column of N display element groups arranged along the first direction, and extending in the first direction.
2. The display device according to claim 1, wherein in the display element group, one source / drain region of the drive transistor of the first display element, the second display element, and the third display element is connected to a power supply line. N pieces in a first direction, M pieces in a second direction different from the first direction, and a total of N × M pieces, which are arranged in a two-dimensional matrix, are respectively a first display element and a second display element. And a display element group including a third display element,
A first scan line and a second scan line provided for each column of N display element groups arranged along the first direction and extending in the first direction; and
A first data line and a second data line provided in each column of M display element groups arranged along the second direction and extending in the second direction;
Each of the first display element, the second display element, and the third display element includes a drive circuit and a current-driven light emitting unit.
The driving circuit includes a gate electrode, a channel formation region, a write transistor having one source / drain region and the other source / drain region, and a gate electrode connected to the other source / drain region of the write transistor, a channel formation region A drive transistor having one source / drain region and the other source / drain region,
The light emitting part is electrically connected to the other source / drain region of the driving transistor,
In the display element group, the first display element, the second display element, and the third display element are arranged along the first direction, and one of the write transistors of the first display element and the second display element. The source / drain region is connected to the first data line, one source / drain region of the write transistor of the third display element is connected to the second data line, and the gate electrode of the write transistor of the first display element Is connected to the first scan line, the gate electrode of the write transistor of the second display element is connected to the second scan line, and the gate electrode of the write transistor of the third display element is connected to the first scan line and the second scan line. Connected to one of the scan lines,
The direction from one source / drain region of the drive transistor constituting the first display element toward the other source / drain region is constant in the display element group,
The direction from one source / drain region of the driving transistor constituting the second display element to the other source / drain region is constant in the display element group,
The direction from one source / drain region of the driving transistor constituting the third display element to the other source / drain region is a method for manufacturing a display device in which the display element groups are constant with respect to each other,
A driving transistor and a writing transistor each including a thin film transistor are provided, and then scanning with a laser beam is performed so that a semiconductor layer that forms a channel forming region of the driving transistor, one source / drain region, and the other source / drain region, and writing A method for manufacturing a display device, comprising: annealing a semiconductor layer that forms a channel formation region of a transistor, one source / drain region, and the other source / drain region. N pieces in a first direction, M pieces in a second direction different from the first direction, and a total of N × M pieces, which are arranged in a two-dimensional matrix, are respectively a first display element and a second display element. And a display element group including a third display element,
A first scan line and a second scan line provided for each column of N display element groups arranged along the first direction and extending in the first direction; and
A first data line and a second data line provided in each column of M display element groups arranged along the second direction and extending in the second direction;
Each of the first display element, the second display element, and the third display element includes a drive circuit and a current-driven light emitting unit.
The driving circuit includes a gate electrode, a channel formation region, a write transistor having one source / drain region and the other source / drain region, and a gate electrode connected to the other source / drain region of the write transistor, a channel formation region A drive transistor having one source / drain region and the other source / drain region,
The light emitting part is electrically connected to the other source / drain region of the driving transistor,
In the display element group, the first display element, the second display element, and the third display element are arranged along the first direction, and one of the write transistors of the first display element and the second display element. The source / drain region is connected to the first data line, one source / drain region of the write transistor of the third display element is connected to the second data line, and the gate electrode of the write transistor of the first display element Is connected to the first scan line, the gate electrode of the write transistor of the second display element is connected to the second scan line, and the gate electrode of the write transistor of the third display element is connected to the first scan line and the second scan line. Connected to one of the scan lines,
The direction from one source / drain region of the drive transistor constituting the first display element toward the other source / drain region is constant in the display element group,
The direction from one source / drain region of the driving transistor constituting the second display element to the other source / drain region is constant in the display element group,
The driving direction of the display device in which the direction from one source / drain region of the driving transistor constituting the third display element toward the other source / drain region is constant in the display element group,
A first scanning signal and a second scanning signal whose periods do not overlap each other are applied to the first scanning line and the second scanning line, respectively, so that the first display element is based on the first scanning signal. The writing transistor is turned on, the first video signal is applied from the first data line to the gate electrode of the driving transistor, and in the second display element, the writing transistor is turned on based on the second scanning signal. A second video signal is applied from one data line to the gate electrode of the driving transistor. In the third display element, when the gate electrode of the driving transistor is connected to the first scanning line, the first scanning signal is output. Accordingly, when the gate electrode of the driving transistor is connected to the second scanning line, the writing transistor is turned on based on the second scanning signal, and the third video signal is driven from the second data line. The driving method of a display apparatus for performing a writing process to be applied to the gate electrode of the transistor. The display device further includes a power supply line provided for each column of N display element groups arranged along the first direction, and extending in the first direction.
In the display element group, one source / drain region of the drive transistor of the first display element, the second display element, and the third display element is connected to the power supply line,
Prior to the first scanning signal and the second scanning signal, the third scanning signal is applied to the first scanning line and the second scanning line, and the writing transistors of the first display element, the second display element, and the third display element are made conductive. As a state, in the first display element and the second display element, a reference voltage is applied from the first data line to the gate electrode of the driving transistor, and in the third display element, the reference voltage is applied from the second data line. Is applied to the gate electrode of the driving transistor, and a predetermined driving voltage is applied from the feeder line to one of the source / drain regions of the driving transistors of the first display element, the second display element, and the third display element. A threshold voltage capacitor that changes the potential of the other source / drain region of the driving transistor of the one display element, the second display element, and the third display element toward a potential obtained by subtracting the threshold voltage of the driving transistor from the reference voltage. The driving method of a display device according to claim 11 for cell processing.   A writing process is performed in a state where a driving voltage is applied to one of the source / drain regions of the driving transistors of the first display element, the second display element, and the third display element, whereby the first display element and the second display The method for driving a display device according to claim 12, wherein the potential of the other source / drain region of the driving transistor of the element and the third display element is changed. The drive circuit further includes a capacitor having one electrode connected to the other source / drain region of the drive transistor and the other electrode connected to the gate electrode of the drive transistor,
In the first display element, a voltage corresponding to the first video signal is held in the capacitor unit by the writing process, and application of the first video signal to the gate electrode of the driving transistor is stopped, thereby A current corresponding to the value of the held voltage flows to the light emitting part through the driving transistor, and the light emitting part emits light,
In the second display element, a voltage corresponding to the second video signal is held in the capacitor unit by the writing process, and application of the second video signal to the gate electrode of the driving transistor is stopped, thereby A current corresponding to the value of the held voltage flows to the light emitting part through the driving transistor, and the light emitting part emits light,
In the third display element, a voltage corresponding to the third video signal is held in the capacitor unit by the writing process, and application of the third video signal to the gate electrode of the driving transistor is stopped, thereby The method for driving a display device according to claim 13, wherein a current corresponding to the value of the held voltage flows to the light emitting unit through the driving transistor, and the light emitting unit emits light.

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