JP2011114235A - Nonvolatile semiconductor storage device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device, having a laminate type memory structure, which has a hierarchic selective transistor having a simpler structure than before. <P>SOLUTION: A finned laminate structure having an interlayer insulating film 109 and a semiconductor layer 107 laminated alternately has a hierarchic selective transistor formation region R11 formed adjacently to a memory cell formation region R12 where a control gate electrode 118 is disposed via a charge storage layer 112 to cross the finned laminate structure, wherein hierarchical select gate electrodes 116, 117 are provided stepwise so that the hierarchical select gate electrodes covering side faces of semiconductor layers 107 of the finned laminate structure decrease in number, layer by layer, to cover the side faces of the semiconductor layers 107 via the charge storage layer 112 from above the finned laminate structure, and an impurity of a prescribed conductivity type is diffused in semiconductor layers 107 above a bottom-side semiconductor layer 107 among the semiconductor layers 107 covered with the hierarchical select gate electrodes 116, 117. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  In the field of NAND flash memory, a stacked memory is attracting attention in order to achieve high integration without being restricted by the resolution limit of lithography technology. Here, in order to reduce the number of steps when manufacturing a stacked memory, after processing a stacked structure having a semiconductor layer to be a plurality of memory layers into a fin shape, a control gate electrode is collectively formed, There has been proposed a system in which each semiconductor layer is exposed in a stepped manner at the end of the stacked structure, and a hierarchical selection transistor is formed to collectively select each memory layer stacked in this portion (see, for example, Patent Document 1).

  However, in the conventional NAND flash memory stacked structure, the process of providing the hierarchical selection gate electrode of the hierarchical selection transistor in each stacked memory layer tends to be complicated. Therefore, there is a problem that the number of steps increases. There is also a problem that the structure of the hierarchical selection transistor formed in this way is complicated.

JP 2008-78404 A

  It is an object of the present invention to provide a nonvolatile semiconductor memory device having a hierarchical selection transistor having a simpler structure as compared with the conventional nonvolatile semiconductor memory device having a stacked memory structure. Another object of the present invention is to provide a method for manufacturing a nonvolatile semiconductor memory device having a stacked memory structure, in which a hierarchical selection transistor can be formed without increasing the number of processes as compared with the conventional method. And

  According to one aspect of the present invention, a stacked structure in which interlayer insulating films and semiconductor layers are alternately stacked is disposed in a fin shape on a substrate, and intersects the fin-shaped stacked structure and is stacked. A memory cell transistor portion in which a control gate electrode is disposed via a charge storage layer so as to cover the side surface of the fin, and the fin-like laminated structure adjacent to a formation position of the memory cell portion of the fin-like laminated structure And a hierarchy selection transistor portion in which the hierarchy selection gate electrode is arranged by the number of laminations of the semiconductor layer through a gate dielectric film so as to intersect the gate dielectric film, the hierarchy selection gate electrode having the fin-like lamination structure The semiconductor layers are stepped so that the number of the semiconductor layers facing each other is reduced one by one, and the side surfaces of the semiconductor layers are covered from the top of the fin-like stacked structure through the gate dielectric film. Among the semiconductor layers whose side surfaces are covered by the respective level selection gate electrodes, impurities of a predetermined conductivity type are not diffused in the lowermost semiconductor layer, and the upper layer is higher than the lowermost semiconductor layer. A non-volatile semiconductor memory device is provided in which impurities of a predetermined conductivity type are diffused in the semiconductor layer.

  Further, according to one aspect of the present invention, the stacked structure in which the interlayer insulating films and the semiconductor layers are alternately stacked is arranged in a fin shape on the substrate, intersects with the fin-shaped stacked structure, and is stacked. A memory cell transistor portion in which a control gate electrode is disposed via a charge storage layer so as to cover a side surface of the semiconductor layer, and the fin-like stacked structure adjacent to the formation position of the memory cell portion. A hierarchical selection transistor section in which hierarchical selection gate electrodes are arranged in a number corresponding to the number of stacked semiconductor layers through a gate dielectric film so as to cover the side surfaces of the stacked semiconductor layers while crossing the stacked structure, The semiconductor layer covered by the hierarchy selection gate electrode includes a non-diffusion part in which impurities of a predetermined conductivity type are not diffused in a region of each semiconductor layer facing the hierarchy selection gate electrode. A diffusion part into which an impurity of a predetermined conductivity type is introduced, and the non-diffusion part has a region facing each of the layer selection gate regions of different semiconductor layers in each layer selection gate electrode. Thus, a nonvolatile semiconductor memory device is provided.

  Further, according to one aspect of the present invention, a first step of forming a stacked structure in which an interlayer insulating film and a semiconductor layer are alternately formed on a substrate so that the semiconductor layer has a plurality of layers; Between the second step of processing into a fin shape and the fin-shaped stacked structure on the layer selection transistor formation region of the substrate, the semiconductor layers are sequentially exposed at each formation position of the layer selection transistor. A third step of forming a stepped mask film, a fourth step of diffusing impurities into the semiconductor layer exposed from the mask film of the fin-like stacked structure, and after the fourth step, A fifth step of etching the mask film by one layer of the semiconductor layer, and a gate dielectric film so as to cover the exposed side surface of the semiconductor layer on the fin-like stacked structure after the fifth step. The sixth mechanic that forms And a seventh step of forming a gate electrode film on the gate dielectric film, and an eighth step of patterning the gate electrode so as to intersect the fin-like laminated structure. A non-volatile semiconductor memory device manufacturing method is provided.

  According to the present invention, in the nonvolatile semiconductor memory device having a stacked memory structure, it is possible to provide a nonvolatile semiconductor memory device having a hierarchical selection transistor having a simpler structure than conventional ones. Further, in a method for manufacturing a nonvolatile semiconductor memory device having a stacked memory structure, according to the present invention, a method for manufacturing a nonvolatile semiconductor memory device capable of forming a hierarchy selection transistor without increasing the number of steps as compared with the prior art. There is an effect that can be provided.

FIG. 1 is a cross-sectional view schematically showing an example of the structure of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIGS. 2-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 1). FIGS. 2-2 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 2). FIGS. 2-3 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 3). FIG. 2-4 is a sectional view schematically showing an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment (No. 4). 2-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 5). FIGS. 2-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 1st Embodiment (the 6). FIGS. 3-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 1). FIGS. 3-2 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 2). FIGS. 3-3 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 3). 3-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 4). 3-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 5). 3-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 6). 3-7 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 7). 3-8 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 2nd Embodiment (the 8). FIGS. 4-1 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 3rd Embodiment (the 1). FIGS. 4-2 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 3rd Embodiment (the 2). 4-3 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 3rd Embodiment (the 3). 4-4 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 3rd Embodiment (the 4). 4-5 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 3rd Embodiment (the 5). 4-6 is sectional drawing which shows typically an example of the procedure of the manufacturing method of the non-volatile semiconductor memory device by 3rd Embodiment (the 6).

  A nonvolatile semiconductor memory device and a manufacturing method thereof according to embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. In addition, cross-sectional views of the nonvolatile semiconductor memory device used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Furthermore, the film thickness shown below is an example and is not limited thereto.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing an example of the structure of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. FIG. 1A is a cross-sectional view in the bit line direction, and FIG. It is AA sectional drawing of (a), (c) is BB sectional drawing of (a). In addition, (a) is a cut surface in the position corresponding to a cut surface between fin-shaped laminated structures in (b). On the semiconductor substrate 101, a memory cell portion R1 in which memory cells such as a NAND flash memory are formed, and a peripheral circuit portion R2 in which a peripheral circuit for controlling the memory cells is formed are provided. Although not shown, a field effect transistor or the like is formed in the peripheral circuit portion R2.

  On the memory cell portion R1 of the semiconductor substrate 101, a fin-like stacked structure in which interlayer insulating films 109 and semiconductor layers 107 are alternately stacked is disposed. Here, a case where two semiconductor layers 107 are stacked is shown. Further, the fin-like laminated structure has a shape extending in the first direction, and a plurality of fin-like laminated structures are arranged in parallel in the second direction at predetermined intervals. Near the end of the fin-like stacked structure is a hierarchy selection transistor formation region R11 in which a hierarchy selection transistor is formed, and the other region is a memory cell formation region R12 in which a memory cell transistor is formed.

  In the memory cell formation region R12, a control gate electrode 118 is disposed via the charge storage layer 112 so as to intersect with the fin-like stacked structure, thereby constituting a memory cell transistor. Here, the control gate electrode 118 is disposed to face the side surface of the semiconductor layer 107 with the charge storage layer 112 interposed therebetween, and a channel region can be formed on the side surface of the semiconductor layer 107.

  Similarly, in the hierarchical selection transistor formation region R11, the hierarchical selection gate electrodes 116 and 117 are provided by the number of the semiconductor layers 107 in the fin-shaped stacked structure through the charge storage layer 112 so as to intersect the fin-shaped stacked structure. Arranged to constitute a hierarchical selection transistor. That is, in the case of FIG. 1, since the semiconductor layer 107 has two layers, two hierarchical selection gate electrodes 116 and 117 are provided. Further, the hierarchy selection gate electrodes 116 and 117 are disposed to face the side surface of the semiconductor layer 107 with the charge storage layer 112 interposed therebetween, and a channel region can be formed on the side surface of the semiconductor layer 107.

  Here, the hierarchy selection gate electrodes 116 and 117 of the respective hierarchy selection transistors have different lengths along the lamination direction of the fin-like laminated structure. Specifically, the number of semiconductor layers 107 covering the side faces increases one by one from the hierarchy selection transistor arranged on the memory cell formation region R12 side toward the hierarchy selection transistor arranged at the end of the fin-like stacked structure. Thus, the layer selection gate electrodes 116 and 117 are formed in a staircase pattern. Note that this is an example, and the hierarchical selection gate electrodes 116, staircases are formed so that the number of semiconductor layers 107 covering the side faces decreases one by one from the memory cell formation region R12 toward the end of the fin-like stacked structure. 117 may be formed.

  For example, in the case of FIG. 1, the hierarchical selection gate electrode 116 of the hierarchical selection transistor closest to the memory cell formation region R12 covers the side surface of the uppermost semiconductor layer 107, but the side surface of the lower semiconductor layer 107. The length is not covered. Here, a convex embedded insulating film 111 extending from the top surface of the substrate to the second-layer interlayer insulating film 109 is formed below the hierarchical selection gate electrode 116. The hierarchical selection gate electrode 117 of the hierarchical selection transistor formed on the opposite side of the hierarchical selection transistor formation region R11 to the memory cell formation region R12 is the uppermost semiconductor layer 107 and the second layer from the top (= the lowest layer). ) To cover the side surface of the semiconductor layer 107.

  Further, in the hierarchical selection transistor, a region of the semiconductor layer 107 that covers the side surface of the hierarchical selection gate electrode 117 has a high concentration in a region facing the hierarchical selection gate electrode 117 of the upper semiconductor layer 107 other than the lowermost semiconductor layer 107. Impurities are doped. As a result, in the semiconductor layer 107 doped with impurities, the depletion layer extends even when a voltage is applied to the hierarchy selection gate electrode 117 of the hierarchy selection transistor because the semiconductor layer 107 is always turned on even if the hierarchy selection transistor is formed. The continuity is not interrupted. Further, since the lowermost semiconductor layer 107 covered by the hierarchy selection gate electrodes 116 and 117 of the hierarchy selection transistor is not doped with impurities, when a voltage is applied to the hierarchy selection gate electrodes 116 and 117, the depletion layer is extended. The conduction can be cut off. With such a structure, each of the hierarchical selection gate electrodes 116 and 117 can block each semiconductor layer 107 independently. The hierarchical selection gate electrode 116 selects the uppermost semiconductor layer 107, and the hierarchical selection gate electrode. 117 functions as a gate for selecting the semiconductor layer 107 of the second layer (lowermost layer).

  Here, the material of the semiconductor substrate 101 and the semiconductor layer 107 can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, or InGaAsP. Further, the semiconductor layer 107 may be made of a single crystal semiconductor, may be made of a polycrystalline semiconductor, or may be made of a continuous grain boundary crystal semiconductor (Continuous Grain Semiconductor). Good. Note that a continuous grain boundary crystal semiconductor can be formed by crystallizing a polycrystalline silicon film by a laser annealing method or a Ni catalyst method.

As the charge storage layer 112, for example, an ONO (silicon oxide film / silicon nitride film / silicon oxide film) structure or an ANO (aluminum oxide film / silicon nitride film / silicon oxide film) structure may be used. Alternatively, a floating gate structure may be used. Alternatively, instead of an aluminum oxide film having an ANO structure, a metal oxide film such as HfO ₂ , La ₂ O ₃ , Pr ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , or a combination of a plurality of such metal oxide films is used. A film may be used.

  Further, as a material of the interlayer insulating film 109, for example, a silicon oxide film may be used, or an organic film may be used.

  The material of the control gate electrode 118 and the hierarchy selection gate electrodes 116 and 117 can be, for example, polycrystalline silicon. In FIG. 1, the control gate electrode 118 of the memory cell of the memory cell part R1, the hierarchy selection gate electrodes 116 and 117 of the hierarchy selection transistor, and the gate electrode of the field effect transistor of the peripheral circuit part R2 are the first gate. Although the electrode film 113 and the second gate electrode film 114 are stacked, different materials may be stacked, or the same kind of materials may be stacked.

Next, a method for manufacturing the nonvolatile semiconductor memory device having such a structure will be described. 2-1 to 2-6 are cross-sectional views schematically showing an example of the procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment. In these drawings, (a) shows a cross section in the bit line direction, (b) shows a cross section in AA of (a), and is a cross section in the word line direction of one hierarchical selection transistor. (C) is a cross-sectional view taken along the line BB of (a), and is a cross-sectional view in the word line direction of another hierarchical selection transistor. In the manufacturing method described below, a cell corresponding to the 19 nm generation in a planar structure is formed by stacking two memory cells having a design in which the bit line half pitch is 32 nm and the word line half pitch is 22 nm. A flash memory realizing an area of 1,320 nm ² will be described as an example.

  First, the structure shown in FIG. 2-1 is formed. Here, the peripheral circuit portion R2 is formed first. That is, the gate insulating film 102 of the peripheral circuit portion R2 is formed on the semiconductor substrate 101 by performing thermal oxidation of the semiconductor substrate 101. As this gate insulating film 102, for example, a silicon thermal oxide film can be used. Then, a gate electrode film 103 which is a part of the gate electrode of the peripheral circuit is formed by a film forming method such as a CVD (Chemical Vapor Deposition) method, and further a stopper film serving as a stopper in a subsequent CMP (Chemical Mechanical Polishing) process 104 are sequentially formed by a film forming method such as a CVD method. An n-type polycrystalline silicon film can be used as the gate electrode film 103, and a silicon nitride film can be used as the stopper film 104. Further, the thickness of the gate electrode film 103 can be set to, for example, about 110 nm, and the thickness of the stopper film 104 can be set to, for example, about 30 nm.

Thereafter, the stopper film 104, the gate electrode film 103, the gate insulating film 102, and the semiconductor substrate 101 of the peripheral circuit portion R2 are formed on the STI (reactive ion etching (RIE) method) (hereinafter referred to as RIE (Reactive Ion Etching) method). An isolation groove (not shown) to be Shallow Trench Isolation) is formed. Next, a buried insulating film (not shown) is formed so as to be buried in the isolation trench. As this buried insulating film, for example, a high density plasma enhanced SiO ₂ (HDP-SiO ₂ ) film or a TEOS (Tetraethyl orthosilicate) / O ₃ film can be used. Then, planarization is performed by a CMP technique until the stopper film 104 is exposed. Through the above processing, an STI (not shown) is formed in the peripheral circuit portion R2.

  Next, the stopper film 104, the gate electrode film 103, and the gate insulating film 102 of the memory cell portion R1 are removed by lithography and RIE, and the semiconductor substrate 101 is further dug to form a recess in the memory cell portion R1.

  Subsequently, an HTO (High Temperature Oxide) film 105 is formed on the entire surface of the semiconductor substrate 101 with a thickness of, for example, 30 nm by a method such as a CVD method, and etched back by the RIE method. Bottom) and the HTO film 105 on the stopper film 104 is removed, leaving the HTO film 105 only on the side walls of the recess. Then, the clean surface of the semiconductor substrate 101 is exposed by dilute hydrofluoric acid treatment.

  Next, the semiconductor layers 106 and 107 are alternately stacked by LPCVD (Low Pressure CVD) method so that the uppermost layer ends with the semiconductor layer 106. At this time, it is desirable that the semiconductor layers 106 and 107 are epitaxially grown on the underlying semiconductor layer. For the semiconductor layer 106, a semiconductor material having a higher etching rate than that of the semiconductor layer 107 is selected. As materials of such semiconductor layers 106 and 107, for example, lattice matching can be achieved from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, GaInAsP, and the like. The selected combination can be used. Here, an epitaxial silicon germanium film is used as the semiconductor layer 106, and an epitaxial silicon film doped with P is used as the semiconductor layer 107. The film thicknesses of the semiconductor layers 106 and 107 are, for example, 20 nm, 45 nm, 20 nm, 45 nm, and 20 nm in order from the bottom.

  Note that since the semiconductor layers 106 and 107 are not epitaxially grown in the vicinity of the HTO film 105 formed on the side wall of the recess, an inclined surface is generated around the stacked structure of the semiconductor layers 106 and 107, and the HTO film 105. A wedge-shaped recess is formed between the semiconductor layer 106 and the stacked structure of the semiconductor layers 106 and 107.

  Thereafter, a planarizing film 108 is formed on the entire surface of the semiconductor substrate 101 by a film forming method such as a CVD method. As the planarizing film 108, for example, a silicon oxide film can be used. Then, the planarization film 108 is planarized by the CMP method or the like until the stopper film 104 is exposed in the peripheral circuit portion R2. Thus, the structure shown in FIG. 2-1 is formed.

  Next, as shown in FIG. 2B, a trench (not shown) is formed by a lithography technique and an RIE method, and the planarizing film 108 and the semiconductor layers 106 and 107 of the memory cell portion R1 are appropriately sized. Divide into strips. As a result, the side walls of the semiconductor layers 106 and 107 are exposed at a predetermined interval. Subsequently, a gap is formed between the upper and lower semiconductor layers 107 by selectively removing the semiconductor layer 106 by wet etching. Here, since the epitaxial silicon germanium film is used for the semiconductor layer 106 and the epitaxial silicon film is used for the semiconductor layer 107, the silicon germanium film is selectively etched as compared with the silicon film as a chemical solution for wet etching. Thus, for example, a hydrofluoric acid / nitric acid / acetic acid mixed solution can be used. Note that the semiconductor layer 106 may be selectively removed by a CDE (Chemical Dry Etching) method.

  Thereafter, the upper and lower surfaces of the semiconductor layer 107 are steam-oxidized through the trench, thereby completely filling the voids in which the semiconductor layer 106 between the semiconductor layers 107 is removed with the interlayer insulating film 109. For example, a silicon thermal oxide film can be used as the interlayer insulating film 109. Note that as a method of forming the interlayer insulating film 109 embedded between the semiconductor layers 107, a CVD method or an ALD (Atomic Layer Deposition) method may be used in addition to the above-described steam oxidation of the semiconductor layer 107. Alternatively, an SOG (Spin On Glass) film may be embedded by a coating method, or a liquid organic insulating film may be immersed in a gap between the semiconductor layers 107 and then cured.

Next, a trench 110a for forming a bit line contact is formed by lithography and RIE. Here, the laminated film of the interlayer insulating film 109 and the semiconductor layer 107 is collectively processed into a band shape at the peripheral edge where the semiconductor layers 107 and the interlayer insulating films 109 of the memory cell portion R1 are alternately and completely laminated, and trenches are formed. 110a is formed. As a result, the side surfaces of the two semiconductor layers 107 are exposed. Subsequently, heat treatment is performed in a gas atmosphere containing an impurity element for making the semiconductor layer 107 have a predetermined conductivity type, so that impurities are introduced into the semiconductor layer 107. Here, P of 1 × 10 ²⁰ cm ⁻³ or more is doped by performing heat treatment in a PH ₃ atmosphere of 20 Torr at 850 ° C. for 5 minutes. Thereafter, the contact layer 110 is formed on the entire surface of the semiconductor substrate 101 so as to fill the trench 110a. As contact layer 110, for example, an n-type polycrystalline silicon film can be used. Then, the entire surface is etched back by the RIE method, and the contact layer 110 formed on the upper surface of the planarizing film 108 is removed. As a result, a bit line contact is formed in the trench 110a.

  Thereafter, the laminated film of the interlayer insulating film 109 / semiconductor layer 107 of the memory cell portion R1 is collectively processed into a band-shaped structure (fin structure) extending in the first direction by lithography and RIE. As a result, a plurality of fin structures are formed in parallel in the second direction at a predetermined interval, and the side surface of the semiconductor layer 107 is exposed. The semiconductor layer 107 becomes an active region (active area). The width of the fin structure can be set to 20 nm, for example, and the half pitch of the fin structure can be set to 32 nm, for example. Then, the stopper film 104 is removed by wet etching. When the stopper film 104 is composed of a silicon nitride film, hot phosphoric acid can be used as a chemical solution for wet etching. As a result, the structure shown in FIG. 2-2 is obtained.

Next, as shown in FIG. 2-3, a buried insulating film 111 is formed between the fin structures by a film forming method such as a CVD method. As the buried insulating film 111, a TEOS / O ₃ film can be used. Thereafter, the buried insulating film 111 is partially etched using a lithography technique and an RIE method. Here, of the two hierarchy selection transistors, the one adjacent to the memory cell transistor is the first hierarchy selection transistor, and the other is the second hierarchy selection transistor. The region to be etched is the hierarchy of the memory cell portion R1. The selection transistor formation region R11 is a region R3 that includes the formation region of the second hierarchy selection transistor and does not include the formation region of the first hierarchy selection transistor. In this region R3, the side surface of the uppermost semiconductor layer 107 is exposed, and etching is performed to a depth at which the lowermost semiconductor layer 107 is not exposed.

Next, after pretreatment with dilute hydrofluoric acid, impurities of a predetermined conductivity type are diffused from the exposed side surfaces of the semiconductor layer 107. As a method for diffusing impurities into the semiconductor layer 107, GPD (Gas Phase Doping) can be used. For example, the epitaxial silicon film as the semiconductor layer 107 is doped with P of 1 × 10 ¹⁹ cm ⁻³ or more by performing heat treatment for 10 minutes in a PH ₃ atmosphere of 0.1 Torr at a temperature of 850 ° C. In the region of the semiconductor layer 107 doped with P, a voltage is applied to a layer selection gate electrode that selects a layer stacked after a charge storage layer as a gate dielectric film of the layer selection transistor is formed. However, since depletion does not occur, the transistor is always “on”.

  Thereafter, as shown in FIG. 2-4, the buried insulating film 111 formed in the memory cell formation region R12 is etched back by lithography and RIE. As a result, the side surface of the semiconductor layer 107 is exposed in the memory cell formation region R12. Further, the buried insulating film 111 is etched back over the entire surface of the semiconductor substrate 101 by a thickness corresponding to one layer of the laminated film of the interlayer insulating film 109 / semiconductor layer 107. Thus, the side surface of the lowermost semiconductor layer 107 is exposed in the formation region of the second hierarchy selection transistor, and the side surface of the uppermost semiconductor layer 107 is exposed in the formation region of the first hierarchy selection transistor. The side surface of the lower semiconductor layer 107 is covered with the buried insulating film 111.

  Next, as shown in FIG. 2-5, after the pretreatment with dilute hydrofluoric acid, the side surface of the semiconductor layer 107 is covered by a film formation method such as a CVD method so that the fin structure and the first structure A charge storage layer 112 is formed over the gate electrode film 103. As the charge storage layer 112, for example, an ONO film made of silicon oxide film / silicon nitride film / silicon oxide film can be used, and the film thicknesses at this time are set to 13 nm in total from 3 nm, 2 nm, and 8 nm in order from the bottom. be able to.

  Next, a gate electrode that becomes a part of the control gate electrode 118 of the memory cell transistor and a part of the hierarchy selection gate electrodes 116 and 117 of the hierarchy selection transistor is formed on the entire surface of the semiconductor substrate 101 by a film formation method such as a CVD method. A film 113 is formed. As gate electrode film 113, for example, an n-type polycrystalline silicon film can be used. The film thickness of the gate electrode film 113 can be set to about 40 nm, for example.

  Next, a part of the gate electrode film 113 and the charge storage layer 112 that become the gate electrode of the peripheral circuit portion R <b> 2 is removed by the lithography technique and the RIE method, and an opening 121 that communicates with the gate electrode film 103 is formed. Subsequently, a gate electrode film 114 that becomes a part of the control gate electrode 118 of the memory cell transistor, a part of the hierarchy selection gate electrodes 116 and 117 of the hierarchy selection transistor, and a part of the gate electrode of the peripheral circuit is formed by CVD. It is formed on the entire surface of the semiconductor substrate 101 by a film forming method such as a method. As gate electrode film 114, for example, an n-type polycrystalline silicon film can be used. The film thickness of the gate electrode film 114 can be set to, for example, about 150 nm. Thus, the gate electrode film 103 and the gate electrode film 114 of the peripheral circuit are electrically connected. Thereafter, a mask film 115 for processing the gate electrode of the transistor formed in the memory cell portion R1 is formed on the gate electrode film 114 by a film forming method such as a CVD method. As this mask film 115, for example, a silicon nitride film can be used. The film thickness of the mask film 115 can be set to 100 nm, for example. Thus, the structure shown in FIG. 2-5 is formed.

  Thereafter, as shown in FIG. 2-6, the mask film 115 is patterned by the lithography technique and the RIE method so as to correspond to the planar shapes of the control gate electrode 118 and the hierarchy selection gate electrodes 116 and 117 in the memory cell portion R1. . Then, the gate electrode films 114 and 113 and the charge storage layer 112 are collectively etched by the RIE method through the mask film 115. Thus, the control gate electrode 118 and the hierarchy selection gate electrode 116 disposed via the charge storage layer 112 so as to intersect with the fin structure extending in the first direction (extending in the second direction). , 117 are formed in the memory cell portion R1. At this time, although not shown, the gate electrode is also processed in the peripheral circuit portion R2. Note that the half pitch of the control gate electrode 118 of the memory cell portion R1 can be set to 22 nm, for example. At this time, since the buried insulating film 111 is partially formed in the hierarchical selection gate electrodes 116 and 117, the depth at which the gate electrode is formed differs depending on the location. For this reason, the lengths of the hierarchy selection gate electrodes 116 and 117 are increased stepwise from the side close to the memory cell formation region R12 toward the end of the fin structure.

  Thereafter, although not shown, the sidewalls of the control gate electrode 118 and the hierarchy selection gate electrodes 116 and 117 are oxidized by high-temperature and short-time oxidation using radicals generated from a hydrogen / oxygen mixed gas, and the control gate electrode 118 and the hierarchy selection are selected. By burning out the polycrystalline silicon film remaining between adjacent gate electrodes due to insufficient processing of the gate electrodes 116 and 117, these short circuits are prevented and processing damage is removed.

  Next, a sidewall spacer film of the peripheral circuit portion R2 is formed, and a buried insulating film (not shown) is formed so as to be buried between the control gate electrode 118 and the hierarchy selection gate electrodes 116 and 117 of the memory cell portion R1. As this buried insulating film, for example, a BPSG (Boron Phosphorus doped Silicate Glass) film or the like can be used. Further, although not shown, the diffusion layer of the peripheral circuit portion R2 is formed by lithography, ion implantation, and activation annealing. Then, an interlayer insulating film is formed, a contact to the diffusion layer / gate electrode is formed, and a multilayer wiring layer is formed to form a flash memory circuit.

  In the first embodiment, the charge storage layer 112 and the control gate electrode 118 are formed so as to intersect the fin structure extending in the first direction in which a plurality of semiconductor layers 107 and interlayer insulating films 109 are alternately stacked. A memory cell transistor was formed, and the same number of layer selection transistors as the number of semiconductor layers 107 were provided at the end of the fin structure so as to cross the fin structure. Therefore, it has an effect that the structure of the hierarchical selection transistor is simplified as compared with the prior art.

  Further, the hierarchy selection gate electrodes 116 and 117 of the hierarchy selection transistor have the same upper position, and the number of the semiconductor layers 107 covering the side surface increases one by one in order from the side where the lower position contacts the memory cell transistor. Of the semiconductor layers 107 that are formed stepwise so as to decrease one layer at a time and are covered with the hierarchical selection gate electrodes 116 and 117, the semiconductor layer 107 that is higher than the lowermost semiconductor layer 107 is formed in the semiconductor layer 107. Impurities of a predetermined conductivity type are diffused. Accordingly, there is an effect that conduction in each semiconductor layer 107 can be cut off independently by each hierarchical selection transistor.

  Furthermore, a memory cell transistor having a DG-FinFET (Double Gate Fin Field Effect Transistor) structure can be formed over a plurality of layers. In this DG-FinFET structure, since it is strong in the short channel effect and has a strong channel dominance, multi-value storage such as 2 bits / cell (= 4 values), 3 bits / cell (= 8 values) can be easily performed. This can be realized and the storage density can be doubled.

  In addition, the formation of the hierarchy selection transistor can be performed simultaneously with the formation of the memory cell transistor, and the semiconductor layer 107 and the control gate electrode 118 that require the finest processing technology are the same as those in a normal non-stacked memory. Processing can be performed in a single lithography process, and the hierarchical selection transistor can be manufactured without increasing the number of processes as compared with the prior art. Further, the semiconductor layer 107 can be doped with impurities without embedding a film containing impurities between the fin-like stacked structures.

  In the above description, the case where the single crystal silicon film and the silicon oxide film are stacked to perform batch processing has been shown. Instead, the polycrystalline silicon film and the silicon oxide film are stacked to perform batch processing. You may make it perform.

(Second Embodiment)
In the first embodiment, the introduction of impurities into the hierarchical selection gate electrode is performed by GPD. In the second embodiment, a case of performing the solid phase diffusion method will be described. In the following description, a method for manufacturing a flash memory having a structure in which six semiconductor layers are stacked in a fin-shaped stacked structure will be described.

3-1 to 3-8 are cross-sectional views schematically showing an example of the procedure of the method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment. In these drawings, (a) shows a cross section in the bit line direction, (b) shows a CC cross section in (a), and is a cross section in the word line direction of the hierarchical selection transistor. Moreover, (a) is a cut surface between the fin structures of (b) or a cut surface at a position corresponding thereto. In this manufacturing method, by stacking six layers of memory cells having a design in which the half pitch of the bit lines is 43 nm and the half pitch of the word lines is 22 nm, the cell area corresponding to the 12 nm generation in the planar structure is 631 nm. ^Take flash memory that implements ² as an example.

  First, as shown in FIG. 3A, the gate insulating film 202 of the peripheral circuit portion R <b> 2 is formed on the semiconductor substrate 201. As this gate insulating film 202, for example, a silicon thermal oxide film can be used. Next, a gate electrode film 203 which is a part of the gate electrode of the peripheral circuit is formed by a film forming method such as a CVD method, and a stopper film 204 serving as a stopper at a later CMP process is formed by a film forming method such as a CVD method. Form in order. As the gate electrode film 203, an n-type polycrystalline silicon film can be used, and as the stopper film 204, a silicon nitride film can be used. Further, the thickness of the gate electrode film 203 can be set to, for example, about 110 nm, and the thickness of the stopper film 204 can be set to, for example, about 30 nm.

Next, the stopper film 204, the gate electrode film 203, and the gate insulating film 202 are etched by a lithography technique and an RIE method to form an isolation groove (not shown) that becomes the STI of the peripheral circuit portion R2. Here, unlike the first embodiment, the trench 205a is formed by digging down the memory cell portion R1 as well as forming the isolation trench. Thereafter, a buried insulating film 205 is formed so as to fill the isolation trench and the trench 205a. As the buried insulating film 205, for example, an HDP-SiO ₂ film or a TEOS / O ₃ film can be used. Then, planarization is performed by a CMP technique until the stopper film 204 is exposed. Through the above processing, the STI of the peripheral circuit portion R2 is formed and the trench 205a of the memory cell portion R1 is filled with the buried insulating film 205.

  Next, as shown in FIG. 3B, the embedded insulating film 205 embedded in the trench 205a of the memory cell portion R1 is etched back by lithography and RIE, and the embedded insulating film 205 is formed only on the sidewall of the trench 205a. Leave. Then, the clean surface of the semiconductor substrate 101 is exposed by dilute hydrofluoric acid treatment.

  Next, a plurality of semiconductor layers 206 and 207 are alternately stacked by LPCVD, and the uppermost layer ends with the semiconductor layer 206. At this time, it is desirable that the semiconductor layers 206 and 207 be epitaxially grown on the underlying semiconductor layer. For the semiconductor layer 206, a semiconductor material having a higher etching rate than that of the semiconductor layer 207 is selected. As materials for such semiconductor layers 206 and 207, for example, lattice matching can be obtained from Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, GaInAsP, and the like. The selected combination can be used. Here, an epitaxial silicon germanium film is used as the semiconductor layer 206, and an epitaxial silicon film doped with B is used as the semiconductor layer 207. Further, the semiconductor layers 206 and 207 are formed to have a thickness of, for example, 15 nm, 25 nm, 15 nm, 25 nm, 15 nm, 25 nm, 15 nm, 25 nm, 15 nm, 25 nm, 15 nm, 25 nm, and 10 nm in order from the bottom. It is assumed that six layers 207 are stacked.

  Note that since the epitaxial growth of the semiconductor layers 206 and 207 is not performed in the vicinity of the buried insulating film 205 formed on the sidewall of the trench 205a, an inclined surface is generated around the stacked structure of the semiconductor layers 206 and 207, and buried. A wedge-shaped recess is formed between the insulating film 205 and the stacked structure of the semiconductor layers 206 and 207.

  Thereafter, a planarizing film 208 is formed on the entire surface of the semiconductor substrate 201 by a film forming method such as a CVD method. As the planarizing film 208, for example, a silicon oxide film can be used. Then, the planarization film 208 is planarized by the CMP method or the like until the stopper film 204 is exposed in the peripheral circuit portion R2.

  Next, as shown in FIG. 3C, a trench (not shown) is formed by lithography and RIE, and the planarizing film 208, the semiconductor layer 206, and the semiconductor layer 207 of the memory cell portion R1 are appropriately sized. Divide into strips. As a result, the side walls of the semiconductor layers 206 and 207 are exposed at a predetermined interval.

  Subsequently, a gap is formed between the upper and lower semiconductor layers 207 by selectively removing the semiconductor layer 206 by wet etching. Here, since the epitaxial silicon germanium film is used for the semiconductor layer 206 and the epitaxial silicon film is used for the semiconductor layer 207, the silicon germanium film can be selectively etched as compared with the silicon film as a chemical solution for wet etching. For example, a mixed solution of hydrofluoric acid / nitric acid / acetic acid can be used. Note that the semiconductor layer 206 may be selectively removed by a CDE method.

  After that, the upper and lower surfaces of the semiconductor layer 207 are steam-oxidized through the trench (not shown), thereby completely filling the space where the semiconductor layer 206 between the semiconductor layers 207 is removed with the interlayer insulating film 209. For example, a silicon thermal oxide film can be used as the interlayer insulating film 209. Note that as a method of forming the interlayer insulating film 209 embedded between the semiconductor layers 207, a CVD method or an ALD method may be used in addition to the steam oxidation of the semiconductor layer 207 described above. Alternatively, the SOG film may be embedded by a coating method, or the liquid organic insulating film may be immersed in the gap between the semiconductor layers 207 and then cured.

Next, a trench 210a for forming a bit line contact is formed by lithography and RIE. Here, the laminated film of the interlayer insulating film 209 and the semiconductor layer 207 is collectively processed into a belt-like shape at the peripheral edge where the semiconductor layers 207 and the interlayer insulating films 209 of the memory cell portion R1 are alternately and completely laminated. 210a is formed. As a result, the side surfaces of the six semiconductor layers 207 are exposed. Subsequently, heat treatment is performed in a gas atmosphere containing an impurity element for making the semiconductor layer 207 have a predetermined conductivity type, so that impurities are introduced into the semiconductor layer 207. Here, P of 1 × 10 ²⁰ cm ⁻³ or more is doped by performing heat treatment in a PH ₃ atmosphere of 20 Torr at a temperature of 850 ° C. for 5 minutes. Thereafter, the contact layer 210 is formed on the entire surface of the semiconductor substrate 201 so as to fill the trench 210a. As contact layer 210, for example, an n-type polycrystalline silicon film can be used. Then, the entire surface is etched back by the RIE method, and the contact layer 210 formed on the upper surface of the planarizing film 208 is removed. As a result, a bit line contact is formed in the trench 210a.

  Thereafter, the laminated film of the interlayer insulating film 209 / semiconductor layer 207 of the memory cell portion R1 is collectively processed into a band-shaped structure (fin structure) extending in the first direction by lithography and RIE. As a result, a plurality of fin structures are formed in parallel in the second direction at a predetermined interval, and the side surface of the semiconductor layer 207 is exposed. Note that the semiconductor layer 207 becomes an active region. The width of the fin structure can be set to 30 nm, for example, and the half pitch of the fin structure can be set to 43 nm, for example.

Next, as shown in FIG. 3-4, a buried insulating film 211 is formed between the fin structures by a film forming method such as a CVD method. As the buried insulating film 211, a TEOS / O ₃ film can be used. Thereafter, the buried insulating film 211 is partially etched by using a lithography technique and an RIE method. Here, if the first, second,..., And sixth hierarchy selection transistors are to be formed in order from the closest to the memory cell formation region R12 among the hierarchy selection transistors to be formed later, the region to be etched is the hierarchy selection transistor. Of the transistor formation region R11, the fourth to sixth layer selection transistor formation region R4 is used. Further, in this region R4, the side surfaces of the uppermost layer to the third layer semiconductor layer 207 are exposed, and etching is performed to such a depth that the fourth layer to the lowermost layer (sixth layer) semiconductor layer 207 is not exposed.

  Next, as shown in FIG. 3-5, the process of partially etching the buried insulating film 211 using the lithography technique and the RIE method is further repeated twice, so that the buried insulating film 211 has five steps. To be processed. As a result, the side surfaces of all the semiconductor layers 207 are covered with the buried insulating film 211 in the formation region of the first hierarchy selection transistor, and the side surfaces of the uppermost semiconductor layer 207 are exposed in the formation region of the second hierarchy selection transistor. In the third layer selection transistor formation region, the uppermost layer and the side surface of the second semiconductor layer 207 from the top are exposed, and in the sixth layer selection transistor formation region, the uppermost layer to the fifth layer are exposed. The side surface of the semiconductor layer 207 is exposed.

Next, as shown in FIG. 3-6, after pretreatment with dilute hydrofluoric acid, a diffusion source film 212 containing impurities of a predetermined conductivity type is formed between the fin structures, and heat treatment is performed, thereby diffusion. Impurities are diffused from the source film 212 to the semiconductor layer 207. As the diffusion source film 212, for example, a PSG (Phosphorous doped Silicate Glass) film doped with 6 atomic% of P can be used. The film thickness of the diffusion source film 212 can be set to a thickness of 20 nm, for example. Further, as the heat treatment, RTA (Rapid Thermal Annealing) treatment can be performed at a temperature of 1,000 ° C. Thus, the semiconductor layer 207 is doped with P of 1 × 10 ¹⁹ cm ⁻³ or more. In the region of the semiconductor layer 207 doped with P, depletion does not occur even when a voltage is applied to a layer selection gate electrode that selects a layered layer after the charge storage layer is formed. Turns on.

Next, the diffusion source film 212 is selectively removed by wet etching. As the chemical solution for wet etching, for example, dilute hydrofluoric acid (DHF) can be used when the diffusion source film 212 is a PSG film. Since the wet etching rate of the PSG film when using dilute hydrofluoric acid is more than 10 times that of the TEOS / O ₃ film constituting the buried insulating film 211 even after RTA treatment at 1,000 ° C., selective removal is possible. It becomes.

  Thereafter, as shown in FIG. 3-7, the buried insulating film 211 is etched back for one layer of the stacked memory layers by the RIE method. As a result, the side surface of the uppermost semiconductor layer 207 is exposed in the formation region of the first layer selection transistor, and the side surface of the second semiconductor layer 207 is exposed in the formation region of the second layer selection transistor. ..., the side surface of the sixth semiconductor layer 207 is exposed in the formation region of the sixth layer selection transistor. Furthermore, the upper surface of the contact layer 210 is also etched back.

  Next, the embedded insulating film 211 formed in the memory cell formation region R12 is etched back by lithography and RIE. As a result, the side surface of the semiconductor layer 207 is exposed in the memory cell formation region R12. Then, the stopper film 204 and the planarizing film 208 above the uppermost interlayer insulating film 209 are removed by wet etching. When the stopper film 204 is formed of a silicon nitride film and the planarization film 208 is formed of a silicon oxide film, hot phosphoric acid can be used as a chemical solution for wet etching.

  Next, as shown in FIG. 3-8, after the pretreatment with diluted hydrofluoric acid, the side surface of the semiconductor layer 207 is covered by a film forming method such as a CVD method so that the fin structure and the gate electrode film are covered. A charge storage layer 213 is formed on 203. As the charge storage layer 213, for example, an ANO film made of alumina film / silicon nitride film / silicon oxide film can be used, and the film thicknesses at this time are set to 18 nm in total from 13 nm, 2 nm, and 3 nm in this order. Can do.

  Next, a gate electrode that becomes a part of the control gate electrode 223 of the memory cell transistor and a part of the hierarchy selection gate electrodes 217 to 222 of the hierarchy selection transistor is formed on the entire surface of the semiconductor substrate 201 by a film formation method such as a CVD method. A film 214 is formed. As gate electrode film 214, for example, a p-type polycrystalline silicon film can be used. The film thickness of the gate electrode film 214 can be set to, for example, about 40 nm.

  Next, a part of the gate electrode film 214 and the charge storage layer 213 in the gate electrode formation portion of the peripheral circuit portion R2 is removed by a lithography technique and an RIE method, and an opening 230a communicating with the gate electrode film 203 is formed. Subsequently, a gate electrode film 215 that becomes a part of the control gate electrode 223 of the memory cell transistor, becomes a part of the hierarchy selection gate electrodes 217 to 222 of the hierarchy selection transistor, and further becomes a part of the gate electrode of the peripheral circuit portion R2. The film is formed on the entire surface of the semiconductor substrate 201 by a film forming method such as a CVD method. As gate electrode film 215, for example, an n-type polycrystalline silicon film can be used. The film thickness of the gate electrode film 215 can be set to, for example, about 150 nm. Thus, the gate electrode film 203 and the gate electrode film 215 of the peripheral circuit are electrically connected.

  Thereafter, a mask film 216 for processing the gate electrode of the transistor formed in the memory cell portion R1 is formed on the gate electrode film 215 by a film forming method such as a CVD method. As the mask film 216, for example, a silicon nitride film can be used. The film thickness of the mask film 216 can be set to 100 nm, for example.

  Thereafter, the mask film 216 is patterned by the lithography technique and the RIE method so as to correspond to the planar shapes of the control gate electrode 223 and the hierarchy selection gate electrodes 217 to 222 in the memory cell portion R1. Then, the gate electrode films 215 and 214 and the charge storage layer 213 are collectively etched by the RIE method through the mask film 216. Accordingly, the control gate electrode 223 and the hierarchy selection gate electrode 217 arranged via the charge storage layer 213 so as to intersect with the fin structure extending in the first direction (extending in the second direction). To 222 are formed in the memory cell portion R1. At this time, although not shown, the gate electrode is also processed in the peripheral circuit portion R2. The half pitch of the control gate electrode 223 of the memory cell portion R1 can be set to 22 nm, for example. At this time, since the buried insulating film 211 is partially formed in the hierarchy selection gate electrodes 217 to 220, the depth at which the gate electrode is formed differs depending on the location. Therefore, the length of the hierarchy selection gate electrodes 217 to 222 increases in a stepped manner from the side close to the memory cell formation region R12 toward the end of the fin structure. As a result, the structure shown in FIGS. 3-8 is obtained.

  Thereafter, although not shown, the sidewalls of the control gate electrode 223 and the hierarchy selection gate electrodes 217 to 222 are oxidized by high-temperature and short-time oxidation using radicals generated from a hydrogen / oxygen mixed gas, and the control gate electrode 223 and the hierarchy selection are performed. The polycrystalline silicon film remaining between adjacent gate electrodes due to insufficient processing of the gate electrodes 217 to 222 is burned out. This prevents these short circuits and removes processing damage. Next, a sidewall spacer film of the peripheral circuit portion R2 is formed by a film forming method such as an ALD method, and embedded so that the space between the control gate electrode 223 and the hierarchy selection gate electrodes 217 to 222 of the memory cell portion R1 is embedded. An insulating film is formed. As this buried insulating film, for example, a BPSG film can be used. Further, the diffusion layer of the peripheral circuit portion is formed by lithography, ion implantation, and activation annealing. Then, an interlayer insulating film is formed, a contact to the diffusion layer / gate electrode is formed, and a multilayer wiring layer is formed to form a flash memory circuit. As described above, the nonvolatile semiconductor memory device according to the second embodiment is completed.

  As shown in FIG. 3-8, the lengths of the hierarchy selection gate electrodes 217 to 222 of the first to sixth hierarchy selection transistors are formed stepwise, and the hierarchy selection gate electrodes 217 to 222 are Of the covered semiconductor layer 207, the lowermost semiconductor layer 207 is not doped with impurities, and the semiconductor layer 207 above these lowermost semiconductor layers 207 is doped with high-concentration impurities. Yes. Therefore, even when a voltage is applied to the hierarchy selection gate electrodes 217 to 222, the depletion layer extends in the region covered with the hierarchy selection gate electrodes 217 to 222 of the semiconductor layer 207 doped with the high-concentration impurities, and the conduction is made. It will not be blocked. That is, each of the hierarchical selection gate electrodes 217 to 222 blocks conduction by extending the depletion layer only in the lowermost semiconductor layer 207 of the multiple semiconductor layers 207 covered by the hierarchical selection gate electrodes 217 to 222. Therefore, the stacked semiconductor layers 207 can be cut off independently. That is, the first to sixth hierarchy selection gate electrodes 217 to 222 are in the uppermost layer (first layer from the top), second layer, third layer, fourth layer, fifth layer, sixth layer (lowermost layer) in order. The semiconductor layer 207 functions as a gate for selecting.

  According to the second embodiment, the semiconductor layer 207, the control gate electrode 223, and the hierarchy selection gate electrodes 217 to 222 can be processed in the same lithography process as that of a normal non-stacked memory. In addition, as in the first embodiment, the manufacturing process of the conventional NAND flash memory is substantially the same as the manufacturing process of the conventional NAND flash memory except for the process of forming the stacked semiconductor layers 207. There is an effect that the above-described nonvolatile semiconductor memory device can be manufactured with only a minimal change in which a manufacturing facility for the process of stacking the semiconductor layer 207 is added to the line. This is extremely effective from the viewpoint of reducing the bit cost by miniaturization.

  In addition, since the impurity is introduced into the semiconductor layer 207 by burying the diffusion source film 212 containing the impurity between the fin-like stacked structures and diffusing by heat treatment, the impurity is diffused by GPD. In addition, the semiconductor layer 207 is less susceptible to the surface state of the semiconductor layer 207 and has an effect of facilitating the diffusion of low concentration impurities. Further, the diffusion source film 212 containing impurities is not removed after the impurities are diffused in the semiconductor layer 207, but is formed to face the side surface of the semiconductor layer 207 via the charge storage layer 213 in a later step. If the groove for embedding this part is processed, it can be used as an insulating layer between adjacent semiconductor layers 207 as it is around the groove.

  In the above description, the case where the single crystal silicon film and the silicon oxide film are stacked to perform batch processing has been shown. Instead, the polycrystalline silicon film and the silicon oxide film are stacked to perform batch processing. You may make it perform.

(Third embodiment)
In the first and second embodiments, the peripheral circuit portion and the memory cell portion are provided in different regions on the semiconductor substrate. In the third embodiment, the peripheral circuit portion is provided on the semiconductor substrate. A structure in which a multilayer wiring structure is formed and a memory cell portion is provided on a peripheral circuit portion will be described. In the third embodiment, the semiconductor layers constituting the fin structure and the interlayer insulating film are alternately stacked by the vapor phase growth method so that the layer selection gate electrode is not required to be depleted. A manufacturing method in the case of performing impurity diffusion collectively by the phase diffusion method will be described.

4A to 4D are cross-sectional views schematically illustrating an example of a procedure of the method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment. In these drawings, (a) shows a cross section in the bit line direction, (b) shows a DD cross section in (a), and is a cross section in the word line direction of the hierarchical selection transistor. Moreover, (a) is a cut surface between the fin structures of (b) or a cut surface at a position corresponding thereto. In this manufacturing method, the cell area corresponding to the 11 nm generation in the planar cell structure is formed by stacking eight memory cells having a design in which the half pitch of the bit lines is 32 nm and the half pitch of the word lines is 32 nm. Take a flash memory that realizes 512 nm ² as an example.

  First, the structure shown in FIG. 4A is formed. That is, after forming the STI 302 of the peripheral circuit portion R2 and the field effect transistor 303 on the semiconductor substrate 301, the interlayer insulating film 304 is formed. Next, a wiring 305 is formed over the interlayer insulating film 304 and is electrically connected to the field effect transistor 303. Further, after the interlayer insulating film 306 is formed, a wiring 307 that is electrically connected to the wiring 305 is formed over the interlayer insulating film 306. Thereafter, an interlayer insulating film 308 is formed, and the upper surface is planarized by a method such as CMP. Note that the field-effect transistor 303 and the wiring 305 are connected via a contact, and the wirings 305 and 307 are connected via a via. Then, a via hole that penetrates the interlayer insulating film 308 and reaches the wiring 307 is formed on a position where the wiring 307 is formed, and a contact plug 309 connected to a memory cell to be formed later is embedded in the via hole. A multilayer wiring structure including the field effect transistor 303 formed on the semiconductor substrate 301 becomes the peripheral circuit portion R2.

  Next, the memory cell portion R1 is formed on the peripheral circuit portion R2. First, a plurality of interlayer insulating films 310 and semiconductor layers 311 are alternately stacked by the LPCVD method, and the uppermost layer is the interlayer insulating film 310. End with. A TEOS film or the like can be used as the interlayer insulating film 310, and the semiconductor layer 311 can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, ZnSe, and GaInAsP. In this example, a p-type polycrystalline silicon film is used. In addition, the interlayer insulating film 310 and the semiconductor layer 311 are formed with eight layers alternately having a thickness of, for example, 20 nm and 20 nm, respectively, and finally the interlayer insulating film 310 is formed with a thickness of 50 nm.

  Thereafter, a trench 312a communicating with the contact plug 309 is formed in the laminated film of the interlayer insulating film 310 / semiconductor layer 311 of the memory cell portion R1 by lithography technique and RIE method. Here, the groove 312a is formed by collectively processing the laminated film of the interlayer insulating film 310 / semiconductor layer 311 at a position corresponding to the position where the contact plug 309 is formed in the lower peripheral circuit portion R2. Thereafter, a contact layer 312 is formed so as to fill the groove 312a. As contact layer 312, for example, an n-type polycrystalline silicon film can be used. Then, the entire surface is etched back by the RIE method, and the contact layer 312 formed on the uppermost interlayer insulating film 310 is removed using the interlayer insulating film 310 as a stopper. The structure shown in FIG. 4A is obtained by the above processing.

  Next, as shown in FIG. 4B, a band-shaped structure (fin fin) extending in the first direction through the laminated film of the interlayer insulating film 310 / semiconductor layer 311 of the memory cell portion R1 by lithography and RIE. (Structure) is batch processed. As a result, a plurality of fin structures are formed in parallel in the second direction at predetermined intervals, and the side surface of the semiconductor layer 311 is exposed. Note that the semiconductor layer 311 serves as an active region. The width of the fin structure can be set to 20 nm, for example, and the half pitch of the fin structure can be set to 32 nm, for example.

Thereafter, as shown in FIG. 4C, a buried insulating film 313 is formed between the fin structures by a film forming method such as a CVD method. As the buried insulating film 313, a TEOS / O ₃ film can be used. Thereafter, the embedded insulating film 313 embedded in the portion of the hierarchical selection transistor formation region R11 in the memory cell portion R1 is etched back by using the lithography technique and the RIE method. Next, a diffusion source film 314 for diffusing impurities of a predetermined conductivity type is formed on the entire surface of the semiconductor substrate 301 in the semiconductor layer 311 of the hierarchical selection transistor formation region R11. Thereafter, the diffusion source film 314 is partially etched using a lithography technique and an RIE method. Here, if the first, second,..., And eighth hierarchical selection transistors are formed in order from the one close to the memory cell formation region R12 among the hierarchical selection transistors to be formed later, the region to be etched is hierarchical selection. Of the transistor formation region R11, the formation region R5 of the first to fourth hierarchy selection transistors is used. Further, in this region R5, the side surfaces of the uppermost layer to the fourth layer semiconductor layer 311 are exposed, and etching is performed to such a depth that the fifth to lowermost layer (eighth layer) semiconductor layer 311 is not exposed. As the diffusion source film 314, for example, a PSG film having a P concentration of 6 atomic% can be used. Further, the film thickness of the diffusion source film 314 can be set to about 30 nm, for example.

  Next, as shown in FIG. 4-4, the process of partially etching the diffusion source film 314 using lithography technique and RIE method is repeated twice more so that the diffusion source film 314 has seven steps. It is processed so that it becomes a shape. As a result, the side surfaces of the semiconductor layer 311 from the top layer to the seventh layer from the top are exposed in the formation region of the first layer selection transistor, and the semiconductor layers from the top layer to the sixth layer are formed in the formation region of the second layer selection transistor. The side surface of 311 is exposed,..., The side surface of the uppermost semiconductor layer 311 is exposed in the formation region of the seventh hierarchy selection transistor, and the side surfaces of all semiconductor layers 311 in the formation region of the eighth hierarchy selection transistor Is covered with the diffusion source film 314.

  Next, as shown in FIG. 4-5, the diffusion source film 314 is etched back for one layer of the stacked memory layers by the RIE method. As a result, the side surfaces of the uppermost to eighth semiconductor layers 311 are exposed in the formation region of the first hierarchical selection transistor, and the uppermost to seventh semiconductor layers 311 are exposed in the formation region of the second hierarchical selection transistor. Side surfaces are exposed; in the formation region of the seventh layer selection transistor, the side surfaces of the uppermost layer to the second layer semiconductor layer 311 are exposed; in the formation region of the eighth layer selection transistor, the uppermost semiconductor layer The side surface of 311 is exposed.

Thereafter, a buried insulating film 315 is formed on the entire surface of the semiconductor substrate 301. As the buried insulating film 315, for example, a TEOS / O ₃ film can be used. The film thickness of the buried insulating film 315 can be set to about 30 nm. Then, the buried insulating film 315 is etched stepwise by the same method as the method of etching the first diffusion source film 314 stepwise.

  After the buried insulating film 315 remaining on the sidewall of the semiconductor layer 311 is removed by wet etching, a diffusion source film 316 is further formed so as to be buried between the fin structures from which the buried insulating film 315 has been removed. As the diffusion source film 316, a PSG film having a P concentration of 6 atomic% can be used. The film thickness of the diffusion source film 316 can be set to about 30 nm. Thereafter, the upper surface of the diffusion source film 316 is planarized by, eg, CMP.

Thereafter, heat treatment is performed to diffuse impurities from the diffusion source films 314 and 316 to the semiconductor layer 311. As this heat treatment, an RTA treatment at a temperature of 1,000 ° C. for 10 seconds can be performed. As a result, P of 5 × 10 ¹⁹ cm ⁻³ or more is diffused into the semiconductor layer 311 in contact with the diffusion source films 314 and 316.

  Next, as shown in FIG. 4-6, the diffusion source film 316, the buried insulating film 315, the diffusion source film 314, and the buried insulating film 313 buried in the memory cell portion R1 are etched back by lithography and RIE. . Further, the diffusion source film 316, the buried insulating film 315, the diffusion source film 314, and the buried insulating film 313 are completely removed from the sidewalls of the semiconductor layer 311 by wet etching.

  Thereafter, the charge storage layer 317 is formed over the fin structure by a film formation method such as a CVD method so that the side surface of the semiconductor layer 311 is covered. As the charge storage layer 317, for example, an ONO film made of silicon oxide film / silicon nitride film / silicon oxide film can be used, and the film thickness at this time is set to 3 nm / 2 nm / 7 nm in order from the bottom to a total of 12 nm. be able to.

  Next, a gate electrode that becomes a part of the control gate electrode 328 of the memory cell transistor and a part of the hierarchy selection gate electrodes 320 to 327 of the hierarchy selection transistor is formed on the entire surface of the semiconductor substrate 301 by a film forming method such as a CVD method. A film 318 is formed. As gate electrode film 318, for example, a p-type polycrystalline silicon film can be used. The film thickness of the gate electrode film 318 can be set to about 100 nm, for example.

  Thereafter, a mask film 319 for processing the gate electrode of the transistor formed in the memory cell portion R1 is formed on the gate electrode film 318 by a film forming method such as a CVD method. As the mask film 319, for example, a silicon nitride film can be used. The film thickness of the mask film 319 can be set to 100 nm, for example.

  Thereafter, the mask film 319 is patterned by the lithography technique and the RIE method so as to correspond to the planar shapes of the control gate electrode 328 and the hierarchy selection gate electrodes 320 to 327 in the memory cell portion R1. Then, the gate electrode film 318 and the charge storage layer 317 are collectively etched by the RIE method through the mask film 319. As a result, the control gate electrode 328 and the hierarchy selection gate electrode 320 disposed through the charge storage layer 317 so as to intersect with the fin structure extending in the first direction (extending in the second direction). 327 are formed in the memory cell portion R1. Note that the half pitch of the control gate electrodes 328 of the memory cell portion R1 can be set to 32 nm, for example. At this time, the gate electrodes to be the hierarchy selection gate electrodes 320 to 327 are all formed in the same shape (the same length), unlike the first and second embodiments. As a result, the structure shown in FIG. 4-6 is obtained.

  Thereafter, although not shown, the sidewalls of the control gate electrode 328 and the hierarchy selection gate electrodes 320 to 327 are oxidized by high-temperature and short-time oxidation treatment using radicals generated from a hydrogen / oxygen mixed gas, and the control gate electrode 328 and the hierarchy selection are performed. The polycrystalline silicon film remaining between adjacent gate electrodes due to insufficient processing of the gate electrodes 320 to 327 is burned out. This prevents these short circuits and removes processing damage. Then, an interlayer insulating film is formed, and the peripheral circuit portion R2 formed before the formation of the memory cell portion R1 by the multilayer wiring process is connected to the word line and the bit line of the memory cell. Thus, the nonvolatile semiconductor memory device according to the third embodiment is completed.

  As shown in FIG. 4-6, in the third embodiment, the hierarchy selection gate electrodes 320 to 327 of the first to eighth hierarchy selection transistors are all formed in the same shape. As described above, of the semiconductor layers 311 covered with the layer selection gate electrodes 320 to 327, the seven semiconductor layers 311 become diffusion portions doped with high-concentration P by solid phase diffusion from the diffusion source films 314 and 316. Therefore, even if a voltage is applied to the hierarchy selection gate electrodes 320 to 327, the depletion layer extends in these semiconductor layers 311 and conduction is not cut off. On the other hand, the remaining semiconductor layer 311 is a non-diffusion part that is not doped with P. Therefore, when a voltage is applied to the hierarchy selection gate electrodes 320 to 327, the semiconductor layer 311 The depletion layer extends and interrupts conduction. That is, each of the hierarchical selection gate electrodes 320 to 327 is conductive by extending a depletion layer when only a voltage is applied to one semiconductor layer 311 out of the plurality of semiconductor layers 311 covered by the hierarchical selection gate electrodes 320 to 327. Therefore, each stacked semiconductor layer 311 has a function of independently blocking. Specifically, the first to eighth hierarchy selection gate electrodes 320 to 327 are in the lowest layer (the eighth layer from the top), the seventh layer, the sixth layer, the fifth layer, the fourth layer, and the third layer in order. It functions as a gate for selecting the second and uppermost (first) semiconductor layer 311.

According to the third embodiment, since the memory cell portion R1 is formed on the peripheral circuit portion R2, the area of the nonvolatile semiconductor memory device can be further reduced as compared with the first and second embodiments. In addition to the effects of the first and second embodiments, it is possible to obtain the effect that In addition, when an impurity is introduced into the semiconductor layer 311 having a fin-shaped stacked structure, an insulating film embedded between the fin-shaped stacked structures is processed stepwise, the number of stacked layers of the semiconductor layers 311 is 2 ⁿ layers. On the other hand, there is also an effect that processing can be performed in a processing process using n times of lithography technology and RIE method.

  In the first and second embodiments described above, the control gate electrode and the layer selection gate electrode formed on the charge storage layers 112 and 213 of the memory cell portion R1 and the gate electrode of the peripheral circuit portion R2 are formed above. A silicide film may be formed. In this case, in order to form the electrode of the peripheral circuit portion R2 by silicidation, a silicon-based electrode is used as the electrode film composed of the first gate electrode films 113 and 214 and the second gate electrode films 114 and 215. preferable. Further, the gate electrode of the peripheral circuit portion R2 can be formed by depositing a metal film such as W / TiN / Ti, TiN / Ti, WSi, or W / TaN on the polycrystalline silicon film.

  The structures of the nonvolatile semiconductor memory devices shown in the first to third embodiments are merely examples, and the number of memory layers (semiconductor layers) may be any number as long as it is two or more layers. Thus, the integration degree of the nonvolatile semiconductor memory device can be improved.

  Furthermore, in the first to third embodiments, the charge storage layers 112, 213, and 317 of the memory cell transistor are also used as the gate dielectric film in the hierarchy selection transistor, and the hierarchy selection transistor and the memory cell transistor are formed at the same time. As shown, the hierarchical selection transistor may be formed with a gate dielectric film different from the charge storage layer.

  101, 201, 301 ... semiconductor substrate, 102, 202 ... gate insulating film, 103, 113, 114, 203, 214, 215, 318 ... gate electrode film, 104, 204 ... stopper film, 105 ... HTO film, 106, 107 , 206, 207, 311 ... semiconductor layer, 108, 208 ... planarization film, 109, 209, 304, 306, 308, 310 ... interlayer insulating film, 110, 210, 312 ... contact layer, 111, 205, 211, 313 , 315 ... buried insulating film, 112, 213, 317 ... charge storage layer, 115, 216, 319 ... mask film, 116, 117, 217 to 222, 320 to 327 ... hierarchy selection gate electrode, 118, 223, 328 ... control Gate electrode, 212, 314, 316 ... diffusion source film, 309 ... contact plug, R1 ... memory cell , R11 ... layer selection transistor forming region, R12 ... memory cell formation region, R2 ... peripheral circuit portion.

Claims (5)

A stacked structure in which interlayer insulating films and semiconductor layers are alternately stacked is arranged in a fin shape on a substrate, intersects with the fin-shaped stacked structure, and covers a side surface of the stacked semiconductor layers. A memory cell transistor portion in which a control gate electrode is disposed via,
Adjacent to the formation position of the memory cell portion of the fin-shaped stacked structure, hierarchical selection gate electrodes are arranged by the number of stacked semiconductor layers through a gate dielectric film so as to intersect the fin-shaped stacked structure. A hierarchical selection transistor unit,
With
The hierarchy selection gate electrode is stepped so that the number of the semiconductor layers facing each other on the side surface of the fin-like stacked structure is decreased step by step, and the side surface of the semiconductor layer is interposed between the fin dielectric film via the gate dielectric film. Is provided so as to cover from the top of the laminated structure,
Among the semiconductor layers whose side surfaces are covered by the respective hierarchy selection gate electrodes, impurities of a predetermined conductivity type are not diffused in the lowermost semiconductor layer, and the upper semiconductor layer is higher than the lowermost semiconductor layer. A non-volatile semiconductor memory device, wherein impurities of a predetermined conductivity type are diffused. A stacked structure in which interlayer insulating films and semiconductor layers are alternately stacked is arranged in a fin shape on a substrate, intersects with the fin-shaped stacked structure, and covers a side surface of the stacked semiconductor layers. A memory cell transistor portion in which a control gate electrode is disposed via,
Hierarchical selection via a gate dielectric film so as to cross the fin-like stacked structure and cover the side surface of the stacked semiconductor layer adjacent to the formation position of the memory cell portion of the fin-shaped stacked structure A hierarchical selection transistor portion in which gate electrodes are arranged by the number of stacked semiconductor layers;
With
The semiconductor layer covered by the hierarchy selection gate electrode includes a non-diffusion part in which a predetermined conductivity type impurity is not diffused in a region facing each of the hierarchy selection gate electrodes of each semiconductor layer, and a predetermined conductivity type impurity. And a diffusion part that has been introduced,
The non-diffusion part is formed in such a manner that a region facing the hierarchy selection gate region of a different semiconductor layer in each hierarchy selection gate electrode is the non-diffusion part. A first step of alternately forming an interlayer insulating film and a semiconductor layer on a substrate and forming a stacked structure so that the semiconductor layer is a plurality of layers;
A second step of processing the laminated structure into a fin shape;
A stepped mask film is formed between the fin-like stacked structures on the layer selection transistor formation region of the substrate so that the semiconductor layers are sequentially exposed one by one at each formation position of the layer selection transistor. Process,
A fourth step of diffusing impurities in the semiconductor layer exposed from the mask film having the fin-like stacked structure;
After the fourth step, a fifth step of etching the mask film by one layer of the semiconductor layer;
After the fifth step, a sixth step of forming a gate dielectric film on the fin-like stacked structure so as to cover the exposed side surface of the semiconductor layer;
A seventh step of forming a gate electrode film on the gate dielectric film;
An eighth step of patterning the gate electrode so as to intersect the fin-shaped stacked structure;
A method for manufacturing a nonvolatile semiconductor memory device, comprising:   4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein in the fourth step, the impurity is diffused in the semiconductor layer by performing a heat treatment in a gas containing the impurity as an element. In the fourth step, the diffusion source film containing the impurity is embedded in the mask film between the fin-like stacked structures, and heat treatment is performed to diffuse the impurity into the semiconductor layer in contact with the diffusion source film. Let
4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein, in the fifth step, the mask film is etched after the diffusion source film is removed.

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