JP2011113457A - Simultaneous multi-threading processor, control method, program, compiling method, and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce thread execution time in a simultaneous multi-threading processor. <P>SOLUTION: The simultaneous multi-threading processor includes: a fetching means which fetches a plurality of instructions belonging to one thread with thread identifiers added thereto for identifying threads where the instructions are executed, so that the instructions may be executed in the plurality of threads after decoded; a decoding means which decodes the plurality of instructions fetched by the fetching means to generate the plurality of threads, and assigns the instructions to threads indicated by the thread identifiers added to the instructions; and an execution means which executes the plurality of instructions by operating, in parallel, the plurality of threads generated by the decoding means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique for executing a plurality of threads by a simultaneous multi-threading method.

  In recent years, a multi-thread method for executing a plurality of threads on a physically single processor has been adopted for some processors. The processors disclosed in Patent Document 1 and Patent Document 2 adopt this multi-thread method, and improve the usage rate of an arithmetic unit by hiding a plurality of threads, or conceal memory access latency and the like. be able to.

  The multi-thread method includes a plurality of methods regarding how to control the timing of thread switching.

  For example, a time-division multi-threading method that switches threads at regular intervals, a method that switches to another thread when the processor enters a standby state due to a cache miss, etc. There are simultaneous multi-threading methods to judge.

  Here, the simultaneous multi-threading method will be described. Non-Patent Document 1 describes Hyper-Threading (registered trademark) technology in which simultaneous multi-threading is introduced.

  FIG. 17 is a block diagram illustrating a configuration of the simultaneous multi-threading processor 801 described in Non-Patent Document 1. Referring to the figure, in the simultaneous multi-threading processor 801, the execution resource 804 is single, but the architecture state (802 and 803) such as a register for holding the process state is multiplexed by the number of threads. . In general, the architecture state is duplicated.

  FIG. 18 is a diagram for explaining the pipeline structure of the processor described in Non-Patent Document 1. In the figure, for simplification of explanation, only a part from instruction fetch to register writing for out-of-order execution in the case of a cache hit is extracted, and the other parts are omitted.

  The instruction pointer 901 is used for tracking the instruction execution status of each thread. In the cache memory 902, the instruction sequence to be executed is cached.

  The processor fetches the instruction specified by the instruction pointer 901 from the instruction sequence cached in the cache memory 902. The instruction fetch queue 903 holds fetched instructions.

  The decoding unit 904 interprets the instruction fetched from the instruction fetch queue 903 and converts it into an instruction described by the micro opcode.

  The opcode queue 905 holds the converted instruction sequence. In the register renaming and allocation control stage 906, register renaming and allocation of resources to instructions are performed so as not to malfunction even if out-of-order execution is performed. The instruction to which the resource is allocated is stored in the queue 907, and execution determination is performed out-of-order by the scheduler 908.

  In the register read stage 909, data is read from the source register, and in the execution stage 910, the read data is processed by a circuit corresponding to the instruction. The processing result is written to the destination register at the register write stage 911.

  Note that the processor described in Non-Patent Document 1 actually has a trace cache for storing decoded instructions, and instructions in a program are almost always fetched from the trace cache. . However, in FIG. 18, for simplification, the trace cache is omitted, and the processor reads the instruction indicated by the instruction pointer 901 directly from the cache memory 902 and inputs the instruction to the opcode queue 905 after decoding.

  Further, after the execution stage 910, there is actually a write stage to the store buffer and the L1D cache before the register write stage, but these are also omitted in FIG. 18 for the sake of simplicity of explanation.

  Such an instruction fetch, decode, and execution procedure is a general operation of a processor regardless of whether or not a simultaneous multi-threading scheme is introduced.

  Next, characteristics of the operation when the simultaneous multi-threading method is adopted will be described. In this case, the instruction pointer 901 is multiplexed, and the processor fetches an instruction sequence of a plurality of threads into the instruction fetch queue 903 by referring to these instruction pointers, decodes each of them, and adds them to the opcode queue 905.

  As shown in FIG. 18, the instruction pointer 901, the instruction fetch queue 903, and the opcode queue 905 are duplicated.

  In the register rename and allocation control stage 906, the processor manages registers for each thread. That is, the processor uses the register belonging to the thread 1 for the instruction of the thread 1 and uses the register belonging to the thread 2 for the instruction of the thread 2.

  However, physical register numbers after register renaming are not managed separately for each thread. For this reason, in the register renaming and allocation control stage 906, the instruction does not need to be managed for each thread, and the instruction of the thread 1 and the instruction of the thread 2 are mixed.

  In the stage after the scheduler 908, since the registers are distinguished by physical register numbers, the processor does not need to be aware of which instruction of the thread 1 or 2 is the instruction to be executed. The processor uses the register designated by the physical register number to execute processing.

  A processor that has introduced the simultaneous multi-threading method selects instructions that can be executed by the scheduler from instructions supplied from a plurality of instruction sequences and sends them to the execution stage in the above-described procedure.

  When an instruction is supplied from a single instruction sequence, an instruction that can be executed by the scheduler cannot be selected, and an idle time may occur in the execution stage. Even in this case, the simultaneous multi-threading type processor may be able to execute an instruction of another thread during this idle time. As a result, the utilization rate of execution resources is improved. As a result, the data waiting time is concealed, and the total processing time, that is, the total processing time of a plurality of threads can be reduced.

JP 2001-236221 A JP 2006-39815 A

Deborah T. Marr, Frank Ninns, David L. Hill, Glenn Hinton, David A Koufaty, J Alan Miller, Michel Upton, "Hyper-Threading Technology Architecture and Microarchitecture", Intel Technology Journal Q1, 2002, Vol. .6, Issue 1

  However, the processor described in Non-Patent Document 1 has a problem that it is difficult to reduce the thread execution time.

  As described above, by using the simultaneous multi-threading method described in Non-Patent Document 1, the utilization efficiency of resources such as computing units is improved. For this reason, the processing capability of the processor can be effectively utilized.

  However, in the simultaneous multithreading processor, since a plurality of threads physically share a single resource, there is a problem that if only a single thread is focused, the execution time increases.

  This increase in execution time will be described with reference to FIG. As shown in FIG. 5A, it is assumed that the execution time when the thread 1 is executed alone is T1. Among these, if the time when the computing unit is actually used is t1, the computing unit is not used for "T1-t1" for reasons such as waiting for arrival of data.

  Then, as shown in FIG. 15B, if the execution time when the thread 2 is executed independently of the thread 1 is T2, and the time when the arithmetic unit is used is t2, then "T2 The calculator is not used during “−t2”.

  In a processor that can execute only a single thread, the execution time of “T1 + T2” is required to complete the processing of the thread 1 and the thread 2.

  On the other hand, the processor of the simultaneous multi-threading method can execute the instruction of the thread 2 when the arithmetic unit is not used in the thread 1. If the times t1 and t2 are sufficiently small with respect to the times A and B, the processor can execute the other thread 2 in the thread having the longer processing time, for example, the waiting time “T1−t1” of the thread 1. May be able to complete the process.

  For this reason, if the times t1 and t2 are sufficiently smaller than the times T1 and T2, the performance can be sufficiently improved by simultaneous multithreading.

  However, if the times t1 and t2 are not so small with respect to the times T1 and T2, the processing of the other thread may not be completed within the waiting time of the thread having the longer processing time. In this case, even if the data waiting time can be concealed, the performance improvement is negligible. In some cases, the performance may be lower than that of a single-thread processor due to the overhead caused by supplying instructions for two threads and the competition between threads on the cache memory.

  As described above, when the operation time of the arithmetic unit is long with respect to the data waiting time, even if the simultaneous multi-threading method is applied, the execution time increases and the performance may not be improved.

  In order to shorten the execution time of a single thread, it is effective to reduce the data waiting time. As a method for reducing the data waiting time, there are a method in which a processor issues a load instruction for supplying data to a register as early as possible, and a method in which the processor controls so that a number of load instructions can be issued simultaneously.

  However, the effectiveness of these methods for reducing data latency is limited by the number of soft-looking registers that are available to the program. For example, if there is no free register available for each instruction, the processor cannot issue a load instruction in the first place. For this reason, a sufficient number of soft appearance registers are required to reduce data latency.

  Regarding issuance of a load instruction, for example, a large number of physical registers are prepared for the number of logical soft-looking registers, and the register name is renamed by hardware (ie, register renaming). There is a technology to issue.

  However, even with this register renaming, the load / store instruction itself is not deleted. For this reason, in the case where a register spill that explicitly replaces the data on the register occurs, the effect of reducing the data waiting time is limited.

  For this reason, in the simultaneous multithreading processor, it is difficult to reduce the thread execution time, particularly the data waiting time.

  An object of the present invention is to provide a technique for reducing the execution time of a thread executed by a simultaneous multi-threading processor.

  In order to achieve the above object, the simultaneous multithreading processor of the present invention has a thread identifier for identifying a thread in which the instruction is executed among the plurality of threads so that the thread is executed in a plurality of threads after decoding. A fetch means for fetching a plurality of instructions belonging to a single thread, and a plurality of instructions fetched by the fetch means are decoded to generate the plurality of threads, which are added to the instructions. A decoding unit that assigns the instruction to the thread indicated by the thread identifier; and an execution unit that executes the plurality of instructions by operating the plurality of threads generated by the decoding unit in parallel.

  The control method of the simultaneous multi-threading processor of the present invention is such that a thread identifier for identifying a thread in which the instruction is executed among the plurality of threads is added so that the thread is executed by a plurality of threads after decoding. Fetch a plurality of instructions belonging to one thread, decode the fetched instructions, generate the plurality of threads, and assign the instructions to threads indicated by the thread identifier added to the instructions A method for controlling a simultaneous multi-threading processor that executes the plurality of instructions by operating the plurality of generated threads in parallel.

  A program according to the present invention is a program for compiling, and a conversion procedure for converting a source code into a plurality of instructions belonging to a single thread so that the computer can be executed by a plurality of threads after decoding, and It is a program for executing an additional procedure for adding a thread identifier for identifying a thread in which an instruction is executed among the plurality of threads to each of the instructions.

  The compiling method of the present invention converts the source code into a plurality of instructions belonging to a single thread so that it is executed in a plurality of threads after decoding, and identifies a thread in which the instructions are executed among the plurality of threads. This is a compiling method in which a thread identifier for performing is added to each instruction.

  The information processing apparatus according to the present invention converts the source code into a plurality of instructions belonging to a single thread so that the information is executed by a plurality of threads after decoding. A compiler for adding a thread identifier for identification to each of the instructions; and fetching the plurality of instructions to which the thread identifier is added by the compiler; decoding the plurality of fetched instructions; A multithreading processor that executes the plurality of instructions by assigning the instruction to a thread indicated by the thread identifier added to each instruction and causing the plurality of generated threads to operate in parallel. And having.

  According to the present invention, the simultaneous multi-threading processor fetches a plurality of instructions belonging to a single thread, generates a plurality of threads, and assigns an instruction to the thread indicated by the thread identifier. A plurality of instructions belonging to can be processed by a plurality of threads after decoding. For this reason, a single thread can use resources for a plurality of threads, and the execution time of the thread is reduced.

It is a block diagram which shows the example of 1 structure of the information processing apparatus of the 1st Embodiment of this invention. It is a flowchart which shows the compiler method of the 1st Embodiment of this invention. It is a figure which shows an example of the format of the instruction word of the 1st Embodiment of this invention. It is a block diagram which shows one structural example of the processor of the 1st Embodiment of this invention. It is a figure which shows an example of the format of the instruction word of the 1st Embodiment of this invention. It is a block diagram which shows one structural example of the execution part of the 1st Embodiment of this invention. It is a figure which shows an example of the pipeline of the 1st Embodiment of this invention. (A) It is a figure for demonstrating operation | movement of the decoding part of the 1st Embodiment of this invention. (B) It is a figure for demonstrating operation | movement of the decoding part of the 1st Embodiment of this invention. (A) It is a figure for demonstrating operation | movement of the decoding part of the 1st Embodiment of this invention. (B) It is a figure for demonstrating operation | movement of the decoding part of the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the decoding part of the 1st Embodiment of this invention. (A) It is a figure which shows an example of the operation result of the control part and execution part of the 1st Embodiment of this invention. (B) It is a figure which shows an example of the operation result of the control part and execution part of the 1st Embodiment of this invention. (A) It is a figure which shows an example of the operation result of the control part and execution part of the 1st Embodiment of this invention. (B) It is a figure which shows an example of the operation result of the control part and execution part of the 1st Embodiment of this invention. It is an example of the source code of the 1st Embodiment of this invention. It is an example of the instruction sequence held in the instruction fetch queue according to the first embodiment of the present invention. (A) It is an example of the instruction sequence hold | maintained at the opcode queue of the 1st Embodiment of this invention. (B) It is an example of the instruction sequence held in the opcode queue according to the first embodiment of this invention. It is a figure which shows an example of the operation result of the control part and execution part of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of a general processor. It is a figure which shows a general pipeline. (A) It is a figure which shows the execution time of a general single thread. (B) It is a figure which shows the execution time of a general single thread. (C) It is a figure which shows the execution time of a general single thread. (D) It is a figure which shows the general execution time of a single thread. (E) It is a figure which shows the general execution time of a single thread. (F) It is a figure which shows the execution time of a general single thread.

(First embodiment)
A first embodiment for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of the information processing apparatus 1 according to the present embodiment. Referring to FIG. 1, the information processing apparatus 1 includes a processor 10, a main memory 20, and a storage unit 30.

  The processor 10 is a microprocessor capable of executing a plurality of threads by a simultaneous multi-threading method. The processing main memory 20 that is a feature of the present invention is a main storage device that temporarily stores data and programs. The storage unit 30 stores a compiler 301.

  The compiler 301 will be described with reference to FIG. This figure is a flowchart showing the marriage compilation method of the present embodiment. This flowchart is realized when the processor 301 executes the compiler 301.

  The processor 10 converts the source code into an object code including an instruction sequence that can be executed by the processor 10 (step S1). In the present embodiment, the compiler 10 generates an instruction sequence belonging to a single thread on the premise that the conversion is executed by a plurality of threads after decoding.

  Then, the processor 10 adds a thread identifier to each instruction (step S2). Here, the thread identifier is an identifier for identifying a thread in which an instruction is executed.

  An example of a method for adding a thread identifier to each instruction will be described. For example, assume that a DO loop statement is executed by two threads after decoding. In this case, the processor 10 assigns a thread identifier to an instruction corresponding to each process so that the process with the odd number of the loop variable is executed by one thread and the process with the even number of the loop variable is executed by the other thread. Is added.

  Next, the format of an instruction word for describing the contents of each instruction will be described. FIG. 3 is a diagram showing an example of the format of the instruction word 401 used in the present embodiment. Referring to the figure, an instruction word 401 is a fixed-length bit string, and includes an instruction code 402, a destination register designation field 403, a source register designation field 404, and a thread identifier 405.

  The instruction code 402 stores a number for designating an instruction to be executed by the processor 10. The destination register designation field 403 stores the register number to which the instruction execution result is written. The source register designation field 404 stores the number of the register from which data used at the time of instruction execution is read. The thread identifier 405 is a thread identifier corresponding to the instruction code 402.

  Here, in the source register designation field 404, one or a plurality of register numbers are usually designated, but the number differs for each instruction code. Depending on the instruction set architecture, a register whose use is implicitly limited is used as a destination register or a source register, and an explicit specification in the instruction word may be omitted. In either case, the registers that can be designated as destination registers or source registers are limited to those in the single-threaded architectural state.

  In the present embodiment, the thread identifier 405 is stored in the field of the instruction word 401 and is decoded together with the instruction code 402 by the processor 10 as shown in FIG.

  The processor 10 generates and executes an object code including an instruction sequence to which a thread identifier is added by executing the compiler 301.

  FIG. 4 is a block diagram illustrating a configuration example of the processor 10 according to the present embodiment. Referring to FIG. 1, the processor 10 includes an instruction fetch unit 101, a decoding unit 102, a control unit 103, and an execution unit 104.

  The decoding unit 102 includes a thread identifier determination unit 1021, and the control unit 103 includes an output destination identifier determination unit 1031.

  The instruction fetch unit 101 fetches an instruction specified by an instruction pointer from the object code output from the compiler 301.

  The decoding unit 102 decodes a plurality of fetched instructions. The thread identifier determination unit 1021 generates a plurality of threads, refers to the thread identifier added to each instruction, and assigns the instruction to the thread corresponding to the thread identifier.

  Further, the thread identifier determination unit 1021 adds an output destination identifier to each command word according to the thread identifier added to the command word. The output destination identifier is an identifier for identifying a register as an output destination of an instruction execution result. More specifically, the output destination identifier is an identifier for specifying a thread to which an output destination register belongs among a plurality of threads.

  The control unit 103 performs register renaming and assignment control according to the output destination identifier.

  FIG. 5 is a diagram illustrating an instruction word 401 to which an output destination identifier is added. As shown in the figure, an output destination identifier 406 is added to the instruction word 401 instead of the thread identifier 405.

  The execution unit 104 will be described. FIG. 6 is a block diagram illustrating a configuration example of the execution unit 104. As shown in the figure, the execution unit 104 includes register groups 1041 and 1042 and an arithmetic unit 1043.

  The register groups 1041 and 1042 belong to different threads and share the arithmetic unit 1043.

  The register groups 1041 and 1042 in FIG. 6 correspond to the architectural state in FIG. The computing unit 1043 in FIG. 6 is an example of the execution resource in FIG.

  Actually, there is no distinction between threads in the register file itself, and each time a register corresponding to a thread is specified by a physical number. In FIG. 6, for ease of explanation, logical division is made for each thread. A group of registers in the selected state is shown.

  In addition, the execution resource usually includes a plurality of arithmetic units, but in FIG. 6, arithmetic units other than the arithmetic unit 1043 are omitted for easy explanation.

  The execution unit 104 performs scheduling by out-of-order execution. The execution unit 104 is an arithmetic unit corresponding to the instruction, processes the data read from the source register, and stores the processing result in the destination register.

  Next, the pipeline structure of the processor 10 will be described in detail. FIG. 7 is a diagram illustrating an example of a pipeline structure of the processor 10.

  The cache memory 1012 is supplied with an instruction sequence in the object code. The processor 10 fetches the instruction specified by the instruction pointer 1011 from the instruction sequence and adds it to the instruction fetch queue C1. The instruction fetch queue C1 holds fetched instructions.

  The decoding unit 102 interprets the instruction fetched from the instruction fetch queue C1, and converts it into an instruction described in micro opcode.

  The thread identifier determination unit 1021 determines to which opcode queue the instruction is added according to the thread identifier. In this embodiment, the opcode queue is multiplexed with C2 and C3, and an instruction is added to one or both of the opcode queues C1 and C2.

  Further, the thread identifier determination unit 1021 adds an output destination identifier to the instruction according to the thread identifier added to the instruction.

  The opcode queues C1 and C2 hold the added instruction together with the added output identifier.

  Based on the output identifier added to the instruction, the output destination identifier determination unit 1031 determines which thread belongs to the output destination register. In other words, the output destination identifier determination unit 1031 switches the thread to which the destination register belongs according to the output destination identifier.

  The control unit 103 performs register renaming and register allocation for each instruction according to the determination of the output destination identifier determination unit 1031. The control unit 103 adds the instruction to which the register is assigned to the queue C4. The queue C4 holds the added instruction.

  The scheduler in the execution unit 104 performs execution determination out-of-order with respect to the instruction fetched from the queue C4 (S11).

  The execution unit 104 reads data from the source register (S12). The execution unit 104 executes the instruction by processing the read data with a circuit corresponding to the instruction (S13). The execution unit 104 writes the execution result of the instruction to the destination register (S13).

  Differences between the pipeline structure of the present embodiment described in FIG. 7 and the general pipeline structure described in FIG. 18 will be summarized and described.

  First, as described above, the decoding unit 102 according to the present embodiment includes the thread identifier determination unit 1021 as illustrated in FIG. 7, but does not include the decoding unit 904 illustrated in FIG.

  Next, as shown in FIG. 7, the operation code queues C2 and C3 of this embodiment hold not only instructions but also output destination identifiers added to the instructions before decoding. On the other hand, the output code identifier is not held in the operation code queue 905 of FIG.

  Further, the control unit 103 according to the present embodiment has an output destination identifier determination unit 1031 as shown in FIG. 7, and designates an output destination register according to the output destination identifier, but the register renaming and assignment control of FIG. In stage 906, no register is designated according to the output destination identifier.

  Here, the instruction pointer 1011 and the instruction fetch queue C1 of the present embodiment are described as not multiplexed in FIG. 7, but actually, like the instruction pointer and instruction fetch queue of FIG. Multiplexed physically or logically. The processor 10 of this embodiment is intended to improve the performance of a single thread and is not necessary for the following description. Therefore, FIG. 7 shows a description regarding multiplexing of the instruction pointer 1011 and the instruction fetch queue C1. Omitted.

  When the instruction pointer 1011 and the instruction fetch queue C1 are multiplexed, the present invention can be applied if at least one of the multiplexed ones is operating effectively.

  In summary, the pipeline structure of this embodiment has a thread identifier determination unit 1021 and an output destination identifier determination unit 1031, and is different from the pipeline structure of FIG. 18 in that the operation code queue further holds the output destination identifier. .

  The operation of the thread identifier determination unit 1021 will be described with reference to FIGS. 8 to 10 are diagrams for explaining the operation of the thread identifier determination unit 1021.

  In this embodiment, the thread identifier is defined by 3 bits. The most significant bit is a bit indicating the number of threads to which an instruction is assigned. The second bit is a bit indicating which of the two threads is allocated when an instruction is allocated to one thread. The least significant bit is a bit indicating an output destination identifier to be added.

  For example, when the most significant bit is “0”, an instruction is assigned to one thread, and when it is “1”, it is assigned to two threads. When the second bit is “0”, an instruction is assigned to the thread to which the OC 21 belongs, and when it is “1”, the instruction is assigned to the thread to which the OC 22 belongs. When the least significant bit is “0”, the output destination identifier “0” is added, and when it is “1”, the output destination identifier “1” is added.

  The output destination identifier “0” is an identifier for making the destination register a register belonging to the same thread as the thread to which the source register belongs. The output destination identifier “1” is an identifier for making the destination register a register belonging to a thread different from the thread to which the source register belongs.

  The output destination identifier is determined by the compiler 301 according to the processing content indicated by the instruction sequence, the method of dividing the thread, and the like.

  For example, when the process is divided into a plurality of threads and then the results of those threads are aggregated, the output identifier “1” is added.

  Specifically, consider a case where the loop variable is set to “I” of 1 to 256, and A = A + B (I) is calculated. The compiler 301 obtains the sum of B when “I” is an odd number in the thread 1, obtains the sum of B when “I” is an odd number in the thread 2, and adds the execution results of both threads outside the loop. An instruction sequence is generated assuming that In this case, the output destination identifier “1” is added to the instruction for adding the execution results of both threads.

  FIG. 8A is a diagram for explaining the operation of the thread identifier determination unit 1021 when an instruction to which the thread identifier “000” is added is decoded. Since the most significant bit is “0”, the thread identifier determination unit 1021 assigns an instruction to one thread, and since the second bit is “0”, the thread to which the instruction is assigned is a thread to which the OC 21 belongs. Since the least significant bit is “0”, the thread identifier determination unit 1021 adds the output destination identifier “0”.

  FIG. 8B is a diagram for explaining the operation of the thread identifier determination unit 1021 when an instruction to which the thread identifier “001” is added is decoded. Since the most significant bit is “0” and the second bit is “0”, the thread identifier determination unit 1021 assigns an instruction to the thread to which the OC 21 belongs. Since the least significant bit is “1”, the thread identifier determination unit 1021 adds the output destination identifier “1”.

  FIG. 9A is a diagram for explaining the operation of the thread identifier determination unit 1021 when decoding an instruction to which the thread identifier “010” is added. Since the most significant bit is “0” and the second bit is “1”, the thread identifier determination unit 1021 assigns an instruction to the thread to which the OC 22 belongs. Since the least significant bit is “0”, the thread identifier determination unit 1021 adds the output destination identifier “0”.

  FIG. 9B is a diagram for explaining the operation of the thread identifier determination unit 1021 when decoding an instruction to which the thread identifier “011” is added. Since the most significant bit is “0” and the second bit is “1”, the thread identifier determination unit 1021 assigns an instruction to the thread to which the OC 22 belongs. Since the least significant bit is “1”, the thread identifier determination unit 1021 adds the output destination identifier “1”.

  FIG. 10 is a diagram for explaining the operation of the thread identifier determination unit 1021 when an instruction to which the thread identifier “100” is added is decoded. Since the most significant bit is “1”, the thread identifier determination unit 1021 assigns instructions to two threads. Since the least significant bit is “0”, the thread identifier determination unit 1021 adds the output destination identifier “0”.

  The operation result of the output destination identifier determination unit 1031 will be described with reference to FIGS. 11 and 12. 11 and 12 are diagrams for explaining the operation of the execution unit 104 under the control of the output destination identifier determination unit 1031.

  The output destination identifier determination unit 1031 performs register renaming and resource allocation based on the output destination identifier added to the instruction.

  Specifically, when the output destination identifier is “0”, the output destination identifier determination unit 1031 performs register renaming, so that the thread to which the source register belongs and the thread to which the destination register belongs are the same thread. And perform allocation control.

  When the output destination identifier is “1”, the output destination identifier determination unit 1031 performs register renaming and allocation control so that the thread to which the source register belongs and the thread to which the destination register belongs are different threads. .

  When the output destination identifier is “0” and the source register is a register belonging to the register group 1041, as shown in FIG. 11A, the computing unit 1043 displays the execution result as a register belonging to the same register group 1041. Output to.

  When the output destination identifier is “0” and the source register is a register belonging to the register group 1042, the computing unit 1043 displays the execution result as a register belonging to the same register group 1042, as shown in FIG. Output to.

  When the output destination identifier is “1” and the source register is a register belonging to the register group 1041, the arithmetic unit 1043 transfers the execution result to a register belonging to a different register group 1042, as shown in FIG. Output.

  When the output destination identifier is “1” and the source register is a register belonging to the register group 1042, the arithmetic unit 1043 transfers the execution result to a register belonging to a different register group 1041, as shown in FIG. Output.

  11 and 12, the arrows from the register group to the computing unit indicate the input data to be processed. An arrow from the arithmetic unit to the register group indicates execution result data. The computing unit 1043 is, for example, an adder. In this case, the two arrows from the register group to the computing unit are data of the added value and the added value, and the arrow from the computing unit to the register group is the data of the addition result.

  Subsequently, an example of the source code and the object code of the present embodiment will be described with reference to FIGS.

  FIG. 13 is an example of source code for executing predetermined processing by the processor 10. In this source code, a DO loop statement for repeatedly executing the same process while changing the value of the loop variable “I” is described. This source code is described on the assumption that processing is executed by a single thread.

  The processor 10 converts the source code of FIG. 13 into an instruction sequence of an object code so that the instruction sequence can be executed by a plurality of threads after decoding by executing the compiler 301, and each instruction has a thread destination. Add an identifier.

  FIG. 14 is an example of an instruction sequence converted from the source code of FIG. 13 and input to the instruction fetch queue C1. As described above, the instruction sequence in FIG. 14 is generated on the assumption that it is assigned to a plurality of threads. For example, as instructions for setting a pointer, instructions OC3 and OC4 for thread 2 are generated in addition to instructions OC1 and OC2 for thread 1.

  Also, a thread identifier 405 corresponding to the thread in which the instruction is executed is added to each instruction code 402 in the instruction sequence.

  In FIG. 14, the destination register designation field 403 and the source register designation field 404 are omitted. In the column of the instruction code 402, the definition of the instruction code is described instead of the instruction code itself.

  The instruction OC1 and the instruction OC2 are instructions for initializing variable pointers used by the thread 1. Since these pointers are used only by the thread 1, the thread identifier “000” is added to these instructions in accordance with the definition of the thread identifier described above.

  Instructions OC3 and OC4 are instructions for initializing pointers of pointers of variables used by the thread 2. Since these pointers are used only by the thread 2, the thread identifier “010” is added to these instructions.

  The instruction OC5 is an instruction for initial setting of the loop variable “I”. Since this instruction only needs to be executed by the thread 1, the thread identifier “000” is added to this instruction.

  The instructions OC6 and OC7 are instructions for loading the variables A and B, the instruction OC8 is an instruction for executing addition, and the instruction OC9 is an instruction for executing a store of the calculation result A. These instructions are executed in each of the threads 1 and 2 while changing the pointer. Specifically, the process when the loop variable “I” is an odd number is executed by the thread 1, and the process when the loop variable “I” is an even number is executed by the thread 2. Since it is necessary to execute in both threads, a thread identifier “100” is added to these instructions.

  Instructions OC11 and OC12 are instructions for updating the pointers of variables A and B used by each thread. Since this instruction needs to be executed by both threads, a thread identifier “100” is added to these instructions.

  Since the instruction OC13 is a branch instruction and is executed only by the thread 1, the thread identifier “000” is added.

  The decoding unit 102 interprets the instruction fetched from the instruction fetch queue C1, and converts it into an instruction described in micro opcode.

  The thread identifier determination unit 1021 determines to which opcode queue the operation code queues C2 and C3 are to be added according to the thread identifier. Further, the thread identifier determination unit 1021 adds an output destination identifier to the instruction according to the thread identifier added to the instruction.

  FIG. 15A is an example of an instruction sequence added to the opcode queue C2. FIG. 15B is an example of an instruction sequence added to the operation code C3. As shown in FIGS. 4A and 4B, an output destination identifier 406 is added to each instruction code 402 in the instruction sequence. In FIG. 14, the destination register designation field 403 and the source register designation field 404 are omitted. In the column of the instruction code 402, the definition of the instruction code is described instead of the instruction code itself.

  As shown in FIG. 15A, instructions OC1, OC2, and OC5 to OC13, to which the thread identifier “000” or “100” is added, are input to the opcode queue C2 corresponding to the thread 1. As shown in FIG. 15B, instructions OC3 and OC4 to which the thread identifier “010” has been added are input to the opcode queue C3 corresponding to the thread 2, and OC6 to which the thread identifier “100” has been added. -OC12 is duplicated and input. Further, the output destination identifier “0” is added to all the instructions.

  As shown in FIG. 15, the processor 10 decomposes or duplicates an instruction sequence belonging to a single thread and assigns it to each of a plurality of threads. Then, the processor 10 assigns a register corresponding to the thread to each instruction. For example, the same instruction such as OC8 is input to the operation code queues C1 and C2. However, since these instructions belong to different threads, registers belonging to different threads are assigned. Therefore, separate calculations are performed for OC8 and the like.

  After the queue C7 described in FIG. 7, the instruction sequence of this embodiment is processed in the same manner as the instruction sequence belonging to a single thread. However, compared with the method shown in FIG. 18, in this embodiment, multiplexed architecture states such as register groups 1041 and 1042 can be assigned to a single thread in the source code. This increases the number of software-visible registers that can be used, and concealing data latency can reduce the execution time of a single thread in the source code.

  FIG. 3 shows an example in which the instruction code 402 to the source register designation field 404 and the thread identifier 405 are defined as one instruction word, but the instruction code 402 to the source register designation field 404 and the thread identifier 405 may be defined as separate instruction words. In that case, the instruction word including the thread identifier 405 is interpreted as a special instruction for changing the thread designation of the subsequent instruction word.

  In this embodiment, the output destination identifier is defined by 1 bit, but may be defined by 2 bits or more. When a single thread is processed by three or more threads, an output destination identifier of 2 bits or more is defined to specify a thread to which an output destination register belongs.

  In this embodiment, the control unit 103 is provided with the output destination identifier determination unit 1031. However, if there is no need to switch the thread corresponding to the output destination register, the output destination identifier determination unit 1031 may not be provided. Good.

  In the source code illustrated in FIG. 13, iterative processing is described. However, the compiler 301 may convert the source code in which processing other than the iterative processing is described to be executed by a plurality of threads. Of course.

  As described above, according to this embodiment, the simultaneous multi-threading processor fetches a plurality of instructions belonging to a single thread, generates a plurality of threads, and assigns the instruction to the thread indicated by the thread identifier. A plurality of instructions belonging to a single thread before decoding can be processed by a plurality of threads after decoding. For this reason, a single thread can use resources for a plurality of threads, and the execution time of the single thread is reduced.

  When the present invention is applied, it is not necessary to modify the execution resources such as the scheduler, the register file, and the arithmetic unit, and the mechanism of the normal simultaneous multithreading processor can be used as it is except for the decoding unit and the control unit. .

  Further, the simultaneous multithreading processor switches the thread to which the output destination register belongs based on the output destination identifier, so that it can process instruction strings having various processing contents.

  Since the iterative process is easily divided into a plurality of threads, if the process targeted by the compiler 301 is an iterative process belonging to a single thread, the load on the compiler is reduced.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. The processor according to the present embodiment is different from the processor according to the first embodiment in that an execution result of an instruction belonging to a certain thread is written to a register belonging to each of all multiplexed threads.

  FIG. 16 is a diagram for explaining the operation of the execution unit 104 in the present embodiment under the control of the output destination identifier determination unit 1031 illustrated in FIG. 4. Since other configurations are the same as those in the first embodiment, detailed description thereof is omitted in the present embodiment.

  As shown in FIG. 16, the arithmetic unit 1043 outputs the instruction execution result to both the register groups 1041 and 1042.

  Of course, the arithmetic unit may output the execution result to a register belonging to any two or more of the three or more threads instead of the registers corresponding to all the threads. .

  As described above, according to the present embodiment, compared to the configuration of the first embodiment, the execution result of a single thread instruction is more efficient when used by a plurality of thread instructions. It is possible to process an instruction sequence.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 10 Processor 20 Main memory 30 Storage part 101 Instruction fetch part 102 Decoding part 103 Control part 104 Execution part 301 Compiler 401 Instruction code 402 Destination register designation field 403 Source register designation field 404 Thread identifier 405 Output destination identifier 801 Processor 802, 803 Architecture state 804 Execution resource 901 Instruction pointer 902 Cache memory 903 Instruction fetch queue 904 Decode unit 905 Opcode queue 906 Control unit 907 Queue 908 Scheduler 909 Register read stage 910 Execution stage 911 Register write stage 1011 Instruction pointer 1012 Cache memory 1021 Thread identifier Constant unit 1031 Output destination identifier determination unit 1041, 1042 Register group 1043 Operation unit 3011 Conversion unit 3012 Thread identifier addition unit C1 Instruction fetch queue C2, C3 Opcode queue C4 queue S1 Scheduler S2 Register read stage S3 Execution stage S4 Register write stage

Claims (10)

Fetch a plurality of instructions belonging to a single thread to which a thread identifier for identifying a thread in which the instruction is executed is added among the plurality of threads so as to be executed by a plurality of threads after decoding. Fetch means;
Decoding means for decoding the plurality of instructions fetched by the fetch means, generating the plurality of threads, and assigning the instructions to threads indicated by the thread identifiers added to the respective instructions;
Execution means for executing the plurality of instructions by operating the plurality of threads generated by the decoding means in parallel;
A simultaneous multi-threading processor.   2. The decoding unit according to claim 1, wherein the decoding unit adds the instruction to a queue corresponding to a thread indicated by the thread identifier added to the instruction among a plurality of queues holding instructions executed by the thread. Simultaneous multi-threading processor. The decoding means adds, to the instruction, an output destination identifier for identifying an architecture unit that is an output destination of the execution result of the instruction among a plurality of architecture units based on the thread identifier added to the instruction. And
The execution means causes the plurality of threads to operate in parallel by using execution resources shared by the plurality of architecture units, executes the instructions belonging to the respective threads, and executes the execution results of the instructions, The simultaneous multithreading processor according to claim 1, wherein the simultaneous multithreading processor outputs to the architecture unit indicated by the output destination identifier added to the instruction. Control means for designating the architecture unit indicated by the output destination identifier added to the instruction by the decoding means as an output destination of the instruction;
4. The simultaneous multithreading processor according to claim 3, wherein the execution means outputs the execution result of the instruction to the architecture unit designated by the control means.   The simultaneous multithreading processor according to claim 3 or 4, wherein the output destination identifier is an identifier having all of the plurality of architecture states as output destinations. Fetch a plurality of instructions belonging to a single thread to which a thread identifier for identifying a thread in which the instruction is executed is added among the plurality of threads so that the plurality of threads are executed after decoding. ,
Decoding the plurality of fetched instructions;
Creating the plurality of threads;
Assigning the instruction to a thread indicated by the thread identifier added to each instruction;
A method for controlling a simultaneous multi-threading processor, wherein the plurality of instructions are executed by operating the plurality of generated threads in parallel. A program for compiling,
On the computer,
A conversion procedure for converting the source code into a plurality of instructions belonging to a single thread so as to be executed by a plurality of threads after decoding, and a thread for identifying a thread in which the instructions are executed among the plurality of threads An additional procedure for adding an identifier to each said instruction;
A program for running   The program according to claim 7, wherein the source code is a source code in which an iterative process is described. Convert the source code into multiple instructions belonging to a single thread so that it can be executed in multiple threads after decoding,
A compiling method, wherein a thread identifier for identifying a thread in which an instruction is executed among the plurality of threads is added to each of the instructions. The source code is converted into a plurality of instructions belonging to a single thread so as to be executed in a plurality of threads after decoding, and a thread identifier for identifying a thread in which the instructions are executed among the plurality of threads, A compiler attached to each of the instructions;
The plurality of instructions to which a thread identifier is added by the compiler are fetched, the plurality of fetched instructions are decoded, the plurality of threads are generated, and the thread indicated by the thread identifier added to each of the instructions A simultaneous multi-threading processor that executes the plurality of instructions by allocating the instructions and operating the generated threads in parallel;
An information processing apparatus.

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