JP2011108987A - Method of manufacturing crystalline semiconductor film - Google Patents
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Abstract
【課題】非単結晶半導体膜をレーザアニールする際に、適切な走査ピッチと照射回数によって前記半導体膜を結晶化することを可能にする。
【解決手段】非単結晶半導体膜上にラインビーム形状のパルスレーザを照射して結晶化を行う結晶半導体膜の製造方法において、パルスレーザは、走査方向のビーム断面形状に強度の均一な平坦部（ビーム幅ａ）を有し、パルスレーザ照射によって結晶化した半導体膜により形成されるトランジスタのチャンネル領域幅をｂとして、パルスレーザは、非単結晶半導体膜に微結晶化が生じる照射パルスエネルギ密度よりも低い照射パルスエネルギ密度Ｅを有し、パルスレーザの照射回数ｎは、照射パルスエネルギ密度Ｅのパルスレーザの照射によって結晶粒径成長が飽和する照射回数ｎ０として（ｎ０−１）以上とし、パルスレーザの走査方向における移動量ｃをｂ／２以下とする。
【選択図】図１When laser annealing a non-single crystal semiconductor film, the semiconductor film can be crystallized with an appropriate scanning pitch and number of irradiations.
In a manufacturing method of a crystalline semiconductor film in which a non-single crystal semiconductor film is crystallized by irradiating a pulse laser having a line beam shape, the pulse laser has a flat portion having a uniform intensity in a beam cross-sectional shape in a scanning direction. A pulse laser is an irradiation pulse energy density at which microcrystallization occurs in a non-single-crystal semiconductor film, where b is a channel region width of a transistor formed by a semiconductor film having (beam width a) and crystallized by pulse laser irradiation. The irradiation frequency n of the pulse laser is lower than the irradiation frequency n, and the irradiation frequency n0 at which the crystal grain size growth is saturated by irradiation of the pulse laser with the irradiation pulse energy density E is (n0-1) or more. The moving amount c in the scanning direction of the pulse laser is set to b / 2 or less.
[Selection] Figure 1
Description
この発明は、非単結晶半導体膜上に、ラインビーム形状のパルスレーザを複数回照射（オーバラップ照射）しつつ移動させて結晶化を行う結晶半導体膜の製造方法に関するものである。 The present invention relates to a method for manufacturing a crystalline semiconductor film in which a non-single crystal semiconductor film is crystallized by moving a pulse laser having a line beam shape multiple times (overlap irradiation).
一般的にＴＶやＰＣディスプレイで用いられている薄膜トランジスタは、アモルファス（非結晶）シリコン（以降ａ−シリコンという）により構成されているが、何らかの手段でシリコンを結晶化（以降ｐ−シリコンという）して利用することでＴＦＴとしての性能を格段に向上させることができる。現在は、低温度でのＳｉ結晶化プロセスとしてエキシマレーザアニール技術がすでに実用化されており、携帯電話等の小型ディスプレイ向け用途で頻繁に利用されており、さらに大画面ディスプレイなどへの実用化がなされている。
このレーザアニール法では、高いパルスエネルギを持つエキシマレーザを非単結晶半導体膜に照射することで、光エネルギを吸収した半導体が溶融または半溶融状態になり、その後急速に冷却され凝固する際に結晶化する仕組みである。この際には、広い領域を処理するために、ラインビーム形状に整形したパルスレーザを相対的に短軸方向に走査しながら照射する。通常は、単結晶半導体膜を設置した設置台を移動させることでパルスレーザの走査が行われる。
Thin film transistors generally used in TVs and PC displays are composed of amorphous (non-crystalline) silicon (hereinafter referred to as a-silicon), but silicon is crystallized (hereinafter referred to as p-silicon) by some means. The performance as a TFT can be remarkably improved. At present, excimer laser annealing technology has already been put into practical use as a Si crystallization process at low temperature, and is frequently used for small displays such as mobile phones. Has been made.
In this laser annealing method, a non-single crystal semiconductor film is irradiated with an excimer laser having a high pulse energy, so that the semiconductor that has absorbed the light energy is in a molten or semi-molten state, and then rapidly cooled and solidified. It is a mechanism to make it. At this time, in order to process a wide area, a pulse laser shaped into a line beam shape is irradiated while scanning in a relatively short axis direction. Usually, pulse laser scanning is performed by moving an installation table on which a single crystal semiconductor film is installed.
上記パルスレーザの走査においては、非単結晶半導体膜の同一位置にパルスレーザが複数回照射（オーバーラップ照射）されるように、所定のピッチでパルスレーザを走査方向に移動させている（例えば特許文献１参照）。これにより、サイズの大きい半導体膜のレーザアニール処理を可能にしている。なお、特許文献１では、レーザの順次操作に伴う結晶性の不均一性（ばらつき）が素子間のばらつきを生じさせる原因となるため、パルスレーザの走査方向におけるチャンネル領域のサイズＳと、パルスレーザの走査ピッチＰとが概略Ｓ＝ｎＰ（ｎは０を除く整数）となるようにして、結晶性Ｓｉ膜の結晶分布がパルスレーザ光の走査方向に周期的に変化するパターンとし、各薄膜トランジスタのチャンネル領域における結晶性Ｓｉ膜は、結晶性分布のパターンの周期的な変化が等しくなるようにしている。 In the pulse laser scanning, the pulse laser is moved in the scanning direction at a predetermined pitch so that the pulse laser is irradiated a plurality of times (overlap irradiation) at the same position of the non-single crystal semiconductor film (for example, patents). Reference 1). As a result, laser annealing treatment of a semiconductor film having a large size is enabled. In Patent Document 1, since the non-uniformity (variation) in crystallinity caused by the sequential operation of the laser causes variations between elements, the size S of the channel region in the scanning direction of the pulse laser, and the pulse laser The scanning pitch P of the thin film transistor is approximately S = nP (n is an integer other than 0), and the crystal distribution of the crystalline Si film is changed periodically in the scanning direction of the pulsed laser beam. In the crystalline Si film in the channel region, periodic changes in the pattern of the crystalline distribution are made equal.
そして、従来のラインビームを用いたレーザアニール処理では、パルスレーザの走査方向のビーム幅を０．３５〜０．４ｍｍ程度に固定し、パルス毎の基板送り量をビーム幅の３％から８％程度に設定しており、複数の薄膜トランジスタの性能の均一性を確保するには、レーザの照射回数をできるだけ増やすことが必要であると考えられている。
例えば、ＬＣＤ用の半導体膜では、オーバーラップ率を９２〜９５％（照射回数１２〜２０回、走査ピッチ３２〜２０μｍ）、ＯＬＥＤ半導体膜では、オーバーラップ率９３．８〜９７％（照射回数１６〜３３回、走査ピッチ２５〜１２μｍ）に設定している。
In the laser annealing process using the conventional line beam, the beam width in the scanning direction of the pulse laser is fixed to about 0.35 to 0.4 mm, and the substrate feed amount for each pulse is 3% to 8% of the beam width. It is considered that it is necessary to increase the number of laser irradiations as much as possible in order to ensure the uniformity of the performance of the plurality of thin film transistors.
For example, an overlap rate of 92 to 95% (irradiation frequency 12 to 20 times, scanning pitch 32 to 20 μm) is applied to a semiconductor film for LCD, and an overlap rate of 93.8 to 97% (irradiation frequency 16) is set to an OLED semiconductor film. To 33 times and a scanning pitch of 25 to 12 μm).
しかしながら、本発明者らが検討したところ、走査ピッチを小さな値にする程、レーザの照射回数は増加するが、実際には、所定の条件では照射回数８回程度のように、照射回数がある回数以上になると結晶粒径は増大せず飽和することを見出した。すなわち、必要以上に照射回数を増加させても、レーザ出力を有効利用できず、結晶化処理時間の増大に繋がる。
また、ビーム幅を必要以上に大きくすると、レーザパルスエネルギは一定であることから所定のエネルギ密度を得るためには必然的にラインビーム長を短くする必要があり、サイズの大きな半導体膜を処理する場合には、処理効率が低下する。
However, as a result of studies by the present inventors, the number of times of laser irradiation increases as the scanning pitch is reduced, but in practice, there are times of irradiation such as about 8 times of irradiation under a predetermined condition. It has been found that the crystal grain size does not increase and becomes saturated when the number of times exceeds. That is, even if the number of irradiations is increased more than necessary, the laser output cannot be used effectively, leading to an increase in the crystallization processing time.
Further, if the beam width is increased more than necessary, the laser pulse energy is constant. Therefore, in order to obtain a predetermined energy density, it is necessary to shorten the line beam length, and a large semiconductor film is processed. In this case, the processing efficiency decreases.
本願発明は、上記事情を背景としてなされたものであり、レーザパルスの照射回数およびパルス幅を適正に定めて効率的にレーザアニール処理を行うことができる結晶半導体膜の製造方法を提供することを目的とする。 The present invention has been made against the background of the above circumstances, and provides a method for manufacturing a crystalline semiconductor film capable of efficiently performing laser annealing treatment by appropriately determining the number of laser pulses and the pulse width. Objective.
すなわち、本発明の結晶半導体膜の製造方法は、非単結晶半導体膜上に、ラインビーム形状のパルスレーザを相対的に走査しつつ照射して結晶化を行う結晶半導体膜の製造方法において、前記パルスレーザは、走査方向のビーム断面形状に強度の均一な平坦部（ビーム幅ａ）を有し、該パルスレーザの照射によって結晶化した半導体膜により形成されるトランジスタの前記走査方向のチャンネル領域幅をｂとして、
前記パルスレーザは、該パルスレーザの照射によって前記非単結晶半導体膜に微結晶化が生じる照射パルスエネルギ密度よりも低い照射パルスエネルギ密度Ｅを有し、
パルスレーザの照射回数ｎは、前記照射パルスエネルギ密度Ｅのパルスレーザの照射によって結晶粒径成長が飽和する際の照射回数をｎ０として、（ｎ０−１）以上とし、
前記パルスレーザの前記走査方向におけるパルス毎の移動量ｃをｂ／２以下とする、
ことを特徴とする。
That is, the method for producing a crystalline semiconductor film of the present invention is the method for producing a crystalline semiconductor film, wherein the non-single crystal semiconductor film is crystallized by irradiating a line beam shaped pulse laser while relatively scanning. The pulse laser has a flat portion (beam width a) with uniform intensity in the beam cross-sectional shape in the scanning direction, and the channel region width in the scanning direction of a transistor formed of a semiconductor film crystallized by irradiation with the pulse laser. As b
The pulse laser has an irradiation pulse energy density E lower than an irradiation pulse energy density at which microcrystallization occurs in the non-single-crystal semiconductor film by irradiation of the pulse laser;
The pulse laser irradiation number n is (n0-1) or more, where n0 is the number of irradiation times when the crystal grain size growth is saturated by irradiation with the pulse laser having the irradiation pulse energy density E,
The movement amount c of each pulse in the scanning direction of the pulse laser is set to b / 2 or less.
It is characterized by that.
上記パルスレーザは、上記したように、走査方向のビーム断面形状に強度の均一な平坦部（ビーム幅ａ）を有している。この平坦部は、最大エネルギ強度に対し、９０％以上の領域で示すことができる。
上記パルスレーザの照射パルスエネルギ密度Ｅのパルスレーザの照射によって結晶粒径成長が飽和する際の照射回数ｎ０以上とする。なお、照射パルスエネルギ密度Ｅは、パルスレーザの照射によって前記非単結晶半導体膜に微結晶化が生じる照射パルスエネルギ密度よりも低い値とする。微結晶化が生じるか否かは、電子顕微鏡写真等により判定することができる。
照射パルスエネルギ密度を微結晶化が生じる値よりも大きな値とすると、結晶粒径が極端に小さくなり、半導体としての電子移動度が１／１０程度になってしまう。
また、照射パルスエネルギ密度Ｅのパルスレーザの照射によって結晶粒径成長が飽和するとは、個々の粒径が揃い、照射回数を増しても粒径が大きくならない状態をいう。
さらに、レーザ照射回数が、（ｎ０−１）に達しないと、結晶粒径の成長が十分になされず、異なる粒径の結晶が混在し、電子移動度のバラツキが生じる。同様の理由で望ましくはｎ０以上である。
また、レーザ照射回数ｎは、３・ｎ０以下とするのが望ましい。３・ｎ０を越えると、著しく生産性が低下する。さらには、同様の理由で、２・ｎ０以下が一層望ましい。
As described above, the pulse laser has a flat portion (beam width a) with uniform intensity in the beam cross-sectional shape in the scanning direction. This flat portion can be shown in an area of 90% or more with respect to the maximum energy intensity.
The number of irradiation times n0 or more when the crystal grain size growth is saturated by the irradiation of the pulse laser having the irradiation energy density E of the pulse laser is set to be not less than n0. Note that the irradiation pulse energy density E is lower than the irradiation pulse energy density at which microcrystallization occurs in the non-single-crystal semiconductor film by irradiation with a pulse laser. Whether or not microcrystallization occurs can be determined by an electron micrograph or the like.
If the irradiation pulse energy density is set to a value larger than the value at which microcrystallization occurs, the crystal grain size becomes extremely small, and the electron mobility as a semiconductor becomes about 1/10.
Further, the fact that the crystal grain size growth is saturated by irradiation with a pulse laser having an irradiation pulse energy density E means a state in which individual grain sizes are uniform and the grain size does not increase even when the number of irradiations is increased.
Furthermore, if the number of times of laser irradiation does not reach (n0-1), the crystal grain size is not sufficiently grown, crystals having different grain sizes are mixed, and variations in electron mobility occur. For the same reason, it is preferably n0 or more.
The number of times of laser irradiation n is desirably 3 · n0 or less. If it exceeds 3 · n0, the productivity is significantly reduced. Furthermore, 2 · n0 or less is more desirable for the same reason.
上記パルスレーザの照射によって結晶化した半導体膜に形成されるトランジスタの走査方向のチャンネル領域幅をｂとすると、パルスレーザの走査ピッチ、すなわちパルス毎の移動量ｃは、ｂ／２以下とする。これにより、各チャンネル領域で現れるレーザパルスの継ぎ目は２または３本以上となり、トランジスタの性能ばらつきを低減することができる。一方、移動量ｃがｂ／２よりも大きく、ｂ以下であると、チャンネル領域における前記継ぎ目は１本もしくは２本になり、移動量ｃがｂよりも大きくなるとチャンネル領域における前記継ぎ目は０本もしくは１本になり、チャンネル領域でのトランジスタの性能ばらつきが大きくなる。 When the channel region width in the scanning direction of the transistor formed on the semiconductor film crystallized by the pulse laser irradiation is defined as b, the scanning pitch of the pulse laser, that is, the movement amount c per pulse is set to b / 2 or less. As a result, the number of laser pulse seams appearing in each channel region is two or three or more, and variations in transistor performance can be reduced. On the other hand, when the movement amount c is larger than b / 2 and less than or equal to b, the number of seams in the channel region is one or two. When the movement amount c is larger than b, the number of seams in the channel region is zero. Or it becomes one, and the performance variation of the transistor in a channel area becomes large.
上記レーザ照射回数ｎおよびパルス毎の移動量ｃによって、パルスレーザのビーム幅ａは、ａ＝ｎ・ｃで示される。このビーム幅は、５００μｍ以下とするのが望ましい。ビーム幅を大きくしすぎると、エネルギ密度を一定にする場合、パルスレーザの長軸方向におけるビーム長が小さくなるので、一走査で処理できる面積が小さくなり、処理効率が低下する。 The beam width a of the pulse laser is represented by a = n · c by the number of times of laser irradiation n and the movement amount c for each pulse. The beam width is desirably 500 μm or less. If the beam width is made too large, the beam length in the major axis direction of the pulse laser becomes small when the energy density is made constant, so that the area that can be processed in one scan is reduced and the processing efficiency is lowered.
また、パルスレーザ走査方向のチャンネル領域幅は１ｍｍ以下であるのが望ましい。トランジスタの領域幅、すなわちトランジスタを縮小化すれば、トランジスタ中を電子が流れる時間を短くでき、信号処理速度を向上させることができ、性能の優れた薄膜半導体を得ることができる。 The channel region width in the pulse laser scanning direction is preferably 1 mm or less. If the region width of the transistor, that is, the transistor is reduced, the time for electrons to flow through the transistor can be shortened, the signal processing speed can be improved, and a thin film semiconductor with excellent performance can be obtained.
本発明の処理対象となる半導体は、特定の材質に限定されないが、Ｓｉを好適なものとして挙げることができる。また、パルスレーザとしては、エキシマレーザを好適なものとして挙げることができる。 The semiconductor to be processed in the present invention is not limited to a specific material, but Si can be cited as a suitable material. An excimer laser can be cited as a suitable pulse laser.
以上説明したように、本発明の結晶半導体膜の製造方法によれば、非単結晶半導体膜上に、ラインビーム形状のパルスレーザを相対的に走査しつつ照射して結晶化を行う結晶半導体膜の製造方法において、
前記パルスレーザは、走査方向のビーム断面形状に強度の均一な平坦部（ビーム幅ａ）を有し、該パルスレーザの照射によって結晶化した半導体膜により形成されるトランジスタの前記走査方向のチャンネル領域幅をｂとして、
前記パルスレーザは、該パルスレーザの照射によって前記非単結晶半導体膜に微結晶化が生じる照射パルスエネルギ密度よりも低い照射パルスエネルギ密度Ｅを有し、
パルスレーザの照射回数ｎは、前記照射パルスエネルギ密度Ｅのパルスレーザの照射によって結晶粒径成長が飽和する際の照射回数ｎ０以上とし、
前記パルスレーザの前記走査方向におけるパルス毎の移動量ｃをｂ／２以下とするので、適正なパルスレーザ照射回数およびパルス毎の移動量により効率的にレーザアニール処理を行うことができる。また、パルスレーザのビーム幅を適正な値にして、十分なラインビーム長を得ることができ、さらに効率的な処理が可能になる効果がある。
As described above, according to the method for manufacturing a crystalline semiconductor film of the present invention, the non-single crystalline semiconductor film is crystallized by irradiating the line laser beam while relatively scanning the pulse laser. In the manufacturing method of
The pulse laser has a flat portion (beam width a) of uniform intensity in the beam cross-sectional shape in the scanning direction, and a channel region in the scanning direction of a transistor formed of a semiconductor film crystallized by irradiation with the pulse laser. If the width is b,
The pulse laser has an irradiation pulse energy density E lower than an irradiation pulse energy density at which microcrystallization occurs in the non-single-crystal semiconductor film by irradiation of the pulse laser;
The pulse laser irradiation number n is not less than the irradiation number n0 when the crystal grain size growth is saturated by irradiation with the pulse laser having the irradiation pulse energy density E,
Since the movement amount c of each pulse in the scanning direction of the pulse laser is set to b / 2 or less, the laser annealing process can be efficiently performed with an appropriate number of pulse laser irradiations and the movement amount of each pulse. In addition, the beam width of the pulse laser can be set to an appropriate value, a sufficient line beam length can be obtained, and further efficient processing can be achieved.
以下に、本発明の一実施形態を説明する。
図１は、移動台１上に載置された基板にラインビーム状のエキシマレーザからなるパルスレーザ３が照射されている状態を示している。基板には、Ｓｉアモルファスなどの非単結晶半導体膜２が形成されている。パルスレーザ３は、ラインビーム長Ｌおよびビーム幅ａを有しており、移動台１を所定のピッチで移動させることで、パルスレーザ３が走査されつつ、所定のピッチおよび照射回数で非単結晶半導体膜２上に照射される。
図２は、パルスレーザ３の走査方向のビーム断面形状を示すものである。最大エネルギ強度に対し、９０％以上のエネルギ強度を有する平坦部を有しており、該平坦部の幅がビーム幅ａとして示される。
Hereinafter, an embodiment of the present invention will be described.
FIG. 1 shows a state in which a substrate placed on a moving table 1 is irradiated with a pulse laser 3 made of a line beam excimer laser. A non-single crystal semiconductor film 2 such as Si amorphous is formed on the substrate. The pulse laser 3 has a line beam length L and a beam width a. By moving the movable table 1 at a predetermined pitch, the pulse laser 3 is scanned with the non-single crystal at a predetermined pitch and the number of irradiation times. The semiconductor film 2 is irradiated.
FIG. 2 shows a beam cross-sectional shape of the pulse laser 3 in the scanning direction. It has a flat portion having an energy intensity of 90% or more with respect to the maximum energy intensity, and the width of the flat portion is indicated as a beam width a.
また、パルスレーザ３は、非単結晶半導体膜２に照射される際に、該非単結晶半導体膜２が微結晶化しない照射パルスエネルギ密度Ｅに設定されている。
図３は、照射パルスエネルギ密度とレーザパルスの照射による結晶粒径の大きさの関係を示す図である。照射パルスエネルギ密度が低い領域では、照射パルスエネルギ密度が増すに連れて結晶粒径が大きくなっている。例えば、その途中の照射パルスエネルギ密度Ｅ１よりも照射パルスエネルギ密度が大きくなると結晶粒径が急激に大きくなる。一方、照射パルスエネルギ密度がある程度に迄大きくなると、それ以上に照射パルスエネルギ密度が大きくなっても結晶粒径の増大は殆どなく、ある照射パルスエネルギ密度Ｅ２を越えると、結晶粒径が急激に小さくなって微結晶化が生じる。したがって上記照射パルスエネルギ密度Ｅは、Ｅ≦Ｅ２で示すことができる。
Further, the pulse laser 3 is set to an irradiation pulse energy density E that does not cause the non-single crystal semiconductor film 2 to be microcrystallized when the non-single crystal semiconductor film 2 is irradiated.
FIG. 3 is a diagram showing the relationship between the irradiation pulse energy density and the crystal grain size due to laser pulse irradiation. In the region where the irradiation pulse energy density is low, the crystal grain size increases as the irradiation pulse energy density increases. For example, when the irradiation pulse energy density becomes larger than the irradiation pulse energy density E1 in the middle of the process, the crystal grain size rapidly increases. On the other hand, when the irradiation pulse energy density is increased to a certain extent, the crystal grain size hardly increases even if the irradiation pulse energy density is further increased. When the irradiation pulse energy density E2 is exceeded, the crystal grain size rapidly increases. It becomes small and microcrystallization occurs. Therefore, the irradiation pulse energy density E can be expressed by E ≦ E2.
照射パルスエネルギ密度を上記Ｅの値に設定して、非単結晶半導体膜２に照射する際には、ある回数以上に照射回数を設定しても、結晶粒径成長が飽和する。結晶粒径成長の飽和は、ＳＥＭ写真により判定する。
図４は、照射パルスエネルギ密度Ｅを、上記照射パルスエネルギ密度Ｅ１または照射パルスエネルギ密度Ｅ２に設定した場合に、照射回数に対する結晶粒径の関係を示す図である。いずれの照射パルスエネルギ密度の場合も、ある照射回数までは、照射回数が増加するに連れて結晶粒径が大きくなるが、ある照射回数になると結晶粒径成長はそれ以上には進行せず飽和する。この照射回数が本発明における照射回数ｎ０として示される。
実際の照射回数ｎは、前記照射回数ｎ０に対し、（ｎ０−１）以上、３・ｎ０以下に設定する。これにより、非単結晶半導体膜２を効果的かつ効率的に結晶化することができる。
When the irradiation pulse energy density is set to the value E and the non-single crystal semiconductor film 2 is irradiated, the crystal grain size growth is saturated even if the number of irradiations is set to a certain number or more. Saturation of crystal grain size growth is determined by SEM photography.
FIG. 4 is a diagram showing the relationship of the crystal grain size with respect to the number of irradiations when the irradiation pulse energy density E is set to the irradiation pulse energy density E1 or the irradiation pulse energy density E2. In any irradiation pulse energy density, up to a certain number of irradiations, the crystal grain size increases as the number of irradiations increases, but at a certain number of irradiations, the crystal grain size growth does not progress any further and is saturated. To do. This number of times of irradiation is shown as the number of times of irradiation n0 in the present invention.
The actual number of irradiations n is set to (n0-1) or more and 3.n0 or less with respect to the number of irradiations n0. Thereby, the non-single-crystal semiconductor film 2 can be crystallized effectively and efficiently.
上記パルスレーザの照射によって結晶化された結晶化半導体膜では、所定の間隔で薄膜半導体が形成される。薄膜半導体では、それぞれ所定のチャンネル領域幅ｂを有しており、該間隔は、好適には１ｍｍ以下に設定される。
非単結晶半導体膜２上における薄膜半導体１０の配列予定状態を図５に示す。各薄膜半導体１０では、ソース１１、ドレイン１２、ソース、ドレイン間に位置するチャンネル部１３を有しており、該チャンネル部１３のパルスレーザの走査方向幅が、チャンネル領域幅ｂとなっている。上記非単結晶半導体膜２に対し走査ピッチ（パルス毎の移動量）ｃによってパルスレーザ３を照射、移動させると、パルス毎の移動に応じて結晶化半導体膜上にビームの継ぎ目３ａが現れる。
In the crystallized semiconductor film crystallized by the pulse laser irradiation, thin film semiconductors are formed at predetermined intervals. Each thin film semiconductor has a predetermined channel region width b, and the interval is preferably set to 1 mm or less.
FIG. 5 shows a planned arrangement state of the thin film semiconductors 10 on the non-single crystal semiconductor film 2. Each thin film semiconductor 10 has a source 11, a drain 12, and a channel portion 13 located between the source and drain, and the width of the channel portion 13 in the scanning direction of the pulse laser is a channel region width b. When the pulse laser 3 is irradiated and moved on the non-single crystal semiconductor film 2 at a scanning pitch (movement amount per pulse) c, a beam joint 3a appears on the crystallized semiconductor film according to the movement for each pulse.
図５（ａ）は、パルス毎の移動量ｃを前記チャンネル領域幅ｂよりも大きくした場合のビーム継ぎ目３ａの発生状況を示している。この例では、ビーム継ぎ目３ａは、チャンネル部１３に位置しないか１本現れることになり、薄膜半導体１０の性能ばらつきを大きくする。
図５（ｂ）は、パルス毎の移動量ｃを前記チャンネル領域幅ｂの１／２よりも大きくした場合のビーム継ぎ目３ａの発生状況を示している。この例では、ビーム継ぎ目３ａは、チャンネル部１３に１本または２本現れることになり、薄膜半導体１０の性能ばらつきは低減されるものの、十分に低減されるものではない。
図５（ｂ）は、本発明で規定されているものであり、パルス毎の移動量ｃを前記チャンネル領域幅ｂの１／２以下にした場合のビーム継ぎ目３ａの発生状況を示している。この例では、ビーム継ぎ目３ａは、チャンネル部１３に２本または３本現れることになり、薄膜半導体１０の性能ばらつきは効果的に低減される。
FIG. 5A shows the state of occurrence of the beam joint 3a when the movement amount c for each pulse is larger than the channel region width b. In this example, the beam joint 3 a is not located in the channel portion 13 or appears one, and the performance variation of the thin film semiconductor 10 is increased.
FIG. 5B shows the state of occurrence of the beam joint 3a when the movement amount c for each pulse is larger than ½ of the channel region width b. In this example, one or two beam joints 3a appear in the channel portion 13, and although the performance variation of the thin film semiconductor 10 is reduced, it is not sufficiently reduced.
FIG. 5 (b) is defined in the present invention, and shows the state of occurrence of the beam joint 3a when the movement amount c for each pulse is ½ or less of the channel region width b. In this example, two or three beam joints 3a appear in the channel portion 13, and the performance variation of the thin film semiconductor 10 is effectively reduced.
上記パルス毎の移動量ｃにおいて、照射回数をｎ回に設定する場合、ビーム幅ａは、ａ＝ｎ・ｃで示される。上記設定によりパルス毎の移動量ｃは小さく設定でき、また、照射回数も結晶化を良好に行える回数であって必要以上には多くならない。この結果、ビーム幅を例えば５００μｍ以下に小さくすることができ、その結果、ビーム長を大きくして大サイズの非単結晶半導体膜を効率よく処理することが可能になる。 When the number of irradiations is set to n in the movement amount c for each pulse, the beam width a is represented by a = n · c. With the above settings, the amount of movement c for each pulse can be set small, and the number of irradiations is the number of times that crystallization can be performed satisfactorily and does not increase more than necessary. As a result, the beam width can be reduced to, for example, 500 μm or less, and as a result, a large non-single crystal semiconductor film can be efficiently processed by increasing the beam length.
以下に、本発明の一実施例を説明する。
５０ｎｍ厚のＳｉアモルファスを非単結晶半導体膜として、以下の条件で照射回数を変えてパルスレーザの照射を行った。
エキシマレーザ ：ＬＳＸ３１５Ｃ／波長３０８ｎｍ、周波数３００Ｈｚ
ビームサイズ ：ビーム長５００ｍｍ×ビーム幅０．１３ｍｍ
ビーム幅は、最大エネルギ強度９０％以上の平坦部
スキャンピッチ ：３２．５μｍ〜６．５μｍ
照射パルスエネルギ密度
：３２０ｍＪ／ｃｍ２
チャンネル領域幅：４０μｍ
An embodiment of the present invention will be described below.
A 50 nm-thick Si amorphous film was used as a non-single-crystal semiconductor film, and irradiation with a pulsed laser was performed under the following conditions while changing the number of irradiations.
Excimer laser: LSX315C / wavelength 308nm, frequency 300Hz
Beam size: beam length 500 mm x beam width 0.13 mm
The beam width is a flat portion having a maximum energy intensity of 90% or more. Scan pitch: 32.5 μm to 6.5 μm
Irradiation pulse energy density
: 320 mJ / cm 2
Channel area width: 40 μm
上記パルスレーザでは、照射パルスエネルギ密度は、微結晶が生じる照射パルスエネルギ密度以下になっており、照射回数４から照射回数８回までは結晶粒径が次第に成長していることが認められるが、照射回数８回以降では結晶粒径成長が飽和する。 In the above pulse laser, the irradiation pulse energy density is lower than the irradiation pulse energy density at which microcrystals are generated, and it is recognized that the crystal grain size gradually grows from the number of irradiations 4 to 8 times. The crystal grain size growth is saturated after the number of irradiations of 8 or more.
所定の照射回数でパルスレーザを照射した部位について、ＳＥＭ写真により観察し、該写真を図６で示した。図６に示すように、照射回数８回で、良好に結晶化がなされており、照射回数を１２、１６、２０回に増やした場合でも、結晶粒径の増加は殆ど見られなかった。
図７は、照射回数に応じた結晶粒径の変化を示すものであり、照射回数８回に至るまでは、照射回数の増加に応じて結晶粒径が増大している。照射回数８回以降では結晶粒径の増大は見られなかった。
The part irradiated with the pulse laser at a predetermined number of times of irradiation was observed with an SEM photograph, and the photograph is shown in FIG. As shown in FIG. 6, crystallization was carried out satisfactorily with the number of irradiations of 8, and even when the number of irradiations was increased to 12, 16, and 20, almost no increase in crystal grain size was observed.
FIG. 7 shows the change in crystal grain size according to the number of irradiations, and the crystal grain size increases as the number of irradiations increases until the number of irradiations reaches eight. No increase in crystal grain size was observed after 8 irradiations.
１ 移動台
２ 非単結晶半導体膜
３ パルスレーザ
３ａ ビーム継ぎ目
１０ 薄膜半導体
１１ ソース
１２ ドレイン
１３ チャンネル部
DESCRIPTION OF SYMBOLS 1 Moving platform 2 Non-single crystal semiconductor film 3 Pulse laser 3a Beam joint 10 Thin film semiconductor 11 Source 12 Drain 13 Channel part
Claims (6)
前記パルスレーザは、走査方向のビーム断面形状に強度の均一な平坦部を有し、該パルスレーザの照射によって結晶化した半導体膜により形成されるトランジスタの前記走査方向のチャンネル領域幅をｂとして、
前記パルスレーザは、該パルスレーザの照射によって前記非単結晶半導体膜に微結晶化が生じる照射パルスエネルギ密度よりも低い照射パルスエネルギ密度Ｅを有し、
パルスレーザの照射回数ｎは、前記照射パルスエネルギ密度Ｅのパルスレーザの照射によって結晶粒径成長が飽和する際の照射回数をｎ０として（ｎ０−１）以上とし、
前記パルスレーザの前記走査方向におけるパルス毎の移動量ｃをｂ／２以下とする、
ことを特徴とする結晶半導体膜の製造方法。 In a method for manufacturing a crystalline semiconductor film, a non-single crystal semiconductor film is crystallized by irradiating a pulse laser having a line beam shape while relatively scanning,
The pulse laser has a flat portion with uniform intensity in the beam cross-sectional shape in the scanning direction, and b is the channel region width in the scanning direction of a transistor formed of a semiconductor film crystallized by irradiation with the pulse laser.
The pulse laser has an irradiation pulse energy density E lower than an irradiation pulse energy density at which microcrystallization occurs in the non-single-crystal semiconductor film by irradiation of the pulse laser;
The pulse laser irradiation number n is (n0-1) or more, where n0 is the number of irradiation times when the crystal grain size growth is saturated by irradiation with the pulse laser with the irradiation pulse energy density E,
The movement amount c of each pulse in the scanning direction of the pulse laser is set to b / 2 or less.
A method for producing a crystalline semiconductor film.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014097770A1 (en) * | 2012-12-18 | 2014-06-26 | 株式会社日本製鋼所 | Method for manufacturing crystal semiconductor film |
| JP2018067642A (en) * | 2016-10-20 | 2018-04-26 | 株式会社日本製鋼所 | Crystal semiconductor film manufacturing method, crystal semiconductor film manufacturing device and control method for crystal semiconductor film manufacturing device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI462261B (en) * | 2011-10-28 | 2014-11-21 | Alpha & Omega Semiconductor Cayman Ltd | A co-package of high side and low side mosfets and its method |
| KR102480839B1 (en) * | 2016-07-05 | 2022-12-26 | 삼성디스플레이 주식회사 | Laser annealing apparatus and method of driving the same |
| KR102792804B1 (en) | 2018-11-19 | 2025-04-14 | 삼성디스플레이 주식회사 | Method of manufacturing polycrystalline silicon layer, display device, and method of manufacturing display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1074697A (en) * | 1996-08-29 | 1998-03-17 | Toshiba Corp | Polycrystalline silicon film, manufacture thereof, manufacture of thin film transistor and liquid crystal display device, and laser annealing device |
| JP2000183358A (en) * | 1998-07-17 | 2000-06-30 | Sony Corp | Method for manufacturing thin film semiconductor device |
| JP2001053020A (en) * | 1999-08-06 | 2001-02-23 | Sony Corp | Crystallization of semiconductor thin film and manufacture of thin film semiconductor device |
| JP2002176180A (en) * | 2000-12-06 | 2002-06-21 | Hitachi Ltd | Thin film semiconductor device and method of manufacturing the same |
| JP2007035812A (en) * | 2005-07-26 | 2007-02-08 | Mitsubishi Electric Corp | Manufacturing method of polycrystalline silicon film and thin film transistor |
| JP2008091811A (en) * | 2006-10-05 | 2008-04-17 | Ihi Corp | Laser annealing method and laser annealer |
| JP2009004629A (en) * | 2007-06-22 | 2009-01-08 | Semiconductor Energy Lab Co Ltd | Method and apparatus for forming polycrystalline semiconductor film |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1074697A (en) * | 1996-08-29 | 1998-03-17 | Toshiba Corp | Polycrystalline silicon film, manufacture thereof, manufacture of thin film transistor and liquid crystal display device, and laser annealing device |
| JP2000183358A (en) * | 1998-07-17 | 2000-06-30 | Sony Corp | Method for manufacturing thin film semiconductor device |
| JP2001053020A (en) * | 1999-08-06 | 2001-02-23 | Sony Corp | Crystallization of semiconductor thin film and manufacture of thin film semiconductor device |
| JP2002176180A (en) * | 2000-12-06 | 2002-06-21 | Hitachi Ltd | Thin film semiconductor device and method of manufacturing the same |
| JP2007035812A (en) * | 2005-07-26 | 2007-02-08 | Mitsubishi Electric Corp | Manufacturing method of polycrystalline silicon film and thin film transistor |
| JP2008091811A (en) * | 2006-10-05 | 2008-04-17 | Ihi Corp | Laser annealing method and laser annealer |
| JP2009004629A (en) * | 2007-06-22 | 2009-01-08 | Semiconductor Energy Lab Co Ltd | Method and apparatus for forming polycrystalline semiconductor film |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014097770A1 (en) * | 2012-12-18 | 2014-06-26 | 株式会社日本製鋼所 | Method for manufacturing crystal semiconductor film |
| JP2014120686A (en) * | 2012-12-18 | 2014-06-30 | Japan Steel Works Ltd:The | Manufacturing method of crystal semiconductor film |
| JP2018067642A (en) * | 2016-10-20 | 2018-04-26 | 株式会社日本製鋼所 | Crystal semiconductor film manufacturing method, crystal semiconductor film manufacturing device and control method for crystal semiconductor film manufacturing device |
Also Published As
| Publication number | Publication date |
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| TWI457989B (en) | 2014-10-21 |
| WO2011061991A1 (en) | 2011-05-26 |
| CN102630336A (en) | 2012-08-08 |
| JP4947667B2 (en) | 2012-06-06 |
| KR101259936B1 (en) | 2013-05-02 |
| TW201133572A (en) | 2011-10-01 |
| CN102630336B (en) | 2013-05-08 |
| KR20120073371A (en) | 2012-07-04 |
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