JP2011107737A - Device and method for transferring data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer device and data transfer method which enables stable data transfer without complicated asynchronous signal processing. <P>SOLUTION: An edge extraction means extracts an edge of a first clock. A first acquisition means obtains data sent according to the first clock at timing responding to extracting the edge by the edge extraction means. A second acquisition means obtains the data sent according to the first clock timing which is delayed to the first acquisition means. A transfer means collates the data obtained by the first acquisition means with the data obtained by the second acquisition means, and transfers the data when both are in agreement. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a data transfer apparatus and a data transfer method for transferring data transmitted according to a first clock according to a second clock that is asynchronous with the first clock.

  In order to avoid meta stable when the data signal transmitted to the data bus according to the clock on the transmitting side (first clock) is fetched by the operation according to the clock on the receiving side asynchronous with the clock (second clock). It is necessary to adjust the timing for capturing the data signal on the receiving side.

  As a method for adjusting such timing, the edge of the first clock corresponding to the switching of the data signal is latched with the edge of the second clock, and the data signal is further latched with a timing delayed by one cycle of the second clock. There is a way.

  In addition, there is a method in which FIFO (First-In-First-Out) is used to perform writing to the FIFO with a first clock and data reading from the FIFO with a second clock.

RTL Design Style Guide Verilog-HDL Edition ISBN4-9901747-0-4

  However, in the method of delaying the latching timing, the timing of the data signal of the data bus signal varies from bit to bit. Therefore, when the second clock is considerably faster than the first clock, the data in all bits It takes time to stabilize the value, and it is impossible to know the time when the data value is stable. In the case of an FPGA (Filed Programmable Array), there is a restriction that the first clock, which is normally the global clock, cannot be latched by the second clock, which is the global clock.

  Further, in the method using the FIFO, since the write address and the read address are asynchronous, complicated asynchronous signal processing is required. In some cases, a specific RAM area is required for asynchronous signal processing, which makes designing difficult.

  An object of the present invention is to provide a data transfer apparatus and a data transfer method that enable stable data transfer without requiring complicated asynchronous signal processing.

The data transfer apparatus according to the present invention includes an edge extraction means for extracting an edge of the first clock in a data transfer apparatus for transferring data transmitted according to a first clock according to a second clock asynchronous with the first clock; First acquisition means for acquiring data sent in accordance with the first clock at a timing according to edge extraction by the edge extraction means; and the first clock at a timing later than the first acquisition means. The second acquisition means for acquiring the data sent in accordance with the above, the data acquired by the first acquisition means and the data acquired by the second acquisition means are collated, and the two match Transfer means for transferring the data, the edge extraction means, the first acquisition means, the second acquisition means, and the transfer means, Characterized in that it operates in synchronization with the serial second clock.
According to this data transfer apparatus, the data sent in accordance with the first clock is acquired twice, the two data are collated, and when the two match, the data is transferred, so that complicated asynchronous signal processing is required. Stable data transfer can be performed.

The data transfer method of the present invention is a data transfer method for transferring data transmitted according to a first clock according to a second clock asynchronous with the first clock, the step of extracting an edge of the first clock, and the edge A first acquisition step of acquiring data sent in accordance with the first clock at a timing according to edge extraction in the step of extracting the first clock, and a timing delayed from the first acquisition step. The second acquisition step of acquiring the data sent in accordance with the above, the data acquired by the first acquisition step, and the data acquired by the second acquisition step are collated, and the two match Transferring the data, extracting the edge, the first obtaining step, Second acquisition step, and the step of transferring the data is characterized in that it is executed in synchronism with the second clock.
According to this data transfer method, the data sent in accordance with the first clock is acquired twice, the two data are collated, and if both match, the data is transferred, so that complicated asynchronous signal processing is required. Stable data transfer can be performed.

  According to the data transfer device of the present invention, the data sent in accordance with the first clock is acquired twice, the two data are collated, and when the two match, the data is transferred. Stable data transfer can be performed without the need.

  According to the data transfer method of the present invention, the data sent according to the first clock is acquired twice, the two data are collated, and when the two match, the data is transferred, so that complicated asynchronous signal processing is performed. Stable data transfer can be performed without the need.

The block diagram which shows the structure of a data transfer apparatus. The timing chart which shows operation | movement of a data transfer apparatus.

  Hereinafter, an embodiment of a data transfer apparatus according to the present invention will be described.

  FIG. 1 is a block diagram showing the configuration of the data transfer apparatus of this embodiment, and FIG. 2 is a timing chart showing the operation of the data transfer apparatus of this embodiment.

  As shown in FIG. 1, the data transfer apparatus of this embodiment includes a frequency divider 1, an edge extractor 2, and a data transfer unit 3. The first clock 11 and the second clock 21 are asynchronous with each other. The data bus signal 10 input to the data transfer unit 3 is generated based on the first clock 11, and the edge extraction unit 2 and the data transfer unit 3 operate based on the second clock 21.

  The frequency divider 1 divides the first clock 11 by 2 to generate a frequency-divided signal 12.

  The edge extraction unit 2 extracts the edge signal 22 of the first clock 11 by latching the frequency-divided signal 12 with the second clock 21.

  When the edge signal 22 is valid, the data transfer unit 3 latches the data bus signal 10 with the second clock 21, and further latches the data bus signal 10 with the second clock 21 delayed by one clock. When the former data and the latter data match, it is determined that the data is stable, and this data is output as the data bus signal 20.

  Next, the operation of the data transfer unit 3 will be described with reference to FIG.

  In FIG. 2, a signal 22A is a signal obtained by latching the frequency-divided signal 12 with the second clock 21, and a signal 22B is a signal obtained by delaying the signal 22A by one clock with the second clock 21. The edge extraction unit 2 generates the edge signal 22 by taking the exclusive OR of the signal 22A and the signal 22B. Since the signal 22 is slightly delayed from the actual edge of the first clock 11, if the data bus signal 10 is latched by the second clock 21 at the timing of the signal 22 in the data transfer unit 3, ideally the first The data bus signal 20 avoiding the edge position of the clock 11 is obtained, and there should be no worry about meta-stable in the data bus.

  However, in reality, the data bus signal 10 is delayed from the first clock 11 and the delay time differs for each bit of the bus, so that the data may not be stable. In addition, since the timings of the first clock 11 and the second clock 21 are not constant, the substantial timing for latching the data bus signal 10 also varies, and the data stability also varies.

  Therefore, in the data transfer unit 3, the signal 20A obtained by latching the data bus signal 10 with the second clock 21 at the timing of the signal 22 (for example, time T1 in FIG. 2) and the data bus signal 10 for one more clock. The data of the signal 20B obtained by latching at the timing of the delayed second clock 21 (for example, time T2 in FIG. 2) is compared, and after confirming that they match, the signal 20B is converted to the data. It is output as the bus signal 20 (for example, the timing of the second clock 21 at time T3 in FIG. 2 and delayed by one clock from the time T2). The edge signal 22 corresponds to an enable signal that allows latching at the former timing, and the signal 22 ′ in FIG. 2 corresponds to an enable signal that allows latching at the latter timing.

  As described above, in the data transfer device of this embodiment, the data of the data bus signal 10 obtained by latching twice with the second clock 21 is collated, and when the two match, the data is used as the data bus signal 20. Output. For this reason, the stable data can be output without being affected by the meta stable, and the time when the data becomes stable can be grasped. In addition, since the data transfer apparatus according to the present embodiment does not use a FIFO, complicated asynchronous signal processing is not required, and there is no mounting problem caused by using a specific RAM area. Furthermore, an apparatus can be configured using an FPGA.

  Note that the data bus signal 10 may be acquired three or more times, and the data bus signal 20 may be output after waiting for the data to change.

  The scope of application of the present invention is not limited to the above embodiment. The present invention can be widely applied to a data transfer apparatus and a data transfer method for transferring data transmitted according to a first clock according to a second clock asynchronous with the first clock.

2 Edge extraction unit (edge extraction means)
3 Data transfer unit (first acquisition means, second acquisition means, transfer means)
11 First clock 21 Second clock

Claims (2)

In a data transfer device for transferring data transmitted according to a first clock according to a second clock asynchronous with the first clock,
Edge extracting means for extracting an edge of the first clock;
First acquisition means for acquiring data sent according to the first clock at a timing according to edge extraction by the edge extraction means;
Second acquisition means for acquiring data sent in accordance with the first clock at a timing later than the first acquisition means;
A transfer unit that collates the data acquired by the first acquisition unit with the data acquired by the second acquisition unit, and transfers the data when they match;
With
The edge transfer means, the first acquisition means, the second acquisition means, and the transfer means operate in synchronization with the second clock. In a data transfer method for transferring data transmitted according to a first clock according to a second clock asynchronous with the first clock,
Extracting an edge of the first clock;
A first acquisition step of acquiring data sent in accordance with the first clock at a timing according to edge extraction in the step of extracting the edge;
A second acquisition step of acquiring data sent in accordance with the first clock at a timing later than the first acquisition step;
Collating the data acquired by the first acquisition step with the data acquired by the second acquisition step, and transferring the data if they match,
With
The data transfer method, wherein the step of extracting the edge, the first acquisition step, the second acquisition step, and the step of transferring the data are executed in synchronization with the second clock.

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