JP2011198466A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the following problem: test costs such as test time and test program development man-days increase, and human errors increase due to test program complications, because control by individual chips becomes necessary in the case where a plurality of chips are simultaneously measured by an external device, because trimming data is a random data peculiar to each chip.SOLUTION: A trimming value is computed inside a chip and the value is stored in a non-volatile memory. The trimming data is fetched whenever needed, and the Vt level of a reference cell and the frequency of an oscillator are adjusted. As random trimming can be performed peculiar to each chip inside the chip, control for the individual chip becomes unnecessary, even in the case where a plurality of chips are simultaneously measured by the external device. For this reason, test costs such as test time and test program development man-days can be reduced, and human errors caused by test program complications can be reduced.

Description

  The present invention relates to a semiconductor memory device provided with current correcting means and a semiconductor memory device provided with frequency correcting means.

  Trimming (optimization) for correcting voltage, current, and frequency using an external device (for example, LSI tester) and correcting to the closest value to the target value by trimming voltage, current, and oscillator circuits. ) The data was calculated and the trimming data was programmed into the non-volatile memory.

  For example, in the manufacture of a semiconductor memory device, there are variations in parameters such as the thickness of the gate oxide film, the size of each part, the impurity concentration of the diffusion region, etc., for each manufacturing process. As a result, there are variations in the reference voltage for setting the optimum write potential, read potential, and erase potential, and other voltages. Due to such manufacturing variations, the actual state of the semiconductor memory device may differ from the designed state of the semiconductor memory device. Thus, in order to absorb variations in manufacturing of the semiconductor memory device, the semiconductor memory device is trimmed so that optimization can be achieved.

  In such trimming data, for example, with respect to voltage trimming, a voltage generated inside the LSI is monitored by an AD converter, and by always generating trimming data, there is a means for storing special inspections and trimming values. An unnecessary method has been proposed. (For example, refer to Patent Document 1).

JP 2002-343868 A

  However, in the trimming method using a conventional external device, the trimming data is random data unique to each chip. For this reason, when a plurality of chips are simultaneously measured by an external device, it is necessary to control the individual chips when performing measurement, calculation, programming / reading of the nonvolatile memory.

  In the method proposed in Patent Document 1, since correction is performed every time the chip is operated after trimming correction, an extra current is consumed. Furthermore, the resolution of correction is constant, and the time and resolution necessary for correction cannot be flexibly selected.

  For this reason, when trimming is performed inside the chip, there is a problem that current consumption increases and trimming accuracy decreases.

  The first semiconductor memory device of the present invention includes an oscillator, a counter for counting the number of clocks of the oscillator in an arbitrary period inputted from the outside, a clock number outputted from the counter, and a clock number inputted from outside A clock number comparing means for obtaining a difference between the clock number comparing means, a nonvolatile memory cell array for storing the comparison result of the clock number comparing means as trimming data, and a frequency adjusting means for adjusting the frequency of the oscillator according to the value of the trimming data. It is a thing.

  Note that data correction means for correcting trimming data according to the temperature characteristics of the oscillator may be further provided. Further, a data correction means for correcting trimming data according to a plurality of temperature characteristics of the oscillator may be further provided. Furthermore, a temperature detection unit and a data correction unit that corrects trimming data read from the nonvolatile memory array according to a detection result by the temperature detection unit may be further provided.

  According to the first semiconductor memory device of the present invention, the frequency trimming value can be calculated inside the chip and stored in the nonvolatile memory, and thereafter, the frequency of the oscillator is steadily based on the trimming data stored in the nonvolatile memory. Can be kept constant. Also, the time for counting the number of clocks and the trimming resolution can be selected according to the required frequency trimming accuracy.

  According to a second semiconductor memory device of the present invention, an oscillator, phase comparison means for comparing phases of a clock output from the oscillator and an externally input clock, and a comparison result of the phase comparison means are stored as trimming data. And a frequency adjusting means for adjusting the frequency of the oscillator according to the value of the trimming data.

  Note that data correction means for correcting trimming data according to the temperature characteristics of the oscillator may be further provided. Further, a data correction means for correcting trimming data according to a plurality of temperature characteristics of the oscillator may be further provided. Furthermore, a temperature detection unit and a data correction unit that corrects trimming data read from the nonvolatile memory array according to a detection result by the temperature detection unit may be further provided.

  According to the second semiconductor memory device of the present invention, the frequency trimming value can be calculated and stored in the non-volatile memory at a higher speed inside the chip, and thereafter, based on the trimming data stored in the non-volatile memory. The frequency of the oscillator can be kept constant.

  Further, in the first and second semiconductor memory devices of the present invention, the trimming data calculation is performed by further including data correction means for correcting the trimming data according to the reference current, the cell current, and the temperature characteristics of the oscillator. Even when the temperature differs between when the reference cell is reset or when the oscillator is used, accurate trimming can be performed.

  According to the semiconductor memory device of the present invention, the random trimming data unique to each chip can be measured / calculated / programmed in the nonvolatile memory inside the chip. Therefore, even when a plurality of chips are simultaneously measured by an external device, the individual chips This control becomes unnecessary.

  Further, according to the first semiconductor memory device of the present invention, the time and resolution required for correction can be selected flexibly, so that trimming with higher accuracy can be realized while realizing trimming inside the chip.

  Further, according to the second semiconductor memory device of the present invention, when high-frequency and high-precision trimming is required, the frequency trimming value can be calculated at a higher speed, and high-speed operation and test time can be reduced. .

  Furthermore, according to the semiconductor memory device of the present invention, the temperature characteristic correction function is provided in the chip, so that the same effect as that in the case where there is no temperature change can be obtained even during various test conditions and in various temperature conditions during actual use. Obtainable.

The block diagram of the semiconductor memory device in the reference example 1 of this invention Block diagram of a semiconductor memory device in Reference Example 2 of the present invention Block diagram of a semiconductor memory device in Reference Example 3 of the present invention The block diagram of the semiconductor memory device in the reference example 4 of this invention Block diagram of a semiconductor memory device in a fifth embodiment of the present invention Block diagram of a semiconductor memory device in a sixth embodiment of the present invention Block diagram of the semiconductor memory device in the seventh embodiment of the present invention Block diagram of the semiconductor memory device in the eighth embodiment of the present invention Block diagram of the semiconductor memory device in the ninth embodiment of the present invention Block diagram of the semiconductor memory device in the tenth embodiment of the present invention Block diagram of the semiconductor memory device in the eleventh embodiment of the present invention Block diagram of a semiconductor memory device in Embodiment 12 of the present invention

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Reference Example 1)
FIG. 1 is a block diagram of a semiconductor memory device according to Reference Example 1 of the present invention.

  In FIG. 1, reference numeral 100 denotes a reference cell used as a reference (reference) means for current comparison when reading data from a memory cell. Reference numeral 110 denotes an AD converter that converts the current amount of the reference cell 100 into a digital value. Reference numeral 120 denotes a nonvolatile memory cell array that includes a trimming data area in addition to the user use area, and stores a value obtained by AD-converting the current amount of the reference cell 100 as trimming data. Reference numeral 130 denotes a reference current generating unit that adjusts the reference current amount according to the trimming data stored in the nonvolatile memory cell array 120. Reference numeral 140 denotes current comparison means for comparing the reference current and the cell current of the reference cell 100. Reference numeral 150 denotes a writing necessity determination unit that determines whether writing to the reference cell 100 is necessary based on the result of the current comparison unit 140. Reference numeral 160 denotes reference cell writing means for writing to the reference cell 100 based on the determination result of the write necessity determination means 150 or based on an external input signal from the external device 20. The reference cell 100 to the reference cell writing means 160 are provided in the memory core 10 that is a chip. Reference numeral 170 denotes a current measurement and write necessity determination unit that is provided in the external device 20 and performs measurement of the cell current of the reference cell 100 and determination of necessity of writing based on the measurement.

  The switch 181 switches whether the cell current of the reference cell 100 is transmitted to the current comparison unit 140 or the switch 182. The switch 182 switches whether the cell current of the reference cell 100 is transmitted to the AD converter 110 or the current measurement & write necessity determination unit 170. The switch 183 transmits a write-necessary command from the write-necessity determining unit 150 or a write-necessary command from the current measurement & write-necessity determining unit 170 to the reference cell writing unit 160, respectively.

  The operation of the semiconductor memory device of Reference Example 1 configured as described above will be described below.

(Trimming data setting)
First, in order to set the Vt (threshold) level of the reference cell 100 to a predetermined level, the current measurement of the reference cell 100 is performed by the current measurement & write necessity determination unit 170 of the external device 20 (for example, LSI tester). To do. The predetermined level is a level at which data “1” or “0” of a memory cell can be determined, and is an intermediate value between the Vt level of “1” data and the Vt level of “0” data. is there.

  Then, according to the result of current measurement of the reference cell 100, it is determined whether or not writing to the reference cell 100 is necessary. That is, the current measurement & write necessity determination unit 170 does not perform any operation on the memory core 10 when write is not necessary, and issues a write command to the reference cell write unit 160 when write is necessary.

  When the Vt level of the reference cell 100 does not reach the predetermined level, the reference cell writing unit 160 performs writing to raise the Vt level to the reference cell 100.

  When the Vt level of the reference cell 100 reaches a predetermined level, the AD converter 110 digitally converts the cell current amount of the reference cell 100 and stores the digital value in the memory cell array 120 as trimming data. Whether or not the Vt level of the reference cell 100 has reached a predetermined level is determined by the external device 20 in comparison with an expected value of the external device 20 such as an LSI tester or the microcode. .

(Resetting trimming data)
When the Vt level of the reference cell 100 deteriorates due to thermal stress or the like, it is necessary to reset the Vt level. Hereinafter, the operation at the time of resetting will be described.

  Based on the trimming data stored in the memory cell array 120, the reference current of the reference current generator 130 is adjusted. Then, the current comparison unit 140 compares the cell current amount of the reference cell 100 in a state where the Vt level is deteriorated with the adjusted reference current amount.

  In accordance with the comparison result, the write necessity determination unit 150 determines whether or not the reference cell 100 needs to be written. When the Vt level of the reference cell 100 does not reach the predetermined level, the reference cell writing unit 160 performs writing to raise the Vt level to the reference cell 100.

  Thereafter, until the Vt level of the reference cell 100 reaches a predetermined level, the current comparison unit 140 performs the current comparison, the write necessity determination unit 150 determines the necessity of writing, and the reference cell writing unit 160 performs the reference cell 100 writing operation. repeat.

  According to the semiconductor memory device configured as described above, the current trimming value can be calculated and stored in the memory cell array 120 inside the chip, and only when resetting when the Vt level of the reference cell 100 deteriorates due to thermal stress or the like. The trimming data is taken out from the memory cell array 120, and the reference cell 100 can be restored to the pre-degradation Vt level by adjusting the amount of the reference current that is the comparison reference source of the reference cell 100.

  In addition, since the random trimming data unique to each chip can be measured / calculated and the nonvolatile memory program can be performed inside the chip, even when a plurality of chips are simultaneously measured by the external device 20, it is not necessary to control each chip individually. . For this reason, test costs such as test time and test program development man-hours can be reduced, and human errors due to test program complexity can be reduced.

  Furthermore, trimming correction only needs to be performed when the reference cell 100 is reset, and correction is unnecessary during subsequent chip operations, so that current consumption can be reduced while trimming is performed inside the chip.

(Reference Example 2)
FIG. 2 is a block diagram of a semiconductor memory device in Reference Example 2 of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 2, reference numeral 210 denotes a data correction unit that is provided in the memory core 10 and corrects trimming data based on a temperature designation input from the outside. Reference numeral 220 denotes a temperature designation unit provided in the external device 20 when the reference cell 100 is reset.

  The operation of the semiconductor memory device of Reference Example 2 configured as described above will be described below.

  The operation of Reference Example 2 is basically the same as that of Reference Example 1. The difference from the reference example 1 is that after the current amount of the reference cell 100 is digitally converted by the AD converter 110, the trimming data composed of the digital value is corrected according to the specified temperature input from the temperature specifying means 220. The point is that correction is performed by means 210.

  The designated temperature input from the temperature designation means 220 is, for example, the current temperature designated each time when the inspection is performed at a plurality of temperatures of high temperature, normal temperature, and low temperature in the inspection process. That is, as shown in Reference Example 1, the memory cell array 120 stores trimming data. Now, if this trimming data is a value set in the manufacturing process at room temperature and the current inspection process is at room temperature, both temperatures are the same. Therefore, the trimming data stored in the memory cell array 120 is used as it is. When the Vt level of the reference cell 100 deteriorates between the manufacturing process and the inspection process, the Vt level is reset. The trimming data resetting is performed by the method shown in the reference example 1.

  However, when the current inspection process is at a high temperature, the deterioration of the Vt level of the reference cell 100 due to thermal stress is larger than that at the normal temperature. If the deterioration of the Vt level at high temperature is larger by “1” than the deterioration of the Vt level at normal temperature, the data correction unit 210 performs data correction to increment the trimming data stored in the memory cell array 120 by one. . As a result, at a high temperature where the degree of deterioration is large by “1”, the Vt level is reset based on the trimming data that is incremented by 1, and can be accurately restored to the Vt level before the deterioration, similarly to the normal temperature.

  Conversely, when the current inspection process is at a low temperature, the deterioration of the Vt level of the reference cell 100 due to thermal stress is smaller than that at the normal temperature. If the deterioration of the Vt level at low temperature is smaller by “1” than the deterioration of the Vt level at normal temperature, the data correction unit 210 performs data correction to decrement the trimming data stored in the memory cell array 120. Do. As a result, at a low temperature where the degree of deterioration is small by “1”, the Vt level is reset based on the trimmed data that has been decremented by 1, so that it can be accurately restored to the Vt level before the deterioration as at room temperature.

  In addition, the inspection of the high temperature, normal temperature, and low temperature in the inspection process described above is an example, and is not limited to these three types of temperatures. In addition, the manufacturing process and the inspection process are examples, and are not limited to these processes.

  Thus, when the Vt level of the reference cell 100 is reset, the reference current is adjusted based on the corrected trimming data, and the Vt of the reference cell 100 is reset to a predetermined level.

  The trimming data correction based on the specified temperature input from the temperature specifying unit 220 by the data correcting unit 210 can be realized by a circuit or a software calculation process. For example, a circuit that uses an adder and a subtracter to perform an operation of +1 at a high temperature and -1 at a low temperature with respect to room temperature trimming data is mounted. Specifically, the normal temperature trimming data “0010” is corrected to “0011” at a high temperature and “0001” at a low temperature. In the case of software, this calculation is calculated by software such as microcode.

  Also in the semiconductor memory device configured as described above, the same effect as in Reference Example 1 can be obtained. Further, when the configuration is further provided with the data correction means 210 for correcting the trimming data according to the temperature characteristics of the reference current and the cell current, the temperature is different between the trimming data calculation and the reference cell resetting. In addition, accurate trimming can be performed. Therefore, an effect equivalent to that in the case where there is no temperature change can be obtained even under various temperature conditions between test steps and in actual use.

(Reference Example 3)
FIG. 3 is a block diagram of a semiconductor memory device in Reference Example 3 of the present invention. The same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 3, reference numeral 310 denotes a non-volatile memory cell array that stores a plurality of digital values as trimming data.

  The operation of the semiconductor memory device of Reference Example 3 configured as described above will be described below.

  The operation in Reference Example 3 is basically the same as that in Reference Example 2. The difference from Reference Example 2 is that a plurality of temperature correction trimming data is stored in the memory cell array 310. Note that the plurality of temperature correction trimming data are, for example, as shown in Reference Example 2, the trimming data stored in the memory cell array 120 in the manufacturing process at room temperature is high temperature, normal temperature, and low temperature in the inspection process. When the inspection is performed at a plurality of temperatures, the data is corrected for high temperature by the data correction unit 210, the data is corrected for normal temperature (in this case, correction is unnecessary), and the data is corrected for low temperature. These correction data are stored in different areas of the memory cell array 310.

  When the Vt level of the reference cell 100 is reset, the reference current is adjusted based on appropriate data among the corrected trimming data, and the Vt of the reference cell 100 is reset to a predetermined level. The appropriate data is, for example, specified by the temperature specifying unit 220 from the data corrected for high temperature, the data corrected for room temperature, and the data corrected for low temperature stored in the memory cell array 310. Data corresponding to the temperature to be applied, and the corresponding correction data is selected.

  Note that the correction of the trimming data by the specified temperature can be realized by a circuit or a software calculation process as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in Reference Example 2 can be obtained.

(Reference Example 4)
FIG. 4 is a block diagram of a semiconductor memory device in Reference Example 4 of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 4, reference numeral 410 denotes a data correction unit that is provided in the memory core 10 and corrects trimming data based on the current temperature. Reference numeral 420 denotes temperature detection means provided in the memory core 10.

  The operation of the semiconductor memory device of Reference Example 4 configured as described above will be described below.

  The operation in Reference Example 4 is basically the same as that in Reference Example 1. The difference from the reference example 1 is that the trimming data extracted from the memory cell array 120 is corrected by the data correction unit 410 based on the current temperature detected by the temperature detection unit 420. Specifically, for example, as shown in Reference Example 2, the trimming data stored in the memory cell array 120 in the manufacturing process at room temperature is inspected at a plurality of temperatures such as high temperature, normal temperature, and low temperature in the inspection process. When the temperature is detected, the temperature detection means 420 detects the temperature in the current inspection process, corrects the data for high temperature (calculation of addition) when the temperature is high, and maintains the data when the temperature is normal, if the temperature is low For the low temperature, the data is corrected (subtraction operation).

  When the Vt level of the reference cell 100 is reset, the reference current is adjusted based on the corrected trimming data, and the Vt of the reference cell 100 is reset to a predetermined level.

  Note that the correction of the trimming data based on the detected temperature can be realized by a circuit or a software calculation process, as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in Reference Example 2 can be obtained.

(Embodiment 5)
FIG. 5 is a block diagram of the semiconductor memory device according to the fifth embodiment of the present invention.

  In FIG. 5, reference numeral 500 denotes an oscillator. Reference numeral 510 denotes a counter that counts the number of clocks of the oscillator 500 for an arbitrary period inputted from the outside. Reference numeral 520 denotes clock number comparison means for obtaining a difference between the number of clocks output from the counter 510 and the number of clocks input from the outside. Reference numeral 530 denotes a nonvolatile memory cell array that stores the comparison result of the clock number comparison means 520 as trimming data. Reference numeral 540 denotes frequency adjusting means for adjusting the frequency of the oscillator 500 in accordance with the value of the trimming data. Reference numeral 550 denotes a peripheral circuit. The oscillator 500 to the peripheral circuit 550 are provided in the memory core 30 that is a chip. Reference numeral 560 denotes sampling time designation means provided in the external device 40. Reference numeral 570 denotes target count value designation means provided in the external device 40.

  The switch 581 switches whether the comparison result of the clock number comparison means 520 is transmitted to the memory cell array 530 or the switch 582. The switch 582 switches the result of comparison by the clock number comparison means 520 or the trimming data from the memory cell array 530 and transmits it to the frequency adjustment means 540. That is, when the comparison result of the clock number comparison unit 520 is used in real time, data is transmitted in the order of the clock number comparison unit 520, the switch 581, the switch 582, and the frequency adjustment unit 540. When the comparison result of the clock number comparison means 520 is temporarily stored in the memory cell array 530 and is reused after the power is turned off, the clock number comparison means 520, the switch 581, the memory cell array 530, the switch 582, and the frequency adjustment means 540 are used. Data is transmitted in the order of.

  The operation of the semiconductor memory device according to the fifth embodiment configured as described above will be described below.

  First, the clock number of the oscillator 500 is counted by the counter 510 during the sampling time input from the sampling time designating unit 560 of the external device 40. Note that the sampling time input from the sampling time specifying means 560 is arbitrary. If the sampling time is lengthened, the accuracy is improved, and conversely, if the sampling time is shortened, the measurement time can be shortened.

  Next, the clock number comparison means 520 compares the clock number, which is the count value input from the target count value specifying means 570 of the external device 40, with the clock number, which is the counting result of the counter 510, to obtain a difference. The comparison result is stored in the memory cell array 530 as trimming data. The count value input from the target count value designating unit 570 is the number of times that the oscillator 500 originally oscillates during the sampling time input from the sampling time designating unit 560. That is, by determining the difference between the number of clocks output from the counter 510 and the number of clocks input from the target count value specifying means 570, it is determined whether the frequency of the oscillator 500 is adjusted as expected. As a result of the determination, for example, when the number of clocks input from the target count value designating unit 570 is “5”, if the number of clocks output by the counter 510 is “4”, the data is corrected by +1 and the clock output by the counter 510 is When the number is “6”, trimming data such as −1 correction is required.

  Thereafter, the frequency adjusting means 540 adjusts the frequency of the oscillator 500 based on the trimming data stored in the memory cell array 530 (without using the memory cell array 530 when used in real time). The peripheral circuit 570 is operated at.

  According to the semiconductor memory device configured as described above, the frequency trimming value can be calculated inside the chip and stored in the memory cell array 530, and thereafter, the oscillator 500 is constantly tuned based on the trimming data stored in the memory cell array 530. The frequency can be kept constant. Also, the time for counting the number of clocks and the trimming resolution can be selected according to the required frequency trimming accuracy.

  In addition, since the random trimming data unique to each chip can be measured, calculated and programmed in the nonvolatile memory inside the chip, even when a plurality of chips are simultaneously measured by the external device 40, it is not necessary to control each chip individually. . For this reason, test costs such as test time and test program development man-hours can be reduced, and human errors due to test program complexity can be reduced.

  Furthermore, since the time and resolution required for correction can be selected flexibly, trimming with higher accuracy can be achieved while realizing trimming inside the chip.

(Embodiment 6)
FIG. 6 is a block diagram of the semiconductor memory device according to the sixth embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 6, reference numeral 610 denotes a data correction unit that is provided in the memory core 30 and corrects trimming data based on a temperature designation input from the outside. Reference numeral 620 denotes temperature designation means provided in the external device 40 when the oscillator 500 is used.

  The operation of the semiconductor memory device according to the sixth embodiment configured as described above will be described below.

  The operation in the sixth embodiment is basically the same as that in the fifth embodiment. The difference from the fifth embodiment is that the clock number comparing means 520 obtains the difference between the clock number output from the counter 510 and the clock number input from the target count value specifying means 570, The point is that the data correction unit 610 corrects the trimming data in accordance with the specified temperature input from the temperature specifying unit 620.

  As for the correction based on the specified temperature input from the temperature specifying means 620 and the specified temperature performed by the data correction means 610, the specified temperature input from the temperature specifying means 220 shown in Reference Example 2 and the data correction means. This is the same as the correction based on the designated temperature performed at 210.

  When the oscillator 500 is used, the peripheral circuit 550 is operated by adjusting the frequency based on the corrected trimming data.

  Note that the correction of the trimming data by the specified temperature can be realized by a circuit or a software calculation process as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in the fifth embodiment can be obtained. Furthermore, by providing a configuration that further includes data correction means 610 that corrects trimming data according to the temperature characteristics of the oscillator 500, accurate data can be obtained even when the trimming data is calculated and when the oscillator is used. Trimming can be performed. Therefore, an effect equivalent to that in the case where there is no temperature change can be obtained even under various temperature conditions between test steps and in actual use.

(Embodiment 7)
FIG. 7 is a block diagram of the semiconductor memory device according to the seventh embodiment of the present invention. 5 and 6 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 7, reference numeral 710 denotes a nonvolatile memory cell array that stores a plurality of digital values as trimming data.

  The operation of the semiconductor memory device according to the seventh embodiment configured as described above will be described below.

  The operation in the seventh embodiment is basically the same as that in the sixth embodiment. The difference from the sixth embodiment is that a plurality of temperature correction trimming data is stored in the memory cell array 710. The memory cell array 710 that stores a plurality of temperature correction trimming data is the same as the memory cell array 310 of Reference Example 3, and includes, for example, data corrected for high temperature, data corrected for room temperature, and data for low temperature. The corrected data is stored in different areas of the memory cell array 710.

  When the oscillator 500 is used, the peripheral circuit 550 is operated by adjusting the frequency based on appropriate data among a plurality of corrected trimming data. Appropriate data includes, for example, data corrected for high temperature, data corrected for normal temperature, and data corrected for low temperature stored in the memory cell array 710 as shown in Reference Example 3. This is data corresponding to the temperature designated by the temperature designation means 620.

  Note that the correction of the trimming data by the specified temperature can be realized by a circuit or a software calculation process as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in the sixth embodiment can be obtained.

(Embodiment 8)
FIG. 8 is a block diagram of the semiconductor memory device according to the eighth embodiment of the present invention. The same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 8, reference numeral 810 denotes a temperature detection unit provided in the memory core 30, and reference numeral 820 denotes a data correction unit provided in the memory core 30 for correcting trimming data based on the current temperature.

  The operation of the semiconductor memory device according to the eighth embodiment configured as described above will be described below.

  The operation in the eighth embodiment is basically the same as that in the fifth embodiment. The difference from the fifth embodiment is that the data correction unit 820 corrects the trimming data extracted from the memory cell array 530 based on the current temperature specified by the temperature detection unit 810. Specifically, for example, as shown in Reference Example 4, the trimming data stored in the memory cell array 530 at the time of trimming data calculation at a normal temperature is compared with a plurality of temperatures such as a high temperature, a normal temperature, and a low temperature when the oscillator is used. When using, the temperature detection means 810 detects the current temperature, corrects the data for the high temperature when it is high (calculation of addition), keeps the data at room temperature, and at the low temperature Correct (subtract) the data for low temperatures.

  When the oscillator 500 is used, the peripheral circuit 550 is operated by adjusting the frequency based on the corrected trimming data.

  Note that the correction of the trimming data based on the detected temperature can be realized by a circuit or a software calculation process, as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in the sixth embodiment can be obtained.

(Embodiment 9)
FIG. 9 is a block diagram of a semiconductor memory device according to the ninth embodiment of the present invention.

  In FIG. 9, reference numeral 900 denotes an oscillator. Reference numeral 910 denotes phase comparison means for comparing the phases of a clock output from the oscillator 900 and a clock input from the outside. A nonvolatile memory cell array 920 stores the comparison result of the phase comparison unit 910 as trimming data. Reference numeral 930 denotes frequency adjusting means for adjusting the frequency of the oscillator 900 in accordance with the value of the trimming data. Reference numeral 940 denotes a peripheral circuit. The oscillator 900 to the peripheral circuit 940 are provided in a memory core 50 that is a chip. Reference numeral 950 denotes target clock generation means provided in the external device 60.

  The switch 961 switches whether the comparison result of the phase comparison unit 910 is transmitted to the memory cell array 920 or the switch 962. The switch 962 switches the comparison result of the phase comparison unit 910 or the trimming data from the memory cell array 920 and transmits it to the frequency adjustment unit 930. That is, when the comparison result of the phase comparison unit 910 is used in real time, data is transmitted in the order of the phase comparison unit 910, the switch 961, the switch 962, and the frequency adjustment unit 930. Further, when the comparison result of the phase comparison unit 910 is temporarily stored in the memory cell array 920 and then reused after the power is turned off, the phase comparison unit 910, the switch 961, the memory cell array 920, the switch 962, and the frequency adjustment unit 930 are sequentially arranged. Data is transmitted.

  The operation of the semiconductor memory device according to the ninth embodiment configured as described above will be described below.

  The operation in the ninth embodiment is basically the same as that in the fifth embodiment. The difference from the fifth embodiment is that trimming data is calculated by phase comparison between the clock of the oscillator 900 and the clock input from the target clock generation means 950 of the external device. Note that the clock input from the target clock generator 950 is the original number of clocks of the oscillator 900. That is, by determining the difference between the number of clocks output from the oscillator 900 and the number of clocks input from the target clock generation means 950, it is determined whether the frequency of the oscillator 900 is adjusted as expected. As a result of the determination, for example, when the number of clocks input from the target clock generation means 950 is “5”, when the number of clocks output from the oscillator 900 is “4”, the data is corrected by +1, and the number of clocks output from the oscillator 900 When “6” is set, trimming data such as −1 correction is obtained.

  Thereafter, the frequency adjustment means 930 adjusts the frequency of the oscillator 900 based on the trimming data stored in the memory cell array 920 (without using the memory cell array 920 when used in real time). The peripheral circuit 940 is operated at.

  According to the semiconductor memory device configured as described above, the frequency trimming value can be calculated and stored in the memory cell array 920 at a higher speed inside the chip, and thereafter, on a regular basis based on the trimming data stored in the memory cell array 920. The frequency of the oscillator 900 can be kept constant.

  In addition, since the random trimming data specific to each chip can be measured / calculated and the nonvolatile memory program can be performed inside the chip, even when a plurality of chips are simultaneously measured by the external device 60, individual chip control is not required. . For this reason, test costs such as test time and test program development man-hours can be reduced, and human errors due to test program complexity can be reduced.

  Further, when high-frequency and high-precision trimming is required, the frequency trimming value can be calculated at a higher speed, and high-speed operation and test time can be reduced.

(Embodiment 10)
FIG. 10 is a block diagram of the semiconductor memory device according to the tenth embodiment of the present invention. The same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 10, reference numeral 1010 denotes data correction means provided in the memory core 50 for correcting trimming data based on temperature designation input from the outside. Reference numeral 1020 denotes a temperature designation means provided in the external device 60 and used when the oscillator 900 is used.

  The operation of the semiconductor memory device of the tenth embodiment configured as described above will be described below.

  The operation in the tenth embodiment is basically the same as that in the ninth embodiment. The difference from the ninth embodiment is that the phase comparison unit 910 compares the phase of the oscillator clock and the clock input from the outside, and then compares the value according to the specified temperature input from the temperature specifying unit 1020. The data correction means 1010 corrects trimming data.

  As for the correction based on the specified temperature input from the temperature specifying means 1020 and the specified temperature performed by the data correcting means 1010, the specified temperature input from the temperature specifying means 220 shown in Reference Example 2 and the data correcting means. This is the same as the correction based on the designated temperature performed at 210.

  When the oscillator 900 is used, the peripheral circuit 940 is operated by adjusting the frequency based on the corrected trimming data.

  Note that the correction of the trimming data by the specified temperature can be realized by a circuit or a software calculation process as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in the ninth embodiment can be obtained. Furthermore, by providing a configuration that further includes data correction means 1010 that corrects trimming data according to the temperature characteristics of the oscillator 900, even when the temperature differs between the time when trimming data is calculated and the time when the oscillator is used. Trimming can be performed. Therefore, an effect equivalent to that in the case where there is no temperature change can be obtained even under various temperature conditions between test steps and in actual use.

(Embodiment 11)
FIG. 11 is a block diagram of the semiconductor memory device according to the eleventh embodiment of the present invention. In addition, the same part as FIG. 9, 10 is attached | subjected the same code | symbol and the description is abbreviate | omitted.

  In FIG. 11, reference numeral 1110 denotes a nonvolatile memory cell array that stores a plurality of digital values as trimming data.

  The operation of the semiconductor memory device according to the eleventh embodiment configured as described above will be described below.

  The operation in the eleventh embodiment is basically the same as that in the tenth embodiment. The difference from the tenth embodiment is that the memory cell array 1110 stores a plurality of temperature correction trimming data. Note that the memory cell array 1110 that stores a plurality of temperature correction trimming data is the same as the memory cell array 310 of Reference Example 3, and includes, for example, data corrected for high temperature, data corrected for room temperature, and data for low temperature. The corrected data is stored in different areas of the memory cell array 1110.

  When the oscillator 900 is used, the peripheral circuit 940 is operated by adjusting the frequency based on appropriate data among a plurality of corrected trimming data. Appropriate data includes, for example, data corrected for high temperature, data corrected for normal temperature, and data corrected for low temperature stored in the memory cell array 1110 as shown in Reference Example 3. This is data corresponding to the temperature designated by the temperature designation means 1020.

  Note that the correction of the trimming data by the specified temperature can be realized by a circuit or a software calculation process as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in the tenth embodiment can be obtained.

(Embodiment 12)
FIG. 12 is a block diagram of the semiconductor memory device according to the twelfth embodiment of the present invention. The same parts as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 12, reference numeral 1210 denotes temperature detection means provided in the memory core 50. A data correction unit 1220 is provided in the memory core 50 and corrects trimming data based on the current temperature.

  The operation of the semiconductor memory device according to the twelfth embodiment configured as described above will be described below.

  The operation in the twelfth embodiment is basically the same as that in the ninth embodiment. A difference from the ninth embodiment is that the data correction unit 1210 corrects trimming data extracted from the memory cell array 920 based on the current temperature specified by the temperature detection unit 1210. Specifically, for example, as shown in Reference Example 4, the trimming data stored in the memory cell array 920 at the time of trimming data calculation at room temperature is at a plurality of temperatures such as high temperature, normal temperature, and low temperature when the oscillator is used. When using, the temperature detection means 1210 detects the current temperature, corrects the data for the high temperature when it is high (addition calculation), keeps the data at normal temperature, and at low temperature Correct (subtract) the data for low temperatures.

  When the oscillator 900 is used, the peripheral circuit 940 is operated by adjusting the frequency based on the corrected trimming data.

  Note that the correction of the trimming data based on the detected temperature can be realized by a circuit or a software calculation process, as in the second reference example.

  Also in the semiconductor memory device configured as described above, the same effect as in the tenth embodiment can be obtained.

  The semiconductor memory device according to the present invention has a self-current trimming function, a self-frequency trimming function inside the chip, and a temperature correction function, and is useful as a semiconductor memory device capable of realizing highly efficient and highly accurate trimming.

10, 30, 50 Memory core (chip)
20, 40, 60 External device 100 Reference cell 110 AD converter 120, 310, 530, 710, 920, 1110 Nonvolatile memory cell array 130 Reference current generating means 140 Current comparing means 150 Write necessity determining means 160 Reference cell writing means 170 Current measurement & write necessity determination means 210, 410, 610, 820, 1010, 1220 Data correction means 220, 620, 1020 Temperature designation means 420, 810, 1210 Temperature detection means 500, 900 Oscillator 510 Counter 520 Clock number comparison means 540 , 930 Frequency adjustment means 550, 940 Peripheral circuit 560 Sampling time designation means 570 Target count value designation means 910 Phase comparison means 950 Target clock generation means

Claims (8)

  An oscillator, a counter for counting the number of clocks of the oscillator in an arbitrary period inputted from the outside, a clock number comparing means for obtaining a difference between the number of clocks output from the counter and the number of clocks inputted from the outside, A semiconductor memory device comprising: a non-volatile memory cell array for storing the comparison result of the clock number comparison means as trimming data; and a frequency adjustment means for adjusting the frequency of the oscillator according to the value of the trimming data.   2. The semiconductor memory device according to claim 1, further comprising data correction means for correcting trimming data in accordance with a temperature characteristic of the oscillator.   2. The semiconductor memory device according to claim 1, further comprising data correction means for correcting trimming data in accordance with a plurality of temperature characteristics of the oscillator.   2. The semiconductor memory device according to claim 1, further comprising temperature detection means and data correction means for correcting trimming data read from the nonvolatile memory array in accordance with a detection result by the temperature detection means.   An oscillator, phase comparison means for comparing the phase of the clock output from the oscillator and an externally input clock, a nonvolatile memory cell array for storing the comparison result of the phase comparison means as trimming data, and the value of the trimming data A semiconductor memory device comprising frequency adjusting means for adjusting the frequency of the oscillator according to the frequency.   6. The semiconductor memory device according to claim 5, further comprising data correction means for correcting trimming data in accordance with temperature characteristics of the oscillator.   6. The semiconductor memory device according to claim 5, further comprising data correction means for correcting trimming data in accordance with a plurality of temperature characteristics of the oscillator.   6. The semiconductor memory device according to claim 5, further comprising temperature detection means and data correction means for correcting trimming data read from the nonvolatile memory array in accordance with a detection result by the temperature detection means.

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